1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ 2 /* 3 * Wave5 series multi-standard codec IP - product config definitions 4 * 5 * Copyright (C) 2021-2023 CHIPS&MEDIA INC 6 */ 7 8 #ifndef _VPU_CONFIG_H_ 9 #define _VPU_CONFIG_H_ 10 11 #define WAVE517_CODE 0x5170 12 #define WAVE537_CODE 0x5370 13 #define WAVE511_CODE 0x5110 14 #define WAVE521_CODE 0x5210 15 #define WAVE521C_CODE 0x521c 16 #define WAVE521C_DUAL_CODE 0x521d // wave521 dual core 17 #define WAVE521E1_CODE 0x5211 18 19 #define PRODUCT_CODE_W_SERIES(x) ({ \ 20 int c = x; \ 21 ((c) == WAVE517_CODE || (c) == WAVE537_CODE || \ 22 (c) == WAVE511_CODE || (c) == WAVE521_CODE || \ 23 (c) == WAVE521E1_CODE || (c) == WAVE521C_CODE || \ 24 (c) == WAVE521C_DUAL_CODE); \ 25 }) 26 27 #define WAVE517_WORKBUF_SIZE (2 * 1024 * 1024) 28 #define WAVE521ENC_WORKBUF_SIZE (128 * 1024) //HEVC 128K, AVC 40K 29 #define WAVE521DEC_WORKBUF_SIZE (1784 * 1024) 30 31 #define MAX_NUM_INSTANCE 32 32 33 #define W5_MIN_ENC_PIC_WIDTH 256 34 #define W5_MIN_ENC_PIC_HEIGHT 128 35 #define W5_MAX_ENC_PIC_WIDTH 8192 36 #define W5_MAX_ENC_PIC_HEIGHT 8192 37 38 // application specific configuration 39 #define VPU_ENC_TIMEOUT 60000 40 #define VPU_DEC_TIMEOUT 60000 41 42 // for WAVE encoder 43 #define USE_SRC_PRP_AXI 0 44 #define USE_SRC_PRI_AXI 1 45 #define DEFAULT_SRC_AXI USE_SRC_PRP_AXI 46 47 /************************************************************************/ 48 /* VPU COMMON MEMORY */ 49 /************************************************************************/ 50 #define VLC_BUF_NUM (2) 51 52 #define COMMAND_QUEUE_DEPTH (2) 53 54 #define W5_REMAP_INDEX0 0 55 #define W5_REMAP_INDEX1 1 56 #define W5_REMAP_MAX_SIZE (1024 * 1024) 57 58 #define WAVE5_MAX_CODE_BUF_SIZE (2 * 1024 * 1024) 59 #define WAVE5_TEMPBUF_OFFSET WAVE5_MAX_CODE_BUF_SIZE 60 #define WAVE5_TEMPBUF_SIZE (1024 * 1024) 61 62 #define SIZE_COMMON (WAVE5_MAX_CODE_BUF_SIZE + WAVE5_TEMPBUF_SIZE) 63 64 //=====4. VPU REPORT MEMORY ======================// 65 66 #define WAVE5_UPPER_PROC_AXI_ID 0x0 67 68 #define WAVE5_PROC_AXI_ID 0x0 69 #define WAVE5_PRP_AXI_ID 0x0 70 #define WAVE5_FBD_Y_AXI_ID 0x0 71 #define WAVE5_FBC_Y_AXI_ID 0x0 72 #define WAVE5_FBD_C_AXI_ID 0x0 73 #define WAVE5_FBC_C_AXI_ID 0x0 74 #define WAVE5_SEC_AXI_ID 0x0 75 #define WAVE5_PRI_AXI_ID 0x0 76 77 #endif /* _VPU_CONFIG_H_ */ 78