1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ 2 /* 3 * Wave5 series multi-standard codec IP - product config definitions 4 * 5 * Copyright (C) 2021-2023 CHIPS&MEDIA INC 6 */ 7 8 #ifndef _VPU_CONFIG_H_ 9 #define _VPU_CONFIG_H_ 10 11 #define WAVE515_CODE 0x5150 12 #define WAVE517_CODE 0x5170 13 #define WAVE537_CODE 0x5370 14 #define WAVE511_CODE 0x5110 15 #define WAVE521_CODE 0x5210 16 #define WAVE521C_CODE 0x521c 17 #define WAVE521C_DUAL_CODE 0x521d // wave521 dual core 18 #define WAVE521E1_CODE 0x5211 19 20 #define PRODUCT_CODE_W_SERIES(x) ({ \ 21 int c = x; \ 22 ((c) == WAVE517_CODE || (c) == WAVE537_CODE || \ 23 (c) == WAVE511_CODE || (c) == WAVE521_CODE || \ 24 (c) == WAVE521E1_CODE || (c) == WAVE521C_CODE || \ 25 (c) == WAVE521C_DUAL_CODE) || (c) == WAVE515_CODE; \ 26 }) 27 28 #define WAVE517_WORKBUF_SIZE (2 * 1024 * 1024) 29 #define WAVE521ENC_WORKBUF_SIZE (128 * 1024) //HEVC 128K, AVC 40K 30 #define WAVE521DEC_WORKBUF_SIZE (1784 * 1024) 31 #define WAVE515DEC_WORKBUF_SIZE (2 * 1024 * 1024) 32 33 #define MAX_NUM_INSTANCE 32 34 35 #define W5_MIN_ENC_PIC_WIDTH 256 36 #define W5_MIN_ENC_PIC_HEIGHT 128 37 #define W5_MAX_ENC_PIC_WIDTH 8192 38 #define W5_MAX_ENC_PIC_HEIGHT 8192 39 40 // application specific configuration 41 #define VPU_ENC_TIMEOUT 60000 42 #define VPU_DEC_TIMEOUT 60000 43 44 // for WAVE encoder 45 #define USE_SRC_PRP_AXI 0 46 #define USE_SRC_PRI_AXI 1 47 #define DEFAULT_SRC_AXI USE_SRC_PRP_AXI 48 49 /************************************************************************/ 50 /* VPU COMMON MEMORY */ 51 /************************************************************************/ 52 #define VLC_BUF_NUM (2) 53 54 #define WAVE521_COMMAND_QUEUE_DEPTH (2) 55 #define WAVE515_COMMAND_QUEUE_DEPTH (4) 56 57 #define W5_REMAP_INDEX0 0 58 #define W5_REMAP_INDEX1 1 59 #define W5_REMAP_MAX_SIZE (1024 * 1024) 60 61 #define WAVE521_MAX_CODE_BUF_SIZE (2 * 1024 * 1024) 62 #define WAVE515_MAX_CODE_BUF_SIZE (1024 * 1024) 63 #define WAVE5_TEMPBUF_SIZE (1024 * 1024) 64 65 #define WAVE521_SIZE_COMMON (WAVE521_MAX_CODE_BUF_SIZE + WAVE5_TEMPBUF_SIZE) 66 #define WAVE515_ONE_TASKBUF_SIZE (8 * 1024 * 1024) 67 #define WAVE515_SIZE_COMMON (WAVE515_MAX_CODE_BUF_SIZE + WAVE5_TEMPBUF_SIZE + \ 68 WAVE515_COMMAND_QUEUE_DEPTH * WAVE515_ONE_TASKBUF_SIZE) 69 70 //=====4. VPU REPORT MEMORY ======================// 71 72 #define WAVE5_UPPER_PROC_AXI_ID 0x0 73 74 #define WAVE5_PROC_AXI_ID 0x0 75 #define WAVE5_PRP_AXI_ID 0x0 76 #define WAVE5_FBD_Y_AXI_ID 0x0 77 #define WAVE5_FBC_Y_AXI_ID 0x0 78 #define WAVE5_FBD_C_AXI_ID 0x0 79 #define WAVE5_FBC_C_AXI_ID 0x0 80 #define WAVE5_SEC_AXI_ID 0x0 81 #define WAVE5_PRI_AXI_ID 0x0 82 83 #endif /* _VPU_CONFIG_H_ */ 84