145d1a2b9SNas Chung /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ 245d1a2b9SNas Chung /* 345d1a2b9SNas Chung * Wave5 series multi-standard codec IP - product config definitions 445d1a2b9SNas Chung * 545d1a2b9SNas Chung * Copyright (C) 2021-2023 CHIPS&MEDIA INC 645d1a2b9SNas Chung */ 745d1a2b9SNas Chung 845d1a2b9SNas Chung #ifndef _VPU_CONFIG_H_ 945d1a2b9SNas Chung #define _VPU_CONFIG_H_ 1045d1a2b9SNas Chung 11*6aa08291SIvan Bornyakov #define WAVE515_CODE 0x5150 1245d1a2b9SNas Chung #define WAVE517_CODE 0x5170 1345d1a2b9SNas Chung #define WAVE537_CODE 0x5370 1445d1a2b9SNas Chung #define WAVE511_CODE 0x5110 1545d1a2b9SNas Chung #define WAVE521_CODE 0x5210 1645d1a2b9SNas Chung #define WAVE521C_CODE 0x521c 1745d1a2b9SNas Chung #define WAVE521C_DUAL_CODE 0x521d // wave521 dual core 1845d1a2b9SNas Chung #define WAVE521E1_CODE 0x5211 1945d1a2b9SNas Chung 2045d1a2b9SNas Chung #define PRODUCT_CODE_W_SERIES(x) ({ \ 2145d1a2b9SNas Chung int c = x; \ 2245d1a2b9SNas Chung ((c) == WAVE517_CODE || (c) == WAVE537_CODE || \ 2345d1a2b9SNas Chung (c) == WAVE511_CODE || (c) == WAVE521_CODE || \ 2445d1a2b9SNas Chung (c) == WAVE521E1_CODE || (c) == WAVE521C_CODE || \ 25*6aa08291SIvan Bornyakov (c) == WAVE521C_DUAL_CODE) || (c) == WAVE515_CODE; \ 2645d1a2b9SNas Chung }) 2745d1a2b9SNas Chung 2845d1a2b9SNas Chung #define WAVE517_WORKBUF_SIZE (2 * 1024 * 1024) 2945d1a2b9SNas Chung #define WAVE521ENC_WORKBUF_SIZE (128 * 1024) //HEVC 128K, AVC 40K 3045d1a2b9SNas Chung #define WAVE521DEC_WORKBUF_SIZE (1784 * 1024) 31*6aa08291SIvan Bornyakov #define WAVE515DEC_WORKBUF_SIZE (2 * 1024 * 1024) 3245d1a2b9SNas Chung 3345d1a2b9SNas Chung #define MAX_NUM_INSTANCE 32 3445d1a2b9SNas Chung 3545d1a2b9SNas Chung #define W5_MIN_ENC_PIC_WIDTH 256 3645d1a2b9SNas Chung #define W5_MIN_ENC_PIC_HEIGHT 128 3745d1a2b9SNas Chung #define W5_MAX_ENC_PIC_WIDTH 8192 3845d1a2b9SNas Chung #define W5_MAX_ENC_PIC_HEIGHT 8192 3945d1a2b9SNas Chung 4045d1a2b9SNas Chung // application specific configuration 4145d1a2b9SNas Chung #define VPU_ENC_TIMEOUT 60000 4245d1a2b9SNas Chung #define VPU_DEC_TIMEOUT 60000 4345d1a2b9SNas Chung 4445d1a2b9SNas Chung // for WAVE encoder 4545d1a2b9SNas Chung #define USE_SRC_PRP_AXI 0 4645d1a2b9SNas Chung #define USE_SRC_PRI_AXI 1 4745d1a2b9SNas Chung #define DEFAULT_SRC_AXI USE_SRC_PRP_AXI 4845d1a2b9SNas Chung 4945d1a2b9SNas Chung /************************************************************************/ 5045d1a2b9SNas Chung /* VPU COMMON MEMORY */ 5145d1a2b9SNas Chung /************************************************************************/ 5245d1a2b9SNas Chung #define VLC_BUF_NUM (2) 5345d1a2b9SNas Chung 54*6aa08291SIvan Bornyakov #define WAVE521_COMMAND_QUEUE_DEPTH (2) 55*6aa08291SIvan Bornyakov #define WAVE515_COMMAND_QUEUE_DEPTH (4) 5645d1a2b9SNas Chung 5745d1a2b9SNas Chung #define W5_REMAP_INDEX0 0 5845d1a2b9SNas Chung #define W5_REMAP_INDEX1 1 5945d1a2b9SNas Chung #define W5_REMAP_MAX_SIZE (1024 * 1024) 6045d1a2b9SNas Chung 61*6aa08291SIvan Bornyakov #define WAVE521_MAX_CODE_BUF_SIZE (2 * 1024 * 1024) 62*6aa08291SIvan Bornyakov #define WAVE515_MAX_CODE_BUF_SIZE (1024 * 1024) 6345d1a2b9SNas Chung #define WAVE5_TEMPBUF_SIZE (1024 * 1024) 6445d1a2b9SNas Chung 65*6aa08291SIvan Bornyakov #define WAVE521_SIZE_COMMON (WAVE521_MAX_CODE_BUF_SIZE + WAVE5_TEMPBUF_SIZE) 66*6aa08291SIvan Bornyakov #define WAVE515_ONE_TASKBUF_SIZE (8 * 1024 * 1024) 67*6aa08291SIvan Bornyakov #define WAVE515_SIZE_COMMON (WAVE515_MAX_CODE_BUF_SIZE + WAVE5_TEMPBUF_SIZE + \ 68*6aa08291SIvan Bornyakov WAVE515_COMMAND_QUEUE_DEPTH * WAVE515_ONE_TASKBUF_SIZE) 6945d1a2b9SNas Chung 7045d1a2b9SNas Chung //=====4. VPU REPORT MEMORY ======================// 7145d1a2b9SNas Chung 7245d1a2b9SNas Chung #define WAVE5_UPPER_PROC_AXI_ID 0x0 7345d1a2b9SNas Chung 7445d1a2b9SNas Chung #define WAVE5_PROC_AXI_ID 0x0 7545d1a2b9SNas Chung #define WAVE5_PRP_AXI_ID 0x0 7645d1a2b9SNas Chung #define WAVE5_FBD_Y_AXI_ID 0x0 7745d1a2b9SNas Chung #define WAVE5_FBC_Y_AXI_ID 0x0 7845d1a2b9SNas Chung #define WAVE5_FBD_C_AXI_ID 0x0 7945d1a2b9SNas Chung #define WAVE5_FBC_C_AXI_ID 0x0 8045d1a2b9SNas Chung #define WAVE5_SEC_AXI_ID 0x0 8145d1a2b9SNas Chung #define WAVE5_PRI_AXI_ID 0x0 8245d1a2b9SNas Chung 8345d1a2b9SNas Chung #endif /* _VPU_CONFIG_H_ */ 84