1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) 2 /* 3 * Wave5 series multi-standard codec IP - platform driver 4 * 5 * Copyright (C) 2021-2023 CHIPS&MEDIA INC 6 */ 7 #include <linux/kernel.h> 8 #include <linux/module.h> 9 #include <linux/platform_device.h> 10 #include <linux/clk.h> 11 #include <linux/firmware.h> 12 #include <linux/interrupt.h> 13 #include "wave5-vpu.h" 14 #include "wave5-regdefine.h" 15 #include "wave5-vpuconfig.h" 16 #include "wave5.h" 17 18 #define VPU_PLATFORM_DEVICE_NAME "vdec" 19 #define VPU_CLK_NAME "vcodec" 20 21 #define WAVE5_IS_ENC BIT(0) 22 #define WAVE5_IS_DEC BIT(1) 23 24 struct wave5_match_data { 25 int flags; 26 const char *fw_name; 27 }; 28 29 static int vpu_poll_interval = 5; 30 module_param(vpu_poll_interval, int, 0644); 31 32 int wave5_vpu_wait_interrupt(struct vpu_instance *inst, unsigned int timeout) 33 { 34 int ret; 35 36 ret = wait_for_completion_timeout(&inst->irq_done, 37 msecs_to_jiffies(timeout)); 38 if (!ret) 39 return -ETIMEDOUT; 40 41 reinit_completion(&inst->irq_done); 42 43 return 0; 44 } 45 46 static void wave5_vpu_handle_irq(void *dev_id) 47 { 48 u32 seq_done; 49 u32 cmd_done; 50 u32 irq_reason; 51 struct vpu_instance *inst; 52 struct vpu_device *dev = dev_id; 53 54 irq_reason = wave5_vdi_read_register(dev, W5_VPU_VINT_REASON); 55 wave5_vdi_write_register(dev, W5_VPU_VINT_REASON_CLR, irq_reason); 56 wave5_vdi_write_register(dev, W5_VPU_VINT_CLEAR, 0x1); 57 58 list_for_each_entry(inst, &dev->instances, list) { 59 seq_done = wave5_vdi_read_register(dev, W5_RET_SEQ_DONE_INSTANCE_INFO); 60 cmd_done = wave5_vdi_read_register(dev, W5_RET_QUEUE_CMD_DONE_INST); 61 62 if (irq_reason & BIT(INT_WAVE5_INIT_SEQ) || 63 irq_reason & BIT(INT_WAVE5_ENC_SET_PARAM)) { 64 if (seq_done & BIT(inst->id)) { 65 seq_done &= ~BIT(inst->id); 66 wave5_vdi_write_register(dev, W5_RET_SEQ_DONE_INSTANCE_INFO, 67 seq_done); 68 complete(&inst->irq_done); 69 } 70 } 71 72 if (irq_reason & BIT(INT_WAVE5_DEC_PIC) || 73 irq_reason & BIT(INT_WAVE5_ENC_PIC)) { 74 if (cmd_done & BIT(inst->id)) { 75 cmd_done &= ~BIT(inst->id); 76 wave5_vdi_write_register(dev, W5_RET_QUEUE_CMD_DONE_INST, 77 cmd_done); 78 inst->ops->finish_process(inst); 79 } 80 } 81 82 wave5_vpu_clear_interrupt(inst, irq_reason); 83 } 84 } 85 86 static irqreturn_t wave5_vpu_irq_thread(int irq, void *dev_id) 87 { 88 struct vpu_device *dev = dev_id; 89 90 if (wave5_vdi_read_register(dev, W5_VPU_VPU_INT_STS)) 91 wave5_vpu_handle_irq(dev); 92 93 return IRQ_HANDLED; 94 } 95 96 static void wave5_vpu_irq_work_fn(struct kthread_work *work) 97 { 98 struct vpu_device *dev = container_of(work, struct vpu_device, work); 99 100 if (wave5_vdi_read_register(dev, W5_VPU_VPU_INT_STS)) 101 wave5_vpu_handle_irq(dev); 102 } 103 104 static enum hrtimer_restart wave5_vpu_timer_callback(struct hrtimer *timer) 105 { 106 struct vpu_device *dev = 107 container_of(timer, struct vpu_device, hrtimer); 108 109 kthread_queue_work(dev->worker, &dev->work); 110 hrtimer_forward_now(timer, ns_to_ktime(vpu_poll_interval * NSEC_PER_MSEC)); 111 112 return HRTIMER_RESTART; 113 } 114 115 static int wave5_vpu_load_firmware(struct device *dev, const char *fw_name, 116 u32 *revision) 117 { 118 const struct firmware *fw; 119 int ret; 120 unsigned int product_id; 121 122 ret = request_firmware(&fw, fw_name, dev); 123 if (ret) { 124 dev_err(dev, "request_firmware, fail: %d\n", ret); 125 return ret; 126 } 127 128 ret = wave5_vpu_init_with_bitcode(dev, (u8 *)fw->data, fw->size); 129 if (ret) { 130 dev_err(dev, "vpu_init_with_bitcode, fail: %d\n", ret); 131 release_firmware(fw); 132 return ret; 133 } 134 release_firmware(fw); 135 136 ret = wave5_vpu_get_version_info(dev, revision, &product_id); 137 if (ret) { 138 dev_err(dev, "vpu_get_version_info fail: %d\n", ret); 139 return ret; 140 } 141 142 dev_dbg(dev, "%s: enum product_id: %08x, fw revision: %u\n", 143 __func__, product_id, *revision); 144 145 return 0; 146 } 147 148 static int wave5_vpu_probe(struct platform_device *pdev) 149 { 150 int ret; 151 struct vpu_device *dev; 152 const struct wave5_match_data *match_data; 153 u32 fw_revision; 154 155 match_data = device_get_match_data(&pdev->dev); 156 if (!match_data) { 157 dev_err(&pdev->dev, "missing device match data\n"); 158 return -EINVAL; 159 } 160 161 /* physical addresses limited to 32 bits */ 162 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 163 if (ret) { 164 dev_err(&pdev->dev, "Failed to set DMA mask: %d\n", ret); 165 return ret; 166 } 167 168 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); 169 if (!dev) 170 return -ENOMEM; 171 172 dev->vdb_register = devm_platform_ioremap_resource(pdev, 0); 173 if (IS_ERR(dev->vdb_register)) 174 return PTR_ERR(dev->vdb_register); 175 ida_init(&dev->inst_ida); 176 177 mutex_init(&dev->dev_lock); 178 mutex_init(&dev->hw_lock); 179 dev_set_drvdata(&pdev->dev, dev); 180 dev->dev = &pdev->dev; 181 182 ret = devm_clk_bulk_get_all(&pdev->dev, &dev->clks); 183 184 /* continue without clock, assume externally managed */ 185 if (ret < 0) { 186 dev_warn(&pdev->dev, "Getting clocks, fail: %d\n", ret); 187 ret = 0; 188 } 189 dev->num_clks = ret; 190 191 ret = clk_bulk_prepare_enable(dev->num_clks, dev->clks); 192 if (ret) { 193 dev_err(&pdev->dev, "Enabling clocks, fail: %d\n", ret); 194 return ret; 195 } 196 197 ret = of_property_read_u32(pdev->dev.of_node, "sram-size", 198 &dev->sram_size); 199 if (ret) { 200 dev_warn(&pdev->dev, "sram-size not found\n"); 201 dev->sram_size = 0; 202 } 203 204 dev->sram_pool = of_gen_pool_get(pdev->dev.of_node, "sram", 0); 205 if (!dev->sram_pool) 206 dev_warn(&pdev->dev, "sram node not found\n"); 207 208 dev->product_code = wave5_vdi_read_register(dev, VPU_PRODUCT_CODE_REGISTER); 209 ret = wave5_vdi_init(&pdev->dev); 210 if (ret < 0) { 211 dev_err(&pdev->dev, "wave5_vdi_init, fail: %d\n", ret); 212 goto err_clk_dis; 213 } 214 dev->product = wave5_vpu_get_product_id(dev); 215 216 dev->irq = platform_get_irq(pdev, 0); 217 if (dev->irq < 0) { 218 dev_err(&pdev->dev, "failed to get irq resource, falling back to polling\n"); 219 hrtimer_init(&dev->hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL_PINNED); 220 dev->hrtimer.function = &wave5_vpu_timer_callback; 221 dev->worker = kthread_create_worker(0, "vpu_irq_thread"); 222 if (IS_ERR(dev->worker)) { 223 dev_err(&pdev->dev, "failed to create vpu irq worker\n"); 224 ret = PTR_ERR(dev->worker); 225 goto err_vdi_release; 226 } 227 dev->vpu_poll_interval = vpu_poll_interval; 228 kthread_init_work(&dev->work, wave5_vpu_irq_work_fn); 229 } else { 230 ret = devm_request_threaded_irq(&pdev->dev, dev->irq, NULL, 231 wave5_vpu_irq_thread, IRQF_ONESHOT, "vpu_irq", dev); 232 if (ret) { 233 dev_err(&pdev->dev, "Register interrupt handler, fail: %d\n", ret); 234 goto err_enc_unreg; 235 } 236 } 237 238 INIT_LIST_HEAD(&dev->instances); 239 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev); 240 if (ret) { 241 dev_err(&pdev->dev, "v4l2_device_register, fail: %d\n", ret); 242 goto err_vdi_release; 243 } 244 245 if (match_data->flags & WAVE5_IS_DEC) { 246 ret = wave5_vpu_dec_register_device(dev); 247 if (ret) { 248 dev_err(&pdev->dev, "wave5_vpu_dec_register_device, fail: %d\n", ret); 249 goto err_v4l2_unregister; 250 } 251 } 252 if (match_data->flags & WAVE5_IS_ENC) { 253 ret = wave5_vpu_enc_register_device(dev); 254 if (ret) { 255 dev_err(&pdev->dev, "wave5_vpu_enc_register_device, fail: %d\n", ret); 256 goto err_dec_unreg; 257 } 258 } 259 260 ret = wave5_vpu_load_firmware(&pdev->dev, match_data->fw_name, &fw_revision); 261 if (ret) { 262 dev_err(&pdev->dev, "wave5_vpu_load_firmware, fail: %d\n", ret); 263 goto err_enc_unreg; 264 } 265 266 dev_info(&pdev->dev, "Added wave5 driver with caps: %s %s\n", 267 (match_data->flags & WAVE5_IS_ENC) ? "'ENCODE'" : "", 268 (match_data->flags & WAVE5_IS_DEC) ? "'DECODE'" : ""); 269 dev_info(&pdev->dev, "Product Code: 0x%x\n", dev->product_code); 270 dev_info(&pdev->dev, "Firmware Revision: %u\n", fw_revision); 271 return 0; 272 273 err_enc_unreg: 274 if (match_data->flags & WAVE5_IS_ENC) 275 wave5_vpu_enc_unregister_device(dev); 276 err_dec_unreg: 277 if (match_data->flags & WAVE5_IS_DEC) 278 wave5_vpu_dec_unregister_device(dev); 279 err_v4l2_unregister: 280 v4l2_device_unregister(&dev->v4l2_dev); 281 err_vdi_release: 282 wave5_vdi_release(&pdev->dev); 283 err_clk_dis: 284 clk_bulk_disable_unprepare(dev->num_clks, dev->clks); 285 286 return ret; 287 } 288 289 static void wave5_vpu_remove(struct platform_device *pdev) 290 { 291 struct vpu_device *dev = dev_get_drvdata(&pdev->dev); 292 293 if (dev->irq < 0) { 294 kthread_destroy_worker(dev->worker); 295 hrtimer_cancel(&dev->hrtimer); 296 } 297 298 mutex_destroy(&dev->dev_lock); 299 mutex_destroy(&dev->hw_lock); 300 clk_bulk_disable_unprepare(dev->num_clks, dev->clks); 301 wave5_vpu_enc_unregister_device(dev); 302 wave5_vpu_dec_unregister_device(dev); 303 v4l2_device_unregister(&dev->v4l2_dev); 304 wave5_vdi_release(&pdev->dev); 305 ida_destroy(&dev->inst_ida); 306 } 307 308 static const struct wave5_match_data ti_wave521c_data = { 309 .flags = WAVE5_IS_ENC | WAVE5_IS_DEC, 310 .fw_name = "cnm/wave521c_k3_codec_fw.bin", 311 }; 312 313 static const struct of_device_id wave5_dt_ids[] = { 314 { .compatible = "ti,j721s2-wave521c", .data = &ti_wave521c_data }, 315 { /* sentinel */ } 316 }; 317 MODULE_DEVICE_TABLE(of, wave5_dt_ids); 318 319 static struct platform_driver wave5_vpu_driver = { 320 .driver = { 321 .name = VPU_PLATFORM_DEVICE_NAME, 322 .of_match_table = of_match_ptr(wave5_dt_ids), 323 }, 324 .probe = wave5_vpu_probe, 325 .remove_new = wave5_vpu_remove, 326 }; 327 328 module_platform_driver(wave5_vpu_driver); 329 MODULE_DESCRIPTION("chips&media VPU V4L2 driver"); 330 MODULE_LICENSE("Dual BSD/GPL"); 331