1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ 2 /* 3 * Wave5 series multi-standard codec IP - wave5 register definitions 4 * 5 * Copyright (C) 2021-2023 CHIPS&MEDIA INC 6 */ 7 8 #ifndef __WAVE5_REGISTER_DEFINE_H__ 9 #define __WAVE5_REGISTER_DEFINE_H__ 10 11 enum W5_VPU_COMMAND { 12 W5_INIT_VPU = 0x0001, 13 W5_WAKEUP_VPU = 0x0002, 14 W5_SLEEP_VPU = 0x0004, 15 W5_CREATE_INSTANCE = 0x0008, /* queuing command */ 16 W5_FLUSH_INSTANCE = 0x0010, 17 W5_DESTROY_INSTANCE = 0x0020, /* queuing command */ 18 W5_INIT_SEQ = 0x0040, /* queuing command */ 19 W5_SET_FB = 0x0080, 20 W5_DEC_ENC_PIC = 0x0100, /* queuing command */ 21 W5_ENC_SET_PARAM = 0x0200, /* queuing command */ 22 W5_QUERY = 0x4000, 23 W5_UPDATE_BS = 0x8000, 24 W5_MAX_VPU_COMD = 0x10000, 25 }; 26 27 enum query_opt { 28 GET_VPU_INFO = 0, 29 SET_WRITE_PROT = 1, 30 GET_RESULT = 2, 31 UPDATE_DISP_FLAG = 3, 32 GET_BW_REPORT = 4, 33 GET_BS_RD_PTR = 5, /* for decoder */ 34 GET_BS_WR_PTR = 6, /* for encoder */ 35 GET_SRC_BUF_FLAG = 7, /* for encoder */ 36 SET_BS_RD_PTR = 8, /* for decoder */ 37 GET_DEBUG_INFO = 0x61, 38 }; 39 40 #define W5_REG_BASE 0x00000000 41 #define W5_CMD_REG_BASE 0x00000100 42 #define W5_CMD_REG_END 0x00000200 43 44 /* 45 * COMMON 46 * 47 * ---- 48 * 49 * Power on configuration 50 * PO_DEBUG_MODE [0] 1 - power on with debug mode 51 * USE_PO_CONF [3] 1 - use power-on-configuration 52 */ 53 #define W5_PO_CONF (W5_REG_BASE + 0x0000) 54 #define W5_VCPU_CUR_PC (W5_REG_BASE + 0x0004) 55 #define W5_VCPU_CUR_LR (W5_REG_BASE + 0x0008) 56 #define W5_VPU_PDBG_STEP_MASK_V (W5_REG_BASE + 0x000C) 57 #define W5_VPU_PDBG_CTRL (W5_REG_BASE + 0x0010) /* v_cpu debugger ctrl register */ 58 #define W5_VPU_PDBG_IDX_REG (W5_REG_BASE + 0x0014) /* v_cpu debugger index register */ 59 #define W5_VPU_PDBG_WDATA_REG (W5_REG_BASE + 0x0018) /* v_cpu debugger write data reg */ 60 #define W5_VPU_PDBG_RDATA_REG (W5_REG_BASE + 0x001C) /* v_cpu debugger read data reg */ 61 62 #define W5_VPU_FIO_CTRL_ADDR (W5_REG_BASE + 0x0020) 63 #define W5_VPU_FIO_DATA (W5_REG_BASE + 0x0024) 64 #define W5_VPU_VINT_REASON_USR (W5_REG_BASE + 0x0030) 65 #define W5_VPU_VINT_REASON_CLR (W5_REG_BASE + 0x0034) 66 #define W5_VPU_HOST_INT_REQ (W5_REG_BASE + 0x0038) 67 #define W5_VPU_VINT_CLEAR (W5_REG_BASE + 0x003C) 68 #define W5_VPU_HINT_CLEAR (W5_REG_BASE + 0x0040) 69 #define W5_VPU_VPU_INT_STS (W5_REG_BASE + 0x0044) 70 #define W5_VPU_VINT_ENABLE (W5_REG_BASE + 0x0048) 71 #define W5_VPU_VINT_REASON (W5_REG_BASE + 0x004C) 72 #define W5_VPU_RESET_REQ (W5_REG_BASE + 0x0050) 73 #define W5_RST_BLOCK_CCLK(_core) BIT((_core)) 74 #define W5_RST_BLOCK_CCLK_ALL (0xff) 75 #define W5_RST_BLOCK_BCLK(_core) (0x100 << (_core)) 76 #define W5_RST_BLOCK_BCLK_ALL (0xff00) 77 #define W5_RST_BLOCK_ACLK(_core) (0x10000 << (_core)) 78 #define W5_RST_BLOCK_ACLK_ALL (0xff0000) 79 #define W5_RST_BLOCK_VCPU_ALL (0x3f000000) 80 #define W5_RST_BLOCK_ALL (0x3fffffff) 81 #define W5_VPU_RESET_STATUS (W5_REG_BASE + 0x0054) 82 83 #define W5_VCPU_RESTART (W5_REG_BASE + 0x0058) 84 #define W5_VPU_CLK_MASK (W5_REG_BASE + 0x005C) 85 86 /* REMAP_CTRL 87 * PAGE SIZE: [8:0] 0x001 - 4K 88 * 0x002 - 8K 89 * 0x004 - 16K 90 * ... 91 * 0x100 - 1M 92 * REGION ATTR1 [10] 0 - normal 93 * 1 - make bus error for the region 94 * REGION ATTR2 [11] 0 - normal 95 * 1 - bypass region 96 * REMAP INDEX [15:12] - 0 ~ 3 97 * ENDIAN [19:16] - NOTE: Currently not supported in this driver 98 * AXI-ID [23:20] - upper AXI-ID 99 * BUS_ERROR [29] 0 - bypass 100 * 1 - make BUS_ERROR for unmapped region 101 * BYPASS_ALL [30] 1 - bypass all 102 * ENABLE [31] 1 - update control register[30:16] 103 */ 104 #define W5_VPU_REMAP_CTRL (W5_REG_BASE + 0x0060) 105 #define W5_VPU_REMAP_VADDR (W5_REG_BASE + 0x0064) 106 #define W5_VPU_REMAP_PADDR (W5_REG_BASE + 0x0068) 107 #define W5_VPU_REMAP_CORE_START (W5_REG_BASE + 0x006C) 108 #define W5_VPU_BUSY_STATUS (W5_REG_BASE + 0x0070) 109 #define W5_VPU_HALT_STATUS (W5_REG_BASE + 0x0074) 110 #define W5_VPU_VCPU_STATUS (W5_REG_BASE + 0x0078) 111 #define W5_VPU_RET_PRODUCT_VERSION (W5_REG_BASE + 0x0094) 112 /* 113 * assign vpu_config0 = {conf_map_converter_reg, // [31] 114 * conf_map_converter_sig, // [30] 115 * 8'd0, // [29:22] 116 * conf_std_switch_en, // [21] 117 * conf_bg_detect, // [20] 118 * conf_3dnr_en, // [19] 119 * conf_one_axi_en, // [18] 120 * conf_sec_axi_en, // [17] 121 * conf_bus_info, // [16] 122 * conf_afbc_en, // [15] 123 * conf_afbc_version_id, // [14:12] 124 * conf_fbc_en, // [11] 125 * conf_fbc_version_id, // [10:08] 126 * conf_scaler_en, // [07] 127 * conf_scaler_version_id, // [06:04] 128 * conf_bwb_en, // [03] 129 * 3'd0}; // [02:00] 130 */ 131 #define W5_VPU_RET_VPU_CONFIG0 (W5_REG_BASE + 0x0098) 132 /* 133 * assign vpu_config1 = {4'd0, // [31:28] 134 * conf_perf_timer_en, // [27] 135 * conf_multi_core_en, // [26] 136 * conf_gcu_en, // [25] 137 * conf_cu_report, // [24] 138 * 4'd0, // [23:20] 139 * conf_vcore_id_3, // [19] 140 * conf_vcore_id_2, // [18] 141 * conf_vcore_id_1, // [17] 142 * conf_vcore_id_0, // [16] 143 * conf_bwb_opt, // [15] 144 * 7'd0, // [14:08] 145 * conf_cod_std_en_reserved_7, // [7] 146 * conf_cod_std_en_reserved_6, // [6] 147 * conf_cod_std_en_reserved_5, // [5] 148 * conf_cod_std_en_reserved_4, // [4] 149 * conf_cod_std_en_reserved_3, // [3] 150 * conf_cod_std_en_reserved_2, // [2] 151 * conf_cod_std_en_vp9, // [1] 152 * conf_cod_std_en_hevc}; // [0] 153 * } 154 */ 155 #define W5_VPU_RET_VPU_CONFIG1 (W5_REG_BASE + 0x009C) 156 157 #define W5_VPU_DBG_REG0 (W5_REG_BASE + 0x00f0) 158 #define W5_VPU_DBG_REG1 (W5_REG_BASE + 0x00f4) 159 #define W5_VPU_DBG_REG2 (W5_REG_BASE + 0x00f8) 160 #define W5_VPU_DBG_REG3 (W5_REG_BASE + 0x00fc) 161 162 /************************************************************************/ 163 /* PRODUCT INFORMATION */ 164 /************************************************************************/ 165 #define W5_PRODUCT_NAME (W5_REG_BASE + 0x1040) 166 #define W5_PRODUCT_NUMBER (W5_REG_BASE + 0x1044) 167 168 /************************************************************************/ 169 /* DECODER/ENCODER COMMON */ 170 /************************************************************************/ 171 #define W5_COMMAND (W5_REG_BASE + 0x0100) 172 #define W5_COMMAND_OPTION (W5_REG_BASE + 0x0104) 173 #define W5_QUERY_OPTION (W5_REG_BASE + 0x0104) 174 #define W5_RET_SUCCESS (W5_REG_BASE + 0x0108) 175 #define W5_RET_FAIL_REASON (W5_REG_BASE + 0x010C) 176 #define W5_RET_QUEUE_FAIL_REASON (W5_REG_BASE + 0x0110) 177 #define W5_CMD_INSTANCE_INFO (W5_REG_BASE + 0x0110) 178 179 #define W5_RET_QUEUE_STATUS (W5_REG_BASE + 0x01E0) 180 #define W5_RET_BS_EMPTY_INST (W5_REG_BASE + 0x01E4) 181 #define W5_RET_QUEUE_CMD_DONE_INST (W5_REG_BASE + 0x01E8) 182 #define W5_RET_STAGE0_INSTANCE_INFO (W5_REG_BASE + 0x01EC) 183 #define W5_RET_STAGE1_INSTANCE_INFO (W5_REG_BASE + 0x01F0) 184 #define W5_RET_STAGE2_INSTANCE_INFO (W5_REG_BASE + 0x01F4) 185 186 #define W5_RET_SEQ_DONE_INSTANCE_INFO (W5_REG_BASE + 0x01FC) 187 188 #define W5_BS_OPTION (W5_REG_BASE + 0x0120) 189 190 /* return info when QUERY (GET_RESULT) for en/decoder */ 191 #define W5_RET_VLC_BUF_SIZE (W5_REG_BASE + 0x01B0) 192 /* return info when QUERY (GET_RESULT) for en/decoder */ 193 #define W5_RET_PARAM_BUF_SIZE (W5_REG_BASE + 0x01B4) 194 195 /* set when SET_FB for en/decoder */ 196 #define W5_CMD_SET_FB_ADDR_TASK_BUF (W5_REG_BASE + 0x01D4) 197 #define W5_CMD_SET_FB_TASK_BUF_SIZE (W5_REG_BASE + 0x01D8) 198 /************************************************************************/ 199 /* INIT_VPU - COMMON */ 200 /************************************************************************/ 201 /* note: W5_ADDR_CODE_BASE should be aligned to 4KB */ 202 #define W5_ADDR_CODE_BASE (W5_REG_BASE + 0x0110) 203 #define W5_CODE_SIZE (W5_REG_BASE + 0x0114) 204 #define W5_CODE_PARAM (W5_REG_BASE + 0x0118) 205 #define W5_ADDR_TEMP_BASE (W5_REG_BASE + 0x011C) 206 #define W5_TEMP_SIZE (W5_REG_BASE + 0x0120) 207 #define W5_HW_OPTION (W5_REG_BASE + 0x012C) 208 #define W5_SEC_AXI_PARAM (W5_REG_BASE + 0x0180) 209 210 /************************************************************************/ 211 /* CREATE_INSTANCE - COMMON */ 212 /************************************************************************/ 213 #define W5_ADDR_WORK_BASE (W5_REG_BASE + 0x0114) 214 #define W5_WORK_SIZE (W5_REG_BASE + 0x0118) 215 #define W5_CMD_DEC_BS_START_ADDR (W5_REG_BASE + 0x011C) 216 #define W5_CMD_DEC_BS_SIZE (W5_REG_BASE + 0x0120) 217 #define W5_CMD_BS_PARAM (W5_REG_BASE + 0x0124) 218 #define W5_CMD_ADDR_SEC_AXI (W5_REG_BASE + 0x0130) 219 #define W5_CMD_SEC_AXI_SIZE (W5_REG_BASE + 0x0134) 220 #define W5_CMD_EXT_ADDR (W5_REG_BASE + 0x0138) 221 #define W5_CMD_NUM_CQ_DEPTH_M1 (W5_REG_BASE + 0x013C) 222 #define W5_CMD_ERR_CONCEAL (W5_REG_BASE + 0x0140) 223 224 /************************************************************************/ 225 /* DECODER - INIT_SEQ */ 226 /************************************************************************/ 227 #define W5_BS_RD_PTR (W5_REG_BASE + 0x0118) 228 #define W5_BS_WR_PTR (W5_REG_BASE + 0x011C) 229 /************************************************************************/ 230 /* SET_FRAME_BUF */ 231 /************************************************************************/ 232 /* SET_FB_OPTION 0x00 REGISTER FRAMEBUFFERS 233 * 0x01 UPDATE FRAMEBUFFER, just one framebuffer(linear, fbc and mvcol) 234 */ 235 #define W5_SFB_OPTION (W5_REG_BASE + 0x0104) 236 #define W5_COMMON_PIC_INFO (W5_REG_BASE + 0x0118) 237 #define W5_PIC_SIZE (W5_REG_BASE + 0x011C) 238 #define W5_SET_FB_NUM (W5_REG_BASE + 0x0120) 239 #define W5_EXTRA_PIC_INFO (W5_REG_BASE + 0x0124) 240 241 #define W5_ADDR_LUMA_BASE0 (W5_REG_BASE + 0x0134) 242 #define W5_ADDR_CB_BASE0 (W5_REG_BASE + 0x0138) 243 #define W5_ADDR_CR_BASE0 (W5_REG_BASE + 0x013C) 244 /* compression offset table for luma */ 245 #define W5_ADDR_FBC_Y_OFFSET0 (W5_REG_BASE + 0x013C) 246 /* compression offset table for chroma */ 247 #define W5_ADDR_FBC_C_OFFSET0 (W5_REG_BASE + 0x0140) 248 #define W5_ADDR_LUMA_BASE1 (W5_REG_BASE + 0x0144) 249 #define W5_ADDR_CB_ADDR1 (W5_REG_BASE + 0x0148) 250 #define W5_ADDR_CR_ADDR1 (W5_REG_BASE + 0x014C) 251 /* compression offset table for luma */ 252 #define W5_ADDR_FBC_Y_OFFSET1 (W5_REG_BASE + 0x014C) 253 /* compression offset table for chroma */ 254 #define W5_ADDR_FBC_C_OFFSET1 (W5_REG_BASE + 0x0150) 255 #define W5_ADDR_LUMA_BASE2 (W5_REG_BASE + 0x0154) 256 #define W5_ADDR_CB_ADDR2 (W5_REG_BASE + 0x0158) 257 #define W5_ADDR_CR_ADDR2 (W5_REG_BASE + 0x015C) 258 /* compression offset table for luma */ 259 #define W5_ADDR_FBC_Y_OFFSET2 (W5_REG_BASE + 0x015C) 260 /* compression offset table for chroma */ 261 #define W5_ADDR_FBC_C_OFFSET2 (W5_REG_BASE + 0x0160) 262 #define W5_ADDR_LUMA_BASE3 (W5_REG_BASE + 0x0164) 263 #define W5_ADDR_CB_ADDR3 (W5_REG_BASE + 0x0168) 264 #define W5_ADDR_CR_ADDR3 (W5_REG_BASE + 0x016C) 265 /* compression offset table for luma */ 266 #define W5_ADDR_FBC_Y_OFFSET3 (W5_REG_BASE + 0x016C) 267 /* compression offset table for chroma */ 268 #define W5_ADDR_FBC_C_OFFSET3 (W5_REG_BASE + 0x0170) 269 #define W5_ADDR_LUMA_BASE4 (W5_REG_BASE + 0x0174) 270 #define W5_ADDR_CB_ADDR4 (W5_REG_BASE + 0x0178) 271 #define W5_ADDR_CR_ADDR4 (W5_REG_BASE + 0x017C) 272 /* compression offset table for luma */ 273 #define W5_ADDR_FBC_Y_OFFSET4 (W5_REG_BASE + 0x017C) 274 /* compression offset table for chroma */ 275 #define W5_ADDR_FBC_C_OFFSET4 (W5_REG_BASE + 0x0180) 276 #define W5_ADDR_LUMA_BASE5 (W5_REG_BASE + 0x0184) 277 #define W5_ADDR_CB_ADDR5 (W5_REG_BASE + 0x0188) 278 #define W5_ADDR_CR_ADDR5 (W5_REG_BASE + 0x018C) 279 /* compression offset table for luma */ 280 #define W5_ADDR_FBC_Y_OFFSET5 (W5_REG_BASE + 0x018C) 281 /* compression offset table for chroma */ 282 #define W5_ADDR_FBC_C_OFFSET5 (W5_REG_BASE + 0x0190) 283 #define W5_ADDR_LUMA_BASE6 (W5_REG_BASE + 0x0194) 284 #define W5_ADDR_CB_ADDR6 (W5_REG_BASE + 0x0198) 285 #define W5_ADDR_CR_ADDR6 (W5_REG_BASE + 0x019C) 286 /* compression offset table for luma */ 287 #define W5_ADDR_FBC_Y_OFFSET6 (W5_REG_BASE + 0x019C) 288 /* compression offset table for chroma */ 289 #define W5_ADDR_FBC_C_OFFSET6 (W5_REG_BASE + 0x01A0) 290 #define W5_ADDR_LUMA_BASE7 (W5_REG_BASE + 0x01A4) 291 #define W5_ADDR_CB_ADDR7 (W5_REG_BASE + 0x01A8) 292 #define W5_ADDR_CR_ADDR7 (W5_REG_BASE + 0x01AC) 293 /* compression offset table for luma */ 294 #define W5_ADDR_FBC_Y_OFFSET7 (W5_REG_BASE + 0x01AC) 295 /* compression offset table for chroma */ 296 #define W5_ADDR_FBC_C_OFFSET7 (W5_REG_BASE + 0x01B0) 297 #define W5_ADDR_MV_COL0 (W5_REG_BASE + 0x01B4) 298 #define W5_ADDR_MV_COL1 (W5_REG_BASE + 0x01B8) 299 #define W5_ADDR_MV_COL2 (W5_REG_BASE + 0x01BC) 300 #define W5_ADDR_MV_COL3 (W5_REG_BASE + 0x01C0) 301 #define W5_ADDR_MV_COL4 (W5_REG_BASE + 0x01C4) 302 #define W5_ADDR_MV_COL5 (W5_REG_BASE + 0x01C8) 303 #define W5_ADDR_MV_COL6 (W5_REG_BASE + 0x01CC) 304 #define W5_ADDR_MV_COL7 (W5_REG_BASE + 0x01D0) 305 306 /* UPDATE_FB */ 307 /* CMD_SET_FB_STRIDE [15:0] - FBC framebuffer stride 308 * [31:15] - linear framebuffer stride 309 */ 310 #define W5_CMD_SET_FB_STRIDE (W5_REG_BASE + 0x0118) 311 #define W5_CMD_SET_FB_INDEX (W5_REG_BASE + 0x0120) 312 #define W5_ADDR_LUMA_BASE (W5_REG_BASE + 0x0134) 313 #define W5_ADDR_CB_BASE (W5_REG_BASE + 0x0138) 314 #define W5_ADDR_CR_BASE (W5_REG_BASE + 0x013C) 315 #define W5_ADDR_MV_COL (W5_REG_BASE + 0x0140) 316 #define W5_ADDR_FBC_Y_BASE (W5_REG_BASE + 0x0144) 317 #define W5_ADDR_FBC_C_BASE (W5_REG_BASE + 0x0148) 318 #define W5_ADDR_FBC_Y_OFFSET (W5_REG_BASE + 0x014C) 319 #define W5_ADDR_FBC_C_OFFSET (W5_REG_BASE + 0x0150) 320 321 /************************************************************************/ 322 /* DECODER - DEC_PIC */ 323 /************************************************************************/ 324 #define W5_CMD_DEC_VCORE_INFO (W5_REG_BASE + 0x0194) 325 /* sequence change enable mask register 326 * CMD_SEQ_CHANGE_ENABLE_FLAG [5] profile_idc 327 * [16] pic_width/height_in_luma_sample 328 * [19] sps_max_dec_pic_buffering, max_num_reorder, max_latency_increase 329 */ 330 #define W5_CMD_SEQ_CHANGE_ENABLE_FLAG (W5_REG_BASE + 0x0128) 331 #define W5_CMD_DEC_USER_MASK (W5_REG_BASE + 0x012C) 332 #define W5_CMD_DEC_TEMPORAL_ID_PLUS1 (W5_REG_BASE + 0x0130) 333 #define W5_CMD_DEC_FORCE_FB_LATENCY_PLUS1 (W5_REG_BASE + 0x0134) 334 #define W5_USE_SEC_AXI (W5_REG_BASE + 0x0150) 335 336 /************************************************************************/ 337 /* DECODER - QUERY : GET_VPU_INFO */ 338 /************************************************************************/ 339 #define W5_RET_FW_VERSION (W5_REG_BASE + 0x0118) 340 #define W5_RET_PRODUCT_NAME (W5_REG_BASE + 0x011C) 341 #define W5_RET_PRODUCT_VERSION (W5_REG_BASE + 0x0120) 342 #define W5_RET_STD_DEF0 (W5_REG_BASE + 0x0124) 343 #define W5_RET_STD_DEF1 (W5_REG_BASE + 0x0128) 344 #define W5_RET_CONF_FEATURE (W5_REG_BASE + 0x012C) 345 #define W5_RET_CONF_DATE (W5_REG_BASE + 0x0130) 346 #define W5_RET_CONF_REVISION (W5_REG_BASE + 0x0134) 347 #define W5_RET_CONF_TYPE (W5_REG_BASE + 0x0138) 348 #define W5_RET_PRODUCT_ID (W5_REG_BASE + 0x013C) 349 #define W5_RET_CUSTOMER_ID (W5_REG_BASE + 0x0140) 350 351 /************************************************************************/ 352 /* DECODER - QUERY : GET_RESULT */ 353 /************************************************************************/ 354 #define W5_CMD_DEC_ADDR_REPORT_BASE (W5_REG_BASE + 0x0114) 355 #define W5_CMD_DEC_REPORT_SIZE (W5_REG_BASE + 0x0118) 356 #define W5_CMD_DEC_REPORT_PARAM (W5_REG_BASE + 0x011C) 357 358 #define W5_RET_DEC_BS_RD_PTR (W5_REG_BASE + 0x011C) 359 #define W5_RET_DEC_SEQ_PARAM (W5_REG_BASE + 0x0120) 360 #define W5_RET_DEC_COLOR_SAMPLE_INFO (W5_REG_BASE + 0x0124) 361 #define W5_RET_DEC_ASPECT_RATIO (W5_REG_BASE + 0x0128) 362 #define W5_RET_DEC_BIT_RATE (W5_REG_BASE + 0x012C) 363 #define W5_RET_DEC_FRAME_RATE_NR (W5_REG_BASE + 0x0130) 364 #define W5_RET_DEC_FRAME_RATE_DR (W5_REG_BASE + 0x0134) 365 #define W5_RET_DEC_NUM_REQUIRED_FB (W5_REG_BASE + 0x0138) 366 #define W5_RET_DEC_NUM_REORDER_DELAY (W5_REG_BASE + 0x013C) 367 #define W5_RET_DEC_SUB_LAYER_INFO (W5_REG_BASE + 0x0140) 368 #define W5_RET_DEC_NOTIFICATION (W5_REG_BASE + 0x0144) 369 /* 370 * USER_DATA_FLAGS for HEVC/H264 only. 371 * Bits: 372 * [1] - User data buffer full boolean 373 * [2] - VUI parameter flag 374 * [4] - Pic_timing SEI flag 375 * [5] - 1st user_data_registed_itu_t_t35 prefix SEI flag 376 * [6] - user_data_unregistered prefix SEI flag 377 * [7] - 1st user_data_registed_itu_t_t35 suffix SEI flag 378 * [8] - user_data_unregistered suffix SEI flag 379 * [10]- mastering_display_color_volume prefix SEI flag 380 * [11]- chroma_resampling_display_color_volume prefix SEI flag 381 * [12]- knee_function_info SEI flag 382 * [13]- tone_mapping_info prefix SEI flag 383 * [14]- film_grain_characteristics_info prefix SEI flag 384 * [15]- content_light_level_info prefix SEI flag 385 * [16]- color_remapping_info prefix SEI flag 386 * [28]- 2nd user_data_registed_itu_t_t35 prefix SEI flag 387 * [29]- 3rd user_data_registed_itu_t_t35 prefix SEI flag 388 * [30]- 2nd user_data_registed_itu_t_t35 suffix SEI flag 389 * [31]- 3rd user_data_registed_itu_t_t35 suffix SEI flag 390 */ 391 #define W5_RET_DEC_USERDATA_IDC (W5_REG_BASE + 0x0148) 392 #define W5_RET_DEC_PIC_SIZE (W5_REG_BASE + 0x014C) 393 #define W5_RET_DEC_CROP_TOP_BOTTOM (W5_REG_BASE + 0x0150) 394 #define W5_RET_DEC_CROP_LEFT_RIGHT (W5_REG_BASE + 0x0154) 395 /* 396 * #define W5_RET_DEC_AU_START_POS (W5_REG_BASE + 0x0158) 397 * => Access unit (AU) Bitstream start position 398 * #define W5_RET_DEC_AU_END_POS (W5_REG_BASE + 0x015C) 399 * => Access unit (AU) Bitstream end position 400 */ 401 402 /* 403 * Decoded picture type: 404 * reg_val & 0x7 => picture type 405 * (reg_val >> 4) & 0x3f => VCL NAL unit type 406 * (reg_val >> 31) & 0x1 => output_flag 407 * 16 << ((reg_val >> 10) & 0x3) => ctu_size 408 */ 409 #define W5_RET_DEC_PIC_TYPE (W5_REG_BASE + 0x0160) 410 #define W5_RET_DEC_PIC_POC (W5_REG_BASE + 0x0164) 411 /* 412 * #define W5_RET_DEC_RECOVERY_POINT (W5_REG_BASE + 0x0168) 413 * => HEVC recovery point 414 * reg_val & 0xff => number of signed recovery picture order counts 415 * (reg_val >> 16) & 0x1 => exact match flag 416 * (reg_val >> 17) & 0x1 => broken link flag 417 * (reg_val >> 18) & 0x1 => exist flag 418 */ 419 #define W5_RET_DEC_DEBUG_INDEX (W5_REG_BASE + 0x016C) 420 #define W5_RET_DEC_DECODED_INDEX (W5_REG_BASE + 0x0170) 421 #define W5_RET_DEC_DISPLAY_INDEX (W5_REG_BASE + 0x0174) 422 /* 423 * #define W5_RET_DEC_REALLOC_INDEX (W5_REG_BASE + 0x0178) 424 * => display picture index in decoded picture buffer 425 * reg_val & 0xf => display picture index for FBC buffer (by reordering) 426 */ 427 #define W5_RET_DEC_DISP_IDC (W5_REG_BASE + 0x017C) 428 /* 429 * #define W5_RET_DEC_ERR_CTB_NUM (W5_REG_BASE + 0x0180) 430 * => Number of error CTUs 431 * reg_val >> 16 => erroneous CTUs in bitstream 432 * reg_val & 0xffff => total CTUs in bitstream 433 * 434 * #define W5_RET_DEC_PIC_PARAM (W5_REG_BASE + 0x01A0) 435 * => Bitstream sequence/picture parameter information (AV1 only) 436 * reg_val & 0x1 => intrabc tool enable 437 * (reg_val >> 1) & 0x1 => screen content tools enable 438 */ 439 #define W5_RET_DEC_HOST_CMD_TICK (W5_REG_BASE + 0x01B8) 440 /* 441 * #define W5_RET_DEC_SEEK_START_TICK (W5_REG_BASE + 0x01BC) 442 * #define W5_RET_DEC_SEEK_END_TICK (W5_REG_BASE + 0x01C0) 443 * => Start and end ticks for seeking slices of the picture 444 * #define W5_RET_DEC_PARSING_START_TICK (W5_REG_BASE + 0x01C4) 445 * #define W5_RET_DEC_PARSING_END_TICK (W5_REG_BASE + 0x01C8) 446 * => Start and end ticks for parsing slices of the picture 447 * #define W5_RET_DEC_DECODING_START_TICK (W5_REG_BASE + 0x01CC) 448 * => Start tick for decoding slices of the picture 449 */ 450 #define W5_RET_DEC_DECODING_ENC_TICK (W5_REG_BASE + 0x01D0) 451 #define W5_RET_DEC_WARN_INFO (W5_REG_BASE + 0x01D4) 452 #define W5_RET_DEC_ERR_INFO (W5_REG_BASE + 0x01D8) 453 #define W5_RET_DEC_DECODING_SUCCESS (W5_REG_BASE + 0x01DC) 454 455 /************************************************************************/ 456 /* DECODER - FLUSH_INSTANCE */ 457 /************************************************************************/ 458 #define W5_CMD_FLUSH_INST_OPT (W5_REG_BASE + 0x104) 459 460 /************************************************************************/ 461 /* DECODER - QUERY : UPDATE_DISP_FLAG */ 462 /************************************************************************/ 463 #define W5_CMD_DEC_SET_DISP_IDC (W5_REG_BASE + 0x0118) 464 #define W5_CMD_DEC_CLR_DISP_IDC (W5_REG_BASE + 0x011C) 465 466 /************************************************************************/ 467 /* DECODER - QUERY : SET_BS_RD_PTR */ 468 /************************************************************************/ 469 #define W5_RET_QUERY_DEC_SET_BS_RD_PTR (W5_REG_BASE + 0x011C) 470 471 /************************************************************************/ 472 /* DECODER - QUERY : GET_BS_RD_PTR */ 473 /************************************************************************/ 474 #define W5_RET_QUERY_DEC_BS_RD_PTR (W5_REG_BASE + 0x011C) 475 476 /************************************************************************/ 477 /* QUERY : GET_DEBUG_INFO */ 478 /************************************************************************/ 479 #define W5_RET_QUERY_DEBUG_PRI_REASON (W5_REG_BASE + 0x114) 480 481 /************************************************************************/ 482 /* GDI register for debugging */ 483 /************************************************************************/ 484 #define W5_GDI_BASE 0x8800 485 #define W5_GDI_BUS_CTRL (W5_GDI_BASE + 0x0F0) 486 #define W5_GDI_BUS_STATUS (W5_GDI_BASE + 0x0F4) 487 488 #define W5_BACKBONE_BASE_VCPU 0xFE00 489 #define W5_BACKBONE_BUS_CTRL_VCPU (W5_BACKBONE_BASE_VCPU + 0x010) 490 #define W5_BACKBONE_BUS_STATUS_VCPU (W5_BACKBONE_BASE_VCPU + 0x014) 491 #define W5_BACKBONE_PROG_AXI_ID (W5_BACKBONE_BASE_VCPU + 0x00C) 492 493 #define W5_BACKBONE_PROC_EXT_ADDR (W5_BACKBONE_BASE_VCPU + 0x0C0) 494 #define W5_BACKBONE_AXI_PARAM (W5_BACKBONE_BASE_VCPU + 0x0E0) 495 496 #define W5_BACKBONE_BASE_VCORE0 0x8E00 497 #define W5_BACKBONE_BUS_CTRL_VCORE0 (W5_BACKBONE_BASE_VCORE0 + 0x010) 498 #define W5_BACKBONE_BUS_STATUS_VCORE0 (W5_BACKBONE_BASE_VCORE0 + 0x014) 499 500 #define W5_BACKBONE_BASE_VCORE1 0x9E00 /* for dual-core product */ 501 #define W5_BACKBONE_BUS_CTRL_VCORE1 (W5_BACKBONE_BASE_VCORE1 + 0x010) 502 #define W5_BACKBONE_BUS_STATUS_VCORE1 (W5_BACKBONE_BASE_VCORE1 + 0x014) 503 504 #define W5_COMBINED_BACKBONE_BASE 0xFE00 505 #define W5_COMBINED_BACKBONE_BUS_CTRL (W5_COMBINED_BACKBONE_BASE + 0x010) 506 #define W5_COMBINED_BACKBONE_BUS_STATUS (W5_COMBINED_BACKBONE_BASE + 0x014) 507 508 /************************************************************************/ 509 /* */ 510 /* for ENCODER */ 511 /* */ 512 /************************************************************************/ 513 #define W5_RET_STAGE3_INSTANCE_INFO (W5_REG_BASE + 0x1F8) 514 /************************************************************************/ 515 /* ENCODER - CREATE_INSTANCE */ 516 /************************************************************************/ 517 /* 0x114 ~ 0x124 : defined above (CREATE_INSTANCE COMMON) */ 518 #define W5_CMD_ENC_VCORE_INFO (W5_REG_BASE + 0x0194) 519 #define W5_CMD_ENC_SRC_OPTIONS (W5_REG_BASE + 0x0128) 520 521 /************************************************************************/ 522 /* ENCODER - SET_FB */ 523 /************************************************************************/ 524 #define W5_FBC_STRIDE (W5_REG_BASE + 0x128) 525 #define W5_ADDR_SUB_SAMPLED_FB_BASE (W5_REG_BASE + 0x12C) 526 #define W5_SUB_SAMPLED_ONE_FB_SIZE (W5_REG_BASE + 0x130) 527 528 /************************************************************************/ 529 /* ENCODER - ENC_SET_PARAM (COMMON & CHANGE_PARAM) */ 530 /************************************************************************/ 531 #define W5_CMD_ENC_SEQ_SET_PARAM_OPTION (W5_REG_BASE + 0x104) 532 #define W5_CMD_ENC_SEQ_SET_PARAM_ENABLE (W5_REG_BASE + 0x118) 533 #define W5_CMD_ENC_SEQ_SRC_SIZE (W5_REG_BASE + 0x11C) 534 #define W5_CMD_ENC_SEQ_CUSTOM_MAP_ENDIAN (W5_REG_BASE + 0x120) 535 #define W5_CMD_ENC_SEQ_SPS_PARAM (W5_REG_BASE + 0x124) 536 #define W5_CMD_ENC_SEQ_PPS_PARAM (W5_REG_BASE + 0x128) 537 #define W5_CMD_ENC_SEQ_GOP_PARAM (W5_REG_BASE + 0x12C) 538 #define W5_CMD_ENC_SEQ_INTRA_PARAM (W5_REG_BASE + 0x130) 539 #define W5_CMD_ENC_SEQ_CONF_WIN_TOP_BOT (W5_REG_BASE + 0x134) 540 #define W5_CMD_ENC_SEQ_CONF_WIN_LEFT_RIGHT (W5_REG_BASE + 0x138) 541 #define W5_CMD_ENC_SEQ_RDO_PARAM (W5_REG_BASE + 0x13C) 542 #define W5_CMD_ENC_SEQ_INDEPENDENT_SLICE (W5_REG_BASE + 0x140) 543 #define W5_CMD_ENC_SEQ_DEPENDENT_SLICE (W5_REG_BASE + 0x144) 544 #define W5_CMD_ENC_SEQ_INTRA_REFRESH (W5_REG_BASE + 0x148) 545 #define W5_CMD_ENC_SEQ_INPUT_SRC_PARAM (W5_REG_BASE + 0x14C) 546 547 #define W5_CMD_ENC_SEQ_RC_FRAME_RATE (W5_REG_BASE + 0x150) 548 #define W5_CMD_ENC_SEQ_RC_TARGET_RATE (W5_REG_BASE + 0x154) 549 #define W5_CMD_ENC_SEQ_RC_PARAM (W5_REG_BASE + 0x158) 550 #define W5_CMD_ENC_SEQ_RC_MIN_MAX_QP (W5_REG_BASE + 0x15C) 551 #define W5_CMD_ENC_SEQ_RC_BIT_RATIO_LAYER_0_3 (W5_REG_BASE + 0x160) 552 #define W5_CMD_ENC_SEQ_RC_BIT_RATIO_LAYER_4_7 (W5_REG_BASE + 0x164) 553 #define W5_CMD_ENC_SEQ_RC_INTER_MIN_MAX_QP (W5_REG_BASE + 0x168) 554 #define W5_CMD_ENC_SEQ_RC_WEIGHT_PARAM (W5_REG_BASE + 0x16C) 555 556 #define W5_CMD_ENC_SEQ_ROT_PARAM (W5_REG_BASE + 0x170) 557 #define W5_CMD_ENC_SEQ_NUM_UNITS_IN_TICK (W5_REG_BASE + 0x174) 558 #define W5_CMD_ENC_SEQ_TIME_SCALE (W5_REG_BASE + 0x178) 559 #define W5_CMD_ENC_SEQ_NUM_TICKS_POC_DIFF_ONE (W5_REG_BASE + 0x17C) 560 561 #define W5_CMD_ENC_SEQ_CUSTOM_MD_PU04 (W5_REG_BASE + 0x184) 562 #define W5_CMD_ENC_SEQ_CUSTOM_MD_PU08 (W5_REG_BASE + 0x188) 563 #define W5_CMD_ENC_SEQ_CUSTOM_MD_PU16 (W5_REG_BASE + 0x18C) 564 #define W5_CMD_ENC_SEQ_CUSTOM_MD_PU32 (W5_REG_BASE + 0x190) 565 #define W5_CMD_ENC_SEQ_CUSTOM_MD_CU08 (W5_REG_BASE + 0x194) 566 #define W5_CMD_ENC_SEQ_CUSTOM_MD_CU16 (W5_REG_BASE + 0x198) 567 #define W5_CMD_ENC_SEQ_CUSTOM_MD_CU32 (W5_REG_BASE + 0x19C) 568 #define W5_CMD_ENC_SEQ_NR_PARAM (W5_REG_BASE + 0x1A0) 569 #define W5_CMD_ENC_SEQ_NR_WEIGHT (W5_REG_BASE + 0x1A4) 570 #define W5_CMD_ENC_SEQ_BG_PARAM (W5_REG_BASE + 0x1A8) 571 #define W5_CMD_ENC_SEQ_CUSTOM_LAMBDA_ADDR (W5_REG_BASE + 0x1AC) 572 #define W5_CMD_ENC_SEQ_USER_SCALING_LIST_ADDR (W5_REG_BASE + 0x1B0) 573 #define W5_CMD_ENC_SEQ_VUI_HRD_PARAM (W5_REG_BASE + 0x180) 574 #define W5_CMD_ENC_SEQ_VUI_RBSP_ADDR (W5_REG_BASE + 0x1B8) 575 #define W5_CMD_ENC_SEQ_HRD_RBSP_ADDR (W5_REG_BASE + 0x1BC) 576 577 /************************************************************************/ 578 /* ENCODER - ENC_SET_PARAM (CUSTOM_GOP) */ 579 /************************************************************************/ 580 #define W5_CMD_ENC_CUSTOM_GOP_PARAM (W5_REG_BASE + 0x11C) 581 #define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_0 (W5_REG_BASE + 0x120) 582 #define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_1 (W5_REG_BASE + 0x124) 583 #define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_2 (W5_REG_BASE + 0x128) 584 #define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_3 (W5_REG_BASE + 0x12C) 585 #define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_4 (W5_REG_BASE + 0x130) 586 #define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_5 (W5_REG_BASE + 0x134) 587 #define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_6 (W5_REG_BASE + 0x138) 588 #define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_7 (W5_REG_BASE + 0x13C) 589 #define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_8 (W5_REG_BASE + 0x140) 590 #define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_9 (W5_REG_BASE + 0x144) 591 #define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_10 (W5_REG_BASE + 0x148) 592 #define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_11 (W5_REG_BASE + 0x14C) 593 #define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_12 (W5_REG_BASE + 0x150) 594 #define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_13 (W5_REG_BASE + 0x154) 595 #define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_14 (W5_REG_BASE + 0x158) 596 #define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_15 (W5_REG_BASE + 0x15C) 597 598 /************************************************************************/ 599 /* ENCODER - ENC_PIC */ 600 /************************************************************************/ 601 #define W5_CMD_ENC_BS_START_ADDR (W5_REG_BASE + 0x118) 602 #define W5_CMD_ENC_BS_SIZE (W5_REG_BASE + 0x11C) 603 #define W5_CMD_ENC_PIC_USE_SEC_AXI (W5_REG_BASE + 0x124) 604 #define W5_CMD_ENC_PIC_REPORT_PARAM (W5_REG_BASE + 0x128) 605 606 #define W5_CMD_ENC_PIC_CUSTOM_MAP_OPTION_PARAM (W5_REG_BASE + 0x138) 607 #define W5_CMD_ENC_PIC_CUSTOM_MAP_OPTION_ADDR (W5_REG_BASE + 0x13C) 608 #define W5_CMD_ENC_PIC_SRC_PIC_IDX (W5_REG_BASE + 0x144) 609 #define W5_CMD_ENC_PIC_SRC_ADDR_Y (W5_REG_BASE + 0x148) 610 #define W5_CMD_ENC_PIC_SRC_ADDR_U (W5_REG_BASE + 0x14C) 611 #define W5_CMD_ENC_PIC_SRC_ADDR_V (W5_REG_BASE + 0x150) 612 #define W5_CMD_ENC_PIC_SRC_STRIDE (W5_REG_BASE + 0x154) 613 #define W5_CMD_ENC_PIC_SRC_FORMAT (W5_REG_BASE + 0x158) 614 #define W5_CMD_ENC_PIC_SRC_AXI_SEL (W5_REG_BASE + 0x160) 615 #define W5_CMD_ENC_PIC_CODE_OPTION (W5_REG_BASE + 0x164) 616 #define W5_CMD_ENC_PIC_PIC_PARAM (W5_REG_BASE + 0x168) 617 #define W5_CMD_ENC_PIC_LONGTERM_PIC (W5_REG_BASE + 0x16C) 618 #define W5_CMD_ENC_PIC_WP_PIXEL_SIGMA_Y (W5_REG_BASE + 0x170) 619 #define W5_CMD_ENC_PIC_WP_PIXEL_SIGMA_C (W5_REG_BASE + 0x174) 620 #define W5_CMD_ENC_PIC_WP_PIXEL_MEAN_Y (W5_REG_BASE + 0x178) 621 #define W5_CMD_ENC_PIC_WP_PIXEL_MEAN_C (W5_REG_BASE + 0x17C) 622 #define W5_CMD_ENC_PIC_CF50_Y_OFFSET_TABLE_ADDR (W5_REG_BASE + 0x190) 623 #define W5_CMD_ENC_PIC_CF50_CB_OFFSET_TABLE_ADDR (W5_REG_BASE + 0x194) 624 #define W5_CMD_ENC_PIC_CF50_CR_OFFSET_TABLE_ADDR (W5_REG_BASE + 0x198) 625 #define W5_CMD_ENC_PIC_PREFIX_SEI_NAL_ADDR (W5_REG_BASE + 0x180) 626 #define W5_CMD_ENC_PIC_PREFIX_SEI_INFO (W5_REG_BASE + 0x184) 627 #define W5_CMD_ENC_PIC_SUFFIX_SEI_NAL_ADDR (W5_REG_BASE + 0x188) 628 #define W5_CMD_ENC_PIC_SUFFIX_SEI_INFO (W5_REG_BASE + 0x18c) 629 630 /************************************************************************/ 631 /* ENCODER - QUERY (GET_RESULT) */ 632 /************************************************************************/ 633 #define W5_RET_ENC_NUM_REQUIRED_FB (W5_REG_BASE + 0x11C) 634 #define W5_RET_ENC_MIN_SRC_BUF_NUM (W5_REG_BASE + 0x120) 635 #define W5_RET_ENC_PIC_TYPE (W5_REG_BASE + 0x124) 636 /* 637 * #define W5_RET_ENC_PIC_POC (W5_REG_BASE + 0x128) 638 * => picture order count value of current encoded picture 639 */ 640 #define W5_RET_ENC_PIC_IDX (W5_REG_BASE + 0x12C) 641 /* 642 * #define W5_RET_ENC_PIC_SLICE_NUM (W5_REG_BASE + 0x130) 643 * reg_val & 0xffff = total independent slice segment number (16 bits) 644 * (reg_val >> 16) & 0xffff = total dependent slice segment number (16 bits) 645 * 646 * #define W5_RET_ENC_PIC_SKIP (W5_REG_BASE + 0x134) 647 * reg_val & 0xfe = picture skip flag (7 bits) 648 * 649 * #define W5_RET_ENC_PIC_NUM_INTRA (W5_REG_BASE + 0x138) 650 * => number of intra blocks in 8x8 (32 bits) 651 * 652 * #define W5_RET_ENC_PIC_NUM_MERGE (W5_REG_BASE + 0x13C) 653 * => number of merge blocks in 8x8 (32 bits) 654 * 655 * #define W5_RET_ENC_PIC_NUM_SKIP (W5_REG_BASE + 0x144) 656 * => number of skip blocks in 8x8 (32 bits) 657 * 658 * #define W5_RET_ENC_PIC_AVG_CTU_QP (W5_REG_BASE + 0x148) 659 * => Average CTU QP value (32 bits) 660 */ 661 #define W5_RET_ENC_PIC_BYTE (W5_REG_BASE + 0x14C) 662 /* 663 * #define W5_RET_ENC_GOP_PIC_IDX (W5_REG_BASE + 0x150) 664 * => picture index in group of pictures 665 */ 666 #define W5_RET_ENC_USED_SRC_IDX (W5_REG_BASE + 0x154) 667 /* 668 * #define W5_RET_ENC_PIC_NUM (W5_REG_BASE + 0x158) 669 * => encoded picture number 670 */ 671 #define W5_RET_ENC_VCL_NUT (W5_REG_BASE + 0x15C) 672 /* 673 * Only for H264: 674 * #define W5_RET_ENC_PIC_DIST_LOW (W5_REG_BASE + 0x164) 675 * => lower 32 bits of the sum of squared difference between source Y picture 676 * and reconstructed Y picture 677 * #define W5_RET_ENC_PIC_DIST_HIGH (W5_REG_BASE + 0x168) 678 * => upper 32 bits of the sum of squared difference between source Y picture 679 * and reconstructed Y picture 680 */ 681 #define W5_RET_ENC_PIC_MAX_LATENCY_PICS (W5_REG_BASE + 0x16C) 682 683 #define W5_RET_ENC_HOST_CMD_TICK (W5_REG_BASE + 0x1B8) 684 /* 685 * #define W5_RET_ENC_PREPARE_START_TICK (W5_REG_BASE + 0x1BC) 686 * #define W5_RET_ENC_PREPARE_END_TICK (W5_REG_BASE + 0x1C0) 687 * => Start and end ticks for preparing slices of the picture 688 * #define W5_RET_ENC_PROCESSING_START_TICK (W5_REG_BASE + 0x1C4) 689 * #define W5_RET_ENC_PROCESSING_END_TICK (W5_REG_BASE + 0x1C8) 690 * => Start and end ticks for processing slices of the picture 691 * #define W5_RET_ENC_ENCODING_START_TICK (W5_REG_BASE + 0x1CC) 692 * => Start tick for encoding slices of the picture 693 */ 694 #define W5_RET_ENC_ENCODING_END_TICK (W5_REG_BASE + 0x1D0) 695 696 #define W5_RET_ENC_WARN_INFO (W5_REG_BASE + 0x1D4) 697 #define W5_RET_ENC_ERR_INFO (W5_REG_BASE + 0x1D8) 698 #define W5_RET_ENC_ENCODING_SUCCESS (W5_REG_BASE + 0x1DC) 699 700 /************************************************************************/ 701 /* ENCODER - QUERY (GET_BS_WR_PTR) */ 702 /************************************************************************/ 703 #define W5_RET_ENC_RD_PTR (W5_REG_BASE + 0x114) 704 #define W5_RET_ENC_WR_PTR (W5_REG_BASE + 0x118) 705 #define W5_CMD_ENC_REASON_SEL (W5_REG_BASE + 0x11C) 706 707 /************************************************************************/ 708 /* ENCODER - QUERY (GET_BW_REPORT) */ 709 /************************************************************************/ 710 #define RET_QUERY_BW_PRP_AXI_READ (W5_REG_BASE + 0x118) 711 #define RET_QUERY_BW_PRP_AXI_WRITE (W5_REG_BASE + 0x11C) 712 #define RET_QUERY_BW_FBD_Y_AXI_READ (W5_REG_BASE + 0x120) 713 #define RET_QUERY_BW_FBC_Y_AXI_WRITE (W5_REG_BASE + 0x124) 714 #define RET_QUERY_BW_FBD_C_AXI_READ (W5_REG_BASE + 0x128) 715 #define RET_QUERY_BW_FBC_C_AXI_WRITE (W5_REG_BASE + 0x12C) 716 #define RET_QUERY_BW_PRI_AXI_READ (W5_REG_BASE + 0x130) 717 #define RET_QUERY_BW_PRI_AXI_WRITE (W5_REG_BASE + 0x134) 718 #define RET_QUERY_BW_SEC_AXI_READ (W5_REG_BASE + 0x138) 719 #define RET_QUERY_BW_SEC_AXI_WRITE (W5_REG_BASE + 0x13C) 720 #define RET_QUERY_BW_PROC_AXI_READ (W5_REG_BASE + 0x140) 721 #define RET_QUERY_BW_PROC_AXI_WRITE (W5_REG_BASE + 0x144) 722 #define RET_QUERY_BW_BWB_AXI_WRITE (W5_REG_BASE + 0x148) 723 #define W5_CMD_BW_OPTION (W5_REG_BASE + 0x14C) 724 725 /************************************************************************/ 726 /* ENCODER - QUERY (GET_SRC_FLAG) */ 727 /************************************************************************/ 728 #define W5_RET_RELEASED_SRC_INSTANCE (W5_REG_BASE + 0x1EC) 729 730 #define W5_ENC_PIC_SUB_FRAME_SYNC_IF (W5_REG_BASE + 0x0300) 731 732 #endif /* __WAVE5_REGISTER_DEFINE_H__ */ 733