1*9707a625SNas Chung /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ 2*9707a625SNas Chung /* 3*9707a625SNas Chung * Wave5 series multi-standard codec IP - basic types 4*9707a625SNas Chung * 5*9707a625SNas Chung * Copyright (C) 2021-2023 CHIPS&MEDIA INC 6*9707a625SNas Chung */ 7*9707a625SNas Chung 8*9707a625SNas Chung #ifndef __WAVE_HELPER_H__ 9*9707a625SNas Chung #define __WAVE_HELPER_H__ 10*9707a625SNas Chung 11*9707a625SNas Chung #include "wave5-vpu.h" 12*9707a625SNas Chung 13*9707a625SNas Chung #define FMT_TYPES 2 14*9707a625SNas Chung #define MAX_FMTS 12 15*9707a625SNas Chung 16*9707a625SNas Chung const char *state_to_str(enum vpu_instance_state state); 17*9707a625SNas Chung void wave5_cleanup_instance(struct vpu_instance *inst); 18*9707a625SNas Chung int wave5_vpu_release_device(struct file *filp, 19*9707a625SNas Chung int (*close_func)(struct vpu_instance *inst, u32 *fail_res), 20*9707a625SNas Chung char *name); 21*9707a625SNas Chung int wave5_vpu_queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq, 22*9707a625SNas Chung const struct vb2_ops *ops); 23*9707a625SNas Chung int wave5_vpu_subscribe_event(struct v4l2_fh *fh, const struct v4l2_event_subscription *sub); 24*9707a625SNas Chung int wave5_vpu_g_fmt_out(struct file *file, void *fh, struct v4l2_format *f); 25*9707a625SNas Chung const struct vpu_format *wave5_find_vpu_fmt(unsigned int v4l2_pix_fmt, 26*9707a625SNas Chung const struct vpu_format fmt_list[MAX_FMTS]); 27*9707a625SNas Chung const struct vpu_format *wave5_find_vpu_fmt_by_idx(unsigned int idx, 28*9707a625SNas Chung const struct vpu_format fmt_list[MAX_FMTS]); 29*9707a625SNas Chung enum wave_std wave5_to_vpu_std(unsigned int v4l2_pix_fmt, enum vpu_instance_type type); 30*9707a625SNas Chung void wave5_return_bufs(struct vb2_queue *q, u32 state); 31*9707a625SNas Chung #endif 32