xref: /linux/drivers/media/platform/cadence/cdns-csi2tx.c (revision e9f0878c4b2004ac19581274c1ae4c61ae3ca70e) 
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Driver for Cadence MIPI-CSI2 TX Controller
4  *
5  * Copyright (C) 2017-2018 Cadence Design Systems Inc.
6  */
7 
8 #include <linux/clk.h>
9 #include <linux/delay.h>
10 #include <linux/io.h>
11 #include <linux/module.h>
12 #include <linux/mutex.h>
13 #include <linux/of.h>
14 #include <linux/of_graph.h>
15 #include <linux/platform_device.h>
16 #include <linux/slab.h>
17 
18 #include <media/v4l2-ctrls.h>
19 #include <media/v4l2-device.h>
20 #include <media/v4l2-fwnode.h>
21 #include <media/v4l2-subdev.h>
22 
23 #define CSI2TX_DEVICE_CONFIG_REG	0x00
24 #define CSI2TX_DEVICE_CONFIG_STREAMS_MASK	GENMASK(6, 4)
25 #define CSI2TX_DEVICE_CONFIG_HAS_DPHY		BIT(3)
26 #define CSI2TX_DEVICE_CONFIG_LANES_MASK		GENMASK(2, 0)
27 
28 #define CSI2TX_CONFIG_REG		0x20
29 #define CSI2TX_CONFIG_CFG_REQ			BIT(2)
30 #define CSI2TX_CONFIG_SRST_REQ			BIT(1)
31 
32 #define CSI2TX_DPHY_CFG_REG		0x28
33 #define CSI2TX_DPHY_CFG_CLK_RESET		BIT(16)
34 #define CSI2TX_DPHY_CFG_LANE_RESET(n)		BIT((n) + 12)
35 #define CSI2TX_DPHY_CFG_MODE_MASK		GENMASK(9, 8)
36 #define CSI2TX_DPHY_CFG_MODE_LPDT		(2 << 8)
37 #define CSI2TX_DPHY_CFG_MODE_HS			(1 << 8)
38 #define CSI2TX_DPHY_CFG_MODE_ULPS		(0 << 8)
39 #define CSI2TX_DPHY_CFG_CLK_ENABLE		BIT(4)
40 #define CSI2TX_DPHY_CFG_LANE_ENABLE(n)		BIT(n)
41 
42 #define CSI2TX_DPHY_CLK_WAKEUP_REG	0x2c
43 #define CSI2TX_DPHY_CLK_WAKEUP_ULPS_CYCLES(n)	((n) & 0xffff)
44 
45 #define CSI2TX_DT_CFG_REG(n)		(0x80 + (n) * 8)
46 #define CSI2TX_DT_CFG_DT(n)			(((n) & 0x3f) << 2)
47 
48 #define CSI2TX_DT_FORMAT_REG(n)		(0x84 + (n) * 8)
49 #define CSI2TX_DT_FORMAT_BYTES_PER_LINE(n)	(((n) & 0xffff) << 16)
50 #define CSI2TX_DT_FORMAT_MAX_LINE_NUM(n)	((n) & 0xffff)
51 
52 #define CSI2TX_STREAM_IF_CFG_REG(n)	(0x100 + (n) * 4)
53 #define CSI2TX_STREAM_IF_CFG_FILL_LEVEL(n)	((n) & 0x1f)
54 
55 #define CSI2TX_LANES_MAX	4
56 #define CSI2TX_STREAMS_MAX	4
57 
58 enum csi2tx_pads {
59 	CSI2TX_PAD_SOURCE,
60 	CSI2TX_PAD_SINK_STREAM0,
61 	CSI2TX_PAD_SINK_STREAM1,
62 	CSI2TX_PAD_SINK_STREAM2,
63 	CSI2TX_PAD_SINK_STREAM3,
64 	CSI2TX_PAD_MAX,
65 };
66 
67 struct csi2tx_fmt {
68 	u32	mbus;
69 	u32	dt;
70 	u32	bpp;
71 };
72 
73 struct csi2tx_priv {
74 	struct device			*dev;
75 	unsigned int			count;
76 
77 	/*
78 	 * Used to prevent race conditions between multiple,
79 	 * concurrent calls to start and stop.
80 	 */
81 	struct mutex			lock;
82 
83 	void __iomem			*base;
84 
85 	struct clk			*esc_clk;
86 	struct clk			*p_clk;
87 	struct clk			*pixel_clk[CSI2TX_STREAMS_MAX];
88 
89 	struct v4l2_subdev		subdev;
90 	struct media_pad		pads[CSI2TX_PAD_MAX];
91 	struct v4l2_mbus_framefmt	pad_fmts[CSI2TX_PAD_MAX];
92 
93 	bool				has_internal_dphy;
94 	u8				lanes[CSI2TX_LANES_MAX];
95 	unsigned int			num_lanes;
96 	unsigned int			max_lanes;
97 	unsigned int			max_streams;
98 };
99 
100 static const struct csi2tx_fmt csi2tx_formats[] = {
101 	{
102 		.mbus	= MEDIA_BUS_FMT_UYVY8_1X16,
103 		.bpp	= 2,
104 		.dt	= 0x1e,
105 	},
106 	{
107 		.mbus	= MEDIA_BUS_FMT_RGB888_1X24,
108 		.bpp	= 3,
109 		.dt	= 0x24,
110 	},
111 };
112 
113 static const struct v4l2_mbus_framefmt fmt_default = {
114 	.width		= 1280,
115 	.height		= 720,
116 	.code		= MEDIA_BUS_FMT_RGB888_1X24,
117 	.field		= V4L2_FIELD_NONE,
118 	.colorspace	= V4L2_COLORSPACE_DEFAULT,
119 };
120 
121 static inline
122 struct csi2tx_priv *v4l2_subdev_to_csi2tx(struct v4l2_subdev *subdev)
123 {
124 	return container_of(subdev, struct csi2tx_priv, subdev);
125 }
126 
127 static const struct csi2tx_fmt *csi2tx_get_fmt_from_mbus(u32 mbus)
128 {
129 	unsigned int i;
130 
131 	for (i = 0; i < ARRAY_SIZE(csi2tx_formats); i++)
132 		if (csi2tx_formats[i].mbus == mbus)
133 			return &csi2tx_formats[i];
134 
135 	return NULL;
136 }
137 
138 static int csi2tx_enum_mbus_code(struct v4l2_subdev *subdev,
139 				 struct v4l2_subdev_pad_config *cfg,
140 				 struct v4l2_subdev_mbus_code_enum *code)
141 {
142 	if (code->pad || code->index >= ARRAY_SIZE(csi2tx_formats))
143 		return -EINVAL;
144 
145 	code->code = csi2tx_formats[code->index].mbus;
146 
147 	return 0;
148 }
149 
150 static struct v4l2_mbus_framefmt *
151 __csi2tx_get_pad_format(struct v4l2_subdev *subdev,
152 			struct v4l2_subdev_pad_config *cfg,
153 			struct v4l2_subdev_format *fmt)
154 {
155 	struct csi2tx_priv *csi2tx = v4l2_subdev_to_csi2tx(subdev);
156 
157 	if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
158 		return v4l2_subdev_get_try_format(subdev, cfg,
159 						  fmt->pad);
160 
161 	return &csi2tx->pad_fmts[fmt->pad];
162 }
163 
164 static int csi2tx_get_pad_format(struct v4l2_subdev *subdev,
165 				 struct v4l2_subdev_pad_config *cfg,
166 				 struct v4l2_subdev_format *fmt)
167 {
168 	const struct v4l2_mbus_framefmt *format;
169 
170 	/* Multiplexed pad? */
171 	if (fmt->pad == CSI2TX_PAD_SOURCE)
172 		return -EINVAL;
173 
174 	format = __csi2tx_get_pad_format(subdev, cfg, fmt);
175 	if (!format)
176 		return -EINVAL;
177 
178 	fmt->format = *format;
179 
180 	return 0;
181 }
182 
183 static int csi2tx_set_pad_format(struct v4l2_subdev *subdev,
184 				 struct v4l2_subdev_pad_config *cfg,
185 				 struct v4l2_subdev_format *fmt)
186 {
187 	const struct v4l2_mbus_framefmt *src_format = &fmt->format;
188 	struct v4l2_mbus_framefmt *dst_format;
189 
190 	/* Multiplexed pad? */
191 	if (fmt->pad == CSI2TX_PAD_SOURCE)
192 		return -EINVAL;
193 
194 	if (!csi2tx_get_fmt_from_mbus(fmt->format.code))
195 		src_format = &fmt_default;
196 
197 	dst_format = __csi2tx_get_pad_format(subdev, cfg, fmt);
198 	if (!dst_format)
199 		return -EINVAL;
200 
201 	*dst_format = *src_format;
202 
203 	return 0;
204 }
205 
206 static const struct v4l2_subdev_pad_ops csi2tx_pad_ops = {
207 	.enum_mbus_code	= csi2tx_enum_mbus_code,
208 	.get_fmt	= csi2tx_get_pad_format,
209 	.set_fmt	= csi2tx_set_pad_format,
210 };
211 
212 static void csi2tx_reset(struct csi2tx_priv *csi2tx)
213 {
214 	writel(CSI2TX_CONFIG_SRST_REQ, csi2tx->base + CSI2TX_CONFIG_REG);
215 
216 	udelay(10);
217 }
218 
219 static int csi2tx_start(struct csi2tx_priv *csi2tx)
220 {
221 	struct media_entity *entity = &csi2tx->subdev.entity;
222 	struct media_link *link;
223 	unsigned int i;
224 	u32 reg;
225 
226 	csi2tx_reset(csi2tx);
227 
228 	writel(CSI2TX_CONFIG_CFG_REQ, csi2tx->base + CSI2TX_CONFIG_REG);
229 
230 	udelay(10);
231 
232 	/* Configure our PPI interface with the D-PHY */
233 	writel(CSI2TX_DPHY_CLK_WAKEUP_ULPS_CYCLES(32),
234 	       csi2tx->base + CSI2TX_DPHY_CLK_WAKEUP_REG);
235 
236 	/* Put our lanes (clock and data) out of reset */
237 	reg = CSI2TX_DPHY_CFG_CLK_RESET | CSI2TX_DPHY_CFG_MODE_LPDT;
238 	for (i = 0; i < csi2tx->num_lanes; i++)
239 		reg |= CSI2TX_DPHY_CFG_LANE_RESET(csi2tx->lanes[i]);
240 	writel(reg, csi2tx->base + CSI2TX_DPHY_CFG_REG);
241 
242 	udelay(10);
243 
244 	/* Enable our (clock and data) lanes */
245 	reg |= CSI2TX_DPHY_CFG_CLK_ENABLE;
246 	for (i = 0; i < csi2tx->num_lanes; i++)
247 		reg |= CSI2TX_DPHY_CFG_LANE_ENABLE(csi2tx->lanes[i]);
248 	writel(reg, csi2tx->base + CSI2TX_DPHY_CFG_REG);
249 
250 	udelay(10);
251 
252 	/* Switch to HS mode */
253 	reg &= ~CSI2TX_DPHY_CFG_MODE_MASK;
254 	writel(reg | CSI2TX_DPHY_CFG_MODE_HS,
255 	       csi2tx->base + CSI2TX_DPHY_CFG_REG);
256 
257 	udelay(10);
258 
259 	/*
260 	 * Create a static mapping between the CSI virtual channels
261 	 * and the input streams.
262 	 *
263 	 * This should be enhanced, but v4l2 lacks the support for
264 	 * changing that mapping dynamically at the moment.
265 	 *
266 	 * We're protected from the userspace setting up links at the
267 	 * same time by the upper layer having called
268 	 * media_pipeline_start().
269 	 */
270 	list_for_each_entry(link, &entity->links, list) {
271 		struct v4l2_mbus_framefmt *mfmt;
272 		const struct csi2tx_fmt *fmt;
273 		unsigned int stream;
274 		int pad_idx = -1;
275 
276 		/* Only consider our enabled input pads */
277 		for (i = CSI2TX_PAD_SINK_STREAM0; i < CSI2TX_PAD_MAX; i++) {
278 			struct media_pad *pad = &csi2tx->pads[i];
279 
280 			if ((pad == link->sink) &&
281 			    (link->flags & MEDIA_LNK_FL_ENABLED)) {
282 				pad_idx = i;
283 				break;
284 			}
285 		}
286 
287 		if (pad_idx < 0)
288 			continue;
289 
290 		mfmt = &csi2tx->pad_fmts[pad_idx];
291 		fmt = csi2tx_get_fmt_from_mbus(mfmt->code);
292 		if (!fmt)
293 			continue;
294 
295 		stream = pad_idx - CSI2TX_PAD_SINK_STREAM0;
296 
297 		/*
298 		 * We use the stream ID there, but it's wrong.
299 		 *
300 		 * A stream could very well send a data type that is
301 		 * not equal to its stream ID. We need to find a
302 		 * proper way to address it.
303 		 */
304 		writel(CSI2TX_DT_CFG_DT(fmt->dt),
305 		       csi2tx->base + CSI2TX_DT_CFG_REG(stream));
306 
307 		writel(CSI2TX_DT_FORMAT_BYTES_PER_LINE(mfmt->width * fmt->bpp) |
308 		       CSI2TX_DT_FORMAT_MAX_LINE_NUM(mfmt->height + 1),
309 		       csi2tx->base + CSI2TX_DT_FORMAT_REG(stream));
310 
311 		/*
312 		 * TODO: This needs to be calculated based on the
313 		 * output CSI2 clock rate.
314 		 */
315 		writel(CSI2TX_STREAM_IF_CFG_FILL_LEVEL(4),
316 		       csi2tx->base + CSI2TX_STREAM_IF_CFG_REG(stream));
317 	}
318 
319 	/* Disable the configuration mode */
320 	writel(0, csi2tx->base + CSI2TX_CONFIG_REG);
321 
322 	return 0;
323 }
324 
325 static void csi2tx_stop(struct csi2tx_priv *csi2tx)
326 {
327 	writel(CSI2TX_CONFIG_CFG_REQ | CSI2TX_CONFIG_SRST_REQ,
328 	       csi2tx->base + CSI2TX_CONFIG_REG);
329 }
330 
331 static int csi2tx_s_stream(struct v4l2_subdev *subdev, int enable)
332 {
333 	struct csi2tx_priv *csi2tx = v4l2_subdev_to_csi2tx(subdev);
334 	int ret = 0;
335 
336 	mutex_lock(&csi2tx->lock);
337 
338 	if (enable) {
339 		/*
340 		 * If we're not the first users, there's no need to
341 		 * enable the whole controller.
342 		 */
343 		if (!csi2tx->count) {
344 			ret = csi2tx_start(csi2tx);
345 			if (ret)
346 				goto out;
347 		}
348 
349 		csi2tx->count++;
350 	} else {
351 		csi2tx->count--;
352 
353 		/*
354 		 * Let the last user turn off the lights.
355 		 */
356 		if (!csi2tx->count)
357 			csi2tx_stop(csi2tx);
358 	}
359 
360 out:
361 	mutex_unlock(&csi2tx->lock);
362 	return ret;
363 }
364 
365 static const struct v4l2_subdev_video_ops csi2tx_video_ops = {
366 	.s_stream	= csi2tx_s_stream,
367 };
368 
369 static const struct v4l2_subdev_ops csi2tx_subdev_ops = {
370 	.pad		= &csi2tx_pad_ops,
371 	.video		= &csi2tx_video_ops,
372 };
373 
374 static int csi2tx_get_resources(struct csi2tx_priv *csi2tx,
375 				struct platform_device *pdev)
376 {
377 	struct resource *res;
378 	unsigned int i;
379 	u32 dev_cfg;
380 
381 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
382 	csi2tx->base = devm_ioremap_resource(&pdev->dev, res);
383 	if (IS_ERR(csi2tx->base))
384 		return PTR_ERR(csi2tx->base);
385 
386 	csi2tx->p_clk = devm_clk_get(&pdev->dev, "p_clk");
387 	if (IS_ERR(csi2tx->p_clk)) {
388 		dev_err(&pdev->dev, "Couldn't get p_clk\n");
389 		return PTR_ERR(csi2tx->p_clk);
390 	}
391 
392 	csi2tx->esc_clk = devm_clk_get(&pdev->dev, "esc_clk");
393 	if (IS_ERR(csi2tx->esc_clk)) {
394 		dev_err(&pdev->dev, "Couldn't get the esc_clk\n");
395 		return PTR_ERR(csi2tx->esc_clk);
396 	}
397 
398 	clk_prepare_enable(csi2tx->p_clk);
399 	dev_cfg = readl(csi2tx->base + CSI2TX_DEVICE_CONFIG_REG);
400 	clk_disable_unprepare(csi2tx->p_clk);
401 
402 	csi2tx->max_lanes = dev_cfg & CSI2TX_DEVICE_CONFIG_LANES_MASK;
403 	if (csi2tx->max_lanes > CSI2TX_LANES_MAX) {
404 		dev_err(&pdev->dev, "Invalid number of lanes: %u\n",
405 			csi2tx->max_lanes);
406 		return -EINVAL;
407 	}
408 
409 	csi2tx->max_streams = (dev_cfg & CSI2TX_DEVICE_CONFIG_STREAMS_MASK) >> 4;
410 	if (csi2tx->max_streams > CSI2TX_STREAMS_MAX) {
411 		dev_err(&pdev->dev, "Invalid number of streams: %u\n",
412 			csi2tx->max_streams);
413 		return -EINVAL;
414 	}
415 
416 	csi2tx->has_internal_dphy = !!(dev_cfg & CSI2TX_DEVICE_CONFIG_HAS_DPHY);
417 
418 	for (i = 0; i < csi2tx->max_streams; i++) {
419 		char clk_name[16];
420 
421 		snprintf(clk_name, sizeof(clk_name), "pixel_if%u_clk", i);
422 		csi2tx->pixel_clk[i] = devm_clk_get(&pdev->dev, clk_name);
423 		if (IS_ERR(csi2tx->pixel_clk[i])) {
424 			dev_err(&pdev->dev, "Couldn't get clock %s\n",
425 				clk_name);
426 			return PTR_ERR(csi2tx->pixel_clk[i]);
427 		}
428 	}
429 
430 	return 0;
431 }
432 
433 static int csi2tx_check_lanes(struct csi2tx_priv *csi2tx)
434 {
435 	struct v4l2_fwnode_endpoint v4l2_ep;
436 	struct device_node *ep;
437 	int ret;
438 
439 	ep = of_graph_get_endpoint_by_regs(csi2tx->dev->of_node, 0, 0);
440 	if (!ep)
441 		return -EINVAL;
442 
443 	ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep), &v4l2_ep);
444 	if (ret) {
445 		dev_err(csi2tx->dev, "Could not parse v4l2 endpoint\n");
446 		goto out;
447 	}
448 
449 	if (v4l2_ep.bus_type != V4L2_MBUS_CSI2) {
450 		dev_err(csi2tx->dev, "Unsupported media bus type: 0x%x\n",
451 			v4l2_ep.bus_type);
452 		ret = -EINVAL;
453 		goto out;
454 	}
455 
456 	csi2tx->num_lanes = v4l2_ep.bus.mipi_csi2.num_data_lanes;
457 	if (csi2tx->num_lanes > csi2tx->max_lanes) {
458 		dev_err(csi2tx->dev,
459 			"Current configuration uses more lanes than supported\n");
460 		ret = -EINVAL;
461 		goto out;
462 	}
463 
464 	memcpy(csi2tx->lanes, v4l2_ep.bus.mipi_csi2.data_lanes,
465 	       sizeof(csi2tx->lanes));
466 
467 out:
468 	of_node_put(ep);
469 	return ret;
470 }
471 
472 static int csi2tx_probe(struct platform_device *pdev)
473 {
474 	struct csi2tx_priv *csi2tx;
475 	unsigned int i;
476 	int ret;
477 
478 	csi2tx = kzalloc(sizeof(*csi2tx), GFP_KERNEL);
479 	if (!csi2tx)
480 		return -ENOMEM;
481 	platform_set_drvdata(pdev, csi2tx);
482 	mutex_init(&csi2tx->lock);
483 	csi2tx->dev = &pdev->dev;
484 
485 	ret = csi2tx_get_resources(csi2tx, pdev);
486 	if (ret)
487 		goto err_free_priv;
488 
489 	v4l2_subdev_init(&csi2tx->subdev, &csi2tx_subdev_ops);
490 	csi2tx->subdev.owner = THIS_MODULE;
491 	csi2tx->subdev.dev = &pdev->dev;
492 	csi2tx->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
493 	snprintf(csi2tx->subdev.name, V4L2_SUBDEV_NAME_SIZE, "%s.%s",
494 		 KBUILD_MODNAME, dev_name(&pdev->dev));
495 
496 	ret = csi2tx_check_lanes(csi2tx);
497 	if (ret)
498 		goto err_free_priv;
499 
500 	/* Create our media pads */
501 	csi2tx->subdev.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
502 	csi2tx->pads[CSI2TX_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
503 	for (i = CSI2TX_PAD_SINK_STREAM0; i < CSI2TX_PAD_MAX; i++)
504 		csi2tx->pads[i].flags = MEDIA_PAD_FL_SINK;
505 
506 	/*
507 	 * Only the input pads are considered to have a format at the
508 	 * moment. The CSI link can multiplex various streams with
509 	 * different formats, and we can't expose this in v4l2 right
510 	 * now.
511 	 */
512 	for (i = CSI2TX_PAD_SINK_STREAM0; i < CSI2TX_PAD_MAX; i++)
513 		csi2tx->pad_fmts[i] = fmt_default;
514 
515 	ret = media_entity_pads_init(&csi2tx->subdev.entity, CSI2TX_PAD_MAX,
516 				     csi2tx->pads);
517 	if (ret)
518 		goto err_free_priv;
519 
520 	ret = v4l2_async_register_subdev(&csi2tx->subdev);
521 	if (ret < 0)
522 		goto err_free_priv;
523 
524 	dev_info(&pdev->dev,
525 		 "Probed CSI2TX with %u/%u lanes, %u streams, %s D-PHY\n",
526 		 csi2tx->num_lanes, csi2tx->max_lanes, csi2tx->max_streams,
527 		 csi2tx->has_internal_dphy ? "internal" : "no");
528 
529 	return 0;
530 
531 err_free_priv:
532 	kfree(csi2tx);
533 	return ret;
534 }
535 
536 static int csi2tx_remove(struct platform_device *pdev)
537 {
538 	struct csi2tx_priv *csi2tx = platform_get_drvdata(pdev);
539 
540 	v4l2_async_unregister_subdev(&csi2tx->subdev);
541 	kfree(csi2tx);
542 
543 	return 0;
544 }
545 
546 static const struct of_device_id csi2tx_of_table[] = {
547 	{ .compatible = "cdns,csi2tx" },
548 	{ },
549 };
550 MODULE_DEVICE_TABLE(of, csi2tx_of_table);
551 
552 static struct platform_driver csi2tx_driver = {
553 	.probe	= csi2tx_probe,
554 	.remove	= csi2tx_remove,
555 
556 	.driver	= {
557 		.name		= "cdns-csi2tx",
558 		.of_match_table	= csi2tx_of_table,
559 	},
560 };
561 module_platform_driver(csi2tx_driver);
562 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@bootlin.com>");
563 MODULE_DESCRIPTION("Cadence CSI2-TX controller");
564 MODULE_LICENSE("GPL");
565