1 // SPDX-License-Identifier: GPL-2.0-or-later 2 // Copyright 2020 IBM Corp. 3 // Copyright (c) 2019-2020 Intel Corporation 4 5 #include <linux/atomic.h> 6 #include <linux/bitfield.h> 7 #include <linux/cleanup.h> 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/device.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/interrupt.h> 13 #include <linux/jiffies.h> 14 #include <linux/module.h> 15 #include <linux/mutex.h> 16 #include <linux/of.h> 17 #include <linux/of_irq.h> 18 #include <linux/of_reserved_mem.h> 19 #include <linux/platform_device.h> 20 #include <linux/sched.h> 21 #include <linux/spinlock.h> 22 #include <linux/string.h> 23 #include <linux/v4l2-controls.h> 24 #include <linux/videodev2.h> 25 #include <linux/wait.h> 26 #include <linux/workqueue.h> 27 #include <linux/debugfs.h> 28 #include <linux/ktime.h> 29 #include <linux/reset.h> 30 #include <linux/regmap.h> 31 #include <linux/mfd/syscon.h> 32 #include <media/v4l2-ctrls.h> 33 #include <media/v4l2-dev.h> 34 #include <media/v4l2-device.h> 35 #include <media/v4l2-dv-timings.h> 36 #include <media/v4l2-event.h> 37 #include <media/v4l2-ioctl.h> 38 #include <media/videobuf2-dma-contig.h> 39 #include <uapi/linux/aspeed-video.h> 40 41 #define ASPEED_VIDEO_V4L2_MIN_BUF_REQ 3 42 43 #define DEVICE_NAME "aspeed-video" 44 45 #define ASPEED_VIDEO_JPEG_NUM_QUALITIES 12 46 #define ASPEED_VIDEO_JPEG_HEADER_SIZE 10 47 #define ASPEED_VIDEO_JPEG_QUANT_SIZE 116 48 #define ASPEED_VIDEO_JPEG_DCT_SIZE 34 49 50 #define MAX_FRAME_RATE 60 51 #define MAX_HEIGHT 1200 52 #define MAX_WIDTH 1920 53 #define MIN_HEIGHT 480 54 #define MIN_WIDTH 640 55 56 #define NUM_POLARITY_CHECKS 10 57 #define INVALID_RESOLUTION_RETRIES 2 58 #define INVALID_RESOLUTION_DELAY msecs_to_jiffies(250) 59 #define RESOLUTION_CHANGE_DELAY msecs_to_jiffies(500) 60 #define MODE_DETECT_TIMEOUT msecs_to_jiffies(500) 61 #define STOP_TIMEOUT msecs_to_jiffies(1000) 62 #define DIRECT_FETCH_THRESHOLD 0x0c0000 /* 1024 * 768 */ 63 64 #define VE_MAX_SRC_BUFFER_SIZE 0x8ca000 /* 1920 * 1200, 32bpp */ 65 #define VE_JPEG_HEADER_SIZE 0x006000 /* 512 * 12 * 4 */ 66 #define VE_BCD_BUFF_SIZE 0x9000 /* (1920/8) * (1200/8) */ 67 68 #define VE_PROTECTION_KEY 0x000 69 #define VE_PROTECTION_KEY_UNLOCK 0x1a038aa8 70 71 #define VE_SEQ_CTRL 0x004 72 #define VE_SEQ_CTRL_TRIG_MODE_DET BIT(0) 73 #define VE_SEQ_CTRL_TRIG_CAPTURE BIT(1) 74 #define VE_SEQ_CTRL_FORCE_IDLE BIT(2) 75 #define VE_SEQ_CTRL_MULT_FRAME BIT(3) 76 #define VE_SEQ_CTRL_TRIG_COMP BIT(4) 77 #define VE_SEQ_CTRL_AUTO_COMP BIT(5) 78 #define VE_SEQ_CTRL_EN_WATCHDOG BIT(7) 79 #define VE_SEQ_CTRL_YUV420 BIT(10) 80 #define VE_SEQ_CTRL_COMP_FMT GENMASK(11, 10) 81 #define VE_SEQ_CTRL_HALT BIT(12) 82 #define VE_SEQ_CTRL_EN_WATCHDOG_COMP BIT(14) 83 #define VE_SEQ_CTRL_TRIG_JPG BIT(15) 84 #define VE_SEQ_CTRL_CAP_BUSY BIT(16) 85 #define VE_SEQ_CTRL_COMP_BUSY BIT(18) 86 87 #define AST2500_VE_SEQ_CTRL_JPEG_MODE BIT(13) 88 #define AST2400_VE_SEQ_CTRL_JPEG_MODE BIT(8) 89 90 #define VE_CTRL 0x008 91 #define VE_CTRL_HSYNC_POL BIT(0) 92 #define VE_CTRL_VSYNC_POL BIT(1) 93 #define VE_CTRL_SOURCE BIT(2) 94 #define VE_CTRL_INT_DE BIT(4) 95 #define VE_CTRL_DIRECT_FETCH BIT(5) 96 #define VE_CTRL_CAPTURE_FMT GENMASK(7, 6) 97 #define VE_CTRL_AUTO_OR_CURSOR BIT(8) 98 #define VE_CTRL_CLK_INVERSE BIT(11) 99 #define VE_CTRL_CLK_DELAY GENMASK(11, 9) 100 #define VE_CTRL_INTERLACE BIT(14) 101 #define VE_CTRL_HSYNC_POL_CTRL BIT(15) 102 #define VE_CTRL_FRC GENMASK(23, 16) 103 104 #define VE_TGS_0 0x00c 105 #define VE_TGS_1 0x010 106 #define VE_TGS_FIRST GENMASK(28, 16) 107 #define VE_TGS_LAST GENMASK(12, 0) 108 109 #define VE_SCALING_FACTOR 0x014 110 #define VE_SCALING_FILTER0 0x018 111 #define VE_SCALING_FILTER1 0x01c 112 #define VE_SCALING_FILTER2 0x020 113 #define VE_SCALING_FILTER3 0x024 114 115 #define VE_BCD_CTRL 0x02C 116 #define VE_BCD_CTRL_EN_BCD BIT(0) 117 #define VE_BCD_CTRL_EN_ABCD BIT(1) 118 #define VE_BCD_CTRL_EN_CB BIT(2) 119 #define VE_BCD_CTRL_THR GENMASK(23, 16) 120 #define VE_BCD_CTRL_ABCD_THR GENMASK(31, 24) 121 122 #define VE_CAP_WINDOW 0x030 123 #define VE_COMP_WINDOW 0x034 124 #define VE_COMP_PROC_OFFSET 0x038 125 #define VE_COMP_OFFSET 0x03c 126 #define VE_JPEG_ADDR 0x040 127 #define VE_SRC0_ADDR 0x044 128 #define VE_SRC_SCANLINE_OFFSET 0x048 129 #define VE_SRC1_ADDR 0x04c 130 #define VE_BCD_ADDR 0x050 131 #define VE_COMP_ADDR 0x054 132 133 #define VE_STREAM_BUF_SIZE 0x058 134 #define VE_STREAM_BUF_SIZE_N_PACKETS GENMASK(5, 3) 135 #define VE_STREAM_BUF_SIZE_P_SIZE GENMASK(2, 0) 136 137 #define VE_COMP_CTRL 0x060 138 #define VE_COMP_CTRL_VQ_DCT_ONLY BIT(0) 139 #define VE_COMP_CTRL_VQ_4COLOR BIT(1) 140 #define VE_COMP_CTRL_QUANTIZE BIT(2) 141 #define VE_COMP_CTRL_EN_BQ BIT(4) 142 #define VE_COMP_CTRL_EN_CRYPTO BIT(5) 143 #define VE_COMP_CTRL_DCT_CHR GENMASK(10, 6) 144 #define VE_COMP_CTRL_DCT_LUM GENMASK(15, 11) 145 #define VE_COMP_CTRL_EN_HQ BIT(16) 146 #define VE_COMP_CTRL_RSVD BIT(19) 147 #define VE_COMP_CTRL_ENCODE GENMASK(21, 20) 148 #define VE_COMP_CTRL_HQ_DCT_CHR GENMASK(26, 22) 149 #define VE_COMP_CTRL_HQ_DCT_LUM GENMASK(31, 27) 150 151 #define VE_CB_ADDR 0x06C 152 153 #define AST2400_VE_COMP_SIZE_READ_BACK 0x078 154 #define AST2600_VE_COMP_SIZE_READ_BACK 0x084 155 156 #define VE_SRC_LR_EDGE_DET 0x090 157 #define VE_SRC_LR_EDGE_DET_LEFT GENMASK(11, 0) 158 #define VE_SRC_LR_EDGE_DET_NO_V BIT(12) 159 #define VE_SRC_LR_EDGE_DET_NO_H BIT(13) 160 #define VE_SRC_LR_EDGE_DET_NO_DISP BIT(14) 161 #define VE_SRC_LR_EDGE_DET_NO_CLK BIT(15) 162 #define VE_SRC_LR_EDGE_DET_RT GENMASK(27, 16) 163 #define VE_SRC_LR_EDGE_DET_INTERLACE BIT(31) 164 165 #define VE_SRC_TB_EDGE_DET 0x094 166 #define VE_SRC_TB_EDGE_DET_TOP GENMASK(12, 0) 167 #define VE_SRC_TB_EDGE_DET_BOT GENMASK(28, 16) 168 169 #define VE_MODE_DETECT_STATUS 0x098 170 #define VE_MODE_DETECT_H_PERIOD GENMASK(11, 0) 171 #define VE_MODE_DETECT_EXTSRC_ADC BIT(12) 172 #define VE_MODE_DETECT_H_STABLE BIT(13) 173 #define VE_MODE_DETECT_V_STABLE BIT(14) 174 #define VE_MODE_DETECT_V_LINES GENMASK(27, 16) 175 #define VE_MODE_DETECT_STATUS_VSYNC BIT(28) 176 #define VE_MODE_DETECT_STATUS_HSYNC BIT(29) 177 #define VE_MODE_DETECT_VSYNC_RDY BIT(30) 178 #define VE_MODE_DETECT_HSYNC_RDY BIT(31) 179 180 #define VE_SYNC_STATUS 0x09c 181 #define VE_SYNC_STATUS_HSYNC GENMASK(11, 0) 182 #define VE_SYNC_STATUS_VSYNC GENMASK(27, 16) 183 184 #define VE_H_TOTAL_PIXELS 0x0A0 185 186 #define VE_INTERRUPT_CTRL 0x304 187 #define VE_INTERRUPT_STATUS 0x308 188 #define VE_INTERRUPT_MODE_DETECT_WD BIT(0) 189 #define VE_INTERRUPT_CAPTURE_COMPLETE BIT(1) 190 #define VE_INTERRUPT_COMP_READY BIT(2) 191 #define VE_INTERRUPT_COMP_COMPLETE BIT(3) 192 #define VE_INTERRUPT_MODE_DETECT BIT(4) 193 #define VE_INTERRUPT_FRAME_COMPLETE BIT(5) 194 #define VE_INTERRUPT_DECODE_ERR BIT(6) 195 #define VE_INTERRUPT_HALT_READY BIT(8) 196 #define VE_INTERRUPT_HANG_WD BIT(9) 197 #define VE_INTERRUPT_STREAM_DESC BIT(10) 198 #define VE_INTERRUPT_VSYNC_DESC BIT(11) 199 200 #define VE_MODE_DETECT 0x30c 201 #define VE_MODE_DT_HOR_TOLER GENMASK(31, 28) 202 #define VE_MODE_DT_VER_TOLER GENMASK(27, 24) 203 #define VE_MODE_DT_HOR_STABLE GENMASK(23, 20) 204 #define VE_MODE_DT_VER_STABLE GENMASK(19, 16) 205 #define VE_MODE_DT_EDG_THROD GENMASK(15, 8) 206 207 #define VE_MEM_RESTRICT_START 0x310 208 #define VE_MEM_RESTRICT_END 0x314 209 210 /* SCU's registers */ 211 #define SCU_MISC_CTRL 0xC0 212 #define SCU_DPLL_SOURCE BIT(20) 213 214 /* GFX's registers */ 215 #define GFX_CTRL 0x60 216 #define GFX_CTRL_ENABLE BIT(0) 217 #define GFX_CTRL_FMT GENMASK(9, 7) 218 219 #define GFX_H_DISPLAY 0x70 220 #define GFX_H_DISPLAY_DE GENMASK(28, 16) 221 #define GFX_H_DISPLAY_TOTAL GENMASK(12, 0) 222 223 #define GFX_V_DISPLAY 0x78 224 #define GFX_V_DISPLAY_DE GENMASK(27, 16) 225 #define GFX_V_DISPLAY_TOTAL GENMASK(11, 0) 226 227 #define GFX_DISPLAY_ADDR 0x80 228 229 /* 230 * VIDEO_MODE_DETECT_DONE: a flag raised if signal lock 231 * VIDEO_RES_CHANGE: a flag raised if res_change work on-going 232 * VIDEO_RES_DETECT: a flag raised if res. detection on-going 233 * VIDEO_STREAMING: a flag raised if user requires stream-on 234 * VIDEO_FRAME_INPRG: a flag raised if hw working on a frame 235 * VIDEO_STOPPED: a flag raised if device release 236 * VIDEO_CLOCKS_ON: a flag raised if clk is on 237 */ 238 enum { 239 VIDEO_MODE_DETECT_DONE, 240 VIDEO_RES_CHANGE, 241 VIDEO_RES_DETECT, 242 VIDEO_STREAMING, 243 VIDEO_FRAME_INPRG, 244 VIDEO_STOPPED, 245 VIDEO_CLOCKS_ON, 246 }; 247 248 enum aspeed_video_format { 249 VIDEO_FMT_STANDARD = 0, 250 VIDEO_FMT_ASPEED, 251 VIDEO_FMT_MAX = VIDEO_FMT_ASPEED 252 }; 253 254 // for VE_CTRL_CAPTURE_FMT 255 enum aspeed_video_capture_format { 256 VIDEO_CAP_FMT_YUV_STUDIO_SWING = 0, 257 VIDEO_CAP_FMT_YUV_FULL_SWING, 258 VIDEO_CAP_FMT_RGB, 259 VIDEO_CAP_FMT_GRAY, 260 VIDEO_CAP_FMT_MAX 261 }; 262 263 struct aspeed_video_addr { 264 unsigned int size; 265 dma_addr_t dma; 266 void *virt; 267 }; 268 269 struct aspeed_video_buffer { 270 struct vb2_v4l2_buffer vb; 271 struct list_head link; 272 }; 273 274 struct aspeed_video_perf { 275 ktime_t last_sample; 276 u32 totaltime; 277 u32 duration; 278 u32 duration_min; 279 u32 duration_max; 280 }; 281 282 #define to_aspeed_video_buffer(x) \ 283 container_of((x), struct aspeed_video_buffer, vb) 284 285 /* 286 * struct aspeed_video - driver data 287 * 288 * version: holds the version of aspeed SoC 289 * res_work: holds the delayed_work for res-detection if unlock 290 * buffers: holds the list of buffer queued from user 291 * flags: holds the state of video 292 * sequence: holds the last number of frame completed 293 * max_compressed_size: holds max compressed stream's size 294 * srcs: holds the buffer information for srcs 295 * jpeg: holds the buffer information for jpeg header 296 * bcd: holds the buffer information for bcd work 297 * yuv420: a flag raised if JPEG subsampling is 420 298 * format: holds the video format 299 * hq_mode: a flag raised if HQ is enabled. Only for VIDEO_FMT_ASPEED 300 * input: holds the video input 301 * frame_rate: holds the frame_rate 302 * jpeg_quality: holds jpeq's quality (0~11) 303 * jpeg_hq_quality: holds hq's quality (1~12) only if hq_mode enabled 304 * frame_bottom: end position of video data in vertical direction 305 * frame_left: start position of video data in horizontal direction 306 * frame_right: end position of video data in horizontal direction 307 * frame_top: start position of video data in vertical direction 308 * perf: holds the statistics primary for debugfs 309 */ 310 struct aspeed_video { 311 void __iomem *base; 312 struct clk *eclk; 313 struct clk *vclk; 314 struct reset_control *reset; 315 316 struct device *dev; 317 struct v4l2_ctrl_handler ctrl_handler; 318 struct v4l2_device v4l2_dev; 319 struct v4l2_pix_format pix_fmt; 320 struct v4l2_bt_timings active_timings; 321 struct v4l2_bt_timings detected_timings; 322 u32 v4l2_input_status; 323 struct vb2_queue queue; 324 struct video_device vdev; 325 struct mutex video_lock; /* v4l2 and videobuf2 lock */ 326 327 struct regmap *scu; 328 struct regmap *gfx; 329 u32 version; 330 u32 jpeg_mode; 331 u32 comp_size_read; 332 333 wait_queue_head_t wait; 334 spinlock_t lock; /* buffer list lock */ 335 struct delayed_work res_work; 336 struct list_head buffers; 337 unsigned long flags; 338 unsigned int sequence; 339 340 unsigned int max_compressed_size; 341 struct aspeed_video_addr srcs[2]; 342 struct aspeed_video_addr jpeg; 343 struct aspeed_video_addr bcd; 344 345 bool yuv420; 346 enum aspeed_video_format format; 347 bool hq_mode; 348 enum aspeed_video_input input; 349 unsigned int frame_rate; 350 unsigned int jpeg_quality; 351 unsigned int jpeg_hq_quality; 352 353 unsigned int frame_bottom; 354 unsigned int frame_left; 355 unsigned int frame_right; 356 unsigned int frame_top; 357 358 struct aspeed_video_perf perf; 359 }; 360 361 #define to_aspeed_video(x) container_of((x), struct aspeed_video, v4l2_dev) 362 363 struct aspeed_video_config { 364 u32 version; 365 u32 jpeg_mode; 366 u32 comp_size_read; 367 }; 368 369 static const struct aspeed_video_config ast2400_config = { 370 .version = 4, 371 .jpeg_mode = AST2400_VE_SEQ_CTRL_JPEG_MODE, 372 .comp_size_read = AST2400_VE_COMP_SIZE_READ_BACK, 373 }; 374 375 static const struct aspeed_video_config ast2500_config = { 376 .version = 5, 377 .jpeg_mode = AST2500_VE_SEQ_CTRL_JPEG_MODE, 378 .comp_size_read = AST2400_VE_COMP_SIZE_READ_BACK, 379 }; 380 381 static const struct aspeed_video_config ast2600_config = { 382 .version = 6, 383 .jpeg_mode = AST2500_VE_SEQ_CTRL_JPEG_MODE, 384 .comp_size_read = AST2600_VE_COMP_SIZE_READ_BACK, 385 }; 386 387 static const u32 aspeed_video_jpeg_header[ASPEED_VIDEO_JPEG_HEADER_SIZE] = { 388 0xe0ffd8ff, 0x464a1000, 0x01004649, 0x60000101, 0x00006000, 0x0f00feff, 389 0x00002d05, 0x00000000, 0x00000000, 0x00dbff00 390 }; 391 392 static const u32 aspeed_video_jpeg_quant[ASPEED_VIDEO_JPEG_QUANT_SIZE] = { 393 0x081100c0, 0x00000000, 0x00110103, 0x03011102, 0xc4ff0111, 0x00001f00, 394 0x01010501, 0x01010101, 0x00000000, 0x00000000, 0x04030201, 0x08070605, 395 0xff0b0a09, 0x10b500c4, 0x03010200, 0x03040203, 0x04040505, 0x7d010000, 396 0x00030201, 0x12051104, 0x06413121, 0x07615113, 0x32147122, 0x08a19181, 397 0xc1b14223, 0xf0d15215, 0x72623324, 0x160a0982, 0x1a191817, 0x28272625, 398 0x35342a29, 0x39383736, 0x4544433a, 0x49484746, 0x5554534a, 0x59585756, 399 0x6564635a, 0x69686766, 0x7574736a, 0x79787776, 0x8584837a, 0x89888786, 400 0x9493928a, 0x98979695, 0xa3a29a99, 0xa7a6a5a4, 0xb2aaa9a8, 0xb6b5b4b3, 401 0xbab9b8b7, 0xc5c4c3c2, 0xc9c8c7c6, 0xd4d3d2ca, 0xd8d7d6d5, 0xe2e1dad9, 402 0xe6e5e4e3, 0xeae9e8e7, 0xf4f3f2f1, 0xf8f7f6f5, 0xc4fffaf9, 0x00011f00, 403 0x01010103, 0x01010101, 0x00000101, 0x00000000, 0x04030201, 0x08070605, 404 0xff0b0a09, 0x11b500c4, 0x02010200, 0x04030404, 0x04040507, 0x77020100, 405 0x03020100, 0x21050411, 0x41120631, 0x71610751, 0x81322213, 0x91421408, 406 0x09c1b1a1, 0xf0523323, 0xd1726215, 0x3424160a, 0x17f125e1, 0x261a1918, 407 0x2a292827, 0x38373635, 0x44433a39, 0x48474645, 0x54534a49, 0x58575655, 408 0x64635a59, 0x68676665, 0x74736a69, 0x78777675, 0x83827a79, 0x87868584, 409 0x928a8988, 0x96959493, 0x9a999897, 0xa5a4a3a2, 0xa9a8a7a6, 0xb4b3b2aa, 410 0xb8b7b6b5, 0xc3c2bab9, 0xc7c6c5c4, 0xd2cac9c8, 0xd6d5d4d3, 0xdad9d8d7, 411 0xe5e4e3e2, 0xe9e8e7e6, 0xf4f3f2ea, 0xf8f7f6f5, 0xdafffaf9, 0x01030c00, 412 0x03110200, 0x003f0011 413 }; 414 415 static const u32 aspeed_video_jpeg_dct[ASPEED_VIDEO_JPEG_NUM_QUALITIES] 416 [ASPEED_VIDEO_JPEG_DCT_SIZE] = { 417 { 0x0d140043, 0x0c0f110f, 0x11101114, 0x17141516, 0x1e20321e, 418 0x3d1e1b1b, 0x32242e2b, 0x4b4c3f48, 0x44463f47, 0x61735a50, 419 0x566c5550, 0x88644644, 0x7a766c65, 0x4d808280, 0x8c978d60, 420 0x7e73967d, 0xdbff7b80, 0x1f014300, 0x272d2121, 0x3030582d, 421 0x697bb958, 0xb8b9b97b, 0xb9b8a6a6, 0xb9b9b9b9, 0xb9b9b9b9, 422 0xb9b9b9b9, 0xb9b9b9b9, 0xb9b9b9b9, 0xb9b9b9b9, 0xb9b9b9b9, 423 0xb9b9b9b9, 0xb9b9b9b9, 0xb9b9b9b9, 0xffb9b9b9 }, 424 { 0x0c110043, 0x0a0d0f0d, 0x0f0e0f11, 0x14111213, 0x1a1c2b1a, 425 0x351a1818, 0x2b1f2826, 0x4142373f, 0x3c3d373e, 0x55644e46, 426 0x4b5f4a46, 0x77573d3c, 0x6b675f58, 0x43707170, 0x7a847b54, 427 0x6e64836d, 0xdbff6c70, 0x1b014300, 0x22271d1d, 0x2a2a4c27, 428 0x5b6ba04c, 0xa0a0a06b, 0xa0a0a0a0, 0xa0a0a0a0, 0xa0a0a0a0, 429 0xa0a0a0a0, 0xa0a0a0a0, 0xa0a0a0a0, 0xa0a0a0a0, 0xa0a0a0a0, 430 0xa0a0a0a0, 0xa0a0a0a0, 0xa0a0a0a0, 0xffa0a0a0 }, 431 { 0x090e0043, 0x090a0c0a, 0x0c0b0c0e, 0x110e0f10, 0x15172415, 432 0x2c151313, 0x241a211f, 0x36372e34, 0x31322e33, 0x4653413a, 433 0x3e4e3d3a, 0x62483231, 0x58564e49, 0x385d5e5d, 0x656d6645, 434 0x5b536c5a, 0xdbff595d, 0x16014300, 0x1c201818, 0x22223f20, 435 0x4b58853f, 0x85858558, 0x85858585, 0x85858585, 0x85858585, 436 0x85858585, 0x85858585, 0x85858585, 0x85858585, 0x85858585, 437 0x85858585, 0x85858585, 0x85858585, 0xff858585 }, 438 { 0x070b0043, 0x07080a08, 0x0a090a0b, 0x0d0b0c0c, 0x11121c11, 439 0x23110f0f, 0x1c141a19, 0x2b2b2429, 0x27282428, 0x3842332e, 440 0x313e302e, 0x4e392827, 0x46443e3a, 0x2c4a4a4a, 0x50565137, 441 0x48425647, 0xdbff474a, 0x12014300, 0x161a1313, 0x1c1c331a, 442 0x3d486c33, 0x6c6c6c48, 0x6c6c6c6c, 0x6c6c6c6c, 0x6c6c6c6c, 443 0x6c6c6c6c, 0x6c6c6c6c, 0x6c6c6c6c, 0x6c6c6c6c, 0x6c6c6c6c, 444 0x6c6c6c6c, 0x6c6c6c6c, 0x6c6c6c6c, 0xff6c6c6c }, 445 { 0x06090043, 0x05060706, 0x07070709, 0x0a09090a, 0x0d0e160d, 446 0x1b0d0c0c, 0x16101413, 0x21221c20, 0x1e1f1c20, 0x2b332824, 447 0x26302624, 0x3d2d1f1e, 0x3735302d, 0x22393a39, 0x3f443f2b, 448 0x38334338, 0xdbff3739, 0x0d014300, 0x11130e0e, 0x15152613, 449 0x2d355026, 0x50505035, 0x50505050, 0x50505050, 0x50505050, 450 0x50505050, 0x50505050, 0x50505050, 0x50505050, 0x50505050, 451 0x50505050, 0x50505050, 0x50505050, 0xff505050 }, 452 { 0x04060043, 0x03040504, 0x05040506, 0x07060606, 0x09090f09, 453 0x12090808, 0x0f0a0d0d, 0x16161315, 0x14151315, 0x1d221b18, 454 0x19201918, 0x281e1514, 0x2423201e, 0x17262726, 0x2a2d2a1c, 455 0x25222d25, 0xdbff2526, 0x09014300, 0x0b0d0a0a, 0x0e0e1a0d, 456 0x1f25371a, 0x37373725, 0x37373737, 0x37373737, 0x37373737, 457 0x37373737, 0x37373737, 0x37373737, 0x37373737, 0x37373737, 458 0x37373737, 0x37373737, 0x37373737, 0xff373737 }, 459 { 0x02030043, 0x01020202, 0x02020203, 0x03030303, 0x04040704, 460 0x09040404, 0x07050606, 0x0b0b090a, 0x0a0a090a, 0x0e110d0c, 461 0x0c100c0c, 0x140f0a0a, 0x1211100f, 0x0b131313, 0x1516150e, 462 0x12111612, 0xdbff1213, 0x04014300, 0x05060505, 0x07070d06, 463 0x0f121b0d, 0x1b1b1b12, 0x1b1b1b1b, 0x1b1b1b1b, 0x1b1b1b1b, 464 0x1b1b1b1b, 0x1b1b1b1b, 0x1b1b1b1b, 0x1b1b1b1b, 0x1b1b1b1b, 465 0x1b1b1b1b, 0x1b1b1b1b, 0x1b1b1b1b, 0xff1b1b1b }, 466 { 0x01020043, 0x01010101, 0x01010102, 0x02020202, 0x03030503, 467 0x06030202, 0x05030404, 0x07070607, 0x06070607, 0x090b0908, 468 0x080a0808, 0x0d0a0706, 0x0c0b0a0a, 0x070c0d0c, 0x0e0f0e09, 469 0x0c0b0f0c, 0xdbff0c0c, 0x03014300, 0x03040303, 0x04040804, 470 0x0a0c1208, 0x1212120c, 0x12121212, 0x12121212, 0x12121212, 471 0x12121212, 0x12121212, 0x12121212, 0x12121212, 0x12121212, 472 0x12121212, 0x12121212, 0x12121212, 0xff121212 }, 473 { 0x01020043, 0x01010101, 0x01010102, 0x02020202, 0x03030503, 474 0x06030202, 0x05030404, 0x07070607, 0x06070607, 0x090b0908, 475 0x080a0808, 0x0d0a0706, 0x0c0b0a0a, 0x070c0d0c, 0x0e0f0e09, 476 0x0c0b0f0c, 0xdbff0c0c, 0x02014300, 0x03030202, 0x04040703, 477 0x080a0f07, 0x0f0f0f0a, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 478 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 479 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0xff0f0f0f }, 480 { 0x01010043, 0x01010101, 0x01010101, 0x01010101, 0x02020302, 481 0x04020202, 0x03020303, 0x05050405, 0x05050405, 0x07080606, 482 0x06080606, 0x0a070505, 0x09080807, 0x05090909, 0x0a0b0a07, 483 0x09080b09, 0xdbff0909, 0x02014300, 0x02030202, 0x03030503, 484 0x07080c05, 0x0c0c0c08, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 485 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 486 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0xff0c0c0c }, 487 { 0x01010043, 0x01010101, 0x01010101, 0x01010101, 0x01010201, 488 0x03010101, 0x02010202, 0x03030303, 0x03030303, 0x04050404, 489 0x04050404, 0x06050303, 0x06050505, 0x03060606, 0x07070704, 490 0x06050706, 0xdbff0606, 0x01014300, 0x01020101, 0x02020402, 491 0x05060904, 0x09090906, 0x09090909, 0x09090909, 0x09090909, 492 0x09090909, 0x09090909, 0x09090909, 0x09090909, 0x09090909, 493 0x09090909, 0x09090909, 0x09090909, 0xff090909 }, 494 { 0x01010043, 0x01010101, 0x01010101, 0x01010101, 0x01010101, 495 0x01010101, 0x01010101, 0x01010101, 0x01010101, 0x02020202, 496 0x02020202, 0x03020101, 0x03020202, 0x01030303, 0x03030302, 497 0x03020303, 0xdbff0403, 0x01014300, 0x01010101, 0x01010201, 498 0x03040602, 0x06060604, 0x06060606, 0x06060606, 0x06060606, 499 0x06060606, 0x06060606, 0x06060606, 0x06060606, 0x06060606, 500 0x06060606, 0x06060606, 0x06060606, 0xff060606 } 501 }; 502 503 static const struct v4l2_dv_timings_cap aspeed_video_timings_cap = { 504 .type = V4L2_DV_BT_656_1120, 505 .bt = { 506 .min_width = MIN_WIDTH, 507 .max_width = MAX_WIDTH, 508 .min_height = MIN_HEIGHT, 509 .max_height = MAX_HEIGHT, 510 .min_pixelclock = 6574080, /* 640 x 480 x 24Hz */ 511 .max_pixelclock = 138240000, /* 1920 x 1200 x 60Hz */ 512 .standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | 513 V4L2_DV_BT_STD_CVT | V4L2_DV_BT_STD_GTF, 514 .capabilities = V4L2_DV_BT_CAP_PROGRESSIVE | 515 V4L2_DV_BT_CAP_REDUCED_BLANKING | 516 V4L2_DV_BT_CAP_CUSTOM, 517 }, 518 }; 519 520 static const char * const format_str[] = {"Standard JPEG", 521 "Aspeed JPEG"}; 522 static const char * const input_str[] = {"HOST VGA", "BMC GFX"}; 523 524 static unsigned int debug; 525 526 static bool aspeed_video_alloc_buf(struct aspeed_video *video, 527 struct aspeed_video_addr *addr, 528 unsigned int size); 529 530 static void aspeed_video_free_buf(struct aspeed_video *video, 531 struct aspeed_video_addr *addr); 532 533 static void aspeed_video_init_jpeg_table(u32 *table, bool yuv420) 534 { 535 int i; 536 unsigned int base; 537 538 for (i = 0; i < ASPEED_VIDEO_JPEG_NUM_QUALITIES; i++) { 539 base = 256 * i; /* AST HW requires this header spacing */ 540 memcpy(&table[base], aspeed_video_jpeg_header, 541 sizeof(aspeed_video_jpeg_header)); 542 543 base += ASPEED_VIDEO_JPEG_HEADER_SIZE; 544 memcpy(&table[base], aspeed_video_jpeg_dct[i], 545 sizeof(aspeed_video_jpeg_dct[i])); 546 547 base += ASPEED_VIDEO_JPEG_DCT_SIZE; 548 memcpy(&table[base], aspeed_video_jpeg_quant, 549 sizeof(aspeed_video_jpeg_quant)); 550 551 if (yuv420) 552 table[base + 2] = 0x00220103; 553 } 554 } 555 556 // just update jpeg dct table per 420/444 557 static void aspeed_video_update_jpeg_table(u32 *table, bool yuv420) 558 { 559 int i; 560 unsigned int base; 561 562 for (i = 0; i < ASPEED_VIDEO_JPEG_NUM_QUALITIES; i++) { 563 base = 256 * i; /* AST HW requires this header spacing */ 564 base += ASPEED_VIDEO_JPEG_HEADER_SIZE + 565 ASPEED_VIDEO_JPEG_DCT_SIZE; 566 567 table[base + 2] = (yuv420) ? 0x00220103 : 0x00110103; 568 } 569 } 570 571 static void aspeed_video_update(struct aspeed_video *video, u32 reg, u32 clear, 572 u32 bits) 573 { 574 u32 t = readl(video->base + reg); 575 u32 before = t; 576 577 t &= ~clear; 578 t |= bits; 579 writel(t, video->base + reg); 580 v4l2_dbg(3, debug, &video->v4l2_dev, "update %03x[%08x -> %08x]\n", 581 reg, before, readl(video->base + reg)); 582 } 583 584 static u32 aspeed_video_read(struct aspeed_video *video, u32 reg) 585 { 586 u32 t = readl(video->base + reg); 587 588 v4l2_dbg(3, debug, &video->v4l2_dev, "read %03x[%08x]\n", reg, t); 589 return t; 590 } 591 592 static void aspeed_video_write(struct aspeed_video *video, u32 reg, u32 val) 593 { 594 writel(val, video->base + reg); 595 v4l2_dbg(3, debug, &video->v4l2_dev, "write %03x[%08x]\n", reg, 596 readl(video->base + reg)); 597 } 598 599 static void update_perf(struct aspeed_video_perf *p) 600 { 601 struct aspeed_video *v = container_of(p, struct aspeed_video, 602 perf); 603 604 p->duration = 605 ktime_to_ms(ktime_sub(ktime_get(), p->last_sample)); 606 p->totaltime += p->duration; 607 608 p->duration_max = max(p->duration, p->duration_max); 609 p->duration_min = min(p->duration, p->duration_min); 610 v4l2_dbg(2, debug, &v->v4l2_dev, "time consumed: %d ms\n", 611 p->duration); 612 } 613 614 static int aspeed_video_start_frame(struct aspeed_video *video) 615 { 616 dma_addr_t addr; 617 unsigned long flags; 618 struct aspeed_video_buffer *buf; 619 u32 seq_ctrl = aspeed_video_read(video, VE_SEQ_CTRL); 620 bool bcd_buf_need = (video->format != VIDEO_FMT_STANDARD); 621 622 if (video->v4l2_input_status) { 623 v4l2_dbg(1, debug, &video->v4l2_dev, "No signal; don't start frame\n"); 624 return 0; 625 } 626 627 if (!(seq_ctrl & VE_SEQ_CTRL_COMP_BUSY) || 628 !(seq_ctrl & VE_SEQ_CTRL_CAP_BUSY)) { 629 v4l2_dbg(1, debug, &video->v4l2_dev, "Engine busy; don't start frame\n"); 630 return -EBUSY; 631 } 632 633 if (bcd_buf_need && !video->bcd.size) { 634 if (!aspeed_video_alloc_buf(video, &video->bcd, 635 VE_BCD_BUFF_SIZE)) { 636 dev_err(video->dev, "Failed to allocate BCD buffer\n"); 637 dev_err(video->dev, "don't start frame\n"); 638 return -ENOMEM; 639 } 640 aspeed_video_write(video, VE_BCD_ADDR, video->bcd.dma); 641 v4l2_dbg(1, debug, &video->v4l2_dev, "bcd addr(%pad) size(%d)\n", 642 &video->bcd.dma, video->bcd.size); 643 } else if (!bcd_buf_need && video->bcd.size) { 644 aspeed_video_free_buf(video, &video->bcd); 645 } 646 647 if (video->input == VIDEO_INPUT_GFX) { 648 u32 val; 649 650 // update input buffer address as gfx's 651 regmap_read(video->gfx, GFX_DISPLAY_ADDR, &val); 652 aspeed_video_write(video, VE_TGS_0, val); 653 } 654 655 spin_lock_irqsave(&video->lock, flags); 656 buf = list_first_entry_or_null(&video->buffers, 657 struct aspeed_video_buffer, link); 658 if (!buf) { 659 spin_unlock_irqrestore(&video->lock, flags); 660 v4l2_dbg(1, debug, &video->v4l2_dev, "No buffers; don't start frame\n"); 661 return -EPROTO; 662 } 663 664 set_bit(VIDEO_FRAME_INPRG, &video->flags); 665 addr = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0); 666 spin_unlock_irqrestore(&video->lock, flags); 667 668 aspeed_video_write(video, VE_COMP_PROC_OFFSET, 0); 669 aspeed_video_write(video, VE_COMP_OFFSET, 0); 670 aspeed_video_write(video, VE_COMP_ADDR, addr); 671 672 aspeed_video_update(video, VE_INTERRUPT_CTRL, 0, 673 VE_INTERRUPT_COMP_COMPLETE); 674 675 video->perf.last_sample = ktime_get(); 676 677 aspeed_video_update(video, VE_SEQ_CTRL, 0, 678 VE_SEQ_CTRL_TRIG_CAPTURE | VE_SEQ_CTRL_TRIG_COMP); 679 680 return 0; 681 } 682 683 static void aspeed_video_enable_mode_detect(struct aspeed_video *video) 684 { 685 /* Enable mode detect interrupts */ 686 aspeed_video_update(video, VE_INTERRUPT_CTRL, 0, 687 VE_INTERRUPT_MODE_DETECT); 688 689 /* Disable mode detect in order to re-trigger */ 690 aspeed_video_update(video, VE_SEQ_CTRL, 691 VE_SEQ_CTRL_TRIG_MODE_DET, 0); 692 693 /* Trigger mode detect */ 694 aspeed_video_update(video, VE_SEQ_CTRL, 0, VE_SEQ_CTRL_TRIG_MODE_DET); 695 } 696 697 static void aspeed_video_off(struct aspeed_video *video) 698 { 699 if (!test_bit(VIDEO_CLOCKS_ON, &video->flags)) 700 return; 701 702 /* Disable interrupts */ 703 aspeed_video_write(video, VE_INTERRUPT_CTRL, 0); 704 aspeed_video_write(video, VE_INTERRUPT_STATUS, 0xffffffff); 705 706 /* Turn off the relevant clocks */ 707 clk_disable(video->eclk); 708 clk_disable(video->vclk); 709 710 clear_bit(VIDEO_CLOCKS_ON, &video->flags); 711 } 712 713 static void aspeed_video_on(struct aspeed_video *video) 714 { 715 if (test_bit(VIDEO_CLOCKS_ON, &video->flags)) 716 return; 717 718 /* Turn on the relevant clocks */ 719 clk_enable(video->vclk); 720 clk_enable(video->eclk); 721 722 set_bit(VIDEO_CLOCKS_ON, &video->flags); 723 } 724 725 static void aspeed_video_reset(struct aspeed_video *v) 726 { 727 reset_control_assert(v->reset); 728 usleep_range(100, 150); 729 reset_control_deassert(v->reset); 730 } 731 732 static void aspeed_video_bufs_done(struct aspeed_video *video, 733 enum vb2_buffer_state state) 734 { 735 unsigned long flags; 736 struct aspeed_video_buffer *buf; 737 738 spin_lock_irqsave(&video->lock, flags); 739 list_for_each_entry(buf, &video->buffers, link) 740 vb2_buffer_done(&buf->vb.vb2_buf, state); 741 INIT_LIST_HEAD(&video->buffers); 742 spin_unlock_irqrestore(&video->lock, flags); 743 } 744 745 static void aspeed_video_irq_res_change(struct aspeed_video *video, ulong delay) 746 { 747 v4l2_dbg(1, debug, &video->v4l2_dev, "Resolution changed; resetting\n"); 748 749 set_bit(VIDEO_RES_CHANGE, &video->flags); 750 clear_bit(VIDEO_FRAME_INPRG, &video->flags); 751 752 video->v4l2_input_status = V4L2_IN_ST_NO_SIGNAL; 753 754 aspeed_video_write(video, VE_INTERRUPT_CTRL, 0); 755 aspeed_video_write(video, VE_INTERRUPT_STATUS, 0xffffffff); 756 aspeed_video_reset(video); 757 aspeed_video_bufs_done(video, VB2_BUF_STATE_ERROR); 758 759 schedule_delayed_work(&video->res_work, delay); 760 } 761 762 static void aspeed_video_swap_src_buf(struct aspeed_video *v) 763 { 764 if (v->format == VIDEO_FMT_STANDARD) 765 return; 766 767 /* Reset bcd buffer to have a full frame update every 8 frames. */ 768 if (IS_ALIGNED(v->sequence, 8)) 769 memset((u8 *)v->bcd.virt, 0x00, VE_BCD_BUFF_SIZE); 770 771 if (v->sequence & 0x01) { 772 aspeed_video_write(v, VE_SRC0_ADDR, v->srcs[1].dma); 773 aspeed_video_write(v, VE_SRC1_ADDR, v->srcs[0].dma); 774 } else { 775 aspeed_video_write(v, VE_SRC0_ADDR, v->srcs[0].dma); 776 aspeed_video_write(v, VE_SRC1_ADDR, v->srcs[1].dma); 777 } 778 } 779 780 static irqreturn_t aspeed_video_irq(int irq, void *arg) 781 { 782 struct aspeed_video *video = arg; 783 u32 sts = aspeed_video_read(video, VE_INTERRUPT_STATUS); 784 785 /* 786 * Hardware sometimes asserts interrupts that we haven't actually 787 * enabled; ignore them if so. 788 */ 789 sts &= aspeed_video_read(video, VE_INTERRUPT_CTRL); 790 791 v4l2_dbg(2, debug, &video->v4l2_dev, "irq sts=%#x %s%s%s%s\n", sts, 792 sts & VE_INTERRUPT_MODE_DETECT_WD ? ", unlock" : "", 793 sts & VE_INTERRUPT_MODE_DETECT ? ", lock" : "", 794 sts & VE_INTERRUPT_CAPTURE_COMPLETE ? ", capture-done" : "", 795 sts & VE_INTERRUPT_COMP_COMPLETE ? ", comp-done" : ""); 796 797 /* 798 * Resolution changed or signal was lost; reset the engine and 799 * re-initialize 800 */ 801 if (sts & VE_INTERRUPT_MODE_DETECT_WD) { 802 aspeed_video_irq_res_change(video, 0); 803 return IRQ_HANDLED; 804 } 805 806 if (sts & VE_INTERRUPT_MODE_DETECT) { 807 if (test_bit(VIDEO_RES_DETECT, &video->flags)) { 808 aspeed_video_update(video, VE_INTERRUPT_CTRL, 809 VE_INTERRUPT_MODE_DETECT, 0); 810 aspeed_video_write(video, VE_INTERRUPT_STATUS, 811 VE_INTERRUPT_MODE_DETECT); 812 sts &= ~VE_INTERRUPT_MODE_DETECT; 813 set_bit(VIDEO_MODE_DETECT_DONE, &video->flags); 814 wake_up_interruptible_all(&video->wait); 815 } else { 816 /* 817 * Signal acquired while NOT doing resolution 818 * detection; reset the engine and re-initialize 819 */ 820 aspeed_video_irq_res_change(video, 821 RESOLUTION_CHANGE_DELAY); 822 return IRQ_HANDLED; 823 } 824 } 825 826 if (sts & VE_INTERRUPT_COMP_COMPLETE) { 827 struct aspeed_video_buffer *buf; 828 bool empty = true; 829 u32 frame_size = aspeed_video_read(video, 830 video->comp_size_read); 831 832 update_perf(&video->perf); 833 834 spin_lock(&video->lock); 835 clear_bit(VIDEO_FRAME_INPRG, &video->flags); 836 buf = list_first_entry_or_null(&video->buffers, 837 struct aspeed_video_buffer, 838 link); 839 if (buf) { 840 vb2_set_plane_payload(&buf->vb.vb2_buf, 0, frame_size); 841 842 /* 843 * aspeed_jpeg requires continuous update. 844 * On the contrary, standard jpeg can keep last buffer 845 * to always have the latest result. 846 */ 847 if (video->format == VIDEO_FMT_STANDARD && 848 list_is_last(&buf->link, &video->buffers)) { 849 empty = false; 850 v4l2_dbg(1, debug, &video->v4l2_dev, "skip to keep last frame updated\n"); 851 } else { 852 buf->vb.vb2_buf.timestamp = ktime_get_ns(); 853 buf->vb.sequence = video->sequence++; 854 buf->vb.field = V4L2_FIELD_NONE; 855 vb2_buffer_done(&buf->vb.vb2_buf, 856 VB2_BUF_STATE_DONE); 857 list_del(&buf->link); 858 empty = list_empty(&video->buffers); 859 } 860 } 861 spin_unlock(&video->lock); 862 863 aspeed_video_update(video, VE_SEQ_CTRL, 864 VE_SEQ_CTRL_TRIG_CAPTURE | 865 VE_SEQ_CTRL_FORCE_IDLE | 866 VE_SEQ_CTRL_TRIG_COMP, 0); 867 aspeed_video_update(video, VE_INTERRUPT_CTRL, 868 VE_INTERRUPT_COMP_COMPLETE, 0); 869 aspeed_video_write(video, VE_INTERRUPT_STATUS, 870 VE_INTERRUPT_COMP_COMPLETE); 871 sts &= ~VE_INTERRUPT_COMP_COMPLETE; 872 873 aspeed_video_swap_src_buf(video); 874 875 if (test_bit(VIDEO_STREAMING, &video->flags) && !empty) 876 aspeed_video_start_frame(video); 877 } 878 879 return sts ? IRQ_NONE : IRQ_HANDLED; 880 } 881 882 static void aspeed_video_check_and_set_polarity(struct aspeed_video *video) 883 { 884 int i; 885 int hsync_counter = 0; 886 int vsync_counter = 0; 887 u32 sts, ctrl; 888 889 for (i = 0; i < NUM_POLARITY_CHECKS; ++i) { 890 sts = aspeed_video_read(video, VE_MODE_DETECT_STATUS); 891 if (sts & VE_MODE_DETECT_STATUS_VSYNC) 892 vsync_counter--; 893 else 894 vsync_counter++; 895 896 if (sts & VE_MODE_DETECT_STATUS_HSYNC) 897 hsync_counter--; 898 else 899 hsync_counter++; 900 } 901 902 ctrl = aspeed_video_read(video, VE_CTRL); 903 904 if (hsync_counter < 0) { 905 ctrl |= VE_CTRL_HSYNC_POL; 906 video->detected_timings.polarities &= 907 ~V4L2_DV_HSYNC_POS_POL; 908 } else { 909 ctrl &= ~VE_CTRL_HSYNC_POL; 910 video->detected_timings.polarities |= 911 V4L2_DV_HSYNC_POS_POL; 912 } 913 914 if (vsync_counter < 0) { 915 ctrl |= VE_CTRL_VSYNC_POL; 916 video->detected_timings.polarities &= 917 ~V4L2_DV_VSYNC_POS_POL; 918 } else { 919 ctrl &= ~VE_CTRL_VSYNC_POL; 920 video->detected_timings.polarities |= 921 V4L2_DV_VSYNC_POS_POL; 922 } 923 924 aspeed_video_write(video, VE_CTRL, ctrl); 925 } 926 927 static bool aspeed_video_alloc_buf(struct aspeed_video *video, 928 struct aspeed_video_addr *addr, 929 unsigned int size) 930 { 931 addr->virt = dma_alloc_coherent(video->dev, size, &addr->dma, 932 GFP_KERNEL); 933 if (!addr->virt) 934 return false; 935 936 addr->size = size; 937 return true; 938 } 939 940 static void aspeed_video_free_buf(struct aspeed_video *video, 941 struct aspeed_video_addr *addr) 942 { 943 dma_free_coherent(video->dev, addr->size, addr->virt, addr->dma); 944 addr->size = 0; 945 addr->dma = 0ULL; 946 addr->virt = NULL; 947 } 948 949 /* 950 * Get the minimum HW-supported compression buffer size for the frame size. 951 * Assume worst-case JPEG compression size is 1/8 raw size. This should be 952 * plenty even for maximum quality; any worse and the engine will simply return 953 * incomplete JPEGs. 954 */ 955 static void aspeed_video_calc_compressed_size(struct aspeed_video *video, 956 unsigned int frame_size) 957 { 958 int i, j; 959 u32 compression_buffer_size_reg = 0; 960 unsigned int size; 961 const unsigned int num_compression_packets = 4; 962 const unsigned int compression_packet_size = 1024; 963 const unsigned int max_compressed_size = frame_size / 2; /* 4bpp / 8 */ 964 965 video->max_compressed_size = UINT_MAX; 966 967 for (i = 0; i < 6; ++i) { 968 for (j = 0; j < 8; ++j) { 969 size = (num_compression_packets << i) * 970 (compression_packet_size << j); 971 if (size < max_compressed_size) 972 continue; 973 974 if (size < video->max_compressed_size) { 975 compression_buffer_size_reg = (i << 3) | j; 976 video->max_compressed_size = size; 977 } 978 } 979 } 980 981 aspeed_video_write(video, VE_STREAM_BUF_SIZE, 982 compression_buffer_size_reg); 983 984 v4l2_dbg(1, debug, &video->v4l2_dev, "Max compressed size: %#x\n", 985 video->max_compressed_size); 986 } 987 988 /* 989 * Update v4l2_bt_timings per current status. 990 * frame_top/frame_bottom/frame_left/frame_right need to be ready. 991 * 992 * The following registers start counting from sync's rising edge: 993 * 1. VR090: frame edge's left and right 994 * 2. VR094: frame edge's top and bottom 995 * 3. VR09C: counting from sync's rising edge to falling edge 996 * 997 * [Vertical timing] 998 * +--+ +-------------------+ +--+ 999 * | | | v i d e o | | | 1000 * +--+ +-----+ +-----+ +---+ 1001 * vsync+--+ 1002 * frame_top+--------+ 1003 * frame_bottom+----------------------------+ 1004 * 1005 * +-------------------+ 1006 * | v i d e o | 1007 * +--+ +-----+ +-----+ +---+ 1008 * | | | | 1009 * +--+ +--+ 1010 * vsync+-------------------------------+ 1011 * frame_top+-----+ 1012 * frame_bottom+-------------------------+ 1013 * 1014 * [Horizontal timing] 1015 * +--+ +-------------------+ +--+ 1016 * | | | v i d e o | | | 1017 * +--+ +-----+ +-----+ +---+ 1018 * hsync+--+ 1019 * frame_left+--------+ 1020 * frame_right+----------------------------+ 1021 * 1022 * +-------------------+ 1023 * | v i d e o | 1024 * +--+ +-----+ +-----+ +---+ 1025 * | | | | 1026 * +--+ +--+ 1027 * hsync+-------------------------------+ 1028 * frame_left+-----+ 1029 * frame_right+-------------------------+ 1030 * 1031 * @v: the struct of aspeed_video 1032 * @det: v4l2_bt_timings to be updated. 1033 */ 1034 static void aspeed_video_get_timings(struct aspeed_video *v, 1035 struct v4l2_bt_timings *det) 1036 { 1037 u32 mds, sync, htotal, vtotal, vsync, hsync; 1038 1039 mds = aspeed_video_read(v, VE_MODE_DETECT_STATUS); 1040 sync = aspeed_video_read(v, VE_SYNC_STATUS); 1041 htotal = aspeed_video_read(v, VE_H_TOTAL_PIXELS); 1042 vtotal = FIELD_GET(VE_MODE_DETECT_V_LINES, mds); 1043 vsync = FIELD_GET(VE_SYNC_STATUS_VSYNC, sync); 1044 hsync = FIELD_GET(VE_SYNC_STATUS_HSYNC, sync); 1045 1046 /* 1047 * This is a workaround for polarity detection. 1048 * Because ast-soc counts sync from sync's rising edge, the reg value 1049 * of sync would be larger than video's active area if negative. 1050 */ 1051 if (vsync > det->height) 1052 det->polarities &= ~V4L2_DV_VSYNC_POS_POL; 1053 else 1054 det->polarities |= V4L2_DV_VSYNC_POS_POL; 1055 if (hsync > det->width) 1056 det->polarities &= ~V4L2_DV_HSYNC_POS_POL; 1057 else 1058 det->polarities |= V4L2_DV_HSYNC_POS_POL; 1059 1060 if (det->polarities & V4L2_DV_VSYNC_POS_POL) { 1061 det->vbackporch = v->frame_top - vsync; 1062 det->vfrontporch = vtotal - v->frame_bottom; 1063 det->vsync = vsync; 1064 } else { 1065 det->vbackporch = v->frame_top; 1066 det->vfrontporch = vsync - v->frame_bottom; 1067 det->vsync = vtotal - vsync; 1068 } 1069 1070 if (det->polarities & V4L2_DV_HSYNC_POS_POL) { 1071 det->hbackporch = v->frame_left - hsync; 1072 det->hfrontporch = htotal - v->frame_right; 1073 det->hsync = hsync; 1074 } else { 1075 det->hbackporch = v->frame_left; 1076 det->hfrontporch = hsync - v->frame_right; 1077 det->hsync = htotal - hsync; 1078 } 1079 } 1080 1081 static void aspeed_video_get_resolution_gfx(struct aspeed_video *video, 1082 struct v4l2_bt_timings *det) 1083 { 1084 u32 h_val, v_val; 1085 1086 regmap_read(video->gfx, GFX_H_DISPLAY, &h_val); 1087 regmap_read(video->gfx, GFX_V_DISPLAY, &v_val); 1088 1089 det->width = FIELD_GET(GFX_H_DISPLAY_DE, h_val) + 1; 1090 det->height = FIELD_GET(GFX_V_DISPLAY_DE, v_val) + 1; 1091 video->v4l2_input_status = 0; 1092 } 1093 1094 #define res_check(v) test_and_clear_bit(VIDEO_MODE_DETECT_DONE, &(v)->flags) 1095 1096 static void aspeed_video_get_resolution_vga(struct aspeed_video *video, 1097 struct v4l2_bt_timings *det) 1098 { 1099 bool invalid_resolution = true; 1100 int rc; 1101 int tries = 0; 1102 u32 mds; 1103 u32 src_lr_edge; 1104 u32 src_tb_edge; 1105 1106 det->width = MIN_WIDTH; 1107 det->height = MIN_HEIGHT; 1108 video->v4l2_input_status = V4L2_IN_ST_NO_SIGNAL; 1109 memset(&video->perf, 0, sizeof(video->perf)); 1110 1111 do { 1112 if (tries) { 1113 set_current_state(TASK_INTERRUPTIBLE); 1114 if (schedule_timeout(INVALID_RESOLUTION_DELAY)) 1115 return; 1116 } 1117 1118 set_bit(VIDEO_RES_DETECT, &video->flags); 1119 aspeed_video_update(video, VE_CTRL, 1120 VE_CTRL_VSYNC_POL | VE_CTRL_HSYNC_POL, 0); 1121 aspeed_video_enable_mode_detect(video); 1122 1123 rc = wait_event_interruptible_timeout(video->wait, 1124 res_check(video), 1125 MODE_DETECT_TIMEOUT); 1126 if (!rc) { 1127 v4l2_dbg(1, debug, &video->v4l2_dev, "Timed out; first mode detect\n"); 1128 clear_bit(VIDEO_RES_DETECT, &video->flags); 1129 return; 1130 } 1131 1132 mds = aspeed_video_read(video, VE_MODE_DETECT_STATUS); 1133 // try detection again if current signal isn't stable 1134 if (!(mds & VE_MODE_DETECT_H_STABLE) || 1135 !(mds & VE_MODE_DETECT_V_STABLE) || 1136 (mds & VE_MODE_DETECT_EXTSRC_ADC)) 1137 continue; 1138 1139 aspeed_video_check_and_set_polarity(video); 1140 1141 aspeed_video_enable_mode_detect(video); 1142 1143 rc = wait_event_interruptible_timeout(video->wait, 1144 res_check(video), 1145 MODE_DETECT_TIMEOUT); 1146 clear_bit(VIDEO_RES_DETECT, &video->flags); 1147 if (!rc) { 1148 v4l2_dbg(1, debug, &video->v4l2_dev, "Timed out; second mode detect\n"); 1149 return; 1150 } 1151 1152 src_lr_edge = aspeed_video_read(video, VE_SRC_LR_EDGE_DET); 1153 src_tb_edge = aspeed_video_read(video, VE_SRC_TB_EDGE_DET); 1154 1155 video->frame_bottom = FIELD_GET(VE_SRC_TB_EDGE_DET_BOT, src_tb_edge); 1156 video->frame_top = FIELD_GET(VE_SRC_TB_EDGE_DET_TOP, src_tb_edge); 1157 1158 if (video->frame_top > video->frame_bottom) 1159 continue; 1160 1161 video->frame_right = FIELD_GET(VE_SRC_LR_EDGE_DET_RT, src_lr_edge); 1162 video->frame_left = FIELD_GET(VE_SRC_LR_EDGE_DET_LEFT, src_lr_edge); 1163 1164 if (video->frame_left > video->frame_right) 1165 continue; 1166 1167 invalid_resolution = false; 1168 } while (invalid_resolution && (tries++ < INVALID_RESOLUTION_RETRIES)); 1169 1170 if (invalid_resolution) { 1171 v4l2_dbg(1, debug, &video->v4l2_dev, "Invalid resolution detected\n"); 1172 return; 1173 } 1174 1175 det->height = (video->frame_bottom - video->frame_top) + 1; 1176 det->width = (video->frame_right - video->frame_left) + 1; 1177 video->v4l2_input_status = 0; 1178 1179 aspeed_video_get_timings(video, det); 1180 1181 /* Enable mode-detect watchdog, resolution-change watchdog */ 1182 aspeed_video_update(video, VE_INTERRUPT_CTRL, 0, 1183 VE_INTERRUPT_MODE_DETECT_WD); 1184 aspeed_video_update(video, VE_SEQ_CTRL, 0, VE_SEQ_CTRL_EN_WATCHDOG); 1185 } 1186 1187 static void aspeed_video_get_resolution(struct aspeed_video *video) 1188 { 1189 struct v4l2_bt_timings *det = &video->detected_timings; 1190 1191 if (video->input == VIDEO_INPUT_GFX) 1192 aspeed_video_get_resolution_gfx(video, det); 1193 else 1194 aspeed_video_get_resolution_vga(video, det); 1195 1196 v4l2_dbg(1, debug, &video->v4l2_dev, "Got resolution: %dx%d\n", 1197 det->width, det->height); 1198 } 1199 1200 static void aspeed_video_set_resolution(struct aspeed_video *video) 1201 { 1202 struct v4l2_bt_timings *act = &video->active_timings; 1203 unsigned int size = act->width * ALIGN(act->height, 8); 1204 1205 /* Set capture/compression frame sizes */ 1206 aspeed_video_calc_compressed_size(video, size); 1207 1208 if (!IS_ALIGNED(act->width, 64)) { 1209 /* 1210 * This is a workaround to fix a AST2500 silicon bug on A1 and 1211 * A2 revisions. Since it doesn't break capturing operation of 1212 * other revisions, use it for all revisions without checking 1213 * the revision ID. It picked new width which is a very next 1214 * 64-pixels aligned value to minimize memory bandwidth 1215 * and to get better access speed from video engine. 1216 */ 1217 u32 width = ALIGN(act->width, 64); 1218 1219 aspeed_video_write(video, VE_CAP_WINDOW, width << 16 | act->height); 1220 size = width * ALIGN(act->height, 8); 1221 } else { 1222 aspeed_video_write(video, VE_CAP_WINDOW, 1223 act->width << 16 | act->height); 1224 } 1225 aspeed_video_write(video, VE_COMP_WINDOW, 1226 act->width << 16 | act->height); 1227 aspeed_video_write(video, VE_SRC_SCANLINE_OFFSET, act->width * 4); 1228 1229 /* Don't use direct mode below 1024 x 768 (irqs don't fire) */ 1230 if (video->input == VIDEO_INPUT_VGA && size < DIRECT_FETCH_THRESHOLD) { 1231 v4l2_dbg(1, debug, &video->v4l2_dev, "Capture: Sync Mode\n"); 1232 aspeed_video_write(video, VE_TGS_0, 1233 FIELD_PREP(VE_TGS_FIRST, 1234 video->frame_left - 1) | 1235 FIELD_PREP(VE_TGS_LAST, 1236 video->frame_right)); 1237 aspeed_video_write(video, VE_TGS_1, 1238 FIELD_PREP(VE_TGS_FIRST, video->frame_top) | 1239 FIELD_PREP(VE_TGS_LAST, 1240 video->frame_bottom + 1)); 1241 aspeed_video_update(video, VE_CTRL, 1242 VE_CTRL_INT_DE | VE_CTRL_DIRECT_FETCH, 1243 VE_CTRL_INT_DE); 1244 } else { 1245 u32 ctrl, val, bpp; 1246 1247 v4l2_dbg(1, debug, &video->v4l2_dev, "Capture: Direct Mode\n"); 1248 ctrl = VE_CTRL_DIRECT_FETCH; 1249 if (video->input == VIDEO_INPUT_GFX) { 1250 regmap_read(video->gfx, GFX_CTRL, &val); 1251 bpp = FIELD_GET(GFX_CTRL_FMT, val) ? 32 : 16; 1252 if (bpp == 16) 1253 ctrl |= VE_CTRL_INT_DE; 1254 aspeed_video_write(video, VE_TGS_1, act->width * (bpp >> 3)); 1255 } 1256 aspeed_video_update(video, VE_CTRL, 1257 VE_CTRL_INT_DE | VE_CTRL_DIRECT_FETCH, 1258 ctrl); 1259 } 1260 1261 size *= 4; 1262 1263 if (size != video->srcs[0].size) { 1264 if (video->srcs[0].size) 1265 aspeed_video_free_buf(video, &video->srcs[0]); 1266 if (video->srcs[1].size) 1267 aspeed_video_free_buf(video, &video->srcs[1]); 1268 1269 if (!aspeed_video_alloc_buf(video, &video->srcs[0], size)) 1270 goto err_mem; 1271 if (!aspeed_video_alloc_buf(video, &video->srcs[1], size)) 1272 goto err_mem; 1273 1274 v4l2_dbg(1, debug, &video->v4l2_dev, "src buf0 addr(%pad) size(%d)\n", 1275 &video->srcs[0].dma, video->srcs[0].size); 1276 v4l2_dbg(1, debug, &video->v4l2_dev, "src buf1 addr(%pad) size(%d)\n", 1277 &video->srcs[1].dma, video->srcs[1].size); 1278 aspeed_video_write(video, VE_SRC0_ADDR, video->srcs[0].dma); 1279 aspeed_video_write(video, VE_SRC1_ADDR, video->srcs[1].dma); 1280 } 1281 1282 return; 1283 1284 err_mem: 1285 dev_err(video->dev, "Failed to allocate source buffers\n"); 1286 1287 if (video->srcs[0].size) 1288 aspeed_video_free_buf(video, &video->srcs[0]); 1289 } 1290 1291 /* 1292 * Update relative parameters when timing changed. 1293 * 1294 * @video: the struct of aspeed_video 1295 * @timings: the new timings 1296 */ 1297 static void aspeed_video_update_timings(struct aspeed_video *video, struct v4l2_bt_timings *timings) 1298 { 1299 video->active_timings = *timings; 1300 aspeed_video_set_resolution(video); 1301 1302 video->pix_fmt.width = timings->width; 1303 video->pix_fmt.height = timings->height; 1304 video->pix_fmt.sizeimage = video->max_compressed_size; 1305 } 1306 1307 static void aspeed_video_update_regs(struct aspeed_video *video) 1308 { 1309 u8 jpeg_hq_quality = clamp((int)video->jpeg_hq_quality - 1, 0, 1310 ASPEED_VIDEO_JPEG_NUM_QUALITIES - 1); 1311 u32 comp_ctrl = FIELD_PREP(VE_COMP_CTRL_DCT_LUM, video->jpeg_quality) | 1312 FIELD_PREP(VE_COMP_CTRL_DCT_CHR, video->jpeg_quality | 0x10) | 1313 FIELD_PREP(VE_COMP_CTRL_EN_HQ, video->hq_mode) | 1314 FIELD_PREP(VE_COMP_CTRL_HQ_DCT_LUM, jpeg_hq_quality) | 1315 FIELD_PREP(VE_COMP_CTRL_HQ_DCT_CHR, jpeg_hq_quality | 0x10); 1316 u32 ctrl = 0; 1317 u32 seq_ctrl = 0; 1318 1319 v4l2_dbg(1, debug, &video->v4l2_dev, "input(%s)\n", 1320 input_str[video->input]); 1321 v4l2_dbg(1, debug, &video->v4l2_dev, "framerate(%d)\n", 1322 video->frame_rate); 1323 v4l2_dbg(1, debug, &video->v4l2_dev, "jpeg format(%s) subsample(%s)\n", 1324 format_str[video->format], 1325 video->yuv420 ? "420" : "444"); 1326 v4l2_dbg(1, debug, &video->v4l2_dev, "compression quality(%d)\n", 1327 video->jpeg_quality); 1328 v4l2_dbg(1, debug, &video->v4l2_dev, "hq_mode(%s) hq_quality(%d)\n", 1329 video->hq_mode ? "on" : "off", video->jpeg_hq_quality); 1330 1331 if (video->format == VIDEO_FMT_ASPEED) 1332 aspeed_video_update(video, VE_BCD_CTRL, 0, VE_BCD_CTRL_EN_BCD); 1333 else 1334 aspeed_video_update(video, VE_BCD_CTRL, VE_BCD_CTRL_EN_BCD, 0); 1335 1336 if (video->input == VIDEO_INPUT_VGA) 1337 ctrl |= VE_CTRL_AUTO_OR_CURSOR; 1338 1339 if (video->frame_rate) 1340 ctrl |= FIELD_PREP(VE_CTRL_FRC, video->frame_rate); 1341 1342 if (video->format == VIDEO_FMT_STANDARD) { 1343 comp_ctrl &= ~FIELD_PREP(VE_COMP_CTRL_EN_HQ, video->hq_mode); 1344 seq_ctrl |= video->jpeg_mode; 1345 } 1346 1347 if (video->yuv420) 1348 seq_ctrl |= VE_SEQ_CTRL_YUV420; 1349 1350 if (video->jpeg.virt) 1351 aspeed_video_update_jpeg_table(video->jpeg.virt, video->yuv420); 1352 1353 /* Set control registers */ 1354 aspeed_video_update(video, VE_SEQ_CTRL, 1355 video->jpeg_mode | VE_SEQ_CTRL_YUV420, 1356 seq_ctrl); 1357 aspeed_video_update(video, VE_CTRL, 1358 VE_CTRL_FRC | VE_CTRL_AUTO_OR_CURSOR | 1359 VE_CTRL_SOURCE, ctrl); 1360 aspeed_video_update(video, VE_COMP_CTRL, 1361 VE_COMP_CTRL_DCT_LUM | VE_COMP_CTRL_DCT_CHR | 1362 VE_COMP_CTRL_EN_HQ | VE_COMP_CTRL_HQ_DCT_LUM | 1363 VE_COMP_CTRL_HQ_DCT_CHR | VE_COMP_CTRL_VQ_4COLOR | 1364 VE_COMP_CTRL_VQ_DCT_ONLY, 1365 comp_ctrl); 1366 } 1367 1368 static void aspeed_video_init_regs(struct aspeed_video *video) 1369 { 1370 u32 ctrl = VE_CTRL_AUTO_OR_CURSOR | 1371 FIELD_PREP(VE_CTRL_CAPTURE_FMT, VIDEO_CAP_FMT_YUV_FULL_SWING); 1372 1373 /* Unlock VE registers */ 1374 aspeed_video_write(video, VE_PROTECTION_KEY, VE_PROTECTION_KEY_UNLOCK); 1375 1376 /* Disable interrupts */ 1377 aspeed_video_write(video, VE_INTERRUPT_CTRL, 0); 1378 aspeed_video_write(video, VE_INTERRUPT_STATUS, 0xffffffff); 1379 1380 /* Clear the offset */ 1381 aspeed_video_write(video, VE_COMP_PROC_OFFSET, 0); 1382 aspeed_video_write(video, VE_COMP_OFFSET, 0); 1383 1384 aspeed_video_write(video, VE_JPEG_ADDR, video->jpeg.dma); 1385 1386 /* Set control registers */ 1387 aspeed_video_write(video, VE_SEQ_CTRL, VE_SEQ_CTRL_AUTO_COMP); 1388 aspeed_video_write(video, VE_CTRL, ctrl); 1389 aspeed_video_write(video, VE_COMP_CTRL, VE_COMP_CTRL_RSVD); 1390 1391 /* Don't downscale */ 1392 aspeed_video_write(video, VE_SCALING_FACTOR, 0x10001000); 1393 aspeed_video_write(video, VE_SCALING_FILTER0, 0x00200000); 1394 aspeed_video_write(video, VE_SCALING_FILTER1, 0x00200000); 1395 aspeed_video_write(video, VE_SCALING_FILTER2, 0x00200000); 1396 aspeed_video_write(video, VE_SCALING_FILTER3, 0x00200000); 1397 1398 /* Set mode detection defaults */ 1399 aspeed_video_write(video, VE_MODE_DETECT, 1400 FIELD_PREP(VE_MODE_DT_HOR_TOLER, 2) | 1401 FIELD_PREP(VE_MODE_DT_VER_TOLER, 2) | 1402 FIELD_PREP(VE_MODE_DT_HOR_STABLE, 6) | 1403 FIELD_PREP(VE_MODE_DT_VER_STABLE, 6) | 1404 FIELD_PREP(VE_MODE_DT_EDG_THROD, 0x65)); 1405 1406 aspeed_video_write(video, VE_BCD_CTRL, 0); 1407 } 1408 1409 static void aspeed_video_start(struct aspeed_video *video) 1410 { 1411 aspeed_video_on(video); 1412 1413 aspeed_video_init_regs(video); 1414 1415 /* Resolution set to 640x480 if no signal found */ 1416 aspeed_video_get_resolution(video); 1417 1418 /* Set timings since the device is being opened for the first time */ 1419 aspeed_video_update_timings(video, &video->detected_timings); 1420 } 1421 1422 static void aspeed_video_stop(struct aspeed_video *video) 1423 { 1424 set_bit(VIDEO_STOPPED, &video->flags); 1425 cancel_delayed_work_sync(&video->res_work); 1426 1427 aspeed_video_off(video); 1428 1429 if (video->srcs[0].size) 1430 aspeed_video_free_buf(video, &video->srcs[0]); 1431 1432 if (video->srcs[1].size) 1433 aspeed_video_free_buf(video, &video->srcs[1]); 1434 1435 if (video->bcd.size) 1436 aspeed_video_free_buf(video, &video->bcd); 1437 1438 video->v4l2_input_status = V4L2_IN_ST_NO_SIGNAL; 1439 video->flags = 0; 1440 } 1441 1442 static int aspeed_video_querycap(struct file *file, void *fh, 1443 struct v4l2_capability *cap) 1444 { 1445 strscpy(cap->driver, DEVICE_NAME, sizeof(cap->driver)); 1446 strscpy(cap->card, "Aspeed Video Engine", sizeof(cap->card)); 1447 snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s", 1448 DEVICE_NAME); 1449 1450 return 0; 1451 } 1452 1453 static int aspeed_video_enum_format(struct file *file, void *fh, 1454 struct v4l2_fmtdesc *f) 1455 { 1456 struct aspeed_video *video = video_drvdata(file); 1457 1458 if (f->index) 1459 return -EINVAL; 1460 1461 f->pixelformat = video->pix_fmt.pixelformat; 1462 1463 return 0; 1464 } 1465 1466 static int aspeed_video_get_format(struct file *file, void *fh, 1467 struct v4l2_format *f) 1468 { 1469 struct aspeed_video *video = video_drvdata(file); 1470 1471 f->fmt.pix = video->pix_fmt; 1472 1473 return 0; 1474 } 1475 1476 static int aspeed_video_set_format(struct file *file, void *fh, 1477 struct v4l2_format *f) 1478 { 1479 struct aspeed_video *video = video_drvdata(file); 1480 1481 if (vb2_is_busy(&video->queue)) 1482 return -EBUSY; 1483 1484 switch (f->fmt.pix.pixelformat) { 1485 case V4L2_PIX_FMT_JPEG: 1486 video->format = VIDEO_FMT_STANDARD; 1487 break; 1488 case V4L2_PIX_FMT_AJPG: 1489 video->format = VIDEO_FMT_ASPEED; 1490 break; 1491 default: 1492 return -EINVAL; 1493 } 1494 video->pix_fmt.pixelformat = f->fmt.pix.pixelformat; 1495 1496 return 0; 1497 } 1498 1499 static int aspeed_video_enum_input(struct file *file, void *fh, 1500 struct v4l2_input *inp) 1501 { 1502 struct aspeed_video *video = video_drvdata(file); 1503 1504 if (inp->index >= VIDEO_INPUT_MAX) 1505 return -EINVAL; 1506 1507 sprintf(inp->name, "%s capture", input_str[inp->index]); 1508 inp->type = V4L2_INPUT_TYPE_CAMERA; 1509 inp->capabilities = V4L2_IN_CAP_DV_TIMINGS; 1510 inp->status = video->v4l2_input_status; 1511 1512 return 0; 1513 } 1514 1515 static int aspeed_video_get_input(struct file *file, void *fh, unsigned int *i) 1516 { 1517 struct aspeed_video *video = video_drvdata(file); 1518 1519 *i = video->input; 1520 1521 return 0; 1522 } 1523 1524 static int aspeed_video_set_input(struct file *file, void *fh, unsigned int i) 1525 { 1526 struct aspeed_video *video = video_drvdata(file); 1527 1528 if (i >= VIDEO_INPUT_MAX) 1529 return -EINVAL; 1530 1531 if (i == video->input) 1532 return 0; 1533 1534 if (vb2_is_busy(&video->queue)) 1535 return -EBUSY; 1536 1537 if (IS_ERR(video->scu)) { 1538 v4l2_dbg(1, debug, &video->v4l2_dev, 1539 "%s: scu isn't ready for input-control\n", __func__); 1540 return -EINVAL; 1541 } 1542 1543 if (IS_ERR(video->gfx) && i == VIDEO_INPUT_GFX) { 1544 v4l2_dbg(1, debug, &video->v4l2_dev, 1545 "%s: gfx isn't ready for GFX input\n", __func__); 1546 return -EINVAL; 1547 } 1548 1549 video->input = i; 1550 1551 if (video->version == 6) { 1552 /* modify dpll source per current input */ 1553 if (video->input == VIDEO_INPUT_VGA) 1554 regmap_update_bits(video->scu, SCU_MISC_CTRL, 1555 SCU_DPLL_SOURCE, 0); 1556 else 1557 regmap_update_bits(video->scu, SCU_MISC_CTRL, 1558 SCU_DPLL_SOURCE, SCU_DPLL_SOURCE); 1559 } 1560 1561 aspeed_video_update_regs(video); 1562 1563 /* update signal status */ 1564 aspeed_video_get_resolution(video); 1565 if (!video->v4l2_input_status) 1566 aspeed_video_update_timings(video, &video->detected_timings); 1567 1568 return 0; 1569 } 1570 1571 static int aspeed_video_get_parm(struct file *file, void *fh, 1572 struct v4l2_streamparm *a) 1573 { 1574 struct aspeed_video *video = video_drvdata(file); 1575 1576 a->parm.capture.capability = V4L2_CAP_TIMEPERFRAME; 1577 a->parm.capture.readbuffers = ASPEED_VIDEO_V4L2_MIN_BUF_REQ; 1578 a->parm.capture.timeperframe.numerator = 1; 1579 if (!video->frame_rate) 1580 a->parm.capture.timeperframe.denominator = MAX_FRAME_RATE; 1581 else 1582 a->parm.capture.timeperframe.denominator = video->frame_rate; 1583 1584 return 0; 1585 } 1586 1587 static int aspeed_video_set_parm(struct file *file, void *fh, 1588 struct v4l2_streamparm *a) 1589 { 1590 unsigned int frame_rate = 0; 1591 struct aspeed_video *video = video_drvdata(file); 1592 1593 a->parm.capture.capability = V4L2_CAP_TIMEPERFRAME; 1594 a->parm.capture.readbuffers = ASPEED_VIDEO_V4L2_MIN_BUF_REQ; 1595 1596 if (a->parm.capture.timeperframe.numerator) 1597 frame_rate = a->parm.capture.timeperframe.denominator / 1598 a->parm.capture.timeperframe.numerator; 1599 1600 if (!frame_rate || frame_rate > MAX_FRAME_RATE) { 1601 frame_rate = 0; 1602 a->parm.capture.timeperframe.denominator = MAX_FRAME_RATE; 1603 a->parm.capture.timeperframe.numerator = 1; 1604 } 1605 1606 if (video->frame_rate != frame_rate) { 1607 video->frame_rate = frame_rate; 1608 aspeed_video_update(video, VE_CTRL, VE_CTRL_FRC, 1609 FIELD_PREP(VE_CTRL_FRC, frame_rate)); 1610 } 1611 1612 return 0; 1613 } 1614 1615 static int aspeed_video_enum_framesizes(struct file *file, void *fh, 1616 struct v4l2_frmsizeenum *fsize) 1617 { 1618 struct aspeed_video *video = video_drvdata(file); 1619 1620 if (fsize->index) 1621 return -EINVAL; 1622 1623 if (fsize->pixel_format != V4L2_PIX_FMT_JPEG) 1624 return -EINVAL; 1625 1626 fsize->discrete.width = video->pix_fmt.width; 1627 fsize->discrete.height = video->pix_fmt.height; 1628 fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE; 1629 1630 return 0; 1631 } 1632 1633 static int aspeed_video_enum_frameintervals(struct file *file, void *fh, 1634 struct v4l2_frmivalenum *fival) 1635 { 1636 struct aspeed_video *video = video_drvdata(file); 1637 1638 if (fival->index) 1639 return -EINVAL; 1640 1641 if (fival->width != video->detected_timings.width || 1642 fival->height != video->detected_timings.height) 1643 return -EINVAL; 1644 1645 if (fival->pixel_format != V4L2_PIX_FMT_JPEG) 1646 return -EINVAL; 1647 1648 fival->type = V4L2_FRMIVAL_TYPE_CONTINUOUS; 1649 1650 fival->stepwise.min.denominator = MAX_FRAME_RATE; 1651 fival->stepwise.min.numerator = 1; 1652 fival->stepwise.max.denominator = 1; 1653 fival->stepwise.max.numerator = 1; 1654 fival->stepwise.step = fival->stepwise.max; 1655 1656 return 0; 1657 } 1658 1659 static int aspeed_video_set_dv_timings(struct file *file, void *fh, 1660 struct v4l2_dv_timings *timings) 1661 { 1662 struct aspeed_video *video = video_drvdata(file); 1663 1664 if (timings->bt.width == video->active_timings.width && 1665 timings->bt.height == video->active_timings.height) 1666 return 0; 1667 1668 if (vb2_is_busy(&video->queue)) 1669 return -EBUSY; 1670 1671 aspeed_video_update_timings(video, &timings->bt); 1672 1673 timings->type = V4L2_DV_BT_656_1120; 1674 1675 v4l2_dbg(1, debug, &video->v4l2_dev, "set new timings(%dx%d)\n", 1676 timings->bt.width, timings->bt.height); 1677 1678 return 0; 1679 } 1680 1681 static int aspeed_video_get_dv_timings(struct file *file, void *fh, 1682 struct v4l2_dv_timings *timings) 1683 { 1684 struct aspeed_video *video = video_drvdata(file); 1685 1686 timings->type = V4L2_DV_BT_656_1120; 1687 timings->bt = video->active_timings; 1688 1689 return 0; 1690 } 1691 1692 static int aspeed_video_query_dv_timings(struct file *file, void *fh, 1693 struct v4l2_dv_timings *timings) 1694 { 1695 int rc; 1696 struct aspeed_video *video = video_drvdata(file); 1697 1698 /* 1699 * This blocks only if the driver is currently in the process of 1700 * detecting a new resolution; in the event of no signal or timeout 1701 * this function is woken up. 1702 */ 1703 if (file->f_flags & O_NONBLOCK) { 1704 if (test_bit(VIDEO_RES_CHANGE, &video->flags)) 1705 return -EAGAIN; 1706 } else { 1707 rc = wait_event_interruptible(video->wait, 1708 !test_bit(VIDEO_RES_CHANGE, 1709 &video->flags)); 1710 if (rc) 1711 return -EINTR; 1712 } 1713 1714 timings->type = V4L2_DV_BT_656_1120; 1715 timings->bt = video->detected_timings; 1716 1717 return video->v4l2_input_status ? -ENOLINK : 0; 1718 } 1719 1720 static int aspeed_video_enum_dv_timings(struct file *file, void *fh, 1721 struct v4l2_enum_dv_timings *timings) 1722 { 1723 return v4l2_enum_dv_timings_cap(timings, &aspeed_video_timings_cap, 1724 NULL, NULL); 1725 } 1726 1727 static int aspeed_video_dv_timings_cap(struct file *file, void *fh, 1728 struct v4l2_dv_timings_cap *cap) 1729 { 1730 *cap = aspeed_video_timings_cap; 1731 1732 return 0; 1733 } 1734 1735 static int aspeed_video_sub_event(struct v4l2_fh *fh, 1736 const struct v4l2_event_subscription *sub) 1737 { 1738 switch (sub->type) { 1739 case V4L2_EVENT_SOURCE_CHANGE: 1740 return v4l2_src_change_event_subscribe(fh, sub); 1741 } 1742 1743 return v4l2_ctrl_subscribe_event(fh, sub); 1744 } 1745 1746 static const struct v4l2_ioctl_ops aspeed_video_ioctl_ops = { 1747 .vidioc_querycap = aspeed_video_querycap, 1748 1749 .vidioc_enum_fmt_vid_cap = aspeed_video_enum_format, 1750 .vidioc_g_fmt_vid_cap = aspeed_video_get_format, 1751 .vidioc_s_fmt_vid_cap = aspeed_video_set_format, 1752 .vidioc_try_fmt_vid_cap = aspeed_video_get_format, 1753 1754 .vidioc_reqbufs = vb2_ioctl_reqbufs, 1755 .vidioc_querybuf = vb2_ioctl_querybuf, 1756 .vidioc_qbuf = vb2_ioctl_qbuf, 1757 .vidioc_expbuf = vb2_ioctl_expbuf, 1758 .vidioc_dqbuf = vb2_ioctl_dqbuf, 1759 .vidioc_create_bufs = vb2_ioctl_create_bufs, 1760 .vidioc_prepare_buf = vb2_ioctl_prepare_buf, 1761 .vidioc_streamon = vb2_ioctl_streamon, 1762 .vidioc_streamoff = vb2_ioctl_streamoff, 1763 1764 .vidioc_enum_input = aspeed_video_enum_input, 1765 .vidioc_g_input = aspeed_video_get_input, 1766 .vidioc_s_input = aspeed_video_set_input, 1767 1768 .vidioc_g_parm = aspeed_video_get_parm, 1769 .vidioc_s_parm = aspeed_video_set_parm, 1770 .vidioc_enum_framesizes = aspeed_video_enum_framesizes, 1771 .vidioc_enum_frameintervals = aspeed_video_enum_frameintervals, 1772 1773 .vidioc_s_dv_timings = aspeed_video_set_dv_timings, 1774 .vidioc_g_dv_timings = aspeed_video_get_dv_timings, 1775 .vidioc_query_dv_timings = aspeed_video_query_dv_timings, 1776 .vidioc_enum_dv_timings = aspeed_video_enum_dv_timings, 1777 .vidioc_dv_timings_cap = aspeed_video_dv_timings_cap, 1778 1779 .vidioc_subscribe_event = aspeed_video_sub_event, 1780 .vidioc_unsubscribe_event = v4l2_event_unsubscribe, 1781 }; 1782 1783 static int aspeed_video_set_ctrl(struct v4l2_ctrl *ctrl) 1784 { 1785 struct aspeed_video *video = container_of(ctrl->handler, 1786 struct aspeed_video, 1787 ctrl_handler); 1788 1789 switch (ctrl->id) { 1790 case V4L2_CID_JPEG_COMPRESSION_QUALITY: 1791 video->jpeg_quality = ctrl->val; 1792 if (test_bit(VIDEO_STREAMING, &video->flags)) 1793 aspeed_video_update_regs(video); 1794 break; 1795 case V4L2_CID_JPEG_CHROMA_SUBSAMPLING: 1796 video->yuv420 = (ctrl->val == V4L2_JPEG_CHROMA_SUBSAMPLING_420); 1797 if (test_bit(VIDEO_STREAMING, &video->flags)) 1798 aspeed_video_update_regs(video); 1799 break; 1800 case V4L2_CID_ASPEED_HQ_MODE: 1801 video->hq_mode = ctrl->val; 1802 if (test_bit(VIDEO_STREAMING, &video->flags)) 1803 aspeed_video_update_regs(video); 1804 break; 1805 case V4L2_CID_ASPEED_HQ_JPEG_QUALITY: 1806 video->jpeg_hq_quality = ctrl->val; 1807 if (test_bit(VIDEO_STREAMING, &video->flags)) 1808 aspeed_video_update_regs(video); 1809 break; 1810 default: 1811 return -EINVAL; 1812 } 1813 1814 return 0; 1815 } 1816 1817 static const struct v4l2_ctrl_ops aspeed_video_ctrl_ops = { 1818 .s_ctrl = aspeed_video_set_ctrl, 1819 }; 1820 1821 static const struct v4l2_ctrl_config aspeed_ctrl_HQ_mode = { 1822 .ops = &aspeed_video_ctrl_ops, 1823 .id = V4L2_CID_ASPEED_HQ_MODE, 1824 .name = "Aspeed HQ Mode", 1825 .type = V4L2_CTRL_TYPE_BOOLEAN, 1826 .min = false, 1827 .max = true, 1828 .step = 1, 1829 .def = false, 1830 }; 1831 1832 static const struct v4l2_ctrl_config aspeed_ctrl_HQ_jpeg_quality = { 1833 .ops = &aspeed_video_ctrl_ops, 1834 .id = V4L2_CID_ASPEED_HQ_JPEG_QUALITY, 1835 .name = "Aspeed HQ Quality", 1836 .type = V4L2_CTRL_TYPE_INTEGER, 1837 .min = 1, 1838 .max = ASPEED_VIDEO_JPEG_NUM_QUALITIES, 1839 .step = 1, 1840 .def = 1, 1841 }; 1842 1843 static void aspeed_video_resolution_work(struct work_struct *work) 1844 { 1845 struct delayed_work *dwork = to_delayed_work(work); 1846 struct aspeed_video *video = container_of(dwork, struct aspeed_video, 1847 res_work); 1848 1849 aspeed_video_on(video); 1850 1851 /* Exit early in case no clients remain */ 1852 if (test_bit(VIDEO_STOPPED, &video->flags)) 1853 goto done; 1854 1855 aspeed_video_init_regs(video); 1856 1857 aspeed_video_update_regs(video); 1858 1859 aspeed_video_get_resolution(video); 1860 1861 if (video->detected_timings.width != video->active_timings.width || 1862 video->detected_timings.height != video->active_timings.height) { 1863 static const struct v4l2_event ev = { 1864 .type = V4L2_EVENT_SOURCE_CHANGE, 1865 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION, 1866 }; 1867 1868 v4l2_dbg(1, debug, &video->v4l2_dev, "fire source change event\n"); 1869 v4l2_event_queue(&video->vdev, &ev); 1870 } else if (test_bit(VIDEO_STREAMING, &video->flags)) { 1871 /* No resolution change so just restart streaming */ 1872 aspeed_video_start_frame(video); 1873 } 1874 1875 done: 1876 clear_bit(VIDEO_RES_CHANGE, &video->flags); 1877 wake_up_interruptible_all(&video->wait); 1878 } 1879 1880 static int aspeed_video_open(struct file *file) 1881 { 1882 int rc; 1883 struct aspeed_video *video = video_drvdata(file); 1884 1885 mutex_lock(&video->video_lock); 1886 1887 rc = v4l2_fh_open(file); 1888 if (rc) { 1889 mutex_unlock(&video->video_lock); 1890 return rc; 1891 } 1892 1893 if (v4l2_fh_is_singular_file(file)) 1894 aspeed_video_start(video); 1895 1896 mutex_unlock(&video->video_lock); 1897 1898 return 0; 1899 } 1900 1901 static int aspeed_video_release(struct file *file) 1902 { 1903 int rc; 1904 struct aspeed_video *video = video_drvdata(file); 1905 1906 mutex_lock(&video->video_lock); 1907 1908 if (v4l2_fh_is_singular_file(file)) 1909 aspeed_video_stop(video); 1910 1911 rc = _vb2_fop_release(file, NULL); 1912 1913 mutex_unlock(&video->video_lock); 1914 1915 return rc; 1916 } 1917 1918 static const struct v4l2_file_operations aspeed_video_v4l2_fops = { 1919 .owner = THIS_MODULE, 1920 .read = vb2_fop_read, 1921 .poll = vb2_fop_poll, 1922 .unlocked_ioctl = video_ioctl2, 1923 .mmap = vb2_fop_mmap, 1924 .open = aspeed_video_open, 1925 .release = aspeed_video_release, 1926 }; 1927 1928 static int aspeed_video_queue_setup(struct vb2_queue *q, 1929 unsigned int *num_buffers, 1930 unsigned int *num_planes, 1931 unsigned int sizes[], 1932 struct device *alloc_devs[]) 1933 { 1934 struct aspeed_video *video = vb2_get_drv_priv(q); 1935 1936 if (*num_planes) { 1937 if (sizes[0] < video->max_compressed_size) 1938 return -EINVAL; 1939 1940 return 0; 1941 } 1942 1943 *num_planes = 1; 1944 sizes[0] = video->max_compressed_size; 1945 1946 return 0; 1947 } 1948 1949 static int aspeed_video_buf_prepare(struct vb2_buffer *vb) 1950 { 1951 struct aspeed_video *video = vb2_get_drv_priv(vb->vb2_queue); 1952 1953 if (vb2_plane_size(vb, 0) < video->max_compressed_size) 1954 return -EINVAL; 1955 1956 return 0; 1957 } 1958 1959 static int aspeed_video_start_streaming(struct vb2_queue *q, 1960 unsigned int count) 1961 { 1962 int rc; 1963 struct aspeed_video *video = vb2_get_drv_priv(q); 1964 1965 video->sequence = 0; 1966 video->perf.duration_max = 0; 1967 video->perf.duration_min = 0xffffffff; 1968 1969 aspeed_video_update_regs(video); 1970 1971 rc = aspeed_video_start_frame(video); 1972 if (rc) { 1973 aspeed_video_bufs_done(video, VB2_BUF_STATE_QUEUED); 1974 return rc; 1975 } 1976 1977 set_bit(VIDEO_STREAMING, &video->flags); 1978 return 0; 1979 } 1980 1981 static void aspeed_video_stop_streaming(struct vb2_queue *q) 1982 { 1983 int rc; 1984 struct aspeed_video *video = vb2_get_drv_priv(q); 1985 1986 clear_bit(VIDEO_STREAMING, &video->flags); 1987 1988 rc = wait_event_timeout(video->wait, 1989 !test_bit(VIDEO_FRAME_INPRG, &video->flags), 1990 STOP_TIMEOUT); 1991 if (!rc) { 1992 v4l2_dbg(1, debug, &video->v4l2_dev, "Timed out when stopping streaming\n"); 1993 1994 /* 1995 * Need to force stop any DMA and try and get HW into a good 1996 * state for future calls to start streaming again. 1997 */ 1998 aspeed_video_reset(video); 1999 2000 aspeed_video_init_regs(video); 2001 2002 aspeed_video_get_resolution(video); 2003 } 2004 2005 aspeed_video_bufs_done(video, VB2_BUF_STATE_ERROR); 2006 } 2007 2008 static void aspeed_video_buf_queue(struct vb2_buffer *vb) 2009 { 2010 bool empty; 2011 struct aspeed_video *video = vb2_get_drv_priv(vb->vb2_queue); 2012 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 2013 struct aspeed_video_buffer *avb = to_aspeed_video_buffer(vbuf); 2014 unsigned long flags; 2015 2016 spin_lock_irqsave(&video->lock, flags); 2017 empty = list_empty(&video->buffers); 2018 list_add_tail(&avb->link, &video->buffers); 2019 spin_unlock_irqrestore(&video->lock, flags); 2020 2021 if (test_bit(VIDEO_STREAMING, &video->flags) && 2022 !test_bit(VIDEO_FRAME_INPRG, &video->flags) && empty) 2023 aspeed_video_start_frame(video); 2024 } 2025 2026 static const struct vb2_ops aspeed_video_vb2_ops = { 2027 .queue_setup = aspeed_video_queue_setup, 2028 .buf_prepare = aspeed_video_buf_prepare, 2029 .start_streaming = aspeed_video_start_streaming, 2030 .stop_streaming = aspeed_video_stop_streaming, 2031 .buf_queue = aspeed_video_buf_queue, 2032 }; 2033 2034 #ifdef CONFIG_DEBUG_FS 2035 static int aspeed_video_debugfs_show(struct seq_file *s, void *data) 2036 { 2037 struct aspeed_video *v = s->private; 2038 u32 val08; 2039 2040 seq_puts(s, "\n"); 2041 2042 seq_puts(s, "Capture:\n"); 2043 val08 = aspeed_video_read(v, VE_CTRL); 2044 if (FIELD_GET(VE_CTRL_DIRECT_FETCH, val08)) { 2045 seq_printf(s, " %-20s:\tDirect fetch\n", "Mode"); 2046 seq_printf(s, " %-20s:\t%s\n", "Input", input_str[v->input]); 2047 seq_printf(s, " %-20s:\t%s\n", "VGA bpp mode", 2048 FIELD_GET(VE_CTRL_INT_DE, val08) ? "16" : "32"); 2049 } else { 2050 seq_printf(s, " %-20s:\tSync\n", "Mode"); 2051 seq_printf(s, " %-20s:\t%s\n", "Video source", 2052 FIELD_GET(VE_CTRL_SOURCE, val08) ? 2053 "external" : "internal"); 2054 seq_printf(s, " %-20s:\t%s\n", "DE source", 2055 FIELD_GET(VE_CTRL_INT_DE, val08) ? 2056 "internal" : "external"); 2057 seq_printf(s, " %-20s:\t%s\n", "Cursor overlay", 2058 FIELD_GET(VE_CTRL_AUTO_OR_CURSOR, val08) ? 2059 "Without" : "With"); 2060 } 2061 2062 seq_printf(s, " %-20s:\t%s\n", "Signal", 2063 v->v4l2_input_status ? "Unlock" : "Lock"); 2064 seq_printf(s, " %-20s:\t%d\n", "Width", v->pix_fmt.width); 2065 seq_printf(s, " %-20s:\t%d\n", "Height", v->pix_fmt.height); 2066 seq_printf(s, " %-20s:\t%d\n", "FRC", v->frame_rate); 2067 2068 seq_puts(s, "\n"); 2069 2070 seq_puts(s, "Compression:\n"); 2071 seq_printf(s, " %-20s:\t%s\n", "Format", format_str[v->format]); 2072 seq_printf(s, " %-20s:\t%s\n", "Subsampling", 2073 v->yuv420 ? "420" : "444"); 2074 seq_printf(s, " %-20s:\t%d\n", "Quality", v->jpeg_quality); 2075 if (v->format == VIDEO_FMT_ASPEED) { 2076 seq_printf(s, " %-20s:\t%s\n", "HQ Mode", 2077 v->hq_mode ? "on" : "off"); 2078 seq_printf(s, " %-20s:\t%d\n", "HQ Quality", 2079 v->hq_mode ? v->jpeg_hq_quality : 0); 2080 } 2081 2082 seq_puts(s, "\n"); 2083 2084 seq_puts(s, "Performance:\n"); 2085 seq_printf(s, " %-20s:\t%d\n", "Frame#", v->sequence); 2086 seq_printf(s, " %-20s:\n", "Frame Duration(ms)"); 2087 seq_printf(s, " %-18s:\t%d\n", "Now", v->perf.duration); 2088 seq_printf(s, " %-18s:\t%d\n", "Min", v->perf.duration_min); 2089 seq_printf(s, " %-18s:\t%d\n", "Max", v->perf.duration_max); 2090 seq_printf(s, " %-20s:\t%d\n", "FPS", 2091 (v->perf.totaltime && v->sequence) ? 2092 1000 / (v->perf.totaltime / v->sequence) : 0); 2093 2094 return 0; 2095 } 2096 DEFINE_SHOW_ATTRIBUTE(aspeed_video_debugfs); 2097 2098 static struct dentry *debugfs_entry; 2099 2100 static void aspeed_video_debugfs_remove(struct aspeed_video *video) 2101 { 2102 debugfs_remove_recursive(debugfs_entry); 2103 debugfs_entry = NULL; 2104 } 2105 2106 static void aspeed_video_debugfs_create(struct aspeed_video *video) 2107 { 2108 debugfs_entry = debugfs_create_file(DEVICE_NAME, 0444, NULL, 2109 video, 2110 &aspeed_video_debugfs_fops); 2111 } 2112 #else 2113 static void aspeed_video_debugfs_remove(struct aspeed_video *video) { } 2114 static void aspeed_video_debugfs_create(struct aspeed_video *video) { } 2115 #endif /* CONFIG_DEBUG_FS */ 2116 2117 static int aspeed_video_setup_video(struct aspeed_video *video) 2118 { 2119 const u64 mask = ~(BIT(V4L2_JPEG_CHROMA_SUBSAMPLING_444) | 2120 BIT(V4L2_JPEG_CHROMA_SUBSAMPLING_420)); 2121 struct v4l2_device *v4l2_dev = &video->v4l2_dev; 2122 struct vb2_queue *vbq = &video->queue; 2123 struct video_device *vdev = &video->vdev; 2124 struct v4l2_ctrl_handler *hdl = &video->ctrl_handler; 2125 int rc; 2126 2127 video->pix_fmt.pixelformat = V4L2_PIX_FMT_JPEG; 2128 video->pix_fmt.field = V4L2_FIELD_NONE; 2129 video->pix_fmt.colorspace = V4L2_COLORSPACE_SRGB; 2130 video->pix_fmt.quantization = V4L2_QUANTIZATION_FULL_RANGE; 2131 video->v4l2_input_status = V4L2_IN_ST_NO_SIGNAL; 2132 2133 rc = v4l2_device_register(video->dev, v4l2_dev); 2134 if (rc) { 2135 dev_err(video->dev, "Failed to register v4l2 device\n"); 2136 return rc; 2137 } 2138 2139 v4l2_ctrl_handler_init(hdl, 4); 2140 v4l2_ctrl_new_std(hdl, &aspeed_video_ctrl_ops, 2141 V4L2_CID_JPEG_COMPRESSION_QUALITY, 0, 2142 ASPEED_VIDEO_JPEG_NUM_QUALITIES - 1, 1, 0); 2143 v4l2_ctrl_new_std_menu(hdl, &aspeed_video_ctrl_ops, 2144 V4L2_CID_JPEG_CHROMA_SUBSAMPLING, 2145 V4L2_JPEG_CHROMA_SUBSAMPLING_420, mask, 2146 V4L2_JPEG_CHROMA_SUBSAMPLING_444); 2147 v4l2_ctrl_new_custom(hdl, &aspeed_ctrl_HQ_mode, NULL); 2148 v4l2_ctrl_new_custom(hdl, &aspeed_ctrl_HQ_jpeg_quality, NULL); 2149 2150 rc = hdl->error; 2151 if (rc) { 2152 v4l2_ctrl_handler_free(&video->ctrl_handler); 2153 v4l2_device_unregister(v4l2_dev); 2154 2155 dev_err(video->dev, "Failed to init controls: %d\n", rc); 2156 return rc; 2157 } 2158 2159 v4l2_dev->ctrl_handler = hdl; 2160 2161 vbq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; 2162 vbq->io_modes = VB2_MMAP | VB2_READ | VB2_DMABUF; 2163 vbq->dev = v4l2_dev->dev; 2164 vbq->lock = &video->video_lock; 2165 vbq->ops = &aspeed_video_vb2_ops; 2166 vbq->mem_ops = &vb2_dma_contig_memops; 2167 vbq->drv_priv = video; 2168 vbq->buf_struct_size = sizeof(struct aspeed_video_buffer); 2169 vbq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; 2170 vbq->min_queued_buffers = ASPEED_VIDEO_V4L2_MIN_BUF_REQ; 2171 2172 rc = vb2_queue_init(vbq); 2173 if (rc) { 2174 v4l2_ctrl_handler_free(&video->ctrl_handler); 2175 v4l2_device_unregister(v4l2_dev); 2176 2177 dev_err(video->dev, "Failed to init vb2 queue\n"); 2178 return rc; 2179 } 2180 2181 vdev->queue = vbq; 2182 vdev->fops = &aspeed_video_v4l2_fops; 2183 vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_READWRITE | 2184 V4L2_CAP_STREAMING; 2185 vdev->v4l2_dev = v4l2_dev; 2186 strscpy(vdev->name, DEVICE_NAME, sizeof(vdev->name)); 2187 vdev->vfl_type = VFL_TYPE_VIDEO; 2188 vdev->vfl_dir = VFL_DIR_RX; 2189 vdev->release = video_device_release_empty; 2190 vdev->ioctl_ops = &aspeed_video_ioctl_ops; 2191 vdev->lock = &video->video_lock; 2192 2193 video_set_drvdata(vdev, video); 2194 rc = video_register_device(vdev, VFL_TYPE_VIDEO, 0); 2195 if (rc) { 2196 v4l2_ctrl_handler_free(&video->ctrl_handler); 2197 v4l2_device_unregister(v4l2_dev); 2198 2199 dev_err(video->dev, "Failed to register video device\n"); 2200 return rc; 2201 } 2202 2203 return 0; 2204 } 2205 2206 /* 2207 * Get regmap without checking res, such as clk/reset, that could lead to 2208 * conflict. 2209 */ 2210 static struct regmap *aspeed_regmap_lookup(struct device_node *np, const char *property) 2211 { 2212 struct device_node *syscon_np __free(device_node) = of_parse_phandle(np, property, 0); 2213 2214 if (!syscon_np) 2215 return ERR_PTR(-ENODEV); 2216 2217 return device_node_to_regmap(syscon_np); 2218 } 2219 2220 static int aspeed_video_init(struct aspeed_video *video) 2221 { 2222 int irq; 2223 int rc; 2224 struct device *dev = video->dev; 2225 2226 video->scu = aspeed_regmap_lookup(dev->of_node, "aspeed,scu"); 2227 video->gfx = aspeed_regmap_lookup(dev->of_node, "aspeed,gfx"); 2228 2229 irq = irq_of_parse_and_map(dev->of_node, 0); 2230 if (!irq) { 2231 dev_err(dev, "Unable to find IRQ\n"); 2232 return -ENODEV; 2233 } 2234 2235 rc = devm_request_threaded_irq(dev, irq, NULL, aspeed_video_irq, 2236 IRQF_ONESHOT, DEVICE_NAME, video); 2237 if (rc < 0) { 2238 dev_err(dev, "Unable to request IRQ %d\n", irq); 2239 return rc; 2240 } 2241 dev_info(video->dev, "irq %d\n", irq); 2242 2243 video->reset = devm_reset_control_get(dev, NULL); 2244 if (IS_ERR(video->reset)) { 2245 dev_err(dev, "Unable to get reset\n"); 2246 return PTR_ERR(video->reset); 2247 } 2248 2249 video->eclk = devm_clk_get(dev, "eclk"); 2250 if (IS_ERR(video->eclk)) { 2251 dev_err(dev, "Unable to get ECLK\n"); 2252 return PTR_ERR(video->eclk); 2253 } 2254 2255 rc = clk_prepare(video->eclk); 2256 if (rc) 2257 return rc; 2258 2259 video->vclk = devm_clk_get(dev, "vclk"); 2260 if (IS_ERR(video->vclk)) { 2261 dev_err(dev, "Unable to get VCLK\n"); 2262 rc = PTR_ERR(video->vclk); 2263 goto err_unprepare_eclk; 2264 } 2265 2266 rc = clk_prepare(video->vclk); 2267 if (rc) 2268 goto err_unprepare_eclk; 2269 2270 of_reserved_mem_device_init(dev); 2271 2272 rc = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); 2273 if (rc) { 2274 dev_err(dev, "Failed to set DMA mask\n"); 2275 goto err_release_reserved_mem; 2276 } 2277 2278 if (!aspeed_video_alloc_buf(video, &video->jpeg, 2279 VE_JPEG_HEADER_SIZE)) { 2280 dev_err(dev, "Failed to allocate DMA for JPEG header\n"); 2281 rc = -ENOMEM; 2282 goto err_release_reserved_mem; 2283 } 2284 dev_info(video->dev, "alloc mem size(%d) at %pad for jpeg header\n", 2285 VE_JPEG_HEADER_SIZE, &video->jpeg.dma); 2286 2287 aspeed_video_init_jpeg_table(video->jpeg.virt, video->yuv420); 2288 2289 return 0; 2290 2291 err_release_reserved_mem: 2292 of_reserved_mem_device_release(dev); 2293 clk_unprepare(video->vclk); 2294 err_unprepare_eclk: 2295 clk_unprepare(video->eclk); 2296 2297 return rc; 2298 } 2299 2300 static const struct of_device_id aspeed_video_of_match[] = { 2301 { .compatible = "aspeed,ast2400-video-engine", .data = &ast2400_config }, 2302 { .compatible = "aspeed,ast2500-video-engine", .data = &ast2500_config }, 2303 { .compatible = "aspeed,ast2600-video-engine", .data = &ast2600_config }, 2304 {} 2305 }; 2306 MODULE_DEVICE_TABLE(of, aspeed_video_of_match); 2307 2308 static int aspeed_video_probe(struct platform_device *pdev) 2309 { 2310 const struct aspeed_video_config *config; 2311 struct aspeed_video *video; 2312 int rc; 2313 2314 video = devm_kzalloc(&pdev->dev, sizeof(*video), GFP_KERNEL); 2315 if (!video) 2316 return -ENOMEM; 2317 2318 video->base = devm_platform_ioremap_resource(pdev, 0); 2319 if (IS_ERR(video->base)) 2320 return PTR_ERR(video->base); 2321 2322 config = of_device_get_match_data(&pdev->dev); 2323 if (!config) 2324 return -ENODEV; 2325 2326 video->version = config->version; 2327 video->jpeg_mode = config->jpeg_mode; 2328 video->comp_size_read = config->comp_size_read; 2329 2330 video->frame_rate = 30; 2331 video->jpeg_hq_quality = 1; 2332 video->dev = &pdev->dev; 2333 spin_lock_init(&video->lock); 2334 mutex_init(&video->video_lock); 2335 init_waitqueue_head(&video->wait); 2336 INIT_DELAYED_WORK(&video->res_work, aspeed_video_resolution_work); 2337 INIT_LIST_HEAD(&video->buffers); 2338 2339 rc = aspeed_video_init(video); 2340 if (rc) 2341 return rc; 2342 2343 rc = aspeed_video_setup_video(video); 2344 if (rc) { 2345 aspeed_video_free_buf(video, &video->jpeg); 2346 clk_unprepare(video->vclk); 2347 clk_unprepare(video->eclk); 2348 return rc; 2349 } 2350 2351 aspeed_video_debugfs_create(video); 2352 2353 return 0; 2354 } 2355 2356 static void aspeed_video_remove(struct platform_device *pdev) 2357 { 2358 struct device *dev = &pdev->dev; 2359 struct v4l2_device *v4l2_dev = dev_get_drvdata(dev); 2360 struct aspeed_video *video = to_aspeed_video(v4l2_dev); 2361 2362 aspeed_video_off(video); 2363 2364 aspeed_video_debugfs_remove(video); 2365 2366 clk_unprepare(video->vclk); 2367 clk_unprepare(video->eclk); 2368 2369 vb2_video_unregister_device(&video->vdev); 2370 2371 v4l2_ctrl_handler_free(&video->ctrl_handler); 2372 2373 v4l2_device_unregister(v4l2_dev); 2374 2375 aspeed_video_free_buf(video, &video->jpeg); 2376 2377 of_reserved_mem_device_release(dev); 2378 } 2379 2380 static struct platform_driver aspeed_video_driver = { 2381 .driver = { 2382 .name = DEVICE_NAME, 2383 .of_match_table = aspeed_video_of_match, 2384 }, 2385 .probe = aspeed_video_probe, 2386 .remove = aspeed_video_remove, 2387 }; 2388 2389 module_platform_driver(aspeed_video_driver); 2390 2391 module_param(debug, int, 0644); 2392 MODULE_PARM_DESC(debug, "Debug level (0=off,1=info,2=debug,3=reg ops)"); 2393 2394 MODULE_DESCRIPTION("ASPEED Video Engine Driver"); 2395 MODULE_AUTHOR("Eddie James"); 2396 MODULE_LICENSE("GPL v2"); 2397