1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright 2020-2021 NXP 4 */ 5 6 #include <linux/init.h> 7 #include <linux/interconnect.h> 8 #include <linux/ioctl.h> 9 #include <linux/list.h> 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/of_device.h> 13 #include <linux/of_address.h> 14 #include <linux/platform_device.h> 15 #include <linux/delay.h> 16 #include <linux/rational.h> 17 #include <media/videobuf2-v4l2.h> 18 #include <media/videobuf2-dma-contig.h> 19 #include <linux/videodev2.h> 20 #include "vpu.h" 21 #include "vpu_rpc.h" 22 #include "vpu_defs.h" 23 #include "vpu_helpers.h" 24 #include "vpu_v4l2.h" 25 #include "vpu_cmds.h" 26 #include "vpu_imx8q.h" 27 #include "vpu_malone.h" 28 29 #define CMD_SIZE 25600 30 #define MSG_SIZE 25600 31 #define CODEC_SIZE 0x1000 32 #define JPEG_SIZE 0x1000 33 #define SEQ_SIZE 0x1000 34 #define GOP_SIZE 0x1000 35 #define PIC_SIZE 0x1000 36 #define QMETER_SIZE 0x1000 37 #define DBGLOG_SIZE 0x10000 38 #define DEBUG_SIZE 0x80000 39 #define ENG_SIZE 0x1000 40 #define MALONE_SKIPPED_FRAME_ID 0x555 41 42 #define MALONE_ALIGN_MBI 0x800 43 #define MALONE_DCP_CHUNK_BIT 16 44 #define MALONE_DCP_SIZE_MAX 0x3000000 45 #define MALONE_DCP_SIZE_MIN 0x100000 46 #define MALONE_DCP_FIXED_MB_ALLOC 250 47 48 #define CONFIG_SET(val, cfg, pos, mask) \ 49 (*(cfg) |= (((val) << (pos)) & (mask))) 50 //x means source data , y means destination data 51 #define STREAM_CONFIG_FORMAT_SET(x, y) CONFIG_SET(x, y, 0, 0x0000000F) 52 #define STREAM_CONFIG_STRBUFIDX_SET(x, y) CONFIG_SET(x, y, 8, 0x00000300) 53 #define STREAM_CONFIG_NOSEQ_SET(x, y) CONFIG_SET(x, y, 10, 0x00000400) 54 #define STREAM_CONFIG_DEBLOCK_SET(x, y) CONFIG_SET(x, y, 11, 0x00000800) 55 #define STREAM_CONFIG_DERING_SET(x, y) CONFIG_SET(x, y, 12, 0x00001000) 56 #define STREAM_CONFIG_IBWAIT_SET(x, y) CONFIG_SET(x, y, 13, 0x00002000) 57 #define STREAM_CONFIG_FBC_SET(x, y) CONFIG_SET(x, y, 14, 0x00004000) 58 #define STREAM_CONFIG_PLAY_MODE_SET(x, y) CONFIG_SET(x, y, 16, 0x00030000) 59 #define STREAM_CONFIG_ENABLE_DCP_SET(x, y) CONFIG_SET(x, y, 20, 0x00100000) 60 #define STREAM_CONFIG_NUM_STR_BUF_SET(x, y) CONFIG_SET(x, y, 21, 0x00600000) 61 #define STREAM_CONFIG_MALONE_USAGE_SET(x, y) CONFIG_SET(x, y, 23, 0x01800000) 62 #define STREAM_CONFIG_MULTI_VID_SET(x, y) CONFIG_SET(x, y, 25, 0x02000000) 63 #define STREAM_CONFIG_OBFUSC_EN_SET(x, y) CONFIG_SET(x, y, 26, 0x04000000) 64 #define STREAM_CONFIG_RC4_EN_SET(x, y) CONFIG_SET(x, y, 27, 0x08000000) 65 #define STREAM_CONFIG_MCX_SET(x, y) CONFIG_SET(x, y, 28, 0x10000000) 66 #define STREAM_CONFIG_PES_SET(x, y) CONFIG_SET(x, y, 29, 0x20000000) 67 #define STREAM_CONFIG_NUM_DBE_SET(x, y) CONFIG_SET(x, y, 30, 0x40000000) 68 #define STREAM_CONFIG_FS_CTRL_MODE_SET(x, y) CONFIG_SET(x, y, 31, 0x80000000) 69 70 enum vpu_malone_stream_input_mode { 71 INVALID_MODE = 0, 72 FRAME_LVL, 73 NON_FRAME_LVL 74 }; 75 76 enum vpu_malone_format { 77 MALONE_FMT_NULL = 0x0, 78 MALONE_FMT_AVC = 0x1, 79 MALONE_FMT_MP2 = 0x2, 80 MALONE_FMT_VC1 = 0x3, 81 MALONE_FMT_AVS = 0x4, 82 MALONE_FMT_ASP = 0x5, 83 MALONE_FMT_JPG = 0x6, 84 MALONE_FMT_RV = 0x7, 85 MALONE_FMT_VP6 = 0x8, 86 MALONE_FMT_SPK = 0x9, 87 MALONE_FMT_VP8 = 0xA, 88 MALONE_FMT_HEVC = 0xB, 89 MALONE_FMT_LAST = MALONE_FMT_HEVC 90 }; 91 92 enum { 93 VID_API_CMD_NULL = 0x00, 94 VID_API_CMD_PARSE_NEXT_SEQ = 0x01, 95 VID_API_CMD_PARSE_NEXT_I = 0x02, 96 VID_API_CMD_PARSE_NEXT_IP = 0x03, 97 VID_API_CMD_PARSE_NEXT_ANY = 0x04, 98 VID_API_CMD_DEC_PIC = 0x05, 99 VID_API_CMD_UPDATE_ES_WR_PTR = 0x06, 100 VID_API_CMD_UPDATE_ES_RD_PTR = 0x07, 101 VID_API_CMD_UPDATE_UDATA = 0x08, 102 VID_API_CMD_GET_FSINFO = 0x09, 103 VID_API_CMD_SKIP_PIC = 0x0a, 104 VID_API_CMD_DEC_CHUNK = 0x0b, 105 VID_API_CMD_START = 0x10, 106 VID_API_CMD_STOP = 0x11, 107 VID_API_CMD_ABORT = 0x12, 108 VID_API_CMD_RST_BUF = 0x13, 109 VID_API_CMD_FS_RELEASE = 0x15, 110 VID_API_CMD_MEM_REGION_ATTACH = 0x16, 111 VID_API_CMD_MEM_REGION_DETACH = 0x17, 112 VID_API_CMD_MVC_VIEW_SELECT = 0x18, 113 VID_API_CMD_FS_ALLOC = 0x19, 114 VID_API_CMD_DBG_GET_STATUS = 0x1C, 115 VID_API_CMD_DBG_START_LOG = 0x1D, 116 VID_API_CMD_DBG_STOP_LOG = 0x1E, 117 VID_API_CMD_DBG_DUMP_LOG = 0x1F, 118 VID_API_CMD_YUV_READY = 0x20, 119 VID_API_CMD_TS = 0x21, 120 121 VID_API_CMD_FIRM_RESET = 0x40, 122 123 VID_API_CMD_SNAPSHOT = 0xAA, 124 VID_API_CMD_ROLL_SNAPSHOT = 0xAB, 125 VID_API_CMD_LOCK_SCHEDULER = 0xAC, 126 VID_API_CMD_UNLOCK_SCHEDULER = 0xAD, 127 VID_API_CMD_CQ_FIFO_DUMP = 0xAE, 128 VID_API_CMD_DBG_FIFO_DUMP = 0xAF, 129 VID_API_CMD_SVC_ILP = 0xBB, 130 VID_API_CMD_FW_STATUS = 0xF0, 131 VID_API_CMD_INVALID = 0xFF 132 }; 133 134 enum { 135 VID_API_EVENT_NULL = 0x00, 136 VID_API_EVENT_RESET_DONE = 0x01, 137 VID_API_EVENT_SEQ_HDR_FOUND = 0x02, 138 VID_API_EVENT_PIC_HDR_FOUND = 0x03, 139 VID_API_EVENT_PIC_DECODED = 0x04, 140 VID_API_EVENT_FIFO_LOW = 0x05, 141 VID_API_EVENT_FIFO_HIGH = 0x06, 142 VID_API_EVENT_FIFO_EMPTY = 0x07, 143 VID_API_EVENT_FIFO_FULL = 0x08, 144 VID_API_EVENT_BS_ERROR = 0x09, 145 VID_API_EVENT_UDATA_FIFO_UPTD = 0x0A, 146 VID_API_EVENT_RES_CHANGE = 0x0B, 147 VID_API_EVENT_FIFO_OVF = 0x0C, 148 VID_API_EVENT_CHUNK_DECODED = 0x0D, 149 VID_API_EVENT_REQ_FRAME_BUFF = 0x10, 150 VID_API_EVENT_FRAME_BUFF_RDY = 0x11, 151 VID_API_EVENT_REL_FRAME_BUFF = 0x12, 152 VID_API_EVENT_STR_BUF_RST = 0x13, 153 VID_API_EVENT_RET_PING = 0x14, 154 VID_API_EVENT_QMETER = 0x15, 155 VID_API_EVENT_STR_FMT_CHANGE = 0x16, 156 VID_API_EVENT_FIRMWARE_XCPT = 0x17, 157 VID_API_EVENT_START_DONE = 0x18, 158 VID_API_EVENT_STOPPED = 0x19, 159 VID_API_EVENT_ABORT_DONE = 0x1A, 160 VID_API_EVENT_FINISHED = 0x1B, 161 VID_API_EVENT_DBG_STAT_UPDATE = 0x1C, 162 VID_API_EVENT_DBG_LOG_STARTED = 0x1D, 163 VID_API_EVENT_DBG_LOG_STOPPED = 0x1E, 164 VID_API_EVENT_DBG_LOG_UPDATED = 0x1F, 165 VID_API_EVENT_DBG_MSG_DEC = 0x20, 166 VID_API_EVENT_DEC_SC_ERR = 0x21, 167 VID_API_EVENT_CQ_FIFO_DUMP = 0x22, 168 VID_API_EVENT_DBG_FIFO_DUMP = 0x23, 169 VID_API_EVENT_DEC_CHECK_RES = 0x24, 170 VID_API_EVENT_DEC_CFG_INFO = 0x25, 171 VID_API_EVENT_UNSUPPORTED_STREAM = 0x26, 172 VID_API_EVENT_STR_SUSPENDED = 0x30, 173 VID_API_EVENT_SNAPSHOT_DONE = 0x40, 174 VID_API_EVENT_FW_STATUS = 0xF0, 175 VID_API_EVENT_INVALID = 0xFF 176 }; 177 178 struct vpu_malone_buffer_desc { 179 struct vpu_rpc_buffer_desc buffer; 180 u32 low; 181 u32 high; 182 }; 183 184 struct vpu_malone_str_buffer { 185 u32 wptr; 186 u32 rptr; 187 u32 start; 188 u32 end; 189 u32 lwm; 190 }; 191 192 struct vpu_malone_picth_info { 193 u32 frame_pitch; 194 }; 195 196 struct vpu_malone_table_desc { 197 u32 array_base; 198 u32 size; 199 }; 200 201 struct vpu_malone_dbglog_desc { 202 u32 addr; 203 u32 size; 204 u32 level; 205 u32 reserved; 206 }; 207 208 struct vpu_malone_frame_buffer { 209 u32 addr; 210 u32 size; 211 }; 212 213 struct vpu_malone_udata { 214 u32 base; 215 u32 total_size; 216 u32 slot_size; 217 }; 218 219 struct vpu_malone_buffer_info { 220 u32 stream_input_mode; 221 u32 stream_pic_input_count; 222 u32 stream_pic_parsed_count; 223 u32 stream_buffer_threshold; 224 u32 stream_pic_end_flag; 225 }; 226 227 struct vpu_malone_encrypt_info { 228 u32 rec4key[8]; 229 u32 obfusc; 230 }; 231 232 struct malone_iface { 233 u32 exec_base_addr; 234 u32 exec_area_size; 235 struct vpu_malone_buffer_desc cmd_buffer_desc; 236 struct vpu_malone_buffer_desc msg_buffer_desc; 237 u32 cmd_int_enable[VID_API_NUM_STREAMS]; 238 struct vpu_malone_picth_info stream_pitch_info[VID_API_NUM_STREAMS]; 239 u32 stream_config[VID_API_NUM_STREAMS]; 240 struct vpu_malone_table_desc codec_param_tab_desc; 241 struct vpu_malone_table_desc jpeg_param_tab_desc; 242 u32 stream_buffer_desc[VID_API_NUM_STREAMS][VID_API_MAX_BUF_PER_STR]; 243 struct vpu_malone_table_desc seq_info_tab_desc; 244 struct vpu_malone_table_desc pic_info_tab_desc; 245 struct vpu_malone_table_desc gop_info_tab_desc; 246 struct vpu_malone_table_desc qmeter_info_tab_desc; 247 u32 stream_error[VID_API_NUM_STREAMS]; 248 u32 fw_version; 249 u32 fw_offset; 250 u32 max_streams; 251 struct vpu_malone_dbglog_desc dbglog_desc; 252 struct vpu_rpc_buffer_desc api_cmd_buffer_desc[VID_API_NUM_STREAMS]; 253 struct vpu_malone_udata udata_buffer[VID_API_NUM_STREAMS]; 254 struct vpu_malone_buffer_desc debug_buffer_desc; 255 struct vpu_malone_buffer_desc eng_access_buff_desc[VID_API_NUM_STREAMS]; 256 u32 encrypt_info[VID_API_NUM_STREAMS]; 257 struct vpu_rpc_system_config system_cfg; 258 u32 api_version; 259 struct vpu_malone_buffer_info stream_buff_info[VID_API_NUM_STREAMS]; 260 }; 261 262 struct malone_jpg_params { 263 u32 rotation_angle; 264 u32 horiz_scale_factor; 265 u32 vert_scale_factor; 266 u32 rotation_mode; 267 u32 rgb_mode; 268 u32 chunk_mode; /* 0 ~ 1 */ 269 u32 last_chunk; /* 0 ~ 1 */ 270 u32 chunk_rows; /* 0 ~ 255 */ 271 u32 num_bytes; 272 u32 jpg_crop_x; 273 u32 jpg_crop_y; 274 u32 jpg_crop_width; 275 u32 jpg_crop_height; 276 u32 jpg_mjpeg_mode; 277 u32 jpg_mjpeg_interlaced; 278 }; 279 280 struct malone_codec_params { 281 u32 disp_imm; 282 u32 fourcc; 283 u32 codec_version; 284 u32 frame_rate; 285 u32 dbglog_enable; 286 u32 bsdma_lwm; 287 u32 bbd_coring; 288 u32 bbd_s_thr_row; 289 u32 bbd_p_thr_row; 290 u32 bbd_s_thr_logo_row; 291 u32 bbd_p_thr_logo_row; 292 u32 bbd_s_thr_col; 293 u32 bbd_p_thr_col; 294 u32 bbd_chr_thr_row; 295 u32 bbd_chr_thr_col; 296 u32 bbd_uv_mid_level; 297 u32 bbd_excl_win_mb_left; 298 u32 bbd_excl_win_mb_right; 299 }; 300 301 struct malone_padding_scode { 302 u32 scode_type; 303 u32 pixelformat; 304 u32 data[2]; 305 }; 306 307 struct malone_fmt_mapping { 308 u32 pixelformat; 309 enum vpu_malone_format malone_format; 310 }; 311 312 struct malone_scode_t { 313 struct vpu_inst *inst; 314 struct vb2_buffer *vb; 315 u32 wptr; 316 u32 need_data; 317 }; 318 319 struct malone_scode_handler { 320 u32 pixelformat; 321 int (*insert_scode_seq)(struct malone_scode_t *scode); 322 int (*insert_scode_pic)(struct malone_scode_t *scode); 323 }; 324 325 struct vpu_dec_ctrl { 326 struct malone_codec_params *codec_param; 327 struct malone_jpg_params *jpg; 328 void *seq_mem; 329 void *pic_mem; 330 void *gop_mem; 331 void *qmeter_mem; 332 void *dbglog_mem; 333 struct vpu_malone_str_buffer __iomem *str_buf[VID_API_NUM_STREAMS]; 334 u32 buf_addr[VID_API_NUM_STREAMS]; 335 }; 336 337 u32 vpu_malone_get_data_size(void) 338 { 339 return sizeof(struct vpu_dec_ctrl); 340 } 341 342 void vpu_malone_init_rpc(struct vpu_shared_addr *shared, 343 struct vpu_buffer *rpc, dma_addr_t boot_addr) 344 { 345 struct malone_iface *iface; 346 struct vpu_dec_ctrl *hc; 347 unsigned long base_phy_addr; 348 unsigned long phy_addr; 349 unsigned long offset; 350 unsigned int i; 351 352 if (rpc->phys < boot_addr) 353 return; 354 355 iface = rpc->virt; 356 base_phy_addr = rpc->phys - boot_addr; 357 hc = shared->priv; 358 359 shared->iface = iface; 360 shared->boot_addr = boot_addr; 361 362 iface->exec_base_addr = base_phy_addr; 363 iface->exec_area_size = rpc->length; 364 365 offset = sizeof(struct malone_iface); 366 phy_addr = base_phy_addr + offset; 367 368 shared->cmd_desc = &iface->cmd_buffer_desc.buffer; 369 shared->cmd_mem_vir = rpc->virt + offset; 370 iface->cmd_buffer_desc.buffer.start = 371 iface->cmd_buffer_desc.buffer.rptr = 372 iface->cmd_buffer_desc.buffer.wptr = phy_addr; 373 iface->cmd_buffer_desc.buffer.end = iface->cmd_buffer_desc.buffer.start + CMD_SIZE; 374 offset += CMD_SIZE; 375 phy_addr = base_phy_addr + offset; 376 377 shared->msg_desc = &iface->msg_buffer_desc.buffer; 378 shared->msg_mem_vir = rpc->virt + offset; 379 iface->msg_buffer_desc.buffer.start = 380 iface->msg_buffer_desc.buffer.wptr = 381 iface->msg_buffer_desc.buffer.rptr = phy_addr; 382 iface->msg_buffer_desc.buffer.end = iface->msg_buffer_desc.buffer.start + MSG_SIZE; 383 offset += MSG_SIZE; 384 phy_addr = base_phy_addr + offset; 385 386 iface->codec_param_tab_desc.array_base = phy_addr; 387 hc->codec_param = rpc->virt + offset; 388 offset += CODEC_SIZE; 389 phy_addr = base_phy_addr + offset; 390 391 iface->jpeg_param_tab_desc.array_base = phy_addr; 392 hc->jpg = rpc->virt + offset; 393 offset += JPEG_SIZE; 394 phy_addr = base_phy_addr + offset; 395 396 iface->seq_info_tab_desc.array_base = phy_addr; 397 hc->seq_mem = rpc->virt + offset; 398 offset += SEQ_SIZE; 399 phy_addr = base_phy_addr + offset; 400 401 iface->pic_info_tab_desc.array_base = phy_addr; 402 hc->pic_mem = rpc->virt + offset; 403 offset += PIC_SIZE; 404 phy_addr = base_phy_addr + offset; 405 406 iface->gop_info_tab_desc.array_base = phy_addr; 407 hc->gop_mem = rpc->virt + offset; 408 offset += GOP_SIZE; 409 phy_addr = base_phy_addr + offset; 410 411 iface->qmeter_info_tab_desc.array_base = phy_addr; 412 hc->qmeter_mem = rpc->virt + offset; 413 offset += QMETER_SIZE; 414 phy_addr = base_phy_addr + offset; 415 416 iface->dbglog_desc.addr = phy_addr; 417 iface->dbglog_desc.size = DBGLOG_SIZE; 418 hc->dbglog_mem = rpc->virt + offset; 419 offset += DBGLOG_SIZE; 420 phy_addr = base_phy_addr + offset; 421 422 for (i = 0; i < VID_API_NUM_STREAMS; i++) { 423 iface->eng_access_buff_desc[i].buffer.start = 424 iface->eng_access_buff_desc[i].buffer.wptr = 425 iface->eng_access_buff_desc[i].buffer.rptr = phy_addr; 426 iface->eng_access_buff_desc[i].buffer.end = 427 iface->eng_access_buff_desc[i].buffer.start + ENG_SIZE; 428 offset += ENG_SIZE; 429 phy_addr = base_phy_addr + offset; 430 } 431 432 for (i = 0; i < VID_API_NUM_STREAMS; i++) { 433 iface->encrypt_info[i] = phy_addr; 434 offset += sizeof(struct vpu_malone_encrypt_info); 435 phy_addr = base_phy_addr + offset; 436 } 437 438 rpc->bytesused = offset; 439 } 440 441 void vpu_malone_set_log_buf(struct vpu_shared_addr *shared, 442 struct vpu_buffer *log) 443 { 444 struct malone_iface *iface = shared->iface; 445 446 iface->debug_buffer_desc.buffer.start = 447 iface->debug_buffer_desc.buffer.wptr = 448 iface->debug_buffer_desc.buffer.rptr = log->phys - shared->boot_addr; 449 iface->debug_buffer_desc.buffer.end = iface->debug_buffer_desc.buffer.start + log->length; 450 } 451 452 static u32 get_str_buffer_offset(u32 instance) 453 { 454 return DEC_MFD_XREG_SLV_BASE + MFD_MCX + MFD_MCX_OFF * instance; 455 } 456 457 void vpu_malone_set_system_cfg(struct vpu_shared_addr *shared, 458 u32 regs_base, void __iomem *regs, u32 core_id) 459 { 460 struct malone_iface *iface = shared->iface; 461 struct vpu_rpc_system_config *config = &iface->system_cfg; 462 struct vpu_dec_ctrl *hc = shared->priv; 463 int i; 464 465 vpu_imx8q_set_system_cfg_common(config, regs_base, core_id); 466 for (i = 0; i < VID_API_NUM_STREAMS; i++) { 467 u32 offset = get_str_buffer_offset(i); 468 469 hc->buf_addr[i] = regs_base + offset; 470 hc->str_buf[i] = regs + offset; 471 } 472 } 473 474 u32 vpu_malone_get_version(struct vpu_shared_addr *shared) 475 { 476 struct malone_iface *iface = shared->iface; 477 478 return iface->fw_version; 479 } 480 481 int vpu_malone_get_stream_buffer_size(struct vpu_shared_addr *shared) 482 { 483 return 0xc00000; 484 } 485 486 int vpu_malone_config_stream_buffer(struct vpu_shared_addr *shared, 487 u32 instance, 488 struct vpu_buffer *buf) 489 { 490 struct malone_iface *iface = shared->iface; 491 struct vpu_dec_ctrl *hc = shared->priv; 492 struct vpu_malone_str_buffer __iomem *str_buf = hc->str_buf[instance]; 493 494 writel(buf->phys, &str_buf->start); 495 writel(buf->phys, &str_buf->rptr); 496 writel(buf->phys, &str_buf->wptr); 497 writel(buf->phys + buf->length, &str_buf->end); 498 writel(0x1, &str_buf->lwm); 499 500 iface->stream_buffer_desc[instance][0] = hc->buf_addr[instance]; 501 502 return 0; 503 } 504 505 int vpu_malone_get_stream_buffer_desc(struct vpu_shared_addr *shared, 506 u32 instance, 507 struct vpu_rpc_buffer_desc *desc) 508 { 509 struct vpu_dec_ctrl *hc = shared->priv; 510 struct vpu_malone_str_buffer __iomem *str_buf = hc->str_buf[instance]; 511 512 if (desc) { 513 desc->wptr = readl(&str_buf->wptr); 514 desc->rptr = readl(&str_buf->rptr); 515 desc->start = readl(&str_buf->start); 516 desc->end = readl(&str_buf->end); 517 } 518 519 return 0; 520 } 521 522 static void vpu_malone_update_wptr(struct vpu_malone_str_buffer __iomem *str_buf, u32 wptr) 523 { 524 /*update wptr after data is written*/ 525 mb(); 526 writel(wptr, &str_buf->wptr); 527 } 528 529 static void vpu_malone_update_rptr(struct vpu_malone_str_buffer __iomem *str_buf, u32 rptr) 530 { 531 /*update rptr after data is read*/ 532 mb(); 533 writel(rptr, &str_buf->rptr); 534 } 535 536 int vpu_malone_update_stream_buffer(struct vpu_shared_addr *shared, 537 u32 instance, u32 ptr, bool write) 538 { 539 struct vpu_dec_ctrl *hc = shared->priv; 540 struct vpu_malone_str_buffer __iomem *str_buf = hc->str_buf[instance]; 541 542 if (write) 543 vpu_malone_update_wptr(str_buf, ptr); 544 else 545 vpu_malone_update_rptr(str_buf, ptr); 546 547 return 0; 548 } 549 550 static struct malone_fmt_mapping fmt_mappings[] = { 551 {V4L2_PIX_FMT_H264, MALONE_FMT_AVC}, 552 {V4L2_PIX_FMT_H264_MVC, MALONE_FMT_AVC}, 553 {V4L2_PIX_FMT_HEVC, MALONE_FMT_HEVC}, 554 {V4L2_PIX_FMT_VC1_ANNEX_G, MALONE_FMT_VC1}, 555 {V4L2_PIX_FMT_VC1_ANNEX_L, MALONE_FMT_VC1}, 556 {V4L2_PIX_FMT_MPEG2, MALONE_FMT_MP2}, 557 {V4L2_PIX_FMT_MPEG4, MALONE_FMT_ASP}, 558 {V4L2_PIX_FMT_XVID, MALONE_FMT_ASP}, 559 {V4L2_PIX_FMT_H263, MALONE_FMT_ASP}, 560 {V4L2_PIX_FMT_JPEG, MALONE_FMT_JPG}, 561 {V4L2_PIX_FMT_VP8, MALONE_FMT_VP8}, 562 }; 563 564 static enum vpu_malone_format vpu_malone_format_remap(u32 pixelformat) 565 { 566 u32 i; 567 568 for (i = 0; i < ARRAY_SIZE(fmt_mappings); i++) { 569 if (pixelformat == fmt_mappings[i].pixelformat) 570 return fmt_mappings[i].malone_format; 571 } 572 573 return MALONE_FMT_NULL; 574 } 575 576 static void vpu_malone_set_stream_cfg(struct vpu_shared_addr *shared, 577 u32 instance, 578 enum vpu_malone_format malone_format) 579 { 580 struct malone_iface *iface = shared->iface; 581 u32 *curr_str_cfg = &iface->stream_config[instance]; 582 583 *curr_str_cfg = 0; 584 STREAM_CONFIG_FORMAT_SET(malone_format, curr_str_cfg); 585 STREAM_CONFIG_STRBUFIDX_SET(0, curr_str_cfg); 586 STREAM_CONFIG_NOSEQ_SET(0, curr_str_cfg); 587 STREAM_CONFIG_DEBLOCK_SET(0, curr_str_cfg); 588 STREAM_CONFIG_DERING_SET(0, curr_str_cfg); 589 STREAM_CONFIG_PLAY_MODE_SET(0x3, curr_str_cfg); 590 STREAM_CONFIG_FS_CTRL_MODE_SET(0x1, curr_str_cfg); 591 STREAM_CONFIG_ENABLE_DCP_SET(1, curr_str_cfg); 592 STREAM_CONFIG_NUM_STR_BUF_SET(1, curr_str_cfg); 593 STREAM_CONFIG_MALONE_USAGE_SET(1, curr_str_cfg); 594 STREAM_CONFIG_MULTI_VID_SET(0, curr_str_cfg); 595 STREAM_CONFIG_OBFUSC_EN_SET(0, curr_str_cfg); 596 STREAM_CONFIG_RC4_EN_SET(0, curr_str_cfg); 597 STREAM_CONFIG_MCX_SET(1, curr_str_cfg); 598 STREAM_CONFIG_PES_SET(0, curr_str_cfg); 599 STREAM_CONFIG_NUM_DBE_SET(1, curr_str_cfg); 600 } 601 602 static int vpu_malone_set_params(struct vpu_shared_addr *shared, 603 u32 instance, 604 struct vpu_decode_params *params) 605 { 606 struct malone_iface *iface = shared->iface; 607 struct vpu_dec_ctrl *hc = shared->priv; 608 enum vpu_malone_format malone_format; 609 610 malone_format = vpu_malone_format_remap(params->codec_format); 611 iface->udata_buffer[instance].base = params->udata.base; 612 iface->udata_buffer[instance].slot_size = params->udata.size; 613 614 vpu_malone_set_stream_cfg(shared, instance, malone_format); 615 616 if (malone_format == MALONE_FMT_JPG) { 617 //1:JPGD_MJPEG_MODE_A; 2:JPGD_MJPEG_MODE_B 618 hc->jpg[instance].jpg_mjpeg_mode = 1; 619 //0: JPGD_MJPEG_PROGRESSIVE 620 hc->jpg[instance].jpg_mjpeg_interlaced = 0; 621 } 622 623 hc->codec_param[instance].disp_imm = params->b_dis_reorder ? 1 : 0; 624 hc->codec_param[instance].dbglog_enable = 0; 625 iface->dbglog_desc.level = 0; 626 627 if (params->b_non_frame) 628 iface->stream_buff_info[instance].stream_input_mode = NON_FRAME_LVL; 629 else 630 iface->stream_buff_info[instance].stream_input_mode = FRAME_LVL; 631 iface->stream_buff_info[instance].stream_buffer_threshold = 0; 632 iface->stream_buff_info[instance].stream_pic_input_count = 0; 633 634 return 0; 635 } 636 637 static bool vpu_malone_is_non_frame_mode(struct vpu_shared_addr *shared, u32 instance) 638 { 639 struct malone_iface *iface = shared->iface; 640 641 if (iface->stream_buff_info[instance].stream_input_mode == NON_FRAME_LVL) 642 return true; 643 644 return false; 645 } 646 647 static int vpu_malone_update_params(struct vpu_shared_addr *shared, 648 u32 instance, 649 struct vpu_decode_params *params) 650 { 651 struct malone_iface *iface = shared->iface; 652 653 if (params->end_flag) 654 iface->stream_buff_info[instance].stream_pic_end_flag = params->end_flag; 655 params->end_flag = 0; 656 657 return 0; 658 } 659 660 int vpu_malone_set_decode_params(struct vpu_shared_addr *shared, 661 u32 instance, 662 struct vpu_decode_params *params, 663 u32 update) 664 { 665 if (!params) 666 return -EINVAL; 667 668 if (!update) 669 return vpu_malone_set_params(shared, instance, params); 670 else 671 return vpu_malone_update_params(shared, instance, params); 672 } 673 674 static struct vpu_pair malone_cmds[] = { 675 {VPU_CMD_ID_START, VID_API_CMD_START}, 676 {VPU_CMD_ID_STOP, VID_API_CMD_STOP}, 677 {VPU_CMD_ID_ABORT, VID_API_CMD_ABORT}, 678 {VPU_CMD_ID_RST_BUF, VID_API_CMD_RST_BUF}, 679 {VPU_CMD_ID_SNAPSHOT, VID_API_CMD_SNAPSHOT}, 680 {VPU_CMD_ID_FIRM_RESET, VID_API_CMD_FIRM_RESET}, 681 {VPU_CMD_ID_FS_ALLOC, VID_API_CMD_FS_ALLOC}, 682 {VPU_CMD_ID_FS_RELEASE, VID_API_CMD_FS_RELEASE}, 683 {VPU_CMD_ID_TIMESTAMP, VID_API_CMD_TS}, 684 {VPU_CMD_ID_DEBUG, VID_API_CMD_FW_STATUS}, 685 }; 686 687 static struct vpu_pair malone_msgs[] = { 688 {VPU_MSG_ID_RESET_DONE, VID_API_EVENT_RESET_DONE}, 689 {VPU_MSG_ID_START_DONE, VID_API_EVENT_START_DONE}, 690 {VPU_MSG_ID_STOP_DONE, VID_API_EVENT_STOPPED}, 691 {VPU_MSG_ID_ABORT_DONE, VID_API_EVENT_ABORT_DONE}, 692 {VPU_MSG_ID_BUF_RST, VID_API_EVENT_STR_BUF_RST}, 693 {VPU_MSG_ID_PIC_EOS, VID_API_EVENT_FINISHED}, 694 {VPU_MSG_ID_SEQ_HDR_FOUND, VID_API_EVENT_SEQ_HDR_FOUND}, 695 {VPU_MSG_ID_RES_CHANGE, VID_API_EVENT_RES_CHANGE}, 696 {VPU_MSG_ID_PIC_HDR_FOUND, VID_API_EVENT_PIC_HDR_FOUND}, 697 {VPU_MSG_ID_PIC_DECODED, VID_API_EVENT_PIC_DECODED}, 698 {VPU_MSG_ID_DEC_DONE, VID_API_EVENT_FRAME_BUFF_RDY}, 699 {VPU_MSG_ID_FRAME_REQ, VID_API_EVENT_REQ_FRAME_BUFF}, 700 {VPU_MSG_ID_FRAME_RELEASE, VID_API_EVENT_REL_FRAME_BUFF}, 701 {VPU_MSG_ID_FIFO_LOW, VID_API_EVENT_FIFO_LOW}, 702 {VPU_MSG_ID_BS_ERROR, VID_API_EVENT_BS_ERROR}, 703 {VPU_MSG_ID_UNSUPPORTED, VID_API_EVENT_UNSUPPORTED_STREAM}, 704 {VPU_MSG_ID_FIRMWARE_XCPT, VID_API_EVENT_FIRMWARE_XCPT}, 705 }; 706 707 static void vpu_malone_pack_fs_alloc(struct vpu_rpc_event *pkt, 708 struct vpu_fs_info *fs) 709 { 710 const u32 fs_type[] = { 711 [MEM_RES_FRAME] = 0, 712 [MEM_RES_MBI] = 1, 713 [MEM_RES_DCP] = 2, 714 }; 715 716 pkt->hdr.num = 7; 717 pkt->data[0] = fs->id | (fs->tag << 24); 718 pkt->data[1] = fs->luma_addr; 719 if (fs->type == MEM_RES_FRAME) { 720 /* 721 * if luma_addr equal to chroma_addr, 722 * means luma(plane[0]) and chromau(plane[1]) used the 723 * same fd -- usage of NXP codec2. Need to manually 724 * offset chroma addr. 725 */ 726 if (fs->luma_addr == fs->chroma_addr) 727 fs->chroma_addr = fs->luma_addr + fs->luma_size; 728 pkt->data[2] = fs->luma_addr + fs->luma_size / 2; 729 pkt->data[3] = fs->chroma_addr; 730 pkt->data[4] = fs->chroma_addr + fs->chromau_size / 2; 731 pkt->data[5] = fs->bytesperline; 732 } else { 733 pkt->data[2] = fs->luma_size; 734 pkt->data[3] = 0; 735 pkt->data[4] = 0; 736 pkt->data[5] = 0; 737 } 738 pkt->data[6] = fs_type[fs->type]; 739 } 740 741 static void vpu_malone_pack_fs_release(struct vpu_rpc_event *pkt, 742 struct vpu_fs_info *fs) 743 { 744 pkt->hdr.num = 1; 745 pkt->data[0] = fs->id | (fs->tag << 24); 746 } 747 748 static void vpu_malone_pack_timestamp(struct vpu_rpc_event *pkt, 749 struct vpu_ts_info *info) 750 { 751 pkt->hdr.num = 3; 752 if (info->timestamp < 0) { 753 pkt->data[0] = (u32)-1; 754 pkt->data[1] = 0; 755 } else { 756 pkt->data[0] = info->timestamp / NSEC_PER_SEC; 757 pkt->data[1] = info->timestamp % NSEC_PER_SEC; 758 } 759 pkt->data[2] = info->size; 760 } 761 762 int vpu_malone_pack_cmd(struct vpu_rpc_event *pkt, u32 index, u32 id, void *data) 763 { 764 int ret; 765 766 ret = vpu_find_dst_by_src(malone_cmds, ARRAY_SIZE(malone_cmds), id); 767 if (ret < 0) 768 return ret; 769 770 pkt->hdr.id = ret; 771 pkt->hdr.num = 0; 772 pkt->hdr.index = index; 773 774 switch (id) { 775 case VPU_CMD_ID_FS_ALLOC: 776 vpu_malone_pack_fs_alloc(pkt, data); 777 break; 778 case VPU_CMD_ID_FS_RELEASE: 779 vpu_malone_pack_fs_release(pkt, data); 780 break; 781 case VPU_CMD_ID_TIMESTAMP: 782 vpu_malone_pack_timestamp(pkt, data); 783 break; 784 } 785 786 pkt->hdr.index = index; 787 return 0; 788 } 789 790 int vpu_malone_convert_msg_id(u32 id) 791 { 792 return vpu_find_src_by_dst(malone_msgs, ARRAY_SIZE(malone_msgs), id); 793 } 794 795 static void vpu_malone_fill_planes(struct vpu_dec_codec_info *info) 796 { 797 u32 interlaced = info->progressive ? 0 : 1; 798 799 info->bytesperline[0] = 0; 800 info->sizeimage[0] = vpu_helper_get_plane_size(info->pixfmt, 801 info->decoded_width, 802 info->decoded_height, 803 0, 804 info->stride, 805 interlaced, 806 &info->bytesperline[0]); 807 info->bytesperline[1] = 0; 808 info->sizeimage[1] = vpu_helper_get_plane_size(info->pixfmt, 809 info->decoded_width, 810 info->decoded_height, 811 1, 812 info->stride, 813 interlaced, 814 &info->bytesperline[1]); 815 } 816 817 static void vpu_malone_init_seq_hdr(struct vpu_dec_codec_info *info) 818 { 819 u32 chunks = info->num_dfe_area >> MALONE_DCP_CHUNK_BIT; 820 821 vpu_malone_fill_planes(info); 822 823 info->mbi_size = (info->sizeimage[0] + info->sizeimage[1]) >> 2; 824 info->mbi_size = ALIGN(info->mbi_size, MALONE_ALIGN_MBI); 825 826 info->dcp_size = MALONE_DCP_SIZE_MAX; 827 if (chunks) { 828 u32 mb_num; 829 u32 mb_w; 830 u32 mb_h; 831 832 mb_w = DIV_ROUND_UP(info->decoded_width, 16); 833 mb_h = DIV_ROUND_UP(info->decoded_height, 16); 834 mb_num = mb_w * mb_h; 835 info->dcp_size = mb_num * MALONE_DCP_FIXED_MB_ALLOC * chunks; 836 info->dcp_size = clamp_t(u32, info->dcp_size, 837 MALONE_DCP_SIZE_MIN, MALONE_DCP_SIZE_MAX); 838 } 839 } 840 841 static void vpu_malone_unpack_seq_hdr(struct vpu_rpc_event *pkt, 842 struct vpu_dec_codec_info *info) 843 { 844 info->num_ref_frms = pkt->data[0]; 845 info->num_dpb_frms = pkt->data[1]; 846 info->num_dfe_area = pkt->data[2]; 847 info->progressive = pkt->data[3]; 848 info->width = pkt->data[5]; 849 info->height = pkt->data[4]; 850 info->decoded_width = pkt->data[12]; 851 info->decoded_height = pkt->data[11]; 852 info->frame_rate.numerator = 1000; 853 info->frame_rate.denominator = pkt->data[8]; 854 info->dsp_asp_ratio = pkt->data[9]; 855 info->level_idc = pkt->data[10]; 856 info->bit_depth_luma = pkt->data[13]; 857 info->bit_depth_chroma = pkt->data[14]; 858 info->chroma_fmt = pkt->data[15]; 859 info->color_primaries = vpu_color_cvrt_primaries_i2v(pkt->data[16]); 860 info->transfer_chars = vpu_color_cvrt_transfers_i2v(pkt->data[17]); 861 info->matrix_coeffs = vpu_color_cvrt_matrix_i2v(pkt->data[18]); 862 info->full_range = vpu_color_cvrt_full_range_i2v(pkt->data[19]); 863 info->vui_present = pkt->data[20]; 864 info->mvc_num_views = pkt->data[21]; 865 info->offset_x = pkt->data[23]; 866 info->offset_y = pkt->data[25]; 867 info->tag = pkt->data[27]; 868 if (info->bit_depth_luma > 8) 869 info->pixfmt = V4L2_PIX_FMT_NV12M_10BE_8L128; 870 else 871 info->pixfmt = V4L2_PIX_FMT_NV12M_8L128; 872 if (info->frame_rate.numerator && info->frame_rate.denominator) { 873 unsigned long n, d; 874 875 rational_best_approximation(info->frame_rate.numerator, 876 info->frame_rate.denominator, 877 info->frame_rate.numerator, 878 info->frame_rate.denominator, 879 &n, &d); 880 info->frame_rate.numerator = n; 881 info->frame_rate.denominator = d; 882 } 883 vpu_malone_init_seq_hdr(info); 884 } 885 886 static void vpu_malone_unpack_pic_info(struct vpu_rpc_event *pkt, 887 struct vpu_dec_pic_info *info) 888 { 889 info->id = pkt->data[7]; 890 info->luma = pkt->data[0]; 891 info->start = pkt->data[10]; 892 info->end = pkt->data[12]; 893 info->pic_size = pkt->data[11]; 894 info->stride = pkt->data[5]; 895 info->consumed_count = pkt->data[13]; 896 if (info->id == MALONE_SKIPPED_FRAME_ID) 897 info->skipped = 1; 898 else 899 info->skipped = 0; 900 } 901 902 static void vpu_malone_unpack_req_frame(struct vpu_rpc_event *pkt, 903 struct vpu_fs_info *info) 904 { 905 info->type = pkt->data[1]; 906 } 907 908 static void vpu_malone_unpack_rel_frame(struct vpu_rpc_event *pkt, 909 struct vpu_fs_info *info) 910 { 911 info->id = pkt->data[0]; 912 info->type = pkt->data[1]; 913 info->not_displayed = pkt->data[2]; 914 } 915 916 static void vpu_malone_unpack_buff_rdy(struct vpu_rpc_event *pkt, 917 struct vpu_dec_pic_info *info) 918 { 919 info->id = pkt->data[0]; 920 info->luma = pkt->data[1]; 921 info->stride = pkt->data[3]; 922 if (info->id == MALONE_SKIPPED_FRAME_ID) 923 info->skipped = 1; 924 else 925 info->skipped = 0; 926 info->timestamp = MAKE_TIMESTAMP(pkt->data[9], pkt->data[10]); 927 } 928 929 int vpu_malone_unpack_msg_data(struct vpu_rpc_event *pkt, void *data) 930 { 931 if (!pkt || !data) 932 return -EINVAL; 933 934 switch (pkt->hdr.id) { 935 case VID_API_EVENT_SEQ_HDR_FOUND: 936 vpu_malone_unpack_seq_hdr(pkt, data); 937 break; 938 case VID_API_EVENT_PIC_DECODED: 939 vpu_malone_unpack_pic_info(pkt, data); 940 break; 941 case VID_API_EVENT_REQ_FRAME_BUFF: 942 vpu_malone_unpack_req_frame(pkt, data); 943 break; 944 case VID_API_EVENT_REL_FRAME_BUFF: 945 vpu_malone_unpack_rel_frame(pkt, data); 946 break; 947 case VID_API_EVENT_FRAME_BUFF_RDY: 948 vpu_malone_unpack_buff_rdy(pkt, data); 949 break; 950 } 951 952 return 0; 953 } 954 955 static const struct malone_padding_scode padding_scodes[] = { 956 {SCODE_PADDING_EOS, V4L2_PIX_FMT_H264, {0x0B010000, 0}}, 957 {SCODE_PADDING_EOS, V4L2_PIX_FMT_H264_MVC, {0x0B010000, 0}}, 958 {SCODE_PADDING_EOS, V4L2_PIX_FMT_HEVC, {0x4A010000, 0x20}}, 959 {SCODE_PADDING_EOS, V4L2_PIX_FMT_VC1_ANNEX_G, {0x0a010000, 0x0}}, 960 {SCODE_PADDING_EOS, V4L2_PIX_FMT_VC1_ANNEX_L, {0x0a010000, 0x0}}, 961 {SCODE_PADDING_EOS, V4L2_PIX_FMT_MPEG2, {0xCC010000, 0x0}}, 962 {SCODE_PADDING_EOS, V4L2_PIX_FMT_MPEG4, {0xb1010000, 0x0}}, 963 {SCODE_PADDING_EOS, V4L2_PIX_FMT_XVID, {0xb1010000, 0x0}}, 964 {SCODE_PADDING_EOS, V4L2_PIX_FMT_H263, {0xb1010000, 0x0}}, 965 {SCODE_PADDING_EOS, V4L2_PIX_FMT_VP8, {0x34010000, 0x0}}, 966 {SCODE_PADDING_EOS, V4L2_PIX_FMT_JPEG, {0xefff0000, 0x0}}, 967 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_H264, {0x0B010000, 0}}, 968 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_H264_MVC, {0x0B010000, 0}}, 969 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_HEVC, {0x4A010000, 0x20}}, 970 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_VC1_ANNEX_G, {0x0a010000, 0x0}}, 971 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_VC1_ANNEX_L, {0x0a010000, 0x0}}, 972 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_MPEG2, {0xb7010000, 0x0}}, 973 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_MPEG4, {0xb1010000, 0x0}}, 974 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_XVID, {0xb1010000, 0x0}}, 975 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_H263, {0xb1010000, 0x0}}, 976 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_VP8, {0x34010000, 0x0}}, 977 {SCODE_PADDING_EOS, V4L2_PIX_FMT_JPEG, {0x0, 0x0}}, 978 {SCODE_PADDING_BUFFLUSH, V4L2_PIX_FMT_H264, {0x15010000, 0x0}}, 979 {SCODE_PADDING_BUFFLUSH, V4L2_PIX_FMT_H264_MVC, {0x15010000, 0x0}}, 980 }; 981 982 static const struct malone_padding_scode padding_scode_dft = {0x0, 0x0}; 983 984 static const struct malone_padding_scode *get_padding_scode(u32 type, u32 fmt) 985 { 986 const struct malone_padding_scode *s; 987 int i; 988 989 for (i = 0; i < ARRAY_SIZE(padding_scodes); i++) { 990 s = &padding_scodes[i]; 991 992 if (s->scode_type == type && s->pixelformat == fmt) 993 return s; 994 } 995 996 if (type != SCODE_PADDING_BUFFLUSH) 997 return &padding_scode_dft; 998 999 return NULL; 1000 } 1001 1002 static int vpu_malone_add_padding_scode(struct vpu_buffer *stream_buffer, 1003 struct vpu_malone_str_buffer __iomem *str_buf, 1004 u32 pixelformat, u32 scode_type) 1005 { 1006 u32 wptr; 1007 u32 size; 1008 u32 total_size = 0; 1009 const struct malone_padding_scode *ps; 1010 const u32 padding_size = 4096; 1011 int ret; 1012 1013 ps = get_padding_scode(scode_type, pixelformat); 1014 if (!ps) 1015 return -EINVAL; 1016 1017 wptr = readl(&str_buf->wptr); 1018 size = ALIGN(wptr, 4) - wptr; 1019 if (size) 1020 vpu_helper_memset_stream_buffer(stream_buffer, &wptr, 0, size); 1021 total_size += size; 1022 1023 size = sizeof(ps->data); 1024 ret = vpu_helper_copy_to_stream_buffer(stream_buffer, &wptr, size, (void *)ps->data); 1025 if (ret < size) 1026 return -EINVAL; 1027 total_size += size; 1028 1029 size = padding_size - sizeof(ps->data); 1030 vpu_helper_memset_stream_buffer(stream_buffer, &wptr, 0, size); 1031 total_size += size; 1032 1033 vpu_malone_update_wptr(str_buf, wptr); 1034 return total_size; 1035 } 1036 1037 int vpu_malone_add_scode(struct vpu_shared_addr *shared, 1038 u32 instance, 1039 struct vpu_buffer *stream_buffer, 1040 u32 pixelformat, 1041 u32 scode_type) 1042 { 1043 struct vpu_dec_ctrl *hc = shared->priv; 1044 struct vpu_malone_str_buffer __iomem *str_buf = hc->str_buf[instance]; 1045 int ret = -EINVAL; 1046 1047 switch (scode_type) { 1048 case SCODE_PADDING_EOS: 1049 case SCODE_PADDING_ABORT: 1050 case SCODE_PADDING_BUFFLUSH: 1051 ret = vpu_malone_add_padding_scode(stream_buffer, str_buf, pixelformat, scode_type); 1052 break; 1053 default: 1054 break; 1055 } 1056 1057 return ret; 1058 } 1059 1060 #define MALONE_PAYLOAD_HEADER_SIZE 16 1061 #define MALONE_CODEC_VERSION_ID 0x1 1062 #define MALONE_CODEC_ID_VC1_SIMPLE 0x10 1063 #define MALONE_CODEC_ID_VC1_MAIN 0x11 1064 #define MALONE_CODEC_ID_ARV8 0x28 1065 #define MALONE_CODEC_ID_ARV9 0x29 1066 #define MALONE_CODEC_ID_VP6 0x36 1067 #define MALONE_CODEC_ID_VP8 0x36 1068 #define MALONE_CODEC_ID_DIVX3 0x38 1069 #define MALONE_CODEC_ID_SPK 0x39 1070 1071 #define MALONE_VP8_IVF_SEQ_HEADER_LEN 32 1072 #define MALONE_VP8_IVF_FRAME_HEADER_LEN 8 1073 1074 #define MALONE_VC1_RCV_CODEC_V1_VERSION 0x85 1075 #define MALONE_VC1_RCV_CODEC_V2_VERSION 0xC5 1076 #define MALONE_VC1_RCV_NUM_FRAMES 0xFF 1077 #define MALONE_VC1_RCV_SEQ_EXT_DATA_SIZE 4 1078 #define MALONE_VC1_RCV_SEQ_HEADER_LEN 20 1079 #define MALONE_VC1_RCV_PIC_HEADER_LEN 4 1080 #define MALONE_VC1_NAL_HEADER_LEN 4 1081 #define MALONE_VC1_CONTAIN_NAL(data) (((data) & 0x00FFFFFF) == 0x00010000) 1082 1083 static void set_payload_hdr(u8 *dst, u32 scd_type, u32 codec_id, 1084 u32 buffer_size, u32 width, u32 height) 1085 { 1086 unsigned int payload_size; 1087 /* payload_size = buffer_size + itself_size(16) - start_code(4) */ 1088 payload_size = buffer_size + 12; 1089 1090 dst[0] = 0x00; 1091 dst[1] = 0x00; 1092 dst[2] = 0x01; 1093 dst[3] = scd_type; 1094 1095 /* length */ 1096 dst[4] = ((payload_size >> 16) & 0xff); 1097 dst[5] = ((payload_size >> 8) & 0xff); 1098 dst[6] = 0x4e; 1099 dst[7] = ((payload_size >> 0) & 0xff); 1100 1101 /* Codec ID and Version */ 1102 dst[8] = codec_id; 1103 dst[9] = MALONE_CODEC_VERSION_ID; 1104 1105 /* width */ 1106 dst[10] = ((width >> 8) & 0xff); 1107 dst[11] = ((width >> 0) & 0xff); 1108 dst[12] = 0x58; 1109 1110 /* height */ 1111 dst[13] = ((height >> 8) & 0xff); 1112 dst[14] = ((height >> 0) & 0xff); 1113 dst[15] = 0x50; 1114 } 1115 1116 static void set_vp8_ivf_seqhdr(u8 *dst, u32 width, u32 height) 1117 { 1118 /* 0-3byte signature "DKIF" */ 1119 dst[0] = 0x44; 1120 dst[1] = 0x4b; 1121 dst[2] = 0x49; 1122 dst[3] = 0x46; 1123 /* 4-5byte version: should be 0*/ 1124 dst[4] = 0x00; 1125 dst[5] = 0x00; 1126 /* 6-7 length of Header */ 1127 dst[6] = MALONE_VP8_IVF_SEQ_HEADER_LEN; 1128 dst[7] = MALONE_VP8_IVF_SEQ_HEADER_LEN >> 8; 1129 /* 8-11 VP8 fourcc */ 1130 dst[8] = 0x56; 1131 dst[9] = 0x50; 1132 dst[10] = 0x38; 1133 dst[11] = 0x30; 1134 /* 12-13 width in pixels */ 1135 dst[12] = width; 1136 dst[13] = width >> 8; 1137 /* 14-15 height in pixels */ 1138 dst[14] = height; 1139 dst[15] = height >> 8; 1140 /* 16-19 frame rate */ 1141 dst[16] = 0xe8; 1142 dst[17] = 0x03; 1143 dst[18] = 0x00; 1144 dst[19] = 0x00; 1145 /* 20-23 time scale */ 1146 dst[20] = 0x01; 1147 dst[21] = 0x00; 1148 dst[22] = 0x00; 1149 dst[23] = 0x00; 1150 /* 24-27 number frames */ 1151 dst[24] = 0xdf; 1152 dst[25] = 0xf9; 1153 dst[26] = 0x09; 1154 dst[27] = 0x00; 1155 /* 28-31 reserved */ 1156 } 1157 1158 static void set_vp8_ivf_pichdr(u8 *dst, u32 frame_size) 1159 { 1160 /* 1161 * firmware just parse 64-bit timestamp(8 bytes). 1162 * As not transfer timestamp to firmware, use default value(ZERO). 1163 * No need to do anything here 1164 */ 1165 } 1166 1167 static void set_vc1_rcv_seqhdr(u8 *dst, u8 *src, u32 width, u32 height) 1168 { 1169 u32 frames = MALONE_VC1_RCV_NUM_FRAMES; 1170 u32 ext_data_size = MALONE_VC1_RCV_SEQ_EXT_DATA_SIZE; 1171 1172 /* 0-2 Number of frames, used default value 0xFF */ 1173 dst[0] = frames; 1174 dst[1] = frames >> 8; 1175 dst[2] = frames >> 16; 1176 1177 /* 3 RCV version, used V1 */ 1178 dst[3] = MALONE_VC1_RCV_CODEC_V1_VERSION; 1179 1180 /* 4-7 extension data size */ 1181 dst[4] = ext_data_size; 1182 dst[5] = ext_data_size >> 8; 1183 dst[6] = ext_data_size >> 16; 1184 dst[7] = ext_data_size >> 24; 1185 /* 8-11 extension data */ 1186 dst[8] = src[0]; 1187 dst[9] = src[1]; 1188 dst[10] = src[2]; 1189 dst[11] = src[3]; 1190 1191 /* height */ 1192 dst[12] = height; 1193 dst[13] = (height >> 8) & 0xff; 1194 dst[14] = (height >> 16) & 0xff; 1195 dst[15] = (height >> 24) & 0xff; 1196 /* width */ 1197 dst[16] = width; 1198 dst[17] = (width >> 8) & 0xff; 1199 dst[18] = (width >> 16) & 0xff; 1200 dst[19] = (width >> 24) & 0xff; 1201 } 1202 1203 static void set_vc1_rcv_pichdr(u8 *dst, u32 buffer_size) 1204 { 1205 dst[0] = buffer_size; 1206 dst[1] = buffer_size >> 8; 1207 dst[2] = buffer_size >> 16; 1208 dst[3] = buffer_size >> 24; 1209 } 1210 1211 static void create_vc1_nal_pichdr(u8 *dst) 1212 { 1213 /* need insert nal header: special ID */ 1214 dst[0] = 0x0; 1215 dst[1] = 0x0; 1216 dst[2] = 0x01; 1217 dst[3] = 0x0D; 1218 } 1219 1220 static int vpu_malone_insert_scode_seq(struct malone_scode_t *scode, u32 codec_id, u32 ext_size) 1221 { 1222 u8 hdr[MALONE_PAYLOAD_HEADER_SIZE]; 1223 int ret; 1224 1225 set_payload_hdr(hdr, 1226 SCODE_SEQUENCE, 1227 codec_id, 1228 ext_size, 1229 scode->inst->out_format.width, 1230 scode->inst->out_format.height); 1231 ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer, 1232 &scode->wptr, 1233 sizeof(hdr), 1234 hdr); 1235 return ret; 1236 } 1237 1238 static int vpu_malone_insert_scode_pic(struct malone_scode_t *scode, u32 codec_id, u32 ext_size) 1239 { 1240 u8 hdr[MALONE_PAYLOAD_HEADER_SIZE]; 1241 1242 set_payload_hdr(hdr, 1243 SCODE_PICTURE, 1244 codec_id, 1245 ext_size + vb2_get_plane_payload(scode->vb, 0), 1246 scode->inst->out_format.width, 1247 scode->inst->out_format.height); 1248 return vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer, 1249 &scode->wptr, 1250 sizeof(hdr), 1251 hdr); 1252 } 1253 1254 static int vpu_malone_insert_scode_vc1_g_pic(struct malone_scode_t *scode) 1255 { 1256 struct vb2_v4l2_buffer *vbuf; 1257 u8 nal_hdr[MALONE_VC1_NAL_HEADER_LEN]; 1258 u32 *data = NULL; 1259 1260 vbuf = to_vb2_v4l2_buffer(scode->vb); 1261 data = vb2_plane_vaddr(scode->vb, 0); 1262 1263 if (vbuf->sequence == 0 || vpu_vb_is_codecconfig(vbuf)) 1264 return 0; 1265 if (MALONE_VC1_CONTAIN_NAL(*data)) 1266 return 0; 1267 1268 create_vc1_nal_pichdr(nal_hdr); 1269 return vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer, 1270 &scode->wptr, 1271 sizeof(nal_hdr), 1272 nal_hdr); 1273 } 1274 1275 static int vpu_malone_insert_scode_vc1_l_seq(struct malone_scode_t *scode) 1276 { 1277 int ret; 1278 int size = 0; 1279 u8 rcv_seqhdr[MALONE_VC1_RCV_SEQ_HEADER_LEN]; 1280 1281 scode->need_data = 0; 1282 1283 ret = vpu_malone_insert_scode_seq(scode, MALONE_CODEC_ID_VC1_SIMPLE, 1284 sizeof(rcv_seqhdr)); 1285 if (ret < 0) 1286 return ret; 1287 size = ret; 1288 1289 set_vc1_rcv_seqhdr(rcv_seqhdr, 1290 vb2_plane_vaddr(scode->vb, 0), 1291 scode->inst->out_format.width, 1292 scode->inst->out_format.height); 1293 ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer, 1294 &scode->wptr, 1295 sizeof(rcv_seqhdr), 1296 rcv_seqhdr); 1297 1298 if (ret < 0) 1299 return ret; 1300 size += ret; 1301 return size; 1302 } 1303 1304 static int vpu_malone_insert_scode_vc1_l_pic(struct malone_scode_t *scode) 1305 { 1306 int ret; 1307 int size = 0; 1308 u8 rcv_pichdr[MALONE_VC1_RCV_PIC_HEADER_LEN]; 1309 1310 ret = vpu_malone_insert_scode_pic(scode, MALONE_CODEC_ID_VC1_SIMPLE, 1311 sizeof(rcv_pichdr)); 1312 if (ret < 0) 1313 return ret; 1314 size = ret; 1315 1316 set_vc1_rcv_pichdr(rcv_pichdr, vb2_get_plane_payload(scode->vb, 0)); 1317 ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer, 1318 &scode->wptr, 1319 sizeof(rcv_pichdr), 1320 rcv_pichdr); 1321 if (ret < 0) 1322 return ret; 1323 size += ret; 1324 return size; 1325 } 1326 1327 static int vpu_malone_insert_scode_vp8_seq(struct malone_scode_t *scode) 1328 { 1329 int ret; 1330 int size = 0; 1331 u8 ivf_hdr[MALONE_VP8_IVF_SEQ_HEADER_LEN]; 1332 1333 ret = vpu_malone_insert_scode_seq(scode, MALONE_CODEC_ID_VP8, sizeof(ivf_hdr)); 1334 if (ret < 0) 1335 return ret; 1336 size = ret; 1337 1338 set_vp8_ivf_seqhdr(ivf_hdr, 1339 scode->inst->out_format.width, 1340 scode->inst->out_format.height); 1341 ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer, 1342 &scode->wptr, 1343 sizeof(ivf_hdr), 1344 ivf_hdr); 1345 if (ret < 0) 1346 return ret; 1347 size += ret; 1348 1349 return size; 1350 } 1351 1352 static int vpu_malone_insert_scode_vp8_pic(struct malone_scode_t *scode) 1353 { 1354 int ret; 1355 int size = 0; 1356 u8 ivf_hdr[MALONE_VP8_IVF_FRAME_HEADER_LEN] = {0}; 1357 1358 ret = vpu_malone_insert_scode_pic(scode, MALONE_CODEC_ID_VP8, sizeof(ivf_hdr)); 1359 if (ret < 0) 1360 return ret; 1361 size = ret; 1362 1363 set_vp8_ivf_pichdr(ivf_hdr, vb2_get_plane_payload(scode->vb, 0)); 1364 ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer, 1365 &scode->wptr, 1366 sizeof(ivf_hdr), 1367 ivf_hdr); 1368 if (ret < 0) 1369 return ret; 1370 size += ret; 1371 1372 return size; 1373 } 1374 1375 static const struct malone_scode_handler scode_handlers[] = { 1376 { 1377 /* fix me, need to swap return operation after gstreamer swap */ 1378 .pixelformat = V4L2_PIX_FMT_VC1_ANNEX_L, 1379 .insert_scode_seq = vpu_malone_insert_scode_vc1_l_seq, 1380 .insert_scode_pic = vpu_malone_insert_scode_vc1_l_pic, 1381 }, 1382 { 1383 .pixelformat = V4L2_PIX_FMT_VC1_ANNEX_G, 1384 .insert_scode_pic = vpu_malone_insert_scode_vc1_g_pic, 1385 }, 1386 { 1387 .pixelformat = V4L2_PIX_FMT_VP8, 1388 .insert_scode_seq = vpu_malone_insert_scode_vp8_seq, 1389 .insert_scode_pic = vpu_malone_insert_scode_vp8_pic, 1390 }, 1391 }; 1392 1393 static const struct malone_scode_handler *get_scode_handler(u32 pixelformat) 1394 { 1395 int i; 1396 1397 for (i = 0; i < ARRAY_SIZE(scode_handlers); i++) { 1398 if (scode_handlers[i].pixelformat == pixelformat) 1399 return &scode_handlers[i]; 1400 } 1401 1402 return NULL; 1403 } 1404 1405 static int vpu_malone_insert_scode(struct malone_scode_t *scode, u32 type) 1406 { 1407 const struct malone_scode_handler *handler; 1408 int ret = 0; 1409 1410 if (!scode || !scode->inst || !scode->vb) 1411 return 0; 1412 1413 scode->need_data = 1; 1414 handler = get_scode_handler(scode->inst->out_format.pixfmt); 1415 if (!handler) 1416 return 0; 1417 1418 switch (type) { 1419 case SCODE_SEQUENCE: 1420 if (handler->insert_scode_seq) 1421 ret = handler->insert_scode_seq(scode); 1422 break; 1423 case SCODE_PICTURE: 1424 if (handler->insert_scode_pic) 1425 ret = handler->insert_scode_pic(scode); 1426 break; 1427 default: 1428 break; 1429 } 1430 1431 return ret; 1432 } 1433 1434 static int vpu_malone_input_frame_data(struct vpu_malone_str_buffer __iomem *str_buf, 1435 struct vpu_inst *inst, struct vb2_buffer *vb, 1436 u32 disp_imm) 1437 { 1438 struct malone_scode_t scode; 1439 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 1440 u32 wptr = readl(&str_buf->wptr); 1441 int size = 0; 1442 int ret = 0; 1443 1444 /*add scode: SCODE_SEQUENCE, SCODE_PICTURE, SCODE_SLICE*/ 1445 scode.inst = inst; 1446 scode.vb = vb; 1447 scode.wptr = wptr; 1448 scode.need_data = 1; 1449 if (vbuf->sequence == 0 || vpu_vb_is_codecconfig(vbuf)) 1450 ret = vpu_malone_insert_scode(&scode, SCODE_SEQUENCE); 1451 1452 if (ret < 0) 1453 return -ENOMEM; 1454 size += ret; 1455 wptr = scode.wptr; 1456 if (!scode.need_data) { 1457 vpu_malone_update_wptr(str_buf, wptr); 1458 return size; 1459 } 1460 1461 ret = vpu_malone_insert_scode(&scode, SCODE_PICTURE); 1462 if (ret < 0) 1463 return -ENOMEM; 1464 size += ret; 1465 wptr = scode.wptr; 1466 1467 ret = vpu_helper_copy_to_stream_buffer(&inst->stream_buffer, 1468 &wptr, 1469 vb2_get_plane_payload(vb, 0), 1470 vb2_plane_vaddr(vb, 0)); 1471 if (ret < vb2_get_plane_payload(vb, 0)) 1472 return -ENOMEM; 1473 size += ret; 1474 1475 vpu_malone_update_wptr(str_buf, wptr); 1476 1477 if (disp_imm && !vpu_vb_is_codecconfig(vbuf)) { 1478 ret = vpu_malone_add_scode(inst->core->iface, 1479 inst->id, 1480 &inst->stream_buffer, 1481 inst->out_format.pixfmt, 1482 SCODE_PADDING_BUFFLUSH); 1483 if (ret < 0) 1484 return ret; 1485 size += ret; 1486 } 1487 1488 return size; 1489 } 1490 1491 static int vpu_malone_input_stream_data(struct vpu_malone_str_buffer __iomem *str_buf, 1492 struct vpu_inst *inst, struct vb2_buffer *vb) 1493 { 1494 u32 wptr = readl(&str_buf->wptr); 1495 int ret = 0; 1496 1497 ret = vpu_helper_copy_to_stream_buffer(&inst->stream_buffer, 1498 &wptr, 1499 vb2_get_plane_payload(vb, 0), 1500 vb2_plane_vaddr(vb, 0)); 1501 if (ret < vb2_get_plane_payload(vb, 0)) 1502 return -ENOMEM; 1503 1504 vpu_malone_update_wptr(str_buf, wptr); 1505 1506 return ret; 1507 } 1508 1509 static int vpu_malone_input_ts(struct vpu_inst *inst, s64 timestamp, u32 size) 1510 { 1511 struct vpu_ts_info info; 1512 1513 memset(&info, 0, sizeof(info)); 1514 info.timestamp = timestamp; 1515 info.size = size; 1516 1517 return vpu_session_fill_timestamp(inst, &info); 1518 } 1519 1520 int vpu_malone_input_frame(struct vpu_shared_addr *shared, 1521 struct vpu_inst *inst, struct vb2_buffer *vb) 1522 { 1523 struct vpu_dec_ctrl *hc = shared->priv; 1524 struct vb2_v4l2_buffer *vbuf; 1525 struct vpu_malone_str_buffer __iomem *str_buf = hc->str_buf[inst->id]; 1526 u32 disp_imm = hc->codec_param[inst->id].disp_imm; 1527 u32 size; 1528 int ret; 1529 1530 if (vpu_malone_is_non_frame_mode(shared, inst->id)) 1531 ret = vpu_malone_input_stream_data(str_buf, inst, vb); 1532 else 1533 ret = vpu_malone_input_frame_data(str_buf, inst, vb, disp_imm); 1534 if (ret < 0) 1535 return ret; 1536 size = ret; 1537 1538 /* 1539 * if buffer only contain codec data, and the timestamp is invalid, 1540 * don't put the invalid timestamp to resync 1541 * merge the data to next frame 1542 */ 1543 vbuf = to_vb2_v4l2_buffer(vb); 1544 if (vpu_vb_is_codecconfig(vbuf) && (s64)vb->timestamp < 0) { 1545 inst->extra_size += size; 1546 return 0; 1547 } 1548 if (inst->extra_size) { 1549 size += inst->extra_size; 1550 inst->extra_size = 0; 1551 } 1552 1553 ret = vpu_malone_input_ts(inst, vb->timestamp, size); 1554 if (ret) 1555 return ret; 1556 1557 return 0; 1558 } 1559 1560 static bool vpu_malone_check_ready(struct vpu_shared_addr *shared, u32 instance) 1561 { 1562 struct malone_iface *iface = shared->iface; 1563 struct vpu_rpc_buffer_desc *desc = &iface->api_cmd_buffer_desc[instance]; 1564 u32 size = desc->end - desc->start; 1565 u32 rptr = desc->rptr; 1566 u32 wptr = desc->wptr; 1567 u32 used = (wptr + size - rptr) % size; 1568 1569 if (!size || used < size / 2) 1570 return true; 1571 1572 return false; 1573 } 1574 1575 bool vpu_malone_is_ready(struct vpu_shared_addr *shared, u32 instance) 1576 { 1577 u32 cnt = 0; 1578 1579 while (!vpu_malone_check_ready(shared, instance)) { 1580 if (cnt > 30) 1581 return false; 1582 mdelay(1); 1583 cnt++; 1584 } 1585 return true; 1586 } 1587 1588 int vpu_malone_pre_cmd(struct vpu_shared_addr *shared, u32 instance) 1589 { 1590 if (!vpu_malone_is_ready(shared, instance)) 1591 return -EINVAL; 1592 1593 return 0; 1594 } 1595 1596 int vpu_malone_post_cmd(struct vpu_shared_addr *shared, u32 instance) 1597 { 1598 struct malone_iface *iface = shared->iface; 1599 struct vpu_rpc_buffer_desc *desc = &iface->api_cmd_buffer_desc[instance]; 1600 1601 desc->wptr++; 1602 if (desc->wptr == desc->end) 1603 desc->wptr = desc->start; 1604 1605 return 0; 1606 } 1607 1608 int vpu_malone_init_instance(struct vpu_shared_addr *shared, u32 instance) 1609 { 1610 struct malone_iface *iface = shared->iface; 1611 struct vpu_rpc_buffer_desc *desc = &iface->api_cmd_buffer_desc[instance]; 1612 1613 desc->wptr = desc->rptr; 1614 if (desc->wptr == desc->end) 1615 desc->wptr = desc->start; 1616 1617 return 0; 1618 } 1619 1620 u32 vpu_malone_get_max_instance_count(struct vpu_shared_addr *shared) 1621 { 1622 struct malone_iface *iface = shared->iface; 1623 1624 return iface->max_streams; 1625 } 1626