1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright 2020-2021 NXP 4 */ 5 6 #ifndef _AMPHION_VPU_DEFS_H 7 #define _AMPHION_VPU_DEFS_H 8 9 enum MSG_TYPE { 10 INIT_DONE = 1, 11 PRC_BUF_OFFSET, 12 BOOT_ADDRESS, 13 COMMAND, 14 EVENT, 15 }; 16 17 enum { 18 VPU_IRQ_CODE_BOOT_DONE = 0x55, 19 VPU_IRQ_CODE_SNAPSHOT_DONE = 0xa5, 20 VPU_IRQ_CODE_SYNC = 0xaa, 21 }; 22 23 enum { 24 VPU_CMD_ID_NOOP = 0x0, 25 VPU_CMD_ID_CONFIGURE_CODEC, 26 VPU_CMD_ID_START, 27 VPU_CMD_ID_STOP, 28 VPU_CMD_ID_ABORT, 29 VPU_CMD_ID_RST_BUF, 30 VPU_CMD_ID_SNAPSHOT, 31 VPU_CMD_ID_FIRM_RESET, 32 VPU_CMD_ID_UPDATE_PARAMETER, 33 VPU_CMD_ID_FRAME_ENCODE, 34 VPU_CMD_ID_SKIP, 35 VPU_CMD_ID_PARSE_NEXT_SEQ, 36 VPU_CMD_ID_PARSE_NEXT_I, 37 VPU_CMD_ID_PARSE_NEXT_IP, 38 VPU_CMD_ID_PARSE_NEXT_ANY, 39 VPU_CMD_ID_DEC_PIC, 40 VPU_CMD_ID_FS_ALLOC, 41 VPU_CMD_ID_FS_RELEASE, 42 VPU_CMD_ID_TIMESTAMP, 43 VPU_CMD_ID_DEBUG 44 }; 45 46 enum { 47 VPU_MSG_ID_NOOP = 0x100, 48 VPU_MSG_ID_RESET_DONE, 49 VPU_MSG_ID_START_DONE, 50 VPU_MSG_ID_STOP_DONE, 51 VPU_MSG_ID_ABORT_DONE, 52 VPU_MSG_ID_BUF_RST, 53 VPU_MSG_ID_MEM_REQUEST, 54 VPU_MSG_ID_PARAM_UPD_DONE, 55 VPU_MSG_ID_FRAME_INPUT_DONE, 56 VPU_MSG_ID_ENC_DONE, 57 VPU_MSG_ID_DEC_DONE, 58 VPU_MSG_ID_FRAME_REQ, 59 VPU_MSG_ID_FRAME_RELEASE, 60 VPU_MSG_ID_SEQ_HDR_FOUND, 61 VPU_MSG_ID_RES_CHANGE, 62 VPU_MSG_ID_PIC_HDR_FOUND, 63 VPU_MSG_ID_PIC_DECODED, 64 VPU_MSG_ID_PIC_EOS, 65 VPU_MSG_ID_FIFO_LOW, 66 VPU_MSG_ID_FIFO_HIGH, 67 VPU_MSG_ID_FIFO_EMPTY, 68 VPU_MSG_ID_FIFO_FULL, 69 VPU_MSG_ID_BS_ERROR, 70 VPU_MSG_ID_UNSUPPORTED, 71 VPU_MSG_ID_TIMESTAMP_INFO, 72 VPU_MSG_ID_FIRMWARE_XCPT, 73 VPU_MSG_ID_PIC_SKIPPED, 74 }; 75 76 enum VPU_ENC_MEMORY_RESOURSE { 77 MEM_RES_ENC, 78 MEM_RES_REF, 79 MEM_RES_ACT 80 }; 81 82 enum VPU_DEC_MEMORY_RESOURCE { 83 MEM_RES_FRAME, 84 MEM_RES_MBI, 85 MEM_RES_DCP 86 }; 87 88 enum VPU_SCODE_TYPE { 89 SCODE_PADDING_EOS = 1, 90 SCODE_PADDING_BUFFLUSH = 2, 91 SCODE_PADDING_ABORT = 3, 92 SCODE_SEQUENCE = 0x31, 93 SCODE_PICTURE = 0x32, 94 SCODE_SLICE = 0x33 95 }; 96 97 struct vpu_pkt_mem_req_data { 98 u32 enc_frame_size; 99 u32 enc_frame_num; 100 u32 ref_frame_size; 101 u32 ref_frame_num; 102 u32 act_buf_size; 103 u32 act_buf_num; 104 }; 105 106 struct vpu_enc_pic_info { 107 u32 frame_id; 108 u32 pic_type; 109 u32 skipped_frame; 110 u32 error_flag; 111 u32 psnr; 112 u32 frame_size; 113 u32 wptr; 114 u32 crc; 115 s64 timestamp; 116 }; 117 118 struct vpu_dec_codec_info { 119 u32 pixfmt; 120 u32 num_ref_frms; 121 u32 num_dpb_frms; 122 u32 num_dfe_area; 123 u32 color_primaries; 124 u32 transfer_chars; 125 u32 matrix_coeffs; 126 u32 full_range; 127 u32 vui_present; 128 u32 progressive; 129 u32 width; 130 u32 height; 131 u32 decoded_width; 132 u32 decoded_height; 133 struct v4l2_fract frame_rate; 134 u32 dsp_asp_ratio; 135 u32 level_idc; 136 u32 bit_depth_luma; 137 u32 bit_depth_chroma; 138 u32 chroma_fmt; 139 u32 mvc_num_views; 140 u32 offset_x; 141 u32 offset_y; 142 u32 tag; 143 u32 sizeimage[VIDEO_MAX_PLANES]; 144 u32 bytesperline[VIDEO_MAX_PLANES]; 145 u32 mbi_size; 146 u32 dcp_size; 147 u32 stride; 148 }; 149 150 struct vpu_dec_pic_info { 151 u32 id; 152 u32 luma; 153 u32 start; 154 u32 end; 155 u32 pic_size; 156 u32 stride; 157 u32 skipped; 158 s64 timestamp; 159 u32 consumed_count; 160 }; 161 162 struct vpu_fs_info { 163 u32 id; 164 u32 type; 165 u32 tag; 166 u32 luma_addr; 167 u32 luma_size; 168 u32 chroma_addr; 169 u32 chromau_size; 170 u32 chromav_addr; 171 u32 chromav_size; 172 u32 bytesperline; 173 u32 not_displayed; 174 }; 175 176 struct vpu_ts_info { 177 s64 timestamp; 178 u32 size; 179 }; 180 181 #define BITRATE_STEP (1024) 182 #define BITRATE_MIN (16 * BITRATE_STEP) 183 #define BITRATE_MAX (240 * 1024 * BITRATE_STEP) 184 #define BITRATE_DEFAULT (2 * 1024 * BITRATE_STEP) 185 #define BITRATE_DEFAULT_PEAK (BITRATE_DEFAULT * 2) 186 187 #endif 188