1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright 2020-2021 NXP 4 */ 5 6 #include <linux/init.h> 7 #include <linux/interconnect.h> 8 #include <linux/ioctl.h> 9 #include <linux/list.h> 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/vmalloc.h> 13 #include <linux/videodev2.h> 14 #include <media/v4l2-device.h> 15 #include <media/v4l2-event.h> 16 #include <media/v4l2-mem2mem.h> 17 #include <media/v4l2-ioctl.h> 18 #include <media/videobuf2-v4l2.h> 19 #include <media/videobuf2-dma-contig.h> 20 #include <media/videobuf2-vmalloc.h> 21 #include "vpu.h" 22 #include "vpu_defs.h" 23 #include "vpu_core.h" 24 #include "vpu_helpers.h" 25 #include "vpu_v4l2.h" 26 #include "vpu_cmds.h" 27 #include "vpu_rpc.h" 28 29 #define VDEC_SLOT_CNT_DFT 32 30 #define VDEC_MIN_BUFFER_CAP 8 31 #define VDEC_MIN_BUFFER_OUT 8 32 33 struct vdec_fs_info { 34 char name[8]; 35 u32 type; 36 u32 max_count; 37 u32 req_count; 38 u32 count; 39 u32 index; 40 u32 size; 41 struct vpu_buffer buffer[32]; 42 u32 tag; 43 }; 44 45 struct vdec_frame_store_t { 46 struct vpu_vb2_buffer *curr; 47 struct vpu_vb2_buffer *pend; 48 dma_addr_t addr; 49 unsigned int state; 50 u32 tag; 51 }; 52 53 struct vdec_t { 54 u32 seq_hdr_found; 55 struct vpu_buffer udata; 56 struct vpu_decode_params params; 57 struct vpu_dec_codec_info codec_info; 58 enum vpu_codec_state state; 59 60 struct vdec_frame_store_t *slots; 61 u32 slot_count; 62 u32 req_frame_count; 63 struct vdec_fs_info mbi; 64 struct vdec_fs_info dcp; 65 u32 seq_tag; 66 67 bool reset_codec; 68 bool fixed_fmt; 69 u32 decoded_frame_count; 70 u32 display_frame_count; 71 u32 sequence; 72 u32 eos_received; 73 bool is_source_changed; 74 u32 source_change; 75 u32 drain; 76 bool aborting; 77 }; 78 79 static const struct vpu_format vdec_formats[] = { 80 { 81 .pixfmt = V4L2_PIX_FMT_NV12M_8L128, 82 .mem_planes = 2, 83 .comp_planes = 2, 84 .type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE, 85 .sibling = V4L2_PIX_FMT_NV12_8L128, 86 }, 87 { 88 .pixfmt = V4L2_PIX_FMT_NV12_8L128, 89 .mem_planes = 1, 90 .comp_planes = 2, 91 .type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE, 92 .sibling = V4L2_PIX_FMT_NV12M_8L128, 93 }, 94 { 95 .pixfmt = V4L2_PIX_FMT_NV12M_10BE_8L128, 96 .mem_planes = 2, 97 .comp_planes = 2, 98 .type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE, 99 .sibling = V4L2_PIX_FMT_NV12_10BE_8L128, 100 }, 101 { 102 .pixfmt = V4L2_PIX_FMT_NV12_10BE_8L128, 103 .mem_planes = 1, 104 .comp_planes = 2, 105 .type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE, 106 .sibling = V4L2_PIX_FMT_NV12M_10BE_8L128 107 }, 108 { 109 .pixfmt = V4L2_PIX_FMT_H264, 110 .mem_planes = 1, 111 .comp_planes = 1, 112 .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, 113 .flags = V4L2_FMT_FLAG_DYN_RESOLUTION | V4L2_FMT_FLAG_COMPRESSED 114 }, 115 { 116 .pixfmt = V4L2_PIX_FMT_H264_MVC, 117 .mem_planes = 1, 118 .comp_planes = 1, 119 .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, 120 .flags = V4L2_FMT_FLAG_DYN_RESOLUTION | V4L2_FMT_FLAG_COMPRESSED 121 }, 122 { 123 .pixfmt = V4L2_PIX_FMT_HEVC, 124 .mem_planes = 1, 125 .comp_planes = 1, 126 .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, 127 .flags = V4L2_FMT_FLAG_DYN_RESOLUTION | V4L2_FMT_FLAG_COMPRESSED 128 }, 129 { 130 .pixfmt = V4L2_PIX_FMT_VC1_ANNEX_G, 131 .mem_planes = 1, 132 .comp_planes = 1, 133 .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, 134 .flags = V4L2_FMT_FLAG_DYN_RESOLUTION | V4L2_FMT_FLAG_COMPRESSED 135 }, 136 { 137 .pixfmt = V4L2_PIX_FMT_VC1_ANNEX_L, 138 .mem_planes = 1, 139 .comp_planes = 1, 140 .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, 141 .flags = V4L2_FMT_FLAG_COMPRESSED 142 }, 143 { 144 .pixfmt = V4L2_PIX_FMT_MPEG2, 145 .mem_planes = 1, 146 .comp_planes = 1, 147 .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, 148 .flags = V4L2_FMT_FLAG_DYN_RESOLUTION | V4L2_FMT_FLAG_COMPRESSED 149 }, 150 { 151 .pixfmt = V4L2_PIX_FMT_MPEG4, 152 .mem_planes = 1, 153 .comp_planes = 1, 154 .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, 155 .flags = V4L2_FMT_FLAG_DYN_RESOLUTION | V4L2_FMT_FLAG_COMPRESSED 156 }, 157 { 158 .pixfmt = V4L2_PIX_FMT_XVID, 159 .mem_planes = 1, 160 .comp_planes = 1, 161 .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, 162 .flags = V4L2_FMT_FLAG_DYN_RESOLUTION | V4L2_FMT_FLAG_COMPRESSED 163 }, 164 { 165 .pixfmt = V4L2_PIX_FMT_VP8, 166 .mem_planes = 1, 167 .comp_planes = 1, 168 .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, 169 .flags = V4L2_FMT_FLAG_DYN_RESOLUTION | V4L2_FMT_FLAG_COMPRESSED 170 }, 171 { 172 .pixfmt = V4L2_PIX_FMT_H263, 173 .mem_planes = 1, 174 .comp_planes = 1, 175 .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, 176 .flags = V4L2_FMT_FLAG_DYN_RESOLUTION | V4L2_FMT_FLAG_COMPRESSED 177 }, 178 { 179 .pixfmt = V4L2_PIX_FMT_SPK, 180 .mem_planes = 1, 181 .comp_planes = 1, 182 .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, 183 .flags = V4L2_FMT_FLAG_DYN_RESOLUTION | V4L2_FMT_FLAG_COMPRESSED 184 }, 185 { 186 .pixfmt = V4L2_PIX_FMT_RV30, 187 .mem_planes = 1, 188 .comp_planes = 1, 189 .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, 190 .flags = V4L2_FMT_FLAG_DYN_RESOLUTION | V4L2_FMT_FLAG_COMPRESSED 191 }, 192 { 193 .pixfmt = V4L2_PIX_FMT_RV40, 194 .mem_planes = 1, 195 .comp_planes = 1, 196 .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, 197 .flags = V4L2_FMT_FLAG_DYN_RESOLUTION | V4L2_FMT_FLAG_COMPRESSED 198 }, 199 {0, 0, 0, 0}, 200 }; 201 202 static int vdec_op_s_ctrl(struct v4l2_ctrl *ctrl) 203 { 204 struct vpu_inst *inst = ctrl_to_inst(ctrl); 205 struct vdec_t *vdec = inst->priv; 206 int ret = 0; 207 208 switch (ctrl->id) { 209 case V4L2_CID_MPEG_VIDEO_DEC_DISPLAY_DELAY_ENABLE: 210 vdec->params.display_delay_enable = ctrl->val; 211 break; 212 case V4L2_CID_MPEG_VIDEO_DEC_DISPLAY_DELAY: 213 vdec->params.display_delay = ctrl->val; 214 break; 215 default: 216 ret = -EINVAL; 217 break; 218 } 219 220 return ret; 221 } 222 223 static const struct v4l2_ctrl_ops vdec_ctrl_ops = { 224 .s_ctrl = vdec_op_s_ctrl, 225 .g_volatile_ctrl = vpu_helper_g_volatile_ctrl, 226 }; 227 228 static int vdec_ctrl_init(struct vpu_inst *inst) 229 { 230 struct v4l2_ctrl *ctrl; 231 int ret; 232 233 ret = v4l2_ctrl_handler_init(&inst->ctrl_handler, 20); 234 if (ret) 235 return ret; 236 237 v4l2_ctrl_new_std(&inst->ctrl_handler, &vdec_ctrl_ops, 238 V4L2_CID_MPEG_VIDEO_DEC_DISPLAY_DELAY, 239 0, 0, 1, 0); 240 241 v4l2_ctrl_new_std(&inst->ctrl_handler, &vdec_ctrl_ops, 242 V4L2_CID_MPEG_VIDEO_DEC_DISPLAY_DELAY_ENABLE, 243 0, 1, 1, 0); 244 245 v4l2_ctrl_new_std_menu(&inst->ctrl_handler, NULL, 246 V4L2_CID_MPEG_VIDEO_H264_PROFILE, 247 V4L2_MPEG_VIDEO_H264_PROFILE_MULTIVIEW_HIGH, 248 ~((1 << V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) | 249 (1 << V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) | 250 (1 << V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) | 251 (1 << V4L2_MPEG_VIDEO_H264_PROFILE_EXTENDED) | 252 (1 << V4L2_MPEG_VIDEO_H264_PROFILE_HIGH)), 253 V4L2_MPEG_VIDEO_H264_PROFILE_MAIN); 254 255 v4l2_ctrl_new_std_menu(&inst->ctrl_handler, NULL, 256 V4L2_CID_MPEG_VIDEO_H264_LEVEL, 257 V4L2_MPEG_VIDEO_H264_LEVEL_6_2, 258 0, 259 V4L2_MPEG_VIDEO_H264_LEVEL_4_0); 260 261 v4l2_ctrl_new_std_menu(&inst->ctrl_handler, NULL, 262 V4L2_CID_MPEG_VIDEO_HEVC_PROFILE, 263 V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10, 264 ~((1 << V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN) | 265 (1 << V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10)), 266 V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN); 267 268 v4l2_ctrl_new_std_menu(&inst->ctrl_handler, NULL, 269 V4L2_CID_MPEG_VIDEO_HEVC_LEVEL, 270 V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2, 271 0, 272 V4L2_MPEG_VIDEO_HEVC_LEVEL_4); 273 274 ctrl = v4l2_ctrl_new_std(&inst->ctrl_handler, &vdec_ctrl_ops, 275 V4L2_CID_MIN_BUFFERS_FOR_CAPTURE, 1, 32, 1, 2); 276 if (ctrl) 277 ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE; 278 279 ctrl = v4l2_ctrl_new_std(&inst->ctrl_handler, &vdec_ctrl_ops, 280 V4L2_CID_MIN_BUFFERS_FOR_OUTPUT, 1, 32, 1, 2); 281 if (ctrl) 282 ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE; 283 284 if (inst->ctrl_handler.error) { 285 ret = inst->ctrl_handler.error; 286 v4l2_ctrl_handler_free(&inst->ctrl_handler); 287 return ret; 288 } 289 290 ret = v4l2_ctrl_handler_setup(&inst->ctrl_handler); 291 if (ret) { 292 dev_err(inst->dev, "[%d] setup ctrls fail, ret = %d\n", inst->id, ret); 293 v4l2_ctrl_handler_free(&inst->ctrl_handler); 294 return ret; 295 } 296 297 return 0; 298 } 299 300 static void vdec_attach_frame_store(struct vpu_inst *inst, struct vb2_buffer *vb) 301 { 302 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 303 struct vpu_vb2_buffer *vpu_buf = to_vpu_vb2_buffer(vbuf); 304 struct vdec_t *vdec = inst->priv; 305 struct vdec_frame_store_t *new_slots = NULL; 306 dma_addr_t addr; 307 int i; 308 309 addr = vpu_get_vb_phy_addr(vb, 0); 310 for (i = 0; i < vdec->slot_count; i++) { 311 if (addr == vdec->slots[i].addr) { 312 if (vdec->slots[i].curr && vdec->slots[i].curr != vpu_buf) { 313 vpu_set_buffer_state(vbuf, VPU_BUF_STATE_CHANGED); 314 vdec->slots[i].pend = vpu_buf; 315 } else { 316 vpu_set_buffer_state(vbuf, vdec->slots[i].state); 317 } 318 vpu_buf->fs_id = i; 319 return; 320 } 321 } 322 323 for (i = 0; i < vdec->slot_count; i++) { 324 if (!vdec->slots[i].addr) { 325 vdec->slots[i].addr = addr; 326 vpu_buf->fs_id = i; 327 return; 328 } 329 } 330 331 new_slots = krealloc_array(vdec->slots, vdec->slot_count * 2, 332 sizeof(*vdec->slots), 333 GFP_KERNEL | __GFP_ZERO); 334 if (!new_slots) { 335 vpu_set_buffer_state(vbuf, VPU_BUF_STATE_ERROR); 336 return; 337 } 338 339 vdec->slots = new_slots; 340 vdec->slot_count *= 2; 341 342 vdec->slots[i].addr = addr; 343 vpu_buf->fs_id = i; 344 } 345 346 static void vdec_reset_frame_store(struct vpu_inst *inst) 347 { 348 struct vdec_t *vdec = inst->priv; 349 350 if (!vdec->slots || !vdec->slot_count) 351 return; 352 353 vpu_trace(inst->dev, "inst[%d] reset slots\n", inst->id); 354 memset(vdec->slots, 0, sizeof(*vdec->slots) * vdec->slot_count); 355 } 356 357 static void vdec_handle_resolution_change(struct vpu_inst *inst) 358 { 359 struct vdec_t *vdec = inst->priv; 360 struct vb2_queue *q; 361 362 if (!inst->fh.m2m_ctx) 363 return; 364 365 if (inst->state != VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE) 366 return; 367 if (!vdec->source_change) 368 return; 369 370 q = v4l2_m2m_get_dst_vq(inst->fh.m2m_ctx); 371 if (!list_empty(&q->done_list)) 372 return; 373 374 vdec->source_change--; 375 vpu_notify_source_change(inst); 376 vpu_set_last_buffer_dequeued(inst, false); 377 } 378 379 static int vdec_update_state(struct vpu_inst *inst, enum vpu_codec_state state, u32 force) 380 { 381 struct vdec_t *vdec = inst->priv; 382 enum vpu_codec_state pre_state = inst->state; 383 384 if (state == VPU_CODEC_STATE_SEEK) { 385 if (inst->state == VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE) 386 vdec->state = inst->state; 387 else 388 vdec->state = VPU_CODEC_STATE_ACTIVE; 389 } 390 if (inst->state != VPU_CODEC_STATE_SEEK || force) 391 inst->state = state; 392 else if (state == VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE) 393 vdec->state = VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE; 394 395 if (inst->state != pre_state) 396 vpu_trace(inst->dev, "[%d] %s -> %s\n", inst->id, 397 vpu_codec_state_name(pre_state), vpu_codec_state_name(inst->state)); 398 399 if (inst->state == VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE) 400 vdec_handle_resolution_change(inst); 401 402 return 0; 403 } 404 405 static void vdec_set_last_buffer_dequeued(struct vpu_inst *inst) 406 { 407 struct vdec_t *vdec = inst->priv; 408 409 if (inst->state == VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE) 410 return; 411 412 if (vdec->eos_received) { 413 if (!vpu_set_last_buffer_dequeued(inst, true)) { 414 vdec->eos_received--; 415 vdec_update_state(inst, VPU_CODEC_STATE_DRAIN, 0); 416 } 417 } 418 } 419 420 static int vdec_querycap(struct file *file, void *fh, struct v4l2_capability *cap) 421 { 422 strscpy(cap->driver, "amphion-vpu", sizeof(cap->driver)); 423 strscpy(cap->card, "amphion vpu decoder", sizeof(cap->card)); 424 strscpy(cap->bus_info, "platform: amphion-vpu", sizeof(cap->bus_info)); 425 426 return 0; 427 } 428 429 static int vdec_enum_fmt(struct file *file, void *fh, struct v4l2_fmtdesc *f) 430 { 431 struct vpu_inst *inst = to_inst(file); 432 struct vdec_t *vdec = inst->priv; 433 const struct vpu_format *fmt; 434 int ret = -EINVAL; 435 436 vpu_inst_lock(inst); 437 if (V4L2_TYPE_IS_CAPTURE(f->type) && vdec->fixed_fmt) { 438 fmt = vpu_get_format(inst, f->type); 439 if (f->index == 1) 440 fmt = vpu_helper_find_sibling(inst, f->type, fmt->pixfmt); 441 if (f->index > 1) 442 fmt = NULL; 443 } else { 444 fmt = vpu_helper_enum_format(inst, f->type, f->index); 445 } 446 if (!fmt) 447 goto exit; 448 449 memset(f->reserved, 0, sizeof(f->reserved)); 450 f->pixelformat = fmt->pixfmt; 451 f->flags = fmt->flags; 452 ret = 0; 453 exit: 454 vpu_inst_unlock(inst); 455 return ret; 456 } 457 458 static int vdec_g_fmt(struct file *file, void *fh, struct v4l2_format *f) 459 { 460 struct vpu_inst *inst = to_inst(file); 461 struct vdec_t *vdec = inst->priv; 462 struct v4l2_pix_format_mplane *pixmp = &f->fmt.pix_mp; 463 struct vpu_format *cur_fmt; 464 int i; 465 466 vpu_inst_lock(inst); 467 cur_fmt = vpu_get_format(inst, f->type); 468 469 pixmp->pixelformat = cur_fmt->pixfmt; 470 pixmp->num_planes = cur_fmt->mem_planes; 471 pixmp->width = cur_fmt->width; 472 pixmp->height = cur_fmt->height; 473 pixmp->field = cur_fmt->field; 474 pixmp->flags = cur_fmt->flags; 475 for (i = 0; i < pixmp->num_planes; i++) { 476 pixmp->plane_fmt[i].bytesperline = cur_fmt->bytesperline[i]; 477 pixmp->plane_fmt[i].sizeimage = vpu_get_fmt_plane_size(cur_fmt, i); 478 } 479 480 f->fmt.pix_mp.colorspace = vdec->codec_info.color_primaries; 481 f->fmt.pix_mp.xfer_func = vdec->codec_info.transfer_chars; 482 f->fmt.pix_mp.ycbcr_enc = vdec->codec_info.matrix_coeffs; 483 f->fmt.pix_mp.quantization = vdec->codec_info.full_range; 484 vpu_inst_unlock(inst); 485 486 return 0; 487 } 488 489 static int vdec_try_fmt(struct file *file, void *fh, struct v4l2_format *f) 490 { 491 struct vpu_inst *inst = to_inst(file); 492 struct vdec_t *vdec = inst->priv; 493 struct vpu_format fmt; 494 495 vpu_inst_lock(inst); 496 if (V4L2_TYPE_IS_CAPTURE(f->type) && vdec->fixed_fmt) { 497 struct vpu_format *cap_fmt = vpu_get_format(inst, f->type); 498 499 if (!vpu_helper_match_format(inst, cap_fmt->type, cap_fmt->pixfmt, 500 f->fmt.pix_mp.pixelformat)) 501 f->fmt.pix_mp.pixelformat = cap_fmt->pixfmt; 502 } 503 504 vpu_try_fmt_common(inst, f, &fmt); 505 506 if (vdec->fixed_fmt) { 507 f->fmt.pix_mp.colorspace = vdec->codec_info.color_primaries; 508 f->fmt.pix_mp.xfer_func = vdec->codec_info.transfer_chars; 509 f->fmt.pix_mp.ycbcr_enc = vdec->codec_info.matrix_coeffs; 510 f->fmt.pix_mp.quantization = vdec->codec_info.full_range; 511 } else { 512 f->fmt.pix_mp.colorspace = V4L2_COLORSPACE_DEFAULT; 513 f->fmt.pix_mp.xfer_func = V4L2_XFER_FUNC_DEFAULT; 514 f->fmt.pix_mp.ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; 515 f->fmt.pix_mp.quantization = V4L2_QUANTIZATION_DEFAULT; 516 } 517 vpu_inst_unlock(inst); 518 519 return 0; 520 } 521 522 static int vdec_s_fmt_common(struct vpu_inst *inst, struct v4l2_format *f) 523 { 524 struct v4l2_pix_format_mplane *pixmp = &f->fmt.pix_mp; 525 struct vpu_format fmt; 526 struct vpu_format *cur_fmt; 527 struct vb2_queue *q; 528 struct vdec_t *vdec = inst->priv; 529 int i; 530 531 if (!inst->fh.m2m_ctx) 532 return -EINVAL; 533 534 q = v4l2_m2m_get_vq(inst->fh.m2m_ctx, f->type); 535 if (!q) 536 return -EINVAL; 537 if (vb2_is_busy(q)) 538 return -EBUSY; 539 540 if (vpu_try_fmt_common(inst, f, &fmt)) 541 return -EINVAL; 542 543 cur_fmt = vpu_get_format(inst, f->type); 544 if (V4L2_TYPE_IS_OUTPUT(f->type) && inst->state != VPU_CODEC_STATE_DEINIT) { 545 if (cur_fmt->pixfmt != fmt.pixfmt) { 546 vdec->reset_codec = true; 547 vdec->fixed_fmt = false; 548 } 549 } 550 if (V4L2_TYPE_IS_OUTPUT(f->type) || !vdec->fixed_fmt) { 551 memcpy(cur_fmt, &fmt, sizeof(*cur_fmt)); 552 } else { 553 if (vpu_helper_match_format(inst, f->type, cur_fmt->pixfmt, pixmp->pixelformat)) { 554 cur_fmt->pixfmt = fmt.pixfmt; 555 cur_fmt->mem_planes = fmt.mem_planes; 556 } 557 pixmp->pixelformat = cur_fmt->pixfmt; 558 pixmp->num_planes = cur_fmt->mem_planes; 559 pixmp->width = cur_fmt->width; 560 pixmp->height = cur_fmt->height; 561 for (i = 0; i < pixmp->num_planes; i++) { 562 pixmp->plane_fmt[i].bytesperline = cur_fmt->bytesperline[i]; 563 pixmp->plane_fmt[i].sizeimage = vpu_get_fmt_plane_size(cur_fmt, i); 564 } 565 pixmp->field = cur_fmt->field; 566 } 567 568 if (!vdec->fixed_fmt) { 569 if (V4L2_TYPE_IS_OUTPUT(f->type)) { 570 vdec->params.codec_format = cur_fmt->pixfmt; 571 vdec->codec_info.color_primaries = f->fmt.pix_mp.colorspace; 572 vdec->codec_info.transfer_chars = f->fmt.pix_mp.xfer_func; 573 vdec->codec_info.matrix_coeffs = f->fmt.pix_mp.ycbcr_enc; 574 vdec->codec_info.full_range = f->fmt.pix_mp.quantization; 575 } else { 576 vdec->params.output_format = cur_fmt->pixfmt; 577 inst->crop.left = 0; 578 inst->crop.top = 0; 579 inst->crop.width = cur_fmt->width; 580 inst->crop.height = cur_fmt->height; 581 } 582 } 583 584 vpu_trace(inst->dev, "[%d] %c%c%c%c %dx%d\n", inst->id, 585 f->fmt.pix_mp.pixelformat, 586 f->fmt.pix_mp.pixelformat >> 8, 587 f->fmt.pix_mp.pixelformat >> 16, 588 f->fmt.pix_mp.pixelformat >> 24, 589 f->fmt.pix_mp.width, 590 f->fmt.pix_mp.height); 591 592 return 0; 593 } 594 595 static int vdec_s_fmt(struct file *file, void *fh, struct v4l2_format *f) 596 { 597 struct vpu_inst *inst = to_inst(file); 598 struct v4l2_pix_format_mplane *pixmp = &f->fmt.pix_mp; 599 struct vdec_t *vdec = inst->priv; 600 int ret = 0; 601 602 vpu_inst_lock(inst); 603 ret = vdec_s_fmt_common(inst, f); 604 if (ret) 605 goto exit; 606 607 if (V4L2_TYPE_IS_OUTPUT(f->type) && !vdec->fixed_fmt) { 608 struct v4l2_format fc; 609 610 memset(&fc, 0, sizeof(fc)); 611 fc.type = inst->cap_format.type; 612 fc.fmt.pix_mp.pixelformat = inst->cap_format.pixfmt; 613 fc.fmt.pix_mp.width = pixmp->width; 614 fc.fmt.pix_mp.height = pixmp->height; 615 vdec_s_fmt_common(inst, &fc); 616 } 617 618 f->fmt.pix_mp.colorspace = vdec->codec_info.color_primaries; 619 f->fmt.pix_mp.xfer_func = vdec->codec_info.transfer_chars; 620 f->fmt.pix_mp.ycbcr_enc = vdec->codec_info.matrix_coeffs; 621 f->fmt.pix_mp.quantization = vdec->codec_info.full_range; 622 623 exit: 624 vpu_inst_unlock(inst); 625 return ret; 626 } 627 628 static int vdec_g_selection(struct file *file, void *fh, struct v4l2_selection *s) 629 { 630 struct vpu_inst *inst = to_inst(file); 631 632 if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE && s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) 633 return -EINVAL; 634 635 switch (s->target) { 636 case V4L2_SEL_TGT_COMPOSE: 637 case V4L2_SEL_TGT_COMPOSE_DEFAULT: 638 case V4L2_SEL_TGT_COMPOSE_PADDED: 639 s->r = inst->crop; 640 break; 641 case V4L2_SEL_TGT_COMPOSE_BOUNDS: 642 s->r.left = 0; 643 s->r.top = 0; 644 s->r.width = inst->cap_format.width; 645 s->r.height = inst->cap_format.height; 646 break; 647 default: 648 return -EINVAL; 649 } 650 651 return 0; 652 } 653 654 static int vdec_drain(struct vpu_inst *inst) 655 { 656 struct vdec_t *vdec = inst->priv; 657 658 if (!inst->fh.m2m_ctx) 659 return 0; 660 661 if (!vdec->drain) 662 return 0; 663 664 if (!vpu_is_source_empty(inst)) 665 return 0; 666 667 if (!vdec->params.frame_count) { 668 vpu_set_last_buffer_dequeued(inst, true); 669 return 0; 670 } 671 672 vpu_iface_add_scode(inst, SCODE_PADDING_EOS); 673 vdec->params.end_flag = 1; 674 vpu_iface_set_decode_params(inst, &vdec->params, 1); 675 vdec->drain = 0; 676 vpu_trace(inst->dev, "[%d] frame_count = %d\n", inst->id, vdec->params.frame_count); 677 678 return 0; 679 } 680 681 static int vdec_cmd_start(struct vpu_inst *inst) 682 { 683 struct vdec_t *vdec = inst->priv; 684 685 switch (inst->state) { 686 case VPU_CODEC_STATE_STARTED: 687 case VPU_CODEC_STATE_DRAIN: 688 case VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE: 689 vdec_update_state(inst, VPU_CODEC_STATE_ACTIVE, 0); 690 break; 691 default: 692 break; 693 } 694 vpu_process_capture_buffer(inst); 695 if (vdec->eos_received) 696 vdec_set_last_buffer_dequeued(inst); 697 return 0; 698 } 699 700 static int vdec_cmd_stop(struct vpu_inst *inst) 701 { 702 struct vdec_t *vdec = inst->priv; 703 704 vpu_trace(inst->dev, "[%d]\n", inst->id); 705 706 if (inst->state == VPU_CODEC_STATE_DEINIT) { 707 vpu_set_last_buffer_dequeued(inst, true); 708 } else { 709 vdec->drain = 1; 710 vdec_drain(inst); 711 } 712 713 return 0; 714 } 715 716 static int vdec_decoder_cmd(struct file *file, void *fh, struct v4l2_decoder_cmd *cmd) 717 { 718 struct vpu_inst *inst = to_inst(file); 719 int ret; 720 721 ret = v4l2_m2m_ioctl_try_decoder_cmd(file, fh, cmd); 722 if (ret) 723 return ret; 724 725 vpu_inst_lock(inst); 726 switch (cmd->cmd) { 727 case V4L2_DEC_CMD_START: 728 vdec_cmd_start(inst); 729 break; 730 case V4L2_DEC_CMD_STOP: 731 vdec_cmd_stop(inst); 732 break; 733 default: 734 break; 735 } 736 vpu_inst_unlock(inst); 737 738 return 0; 739 } 740 741 static int vdec_subscribe_event(struct v4l2_fh *fh, const struct v4l2_event_subscription *sub) 742 { 743 switch (sub->type) { 744 case V4L2_EVENT_EOS: 745 return v4l2_event_subscribe(fh, sub, 0, NULL); 746 case V4L2_EVENT_SOURCE_CHANGE: 747 return v4l2_src_change_event_subscribe(fh, sub); 748 case V4L2_EVENT_CTRL: 749 return v4l2_ctrl_subscribe_event(fh, sub); 750 default: 751 return -EINVAL; 752 } 753 754 return 0; 755 } 756 757 static const struct v4l2_ioctl_ops vdec_ioctl_ops = { 758 .vidioc_querycap = vdec_querycap, 759 .vidioc_enum_fmt_vid_cap = vdec_enum_fmt, 760 .vidioc_enum_fmt_vid_out = vdec_enum_fmt, 761 .vidioc_g_fmt_vid_cap_mplane = vdec_g_fmt, 762 .vidioc_g_fmt_vid_out_mplane = vdec_g_fmt, 763 .vidioc_try_fmt_vid_cap_mplane = vdec_try_fmt, 764 .vidioc_try_fmt_vid_out_mplane = vdec_try_fmt, 765 .vidioc_s_fmt_vid_cap_mplane = vdec_s_fmt, 766 .vidioc_s_fmt_vid_out_mplane = vdec_s_fmt, 767 .vidioc_g_selection = vdec_g_selection, 768 .vidioc_try_decoder_cmd = v4l2_m2m_ioctl_try_decoder_cmd, 769 .vidioc_decoder_cmd = vdec_decoder_cmd, 770 .vidioc_subscribe_event = vdec_subscribe_event, 771 .vidioc_unsubscribe_event = v4l2_event_unsubscribe, 772 .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs, 773 .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs, 774 .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf, 775 .vidioc_querybuf = v4l2_m2m_ioctl_querybuf, 776 .vidioc_qbuf = v4l2_m2m_ioctl_qbuf, 777 .vidioc_expbuf = v4l2_m2m_ioctl_expbuf, 778 .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf, 779 .vidioc_streamon = v4l2_m2m_ioctl_streamon, 780 .vidioc_streamoff = v4l2_m2m_ioctl_streamoff, 781 }; 782 783 static bool vdec_check_ready(struct vpu_inst *inst, unsigned int type) 784 { 785 struct vdec_t *vdec = inst->priv; 786 787 if (V4L2_TYPE_IS_OUTPUT(type)) 788 return true; 789 790 if (vdec->req_frame_count) 791 return true; 792 793 return false; 794 } 795 796 static struct vb2_v4l2_buffer *vdec_get_src_buffer(struct vpu_inst *inst, u32 count) 797 { 798 if (count > 1) 799 vpu_skip_frame(inst, count - 1); 800 801 return vpu_next_src_buf(inst); 802 } 803 804 static int vdec_frame_decoded(struct vpu_inst *inst, void *arg) 805 { 806 struct vdec_t *vdec = inst->priv; 807 struct vpu_dec_pic_info *info = arg; 808 struct vpu_vb2_buffer *vpu_buf; 809 struct vb2_v4l2_buffer *vbuf; 810 struct vb2_v4l2_buffer *src_buf; 811 int ret = 0; 812 813 if (!info || info->id >= vdec->slot_count) 814 return -EINVAL; 815 816 vpu_inst_lock(inst); 817 vpu_buf = vdec->slots[info->id].curr; 818 if (!vpu_buf) { 819 dev_err(inst->dev, "[%d] decoded invalid frame[%d]\n", inst->id, info->id); 820 ret = -EINVAL; 821 goto exit; 822 } 823 vbuf = &vpu_buf->m2m_buf.vb; 824 src_buf = vdec_get_src_buffer(inst, info->consumed_count); 825 if (src_buf) { 826 v4l2_m2m_buf_copy_metadata(src_buf, vbuf, true); 827 if (info->consumed_count) { 828 v4l2_m2m_src_buf_remove(inst->fh.m2m_ctx); 829 vpu_set_buffer_state(src_buf, VPU_BUF_STATE_IDLE); 830 v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE); 831 } else { 832 vpu_set_buffer_state(src_buf, VPU_BUF_STATE_DECODED); 833 } 834 } 835 if (vpu_get_buffer_state(vbuf) == VPU_BUF_STATE_DECODED) 836 dev_info(inst->dev, "[%d] buf[%d] has been decoded\n", inst->id, info->id); 837 vpu_set_buffer_state(vbuf, VPU_BUF_STATE_DECODED); 838 vdec->slots[info->id].state = VPU_BUF_STATE_DECODED; 839 vdec->decoded_frame_count++; 840 if (vdec->params.display_delay_enable) { 841 struct vpu_format *cur_fmt; 842 843 cur_fmt = vpu_get_format(inst, inst->cap_format.type); 844 vdec->slots[info->id].state = VPU_BUF_STATE_READY; 845 vpu_set_buffer_state(vbuf, VPU_BUF_STATE_READY); 846 for (int i = 0; i < vbuf->vb2_buf.num_planes; i++) 847 vb2_set_plane_payload(&vbuf->vb2_buf, 848 i, vpu_get_fmt_plane_size(cur_fmt, i)); 849 vbuf->field = cur_fmt->field; 850 vbuf->sequence = vdec->sequence++; 851 dev_dbg(inst->dev, "[%d][OUTPUT TS]%32lld\n", inst->id, vbuf->vb2_buf.timestamp); 852 853 v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_DONE); 854 vdec->display_frame_count++; 855 } 856 exit: 857 vpu_inst_unlock(inst); 858 859 return ret; 860 } 861 862 static struct vpu_vb2_buffer *vdec_find_buffer(struct vpu_inst *inst, u32 luma) 863 { 864 struct vdec_t *vdec = inst->priv; 865 int i; 866 867 for (i = 0; i < vdec->slot_count; i++) { 868 if (!vdec->slots[i].curr) 869 continue; 870 if (luma == vdec->slots[i].addr) 871 return vdec->slots[i].curr; 872 } 873 874 return NULL; 875 } 876 877 static void vdec_buf_done(struct vpu_inst *inst, struct vpu_frame_info *frame) 878 { 879 struct vdec_t *vdec = inst->priv; 880 struct vpu_format *cur_fmt; 881 struct vpu_vb2_buffer *vpu_buf; 882 struct vb2_v4l2_buffer *vbuf; 883 int i; 884 885 if (!frame) 886 return; 887 888 vpu_inst_lock(inst); 889 if (!vdec->params.display_delay_enable) 890 vdec->sequence++; 891 vpu_buf = vdec_find_buffer(inst, frame->luma); 892 vpu_inst_unlock(inst); 893 if (!vpu_buf) { 894 dev_err(inst->dev, "[%d] can't find buffer, id = %d, addr = 0x%x\n", 895 inst->id, frame->id, frame->luma); 896 return; 897 } 898 if (frame->skipped) { 899 dev_dbg(inst->dev, "[%d] frame skip\n", inst->id); 900 return; 901 } 902 903 cur_fmt = vpu_get_format(inst, inst->cap_format.type); 904 vbuf = &vpu_buf->m2m_buf.vb; 905 if (vpu_buf->fs_id != frame->id) 906 dev_err(inst->dev, "[%d] buffer id(%d(%d), %d) mismatch\n", 907 inst->id, vpu_buf->fs_id, vbuf->vb2_buf.index, frame->id); 908 909 if (vdec->params.display_delay_enable) 910 return; 911 912 if (vpu_get_buffer_state(vbuf) != VPU_BUF_STATE_DECODED) 913 dev_err(inst->dev, "[%d] buffer(%d) ready without decoded\n", inst->id, frame->id); 914 915 vpu_set_buffer_state(vbuf, VPU_BUF_STATE_READY); 916 for (i = 0; i < vbuf->vb2_buf.num_planes; i++) 917 vb2_set_plane_payload(&vbuf->vb2_buf, i, vpu_get_fmt_plane_size(cur_fmt, i)); 918 vbuf->field = cur_fmt->field; 919 vbuf->sequence = vdec->sequence; 920 dev_dbg(inst->dev, "[%d][OUTPUT TS]%32lld\n", inst->id, vbuf->vb2_buf.timestamp); 921 922 vpu_inst_lock(inst); 923 vdec->slots[vpu_buf->fs_id].state = VPU_BUF_STATE_READY; 924 vdec->display_frame_count++; 925 vpu_inst_unlock(inst); 926 v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_DONE); 927 dev_dbg(inst->dev, "[%d] decoded : %d, display : %d, sequence : %d\n", 928 inst->id, vdec->decoded_frame_count, vdec->display_frame_count, vdec->sequence); 929 } 930 931 static void vdec_stop_done(struct vpu_inst *inst) 932 { 933 struct vdec_t *vdec = inst->priv; 934 935 vpu_inst_lock(inst); 936 vdec_update_state(inst, VPU_CODEC_STATE_DEINIT, 0); 937 vdec->seq_hdr_found = 0; 938 vdec->req_frame_count = 0; 939 vdec->reset_codec = false; 940 vdec->fixed_fmt = false; 941 vdec->params.end_flag = 0; 942 vdec->drain = 0; 943 vdec->params.frame_count = 0; 944 vdec->decoded_frame_count = 0; 945 vdec->display_frame_count = 0; 946 vdec->sequence = 0; 947 vdec->eos_received = 0; 948 vdec->is_source_changed = false; 949 vdec->source_change = 0; 950 inst->total_input_count = 0; 951 vpu_inst_unlock(inst); 952 } 953 954 static bool vdec_check_source_change(struct vpu_inst *inst) 955 { 956 struct vdec_t *vdec = inst->priv; 957 const struct vpu_format *sibling; 958 959 if (!inst->fh.m2m_ctx) 960 return false; 961 962 if (vdec->reset_codec) 963 return false; 964 965 sibling = vpu_helper_find_sibling(inst, inst->cap_format.type, inst->cap_format.pixfmt); 966 if (sibling && vdec->codec_info.pixfmt == sibling->pixfmt) 967 vdec->codec_info.pixfmt = inst->cap_format.pixfmt; 968 969 if (!vb2_is_streaming(v4l2_m2m_get_dst_vq(inst->fh.m2m_ctx))) 970 return true; 971 if (inst->cap_format.pixfmt != vdec->codec_info.pixfmt) 972 return true; 973 if (inst->cap_format.width != vdec->codec_info.decoded_width) 974 return true; 975 if (inst->cap_format.height != vdec->codec_info.decoded_height) 976 return true; 977 if (vpu_get_num_buffers(inst, inst->cap_format.type) < inst->min_buffer_cap) 978 return true; 979 if (inst->crop.left != vdec->codec_info.offset_x) 980 return true; 981 if (inst->crop.top != vdec->codec_info.offset_y) 982 return true; 983 if (inst->crop.width != vdec->codec_info.width) 984 return true; 985 if (inst->crop.height != vdec->codec_info.height) 986 return true; 987 988 return false; 989 } 990 991 static void vdec_init_fmt(struct vpu_inst *inst) 992 { 993 struct vdec_t *vdec = inst->priv; 994 struct v4l2_format f; 995 996 memset(&f, 0, sizeof(f)); 997 f.type = inst->cap_format.type; 998 f.fmt.pix_mp.pixelformat = vdec->codec_info.pixfmt; 999 f.fmt.pix_mp.width = vdec->codec_info.decoded_width; 1000 f.fmt.pix_mp.height = vdec->codec_info.decoded_height; 1001 if (vdec->codec_info.progressive) 1002 f.fmt.pix_mp.field = V4L2_FIELD_NONE; 1003 else 1004 f.fmt.pix_mp.field = V4L2_FIELD_SEQ_TB; 1005 vpu_try_fmt_common(inst, &f, &inst->cap_format); 1006 1007 inst->out_format.width = vdec->codec_info.width; 1008 inst->out_format.height = vdec->codec_info.height; 1009 } 1010 1011 static void vdec_init_crop(struct vpu_inst *inst) 1012 { 1013 struct vdec_t *vdec = inst->priv; 1014 1015 inst->crop.left = vdec->codec_info.offset_x; 1016 inst->crop.top = vdec->codec_info.offset_y; 1017 inst->crop.width = vdec->codec_info.width; 1018 inst->crop.height = vdec->codec_info.height; 1019 } 1020 1021 static void vdec_init_mbi(struct vpu_inst *inst) 1022 { 1023 struct vdec_t *vdec = inst->priv; 1024 1025 vdec->mbi.size = vdec->codec_info.mbi_size; 1026 vdec->mbi.max_count = ARRAY_SIZE(vdec->mbi.buffer); 1027 scnprintf(vdec->mbi.name, sizeof(vdec->mbi.name), "mbi"); 1028 vdec->mbi.type = MEM_RES_MBI; 1029 vdec->mbi.tag = vdec->seq_tag; 1030 } 1031 1032 static void vdec_init_dcp(struct vpu_inst *inst) 1033 { 1034 struct vdec_t *vdec = inst->priv; 1035 1036 vdec->dcp.size = vdec->codec_info.dcp_size; 1037 vdec->dcp.max_count = ARRAY_SIZE(vdec->dcp.buffer); 1038 scnprintf(vdec->dcp.name, sizeof(vdec->dcp.name), "dcp"); 1039 vdec->dcp.type = MEM_RES_DCP; 1040 vdec->dcp.tag = vdec->seq_tag; 1041 } 1042 1043 static void vdec_request_one_fs(struct vdec_fs_info *fs) 1044 { 1045 fs->req_count++; 1046 if (fs->req_count > fs->max_count) 1047 fs->req_count = fs->max_count; 1048 } 1049 1050 static int vdec_alloc_fs_buffer(struct vpu_inst *inst, struct vdec_fs_info *fs) 1051 { 1052 struct vpu_buffer *buffer; 1053 1054 if (!fs->size) 1055 return -EINVAL; 1056 1057 if (fs->count >= fs->req_count) 1058 return -EINVAL; 1059 1060 buffer = &fs->buffer[fs->count]; 1061 if (buffer->virt && buffer->length >= fs->size) 1062 return 0; 1063 1064 vpu_free_dma(buffer); 1065 buffer->length = fs->size; 1066 return vpu_alloc_dma(inst->core, buffer); 1067 } 1068 1069 static void vdec_alloc_fs(struct vpu_inst *inst, struct vdec_fs_info *fs) 1070 { 1071 int ret; 1072 1073 while (fs->count < fs->req_count) { 1074 ret = vdec_alloc_fs_buffer(inst, fs); 1075 if (ret) 1076 break; 1077 fs->count++; 1078 } 1079 } 1080 1081 static void vdec_clear_fs(struct vdec_fs_info *fs) 1082 { 1083 u32 i; 1084 1085 if (!fs) 1086 return; 1087 1088 for (i = 0; i < ARRAY_SIZE(fs->buffer); i++) 1089 vpu_free_dma(&fs->buffer[i]); 1090 memset(fs, 0, sizeof(*fs)); 1091 } 1092 1093 static int vdec_response_fs(struct vpu_inst *inst, struct vdec_fs_info *fs) 1094 { 1095 struct vpu_fs_info info; 1096 int ret; 1097 1098 if (fs->index >= fs->count) 1099 return 0; 1100 1101 memset(&info, 0, sizeof(info)); 1102 info.id = fs->index; 1103 info.type = fs->type; 1104 info.tag = fs->tag; 1105 info.luma_addr = fs->buffer[fs->index].phys; 1106 info.luma_size = fs->buffer[fs->index].length; 1107 ret = vpu_session_alloc_fs(inst, &info); 1108 if (ret) 1109 return ret; 1110 1111 fs->index++; 1112 return 0; 1113 } 1114 1115 static int vdec_response_frame_abnormal(struct vpu_inst *inst) 1116 { 1117 struct vdec_t *vdec = inst->priv; 1118 struct vpu_fs_info info; 1119 int ret; 1120 1121 if (!vdec->req_frame_count) 1122 return 0; 1123 1124 memset(&info, 0, sizeof(info)); 1125 info.type = MEM_RES_FRAME; 1126 info.tag = vdec->seq_tag + 0xf0; 1127 ret = vpu_session_alloc_fs(inst, &info); 1128 if (ret) 1129 return ret; 1130 vdec->req_frame_count--; 1131 1132 return 0; 1133 } 1134 1135 static int vdec_response_frame(struct vpu_inst *inst, struct vb2_v4l2_buffer *vbuf) 1136 { 1137 struct vdec_t *vdec = inst->priv; 1138 struct vpu_vb2_buffer *vpu_buf; 1139 struct vpu_fs_info info; 1140 int ret; 1141 1142 if (inst->state != VPU_CODEC_STATE_ACTIVE) 1143 return -EINVAL; 1144 1145 if (vdec->aborting) 1146 return -EINVAL; 1147 1148 if (!vdec->req_frame_count) 1149 return -EINVAL; 1150 1151 if (!vbuf) 1152 return -EINVAL; 1153 1154 vpu_buf = to_vpu_vb2_buffer(vbuf); 1155 if (vpu_buf->fs_id < 0 || vpu_buf->fs_id >= vdec->slot_count) { 1156 dev_err(inst->dev, "invalid fs %d for v4l2 buffer %d\n", 1157 vpu_buf->fs_id, vbuf->vb2_buf.index); 1158 return -EINVAL; 1159 } 1160 1161 if (vdec->slots[vpu_buf->fs_id].curr) { 1162 if (vdec->slots[vpu_buf->fs_id].curr != vpu_buf) { 1163 vpu_set_buffer_state(vbuf, VPU_BUF_STATE_CHANGED); 1164 vdec->slots[vpu_buf->fs_id].pend = vpu_buf; 1165 } else { 1166 vpu_set_buffer_state(vbuf, vdec->slots[vpu_buf->fs_id].state); 1167 } 1168 dev_err(inst->dev, "[%d] repeat alloc fs %d (v4l2 index %d)\n", 1169 inst->id, vpu_buf->fs_id, vbuf->vb2_buf.index); 1170 return -EAGAIN; 1171 } 1172 1173 dev_dbg(inst->dev, "[%d] state = %s, alloc fs %d, tag = 0x%x\n", 1174 inst->id, vpu_codec_state_name(inst->state), vbuf->vb2_buf.index, vdec->seq_tag); 1175 1176 memset(&info, 0, sizeof(info)); 1177 info.id = vpu_buf->fs_id; 1178 info.type = MEM_RES_FRAME; 1179 info.tag = vdec->seq_tag; 1180 info.luma_addr = vpu_get_vb_phy_addr(&vbuf->vb2_buf, 0); 1181 info.luma_size = inst->cap_format.sizeimage[0]; 1182 if (vbuf->vb2_buf.num_planes > 1) 1183 info.chroma_addr = vpu_get_vb_phy_addr(&vbuf->vb2_buf, 1); 1184 else 1185 info.chroma_addr = info.luma_addr + info.luma_size; 1186 info.chromau_size = inst->cap_format.sizeimage[1]; 1187 info.bytesperline = inst->cap_format.bytesperline[0]; 1188 ret = vpu_session_alloc_fs(inst, &info); 1189 if (ret) 1190 return ret; 1191 1192 vpu_buf->luma = info.luma_addr; 1193 vpu_buf->chroma_u = info.chroma_addr; 1194 vpu_buf->chroma_v = 0; 1195 vpu_set_buffer_state(vbuf, VPU_BUF_STATE_INUSE); 1196 vdec->slots[info.id].tag = info.tag; 1197 vdec->slots[info.id].curr = vpu_buf; 1198 vdec->slots[info.id].state = VPU_BUF_STATE_INUSE; 1199 vdec->req_frame_count--; 1200 1201 return 0; 1202 } 1203 1204 static void vdec_response_fs_request(struct vpu_inst *inst, bool force) 1205 { 1206 struct vdec_t *vdec = inst->priv; 1207 int i; 1208 int ret; 1209 1210 if (force) { 1211 for (i = vdec->req_frame_count; i > 0; i--) 1212 vdec_response_frame_abnormal(inst); 1213 return; 1214 } 1215 1216 for (i = vdec->req_frame_count; i > 0; i--) { 1217 ret = vpu_process_capture_buffer(inst); 1218 if (ret) 1219 break; 1220 if (vdec->eos_received) 1221 break; 1222 } 1223 1224 for (i = vdec->mbi.index; i < vdec->mbi.count; i++) { 1225 if (vdec_response_fs(inst, &vdec->mbi)) 1226 break; 1227 if (vdec->eos_received) 1228 break; 1229 } 1230 for (i = vdec->dcp.index; i < vdec->dcp.count; i++) { 1231 if (vdec_response_fs(inst, &vdec->dcp)) 1232 break; 1233 if (vdec->eos_received) 1234 break; 1235 } 1236 } 1237 1238 static void vdec_response_fs_release(struct vpu_inst *inst, u32 id, u32 tag) 1239 { 1240 struct vpu_fs_info info; 1241 1242 memset(&info, 0, sizeof(info)); 1243 info.id = id; 1244 info.tag = tag; 1245 vpu_session_release_fs(inst, &info); 1246 } 1247 1248 static void vdec_recycle_buffer(struct vpu_inst *inst, struct vb2_v4l2_buffer *vbuf) 1249 { 1250 if (!inst->fh.m2m_ctx) 1251 return; 1252 if (vbuf->vb2_buf.state != VB2_BUF_STATE_ACTIVE) 1253 return; 1254 if (vpu_find_buf_by_idx(inst, vbuf->vb2_buf.type, vbuf->vb2_buf.index)) 1255 return; 1256 v4l2_m2m_buf_queue(inst->fh.m2m_ctx, vbuf); 1257 } 1258 1259 static void vdec_release_curr_frame_store(struct vpu_inst *inst, u32 id) 1260 { 1261 struct vdec_t *vdec = inst->priv; 1262 struct vpu_vb2_buffer *vpu_buf; 1263 struct vb2_v4l2_buffer *vbuf; 1264 1265 if (id >= vdec->slot_count) 1266 return; 1267 if (!vdec->slots[id].curr) 1268 return; 1269 1270 vpu_buf = vdec->slots[id].curr; 1271 vbuf = &vpu_buf->m2m_buf.vb; 1272 1273 vdec_response_fs_release(inst, id, vdec->slots[id].tag); 1274 if (vpu_buf->fs_id == id) { 1275 if (vpu_buf->state != VPU_BUF_STATE_READY) 1276 vdec_recycle_buffer(inst, vbuf); 1277 vpu_set_buffer_state(vbuf, VPU_BUF_STATE_IDLE); 1278 } 1279 1280 vdec->slots[id].curr = NULL; 1281 vdec->slots[id].state = VPU_BUF_STATE_IDLE; 1282 1283 if (vdec->slots[id].pend) { 1284 vpu_set_buffer_state(&vdec->slots[id].pend->m2m_buf.vb, VPU_BUF_STATE_IDLE); 1285 vdec->slots[id].pend = NULL; 1286 } 1287 } 1288 1289 static void vdec_clear_slots(struct vpu_inst *inst) 1290 { 1291 struct vdec_t *vdec = inst->priv; 1292 int i; 1293 1294 for (i = 0; i < vdec->slot_count; i++) { 1295 if (!vdec->slots[i].curr) 1296 continue; 1297 1298 vpu_trace(inst->dev, "clear slot %d\n", i); 1299 vdec_release_curr_frame_store(inst, i); 1300 } 1301 } 1302 1303 static void vdec_update_v4l2_ctrl(struct vpu_inst *inst, u32 id, u32 val) 1304 { 1305 struct v4l2_ctrl *ctrl = v4l2_ctrl_find(&inst->ctrl_handler, id); 1306 1307 if (ctrl) 1308 v4l2_ctrl_s_ctrl(ctrl, val); 1309 } 1310 1311 static void vdec_update_v4l2_profile_level(struct vpu_inst *inst, struct vpu_dec_codec_info *hdr) 1312 { 1313 switch (inst->out_format.pixfmt) { 1314 case V4L2_PIX_FMT_H264: 1315 case V4L2_PIX_FMT_H264_MVC: 1316 vdec_update_v4l2_ctrl(inst, V4L2_CID_MPEG_VIDEO_H264_PROFILE, 1317 vpu_get_h264_v4l2_profile(hdr)); 1318 vdec_update_v4l2_ctrl(inst, V4L2_CID_MPEG_VIDEO_H264_LEVEL, 1319 vpu_get_h264_v4l2_level(hdr)); 1320 break; 1321 case V4L2_PIX_FMT_HEVC: 1322 vdec_update_v4l2_ctrl(inst, V4L2_CID_MPEG_VIDEO_HEVC_PROFILE, 1323 vpu_get_hevc_v4l2_profile(hdr)); 1324 vdec_update_v4l2_ctrl(inst, V4L2_CID_MPEG_VIDEO_HEVC_LEVEL, 1325 vpu_get_hevc_v4l2_level(hdr)); 1326 break; 1327 default: 1328 return; 1329 } 1330 } 1331 1332 static void vdec_event_seq_hdr(struct vpu_inst *inst, struct vpu_dec_codec_info *hdr) 1333 { 1334 struct vdec_t *vdec = inst->priv; 1335 1336 vpu_inst_lock(inst); 1337 memcpy(&vdec->codec_info, hdr, sizeof(vdec->codec_info)); 1338 1339 vpu_trace(inst->dev, "[%d] %d x %d, crop : (%d, %d) %d x %d, %d, %d\n", 1340 inst->id, 1341 vdec->codec_info.decoded_width, 1342 vdec->codec_info.decoded_height, 1343 vdec->codec_info.offset_x, 1344 vdec->codec_info.offset_y, 1345 vdec->codec_info.width, 1346 vdec->codec_info.height, 1347 hdr->num_ref_frms, 1348 hdr->num_dpb_frms); 1349 inst->min_buffer_cap = hdr->num_ref_frms + hdr->num_dpb_frms; 1350 vdec->is_source_changed = vdec_check_source_change(inst); 1351 vdec_init_fmt(inst); 1352 vdec_init_crop(inst); 1353 vdec_init_mbi(inst); 1354 vdec_init_dcp(inst); 1355 vdec_update_v4l2_profile_level(inst, hdr); 1356 if (!vdec->seq_hdr_found) { 1357 vdec->seq_tag = vdec->codec_info.tag; 1358 if (vdec->is_source_changed) { 1359 vdec_update_state(inst, VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE, 0); 1360 vdec->source_change++; 1361 vdec_handle_resolution_change(inst); 1362 vdec->is_source_changed = false; 1363 } 1364 } 1365 if (vdec->seq_tag != vdec->codec_info.tag) { 1366 vdec_response_fs_request(inst, true); 1367 vpu_trace(inst->dev, "[%d] seq tag change: %d -> %d\n", 1368 inst->id, vdec->seq_tag, vdec->codec_info.tag); 1369 } 1370 vdec->seq_hdr_found++; 1371 vdec->fixed_fmt = true; 1372 vpu_inst_unlock(inst); 1373 } 1374 1375 static void vdec_event_resolution_change(struct vpu_inst *inst) 1376 { 1377 struct vdec_t *vdec = inst->priv; 1378 1379 vpu_trace(inst->dev, "[%d]\n", inst->id); 1380 vpu_inst_lock(inst); 1381 vdec->seq_tag = vdec->codec_info.tag; 1382 vdec_clear_fs(&vdec->mbi); 1383 vdec_clear_fs(&vdec->dcp); 1384 vdec_clear_slots(inst); 1385 vdec_init_mbi(inst); 1386 vdec_init_dcp(inst); 1387 if (vdec->is_source_changed) { 1388 vdec_update_state(inst, VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE, 0); 1389 vdec->source_change++; 1390 vdec_handle_resolution_change(inst); 1391 vdec->is_source_changed = false; 1392 } 1393 vpu_inst_unlock(inst); 1394 } 1395 1396 static void vdec_event_req_fs(struct vpu_inst *inst, struct vpu_fs_info *fs) 1397 { 1398 struct vdec_t *vdec = inst->priv; 1399 1400 if (!fs) 1401 return; 1402 1403 vpu_inst_lock(inst); 1404 1405 switch (fs->type) { 1406 case MEM_RES_FRAME: 1407 vdec->req_frame_count++; 1408 break; 1409 case MEM_RES_MBI: 1410 vdec_request_one_fs(&vdec->mbi); 1411 break; 1412 case MEM_RES_DCP: 1413 vdec_request_one_fs(&vdec->dcp); 1414 break; 1415 default: 1416 break; 1417 } 1418 1419 vdec_alloc_fs(inst, &vdec->mbi); 1420 vdec_alloc_fs(inst, &vdec->dcp); 1421 1422 vdec_response_fs_request(inst, false); 1423 1424 vpu_inst_unlock(inst); 1425 } 1426 1427 static void vdec_evnet_rel_fs(struct vpu_inst *inst, struct vpu_fs_info *fs) 1428 { 1429 struct vdec_t *vdec = inst->priv; 1430 1431 if (!fs || fs->id >= vdec->slot_count) 1432 return; 1433 if (fs->type != MEM_RES_FRAME) 1434 return; 1435 1436 if (fs->id >= vdec->slot_count) { 1437 dev_err(inst->dev, "[%d] invalid fs(%d) to release\n", inst->id, fs->id); 1438 return; 1439 } 1440 1441 vpu_inst_lock(inst); 1442 if (!vdec->slots[fs->id].curr) { 1443 dev_dbg(inst->dev, "[%d] fs[%d] has bee released\n", inst->id, fs->id); 1444 goto exit; 1445 } 1446 1447 if (vdec->slots[fs->id].state == VPU_BUF_STATE_DECODED) { 1448 dev_dbg(inst->dev, "[%d] frame skip\n", inst->id); 1449 vdec->sequence++; 1450 } 1451 1452 vdec_release_curr_frame_store(inst, fs->id); 1453 vpu_process_capture_buffer(inst); 1454 1455 exit: 1456 vpu_inst_unlock(inst); 1457 } 1458 1459 static void vdec_event_eos(struct vpu_inst *inst) 1460 { 1461 struct vdec_t *vdec = inst->priv; 1462 1463 vpu_trace(inst->dev, "[%d] input : %d, decoded : %d, display : %d, sequence : %d\n", 1464 inst->id, 1465 vdec->params.frame_count, 1466 vdec->decoded_frame_count, 1467 vdec->display_frame_count, 1468 vdec->sequence); 1469 vpu_inst_lock(inst); 1470 vdec->eos_received++; 1471 vdec->fixed_fmt = false; 1472 inst->min_buffer_cap = VDEC_MIN_BUFFER_CAP; 1473 vdec_set_last_buffer_dequeued(inst); 1474 vpu_inst_unlock(inst); 1475 } 1476 1477 static void vdec_event_notify(struct vpu_inst *inst, u32 event, void *data) 1478 { 1479 switch (event) { 1480 case VPU_MSG_ID_SEQ_HDR_FOUND: 1481 vdec_event_seq_hdr(inst, data); 1482 break; 1483 case VPU_MSG_ID_RES_CHANGE: 1484 vdec_event_resolution_change(inst); 1485 break; 1486 case VPU_MSG_ID_FRAME_REQ: 1487 vdec_event_req_fs(inst, data); 1488 break; 1489 case VPU_MSG_ID_FRAME_RELEASE: 1490 vdec_evnet_rel_fs(inst, data); 1491 break; 1492 case VPU_MSG_ID_PIC_EOS: 1493 vdec_event_eos(inst); 1494 break; 1495 default: 1496 break; 1497 } 1498 } 1499 1500 static int vdec_process_output(struct vpu_inst *inst, struct vb2_buffer *vb) 1501 { 1502 struct vdec_t *vdec = inst->priv; 1503 struct vb2_v4l2_buffer *vbuf; 1504 struct vpu_rpc_buffer_desc desc; 1505 u32 free_space; 1506 int ret; 1507 1508 vbuf = to_vb2_v4l2_buffer(vb); 1509 dev_dbg(inst->dev, "[%d] dec output [%d] %d : %ld\n", 1510 inst->id, vbuf->sequence, vb->index, vb2_get_plane_payload(vb, 0)); 1511 1512 if (inst->state == VPU_CODEC_STATE_DEINIT) 1513 return -EINVAL; 1514 if (vdec->reset_codec) 1515 return -EINVAL; 1516 1517 if (inst->state == VPU_CODEC_STATE_STARTED) 1518 vdec_update_state(inst, VPU_CODEC_STATE_ACTIVE, 0); 1519 1520 ret = vpu_iface_get_stream_buffer_desc(inst, &desc); 1521 if (ret) 1522 return ret; 1523 1524 free_space = vpu_helper_get_free_space(inst); 1525 if (free_space < vb2_get_plane_payload(vb, 0) + 0x40000) 1526 return -ENOMEM; 1527 1528 vpu_set_buffer_state(vbuf, VPU_BUF_STATE_INUSE); 1529 ret = vpu_iface_input_frame(inst, vb); 1530 if (ret < 0) 1531 return -ENOMEM; 1532 1533 dev_dbg(inst->dev, "[%d][INPUT TS]%32lld\n", inst->id, vb->timestamp); 1534 vdec->params.frame_count++; 1535 1536 if (vdec->drain) 1537 vdec_drain(inst); 1538 1539 return 0; 1540 } 1541 1542 static int vdec_process_capture(struct vpu_inst *inst, struct vb2_buffer *vb) 1543 { 1544 struct vdec_t *vdec = inst->priv; 1545 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 1546 int ret; 1547 1548 if (inst->state == VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE) 1549 return -EINVAL; 1550 if (vdec->reset_codec) 1551 return -EINVAL; 1552 1553 ret = vdec_response_frame(inst, vbuf); 1554 if (ret) 1555 return ret; 1556 v4l2_m2m_dst_buf_remove_by_buf(inst->fh.m2m_ctx, vbuf); 1557 return 0; 1558 } 1559 1560 static void vdec_on_queue_empty(struct vpu_inst *inst, u32 type) 1561 { 1562 struct vdec_t *vdec = inst->priv; 1563 1564 if (V4L2_TYPE_IS_OUTPUT(type)) 1565 return; 1566 1567 vdec_handle_resolution_change(inst); 1568 if (vdec->eos_received) 1569 vdec_set_last_buffer_dequeued(inst); 1570 } 1571 1572 static void vdec_abort(struct vpu_inst *inst) 1573 { 1574 struct vdec_t *vdec = inst->priv; 1575 struct vpu_rpc_buffer_desc desc; 1576 int ret; 1577 1578 vpu_trace(inst->dev, "[%d] state = %s\n", inst->id, vpu_codec_state_name(inst->state)); 1579 1580 vdec->aborting = true; 1581 vpu_iface_add_scode(inst, SCODE_PADDING_ABORT); 1582 vdec->params.end_flag = 1; 1583 vpu_iface_set_decode_params(inst, &vdec->params, 1); 1584 1585 vpu_session_abort(inst); 1586 1587 ret = vpu_iface_get_stream_buffer_desc(inst, &desc); 1588 if (!ret) 1589 vpu_iface_update_stream_buffer(inst, desc.rptr, 1); 1590 1591 vpu_session_rst_buf(inst); 1592 vpu_trace(inst->dev, "[%d] input : %d, decoded : %d, display : %d, sequence : %d\n", 1593 inst->id, 1594 vdec->params.frame_count, 1595 vdec->decoded_frame_count, 1596 vdec->display_frame_count, 1597 vdec->sequence); 1598 if (!vdec->seq_hdr_found) 1599 vdec->reset_codec = true; 1600 vdec->params.end_flag = 0; 1601 vdec->drain = 0; 1602 vdec->params.frame_count = 0; 1603 vdec->decoded_frame_count = 0; 1604 vdec->display_frame_count = 0; 1605 vdec->sequence = 0; 1606 vdec->aborting = false; 1607 inst->extra_size = 0; 1608 } 1609 1610 static void vdec_stop(struct vpu_inst *inst, bool free) 1611 { 1612 struct vdec_t *vdec = inst->priv; 1613 1614 vdec_clear_slots(inst); 1615 if (inst->state != VPU_CODEC_STATE_DEINIT) 1616 vpu_session_stop(inst); 1617 vdec_clear_fs(&vdec->mbi); 1618 vdec_clear_fs(&vdec->dcp); 1619 if (free) { 1620 vpu_free_dma(&vdec->udata); 1621 vpu_free_dma(&inst->stream_buffer); 1622 } 1623 vdec_update_state(inst, VPU_CODEC_STATE_DEINIT, 1); 1624 vdec->reset_codec = false; 1625 } 1626 1627 static void vdec_release(struct vpu_inst *inst) 1628 { 1629 if (inst->id != VPU_INST_NULL_ID) 1630 vpu_trace(inst->dev, "[%d]\n", inst->id); 1631 vdec_stop(inst, true); 1632 } 1633 1634 static void vdec_cleanup(struct vpu_inst *inst) 1635 { 1636 struct vdec_t *vdec; 1637 1638 if (!inst) 1639 return; 1640 1641 vdec = inst->priv; 1642 if (vdec) { 1643 kfree(vdec->slots); 1644 vdec->slots = NULL; 1645 vdec->slot_count = 0; 1646 } 1647 vfree(vdec); 1648 inst->priv = NULL; 1649 vfree(inst); 1650 } 1651 1652 static void vdec_init_params(struct vdec_t *vdec) 1653 { 1654 vdec->params.frame_count = 0; 1655 vdec->params.end_flag = 0; 1656 } 1657 1658 static int vdec_start(struct vpu_inst *inst) 1659 { 1660 struct vdec_t *vdec = inst->priv; 1661 int stream_buffer_size; 1662 int ret; 1663 1664 if (inst->state != VPU_CODEC_STATE_DEINIT) 1665 return 0; 1666 1667 vpu_trace(inst->dev, "[%d]\n", inst->id); 1668 if (!vdec->udata.virt) { 1669 vdec->udata.length = 0x1000; 1670 ret = vpu_alloc_dma(inst->core, &vdec->udata); 1671 if (ret) { 1672 dev_err(inst->dev, "[%d] alloc udata fail\n", inst->id); 1673 goto error; 1674 } 1675 } 1676 1677 if (!inst->stream_buffer.virt) { 1678 stream_buffer_size = vpu_iface_get_stream_buffer_size(inst->core); 1679 if (stream_buffer_size > 0) { 1680 inst->stream_buffer.length = stream_buffer_size; 1681 ret = vpu_alloc_dma(inst->core, &inst->stream_buffer); 1682 if (ret) { 1683 dev_err(inst->dev, "[%d] alloc stream buffer fail\n", inst->id); 1684 goto error; 1685 } 1686 inst->use_stream_buffer = true; 1687 } 1688 } 1689 1690 if (inst->use_stream_buffer) 1691 vpu_iface_config_stream_buffer(inst, &inst->stream_buffer); 1692 vpu_iface_init_instance(inst); 1693 vdec->params.udata.base = vdec->udata.phys; 1694 vdec->params.udata.size = vdec->udata.length; 1695 ret = vpu_iface_set_decode_params(inst, &vdec->params, 0); 1696 if (ret) { 1697 dev_err(inst->dev, "[%d] set decode params fail\n", inst->id); 1698 goto error; 1699 } 1700 1701 vdec_init_params(vdec); 1702 ret = vpu_session_start(inst); 1703 if (ret) { 1704 dev_err(inst->dev, "[%d] start fail\n", inst->id); 1705 goto error; 1706 } 1707 1708 vdec_update_state(inst, VPU_CODEC_STATE_STARTED, 0); 1709 1710 return 0; 1711 error: 1712 vpu_free_dma(&vdec->udata); 1713 vpu_free_dma(&inst->stream_buffer); 1714 return ret; 1715 } 1716 1717 static int vdec_start_session(struct vpu_inst *inst, u32 type) 1718 { 1719 struct vdec_t *vdec = inst->priv; 1720 int ret = 0; 1721 1722 if (V4L2_TYPE_IS_OUTPUT(type)) { 1723 if (vdec->reset_codec) 1724 vdec_stop(inst, false); 1725 if (inst->state == VPU_CODEC_STATE_DEINIT) { 1726 ret = vdec_start(inst); 1727 if (ret) 1728 return ret; 1729 } 1730 } 1731 1732 if (V4L2_TYPE_IS_OUTPUT(type)) { 1733 vdec_update_state(inst, vdec->state, 1); 1734 vdec->eos_received = 0; 1735 vpu_process_output_buffer(inst); 1736 } else { 1737 vdec_cmd_start(inst); 1738 } 1739 if (inst->state == VPU_CODEC_STATE_ACTIVE) 1740 vdec_response_fs_request(inst, false); 1741 1742 return ret; 1743 } 1744 1745 static int vdec_stop_session(struct vpu_inst *inst, u32 type) 1746 { 1747 struct vdec_t *vdec = inst->priv; 1748 1749 if (inst->state == VPU_CODEC_STATE_DEINIT) 1750 return 0; 1751 1752 if (V4L2_TYPE_IS_OUTPUT(type)) { 1753 vdec_update_state(inst, VPU_CODEC_STATE_SEEK, 0); 1754 vdec->drain = 0; 1755 vdec_abort(inst); 1756 } else { 1757 if (inst->state != VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE) { 1758 if (vb2_is_streaming(v4l2_m2m_get_src_vq(inst->fh.m2m_ctx))) 1759 vdec_abort(inst); 1760 vdec->eos_received = 0; 1761 } 1762 vdec_clear_slots(inst); 1763 } 1764 1765 return 0; 1766 } 1767 1768 static int vdec_get_slot_debug_info(struct vpu_inst *inst, char *str, u32 size, u32 i) 1769 { 1770 struct vdec_t *vdec = inst->priv; 1771 struct vpu_vb2_buffer *vpu_buf; 1772 int num = -1; 1773 1774 vpu_inst_lock(inst); 1775 if (i >= vdec->slot_count || !vdec->slots[i].addr) 1776 goto exit; 1777 1778 vpu_buf = vdec->slots[i].curr; 1779 1780 num = scnprintf(str, size, "slot[%2d] :", i); 1781 if (vpu_buf) { 1782 num += scnprintf(str + num, size - num, " %2d", 1783 vpu_buf->m2m_buf.vb.vb2_buf.index); 1784 num += scnprintf(str + num, size - num, "; state = %d", vdec->slots[i].state); 1785 } else { 1786 num += scnprintf(str + num, size - num, " -1"); 1787 } 1788 1789 if (vdec->slots[i].pend) 1790 num += scnprintf(str + num, size - num, "; %d", 1791 vdec->slots[i].pend->m2m_buf.vb.vb2_buf.index); 1792 1793 num += scnprintf(str + num, size - num, "\n"); 1794 exit: 1795 vpu_inst_unlock(inst); 1796 1797 return num; 1798 } 1799 1800 static int vdec_get_debug_info(struct vpu_inst *inst, char *str, u32 size, u32 i) 1801 { 1802 struct vdec_t *vdec = inst->priv; 1803 int num; 1804 1805 switch (i) { 1806 case 0: 1807 num = scnprintf(str, size, 1808 "req_frame_count = %d\ninterlaced = %d\n", 1809 vdec->req_frame_count, 1810 vdec->codec_info.progressive ? 0 : 1); 1811 break; 1812 case 1: 1813 num = scnprintf(str, size, 1814 "mbi: size = 0x%x request = %d, alloc = %d, response = %d\n", 1815 vdec->mbi.size, 1816 vdec->mbi.req_count, 1817 vdec->mbi.count, 1818 vdec->mbi.index); 1819 break; 1820 case 2: 1821 num = scnprintf(str, size, 1822 "dcp: size = 0x%x request = %d, alloc = %d, response = %d\n", 1823 vdec->dcp.size, 1824 vdec->dcp.req_count, 1825 vdec->dcp.count, 1826 vdec->dcp.index); 1827 break; 1828 case 3: 1829 num = scnprintf(str, size, "input_frame_count = %d\n", vdec->params.frame_count); 1830 break; 1831 case 4: 1832 num = scnprintf(str, size, "decoded_frame_count = %d\n", vdec->decoded_frame_count); 1833 break; 1834 case 5: 1835 num = scnprintf(str, size, "display_frame_count = %d\n", vdec->display_frame_count); 1836 break; 1837 case 6: 1838 num = scnprintf(str, size, "sequence = %d\n", vdec->sequence); 1839 break; 1840 case 7: 1841 num = scnprintf(str, size, "drain = %d, eos = %d, source_change = %d\n", 1842 vdec->drain, vdec->eos_received, vdec->source_change); 1843 break; 1844 case 8: 1845 num = scnprintf(str, size, "fps = %d/%d\n", 1846 vdec->codec_info.frame_rate.numerator, 1847 vdec->codec_info.frame_rate.denominator); 1848 break; 1849 case 9: 1850 num = scnprintf(str, size, "colorspace: %d, %d, %d, %d (%d)\n", 1851 vdec->codec_info.color_primaries, 1852 vdec->codec_info.transfer_chars, 1853 vdec->codec_info.matrix_coeffs, 1854 vdec->codec_info.full_range, 1855 vdec->codec_info.vui_present); 1856 break; 1857 default: 1858 num = vdec_get_slot_debug_info(inst, str, size, i - 10); 1859 break; 1860 } 1861 1862 return num; 1863 } 1864 1865 static struct vpu_inst_ops vdec_inst_ops = { 1866 .ctrl_init = vdec_ctrl_init, 1867 .check_ready = vdec_check_ready, 1868 .buf_done = vdec_buf_done, 1869 .get_one_frame = vdec_frame_decoded, 1870 .stop_done = vdec_stop_done, 1871 .event_notify = vdec_event_notify, 1872 .release = vdec_release, 1873 .cleanup = vdec_cleanup, 1874 .start = vdec_start_session, 1875 .stop = vdec_stop_session, 1876 .process_output = vdec_process_output, 1877 .process_capture = vdec_process_capture, 1878 .on_queue_empty = vdec_on_queue_empty, 1879 .get_debug_info = vdec_get_debug_info, 1880 .wait_prepare = vpu_inst_unlock, 1881 .wait_finish = vpu_inst_lock, 1882 .attach_frame_store = vdec_attach_frame_store, 1883 .reset_frame_store = vdec_reset_frame_store, 1884 }; 1885 1886 static void vdec_init(struct file *file) 1887 { 1888 struct vpu_inst *inst = to_inst(file); 1889 struct v4l2_format f; 1890 1891 memset(&f, 0, sizeof(f)); 1892 f.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 1893 f.fmt.pix_mp.pixelformat = V4L2_PIX_FMT_H264; 1894 f.fmt.pix_mp.width = 1280; 1895 f.fmt.pix_mp.height = 720; 1896 f.fmt.pix_mp.field = V4L2_FIELD_NONE; 1897 vdec_s_fmt(file, &inst->fh, &f); 1898 1899 memset(&f, 0, sizeof(f)); 1900 f.type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; 1901 f.fmt.pix_mp.pixelformat = V4L2_PIX_FMT_NV12M_8L128; 1902 f.fmt.pix_mp.width = 1280; 1903 f.fmt.pix_mp.height = 720; 1904 f.fmt.pix_mp.field = V4L2_FIELD_NONE; 1905 vdec_s_fmt(file, &inst->fh, &f); 1906 } 1907 1908 static int vdec_open(struct file *file) 1909 { 1910 struct vpu_inst *inst; 1911 struct vdec_t *vdec; 1912 int ret; 1913 1914 inst = vzalloc(sizeof(*inst)); 1915 if (!inst) 1916 return -ENOMEM; 1917 1918 vdec = vzalloc(sizeof(*vdec)); 1919 if (!vdec) { 1920 vfree(inst); 1921 return -ENOMEM; 1922 } 1923 1924 vdec->slots = kmalloc_array(VDEC_SLOT_CNT_DFT, 1925 sizeof(*vdec->slots), 1926 GFP_KERNEL | __GFP_ZERO); 1927 if (!vdec->slots) { 1928 vfree(vdec); 1929 vfree(inst); 1930 return -ENOMEM; 1931 } 1932 vdec->slot_count = VDEC_SLOT_CNT_DFT; 1933 1934 inst->ops = &vdec_inst_ops; 1935 inst->formats = vdec_formats; 1936 inst->type = VPU_CORE_TYPE_DEC; 1937 inst->priv = vdec; 1938 1939 ret = vpu_v4l2_open(file, inst); 1940 if (ret) 1941 return ret; 1942 1943 vdec->fixed_fmt = false; 1944 vdec->state = VPU_CODEC_STATE_ACTIVE; 1945 inst->min_buffer_cap = VDEC_MIN_BUFFER_CAP; 1946 inst->min_buffer_out = VDEC_MIN_BUFFER_OUT; 1947 vdec_init(file); 1948 1949 return 0; 1950 } 1951 1952 static const struct v4l2_file_operations vdec_fops = { 1953 .owner = THIS_MODULE, 1954 .open = vdec_open, 1955 .release = vpu_v4l2_close, 1956 .unlocked_ioctl = video_ioctl2, 1957 .poll = v4l2_m2m_fop_poll, 1958 .mmap = v4l2_m2m_fop_mmap, 1959 }; 1960 1961 const struct v4l2_ioctl_ops *vdec_get_ioctl_ops(void) 1962 { 1963 return &vdec_ioctl_ops; 1964 } 1965 1966 const struct v4l2_file_operations *vdec_get_fops(void) 1967 { 1968 return &vdec_fops; 1969 } 1970