xref: /linux/drivers/media/platform/amlogic/c3/isp/c3-isp-regs.h (revision e47a324d6f07c9ef252cfce1f14cfa5110cbed99)
1 /* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
2 /*
3  * Copyright (C) 2024 Amlogic, Inc. All rights reserved
4  */
5 
6 #ifndef __C3_ISP_REGS_H__
7 #define __C3_ISP_REGS_H__
8 
9 #define ISP_TOP_INPUT_SIZE				0x0000
10 #define ISP_TOP_INPUT_SIZE_VERT_SIZE_MASK		GENMASK(15, 0)
11 #define ISP_TOP_INPUT_SIZE_VERT_SIZE(x)			((x) << 0)
12 #define ISP_TOP_INPUT_SIZE_HORIZ_SIZE_MASK		GENMASK(31, 16)
13 #define ISP_TOP_INPUT_SIZE_HORIZ_SIZE(x)		((x) << 16)
14 
15 #define ISP_TOP_FRM_SIZE				0x0004
16 #define ISP_TOP_FRM_SIZE_CORE_VERT_SIZE_MASK		GENMASK(15, 0)
17 #define ISP_TOP_FRM_SIZE_CORE_VERT_SIZE(x)		((x) << 0)
18 #define ISP_TOP_FRM_SIZE_CORE_HORIZ_SIZE_MASK		GENMASK(31, 16)
19 #define ISP_TOP_FRM_SIZE_CORE_HORIZ_SIZE(x)		((x) << 16)
20 
21 #define ISP_TOP_HOLD_SIZE				0x0008
22 #define ISP_TOP_HOLD_SIZE_CORE_HORIZ_SIZE_MASK		GENMASK(31, 16)
23 #define ISP_TOP_HOLD_SIZE_CORE_HORIZ_SIZE(x)		((x) << 16)
24 
25 #define ISP_TOP_PATH_EN					0x0010
26 #define ISP_TOP_PATH_EN_DISP0_EN_MASK			BIT(0)
27 #define ISP_TOP_PATH_EN_DISP0_EN			BIT(0)
28 #define ISP_TOP_PATH_EN_DISP0_DIS			(0 << 0)
29 #define ISP_TOP_PATH_EN_DISP1_EN_MASK			BIT(1)
30 #define ISP_TOP_PATH_EN_DISP1_EN			BIT(1)
31 #define ISP_TOP_PATH_EN_DISP1_DIS			(0 << 1)
32 #define ISP_TOP_PATH_EN_DISP2_EN_MASK			BIT(2)
33 #define ISP_TOP_PATH_EN_DISP2_EN			BIT(2)
34 #define ISP_TOP_PATH_EN_DISP2_DIS			(0 << 2)
35 #define ISP_TOP_PATH_EN_WRMIF0_EN_MASK			BIT(8)
36 #define ISP_TOP_PATH_EN_WRMIF0_EN			BIT(8)
37 #define ISP_TOP_PATH_EN_WRMIF0_DIS			(0 << 8)
38 #define ISP_TOP_PATH_EN_WRMIF1_EN_MASK			BIT(9)
39 #define ISP_TOP_PATH_EN_WRMIF1_EN			BIT(9)
40 #define ISP_TOP_PATH_EN_WRMIF1_DIS			(0 << 9)
41 #define ISP_TOP_PATH_EN_WRMIF2_EN_MASK			BIT(10)
42 #define ISP_TOP_PATH_EN_WRMIF2_EN			BIT(10)
43 #define ISP_TOP_PATH_EN_WRMIF2_DIS			(0 << 10)
44 
45 #define ISP_TOP_PATH_SEL				0x0014
46 #define ISP_TOP_PATH_SEL_CORE_MASK			GENMASK(18, 16)
47 #define ISP_TOP_PATH_SEL_CORE_CORE_DIS			(0 << 16)
48 #define ISP_TOP_PATH_SEL_CORE_MIPI_CORE			BIT(16)
49 
50 #define ISP_TOP_DISPIN_SEL				0x0018
51 #define ISP_TOP_DISPIN_SEL_DISP0_MASK			GENMASK(3, 0)
52 #define ISP_TOP_DISPIN_SEL_DISP0_CORE_OUT		(0 << 0)
53 #define ISP_TOP_DISPIN_SEL_DISP0_MIPI_OUT		(2 << 0)
54 #define ISP_TOP_DISPIN_SEL_DISP1_MASK			GENMASK(7, 4)
55 #define ISP_TOP_DISPIN_SEL_DISP1_CORE_OUT		(0 << 4)
56 #define ISP_TOP_DISPIN_SEL_DISP1_MIPI_OUT		(2 << 4)
57 #define ISP_TOP_DISPIN_SEL_DISP2_MASK			GENMASK(11, 8)
58 #define ISP_TOP_DISPIN_SEL_DISP2_CORE_OUT		(0 << 8)
59 #define ISP_TOP_DISPIN_SEL_DISP2_MIPI_OUT		(2 << 8)
60 
61 #define ISP_TOP_IRQ_EN					0x0080
62 #define ISP_TOP_IRQ_EN_FRM_END_MASK			BIT(0)
63 #define ISP_TOP_IRQ_EN_FRM_END_EN			BIT(0)
64 #define ISP_TOP_IRQ_EN_FRM_END_DIS			(0 << 0)
65 #define ISP_TOP_IRQ_EN_FRM_RST_MASK			BIT(1)
66 #define ISP_TOP_IRQ_EN_FRM_RST_EN			BIT(1)
67 #define ISP_TOP_IRQ_EN_FRM_RST_DIS			(0 << 1)
68 #define ISP_TOP_IRQ_EN_3A_DMA_ERR_MASK			BIT(5)
69 #define ISP_TOP_IRQ_EN_3A_DMA_ERR_EN			BIT(5)
70 #define ISP_TOP_IRQ_EN_3A_DMA_ERR_DIS			(0 << 5)
71 
72 #define ISP_TOP_IRQ_CLR					0x0084
73 #define ISP_TOP_RO_IRQ_STAT				0x01c4
74 #define ISP_TOP_RO_IRQ_STAT_FRM_END_MASK		BIT(0)
75 #define ISP_TOP_RO_IRQ_STAT_FRM_RST_MASK		BIT(1)
76 #define ISP_TOP_RO_IRQ_STAT_3A_DMA_ERR_MASK		BIT(5)
77 
78 #define ISP_TOP_MODE_CTRL				0x0400
79 #define ISP_TOP_FEO_CTRL0				0x040c
80 #define ISP_TOP_FEO_CTRL0_INPUT_FMT_EN_MASK		BIT(8)
81 #define ISP_TOP_FEO_CTRL0_INPUT_FMT_DIS			(0 << 8)
82 #define ISP_TOP_FEO_CTRL0_INPUT_FMT_EN			BIT(8)
83 
84 #define ISP_TOP_FEO_CTRL1_0				0x0410
85 #define ISP_TOP_FEO_CTRL1_0_DPC_EN_MASK			BIT(3)
86 #define ISP_TOP_FEO_CTRL1_0_DPC_DIS			(0 << 3)
87 #define ISP_TOP_FEO_CTRL1_0_DPC_EN			BIT(3)
88 #define ISP_TOP_FEO_CTRL1_0_OG_EN_MASK			BIT(5)
89 #define ISP_TOP_FEO_CTRL1_0_OG_DIS			(0 << 5)
90 #define ISP_TOP_FEO_CTRL1_0_OG_EN			BIT(5)
91 
92 #define ISP_TOP_FED_CTRL				0x0418
93 #define ISP_TOP_FED_CTRL_PDPC_EN_MASK			BIT(1)
94 #define ISP_TOP_FED_CTRL_PDPC_DIS			(0 << 1)
95 #define ISP_TOP_FED_CTRL_PDPC_EN			BIT(1)
96 #define ISP_TOP_FED_CTRL_RAWCNR_EN_MASK			GENMASK(6, 5)
97 #define ISP_TOP_FED_CTRL_RAWCNR_DIS			(0 << 5)
98 #define ISP_TOP_FED_CTRL_RAWCNR_EN			BIT(5)
99 #define ISP_TOP_FED_CTRL_SNR1_EN_MASK			BIT(9)
100 #define ISP_TOP_FED_CTRL_SNR1_DIS			(0 << 9)
101 #define ISP_TOP_FED_CTRL_SNR1_EN			BIT(9)
102 #define ISP_TOP_FED_CTRL_TNR0_EN_MASK			BIT(11)
103 #define ISP_TOP_FED_CTRL_TNR0_DIS			(0 << 11)
104 #define ISP_TOP_FED_CTRL_TNR0_EN			BIT(11)
105 #define ISP_TOP_FED_CTRL_CUBIC_CS_EN_MASK		BIT(12)
106 #define ISP_TOP_FED_CTRL_CUBIC_CS_DIS			(0 << 12)
107 #define ISP_TOP_FED_CTRL_CUBIC_CS_EN			BIT(12)
108 #define ISP_TOP_FED_CTRL_SQRT_EN_MASK			BIT(14)
109 #define ISP_TOP_FED_CTRL_SQRT_DIS			(0 << 14)
110 #define ISP_TOP_FED_CTRL_SQRT_EN			BIT(14)
111 #define ISP_TOP_FED_CTRL_DGAIN_EN_MASK			BIT(16)
112 #define ISP_TOP_FED_CTRL_DGAIN_DIS			(0 << 16)
113 #define ISP_TOP_FED_CTRL_DGAIN_EN			BIT(16)
114 
115 #define ISP_TOP_BEO_CTRL				0x041c
116 #define ISP_TOP_BEO_CTRL_WB_EN_MASK			BIT(6)
117 #define ISP_TOP_BEO_CTRL_WB_DIS				(0 << 6)
118 #define ISP_TOP_BEO_CTRL_WB_EN				BIT(6)
119 #define ISP_TOP_BEO_CTRL_BLC_EN_MASK			BIT(7)
120 #define ISP_TOP_BEO_CTRL_BLC_DIS			(0 << 7)
121 #define ISP_TOP_BEO_CTRL_BLC_EN				BIT(7)
122 #define ISP_TOP_BEO_CTRL_INV_DGAIN_EN_MASK		BIT(8)
123 #define ISP_TOP_BEO_CTRL_INV_DGAIN_DIS			(0 << 8)
124 #define ISP_TOP_BEO_CTRL_INV_DGAIN_EN			BIT(8)
125 #define ISP_TOP_BEO_CTRL_EOTF_EN_MASK			BIT(9)
126 #define ISP_TOP_BEO_CTRL_EOTF_DIS			(0 << 9)
127 #define ISP_TOP_BEO_CTRL_EOTF_EN			BIT(9)
128 
129 #define ISP_TOP_BED_CTRL				0x0420
130 #define ISP_TOP_BED_CTRL_YHS_STAT_EN_MASK		GENMASK(1, 0)
131 #define ISP_TOP_BED_CTRL_YHS_STAT_DIS			(0 << 0)
132 #define ISP_TOP_BED_CTRL_YHS_STAT_EN			BIT(0)
133 #define ISP_TOP_BED_CTRL_GRPH_STAT_EN_MASK		BIT(2)
134 #define ISP_TOP_BED_CTRL_GRPH_STAT_DIS			(0 << 2)
135 #define ISP_TOP_BED_CTRL_GRPH_STAT_EN			BIT(2)
136 #define ISP_TOP_BED_CTRL_FMETER_EN_MASK			BIT(3)
137 #define ISP_TOP_BED_CTRL_FMETER_DIS			(0 << 3)
138 #define ISP_TOP_BED_CTRL_FMETER_EN			BIT(3)
139 #define ISP_TOP_BED_CTRL_BSC_EN_MASK			BIT(10)
140 #define ISP_TOP_BED_CTRL_BSC_DIS			(0 << 10)
141 #define ISP_TOP_BED_CTRL_BSC_EN				BIT(10)
142 #define ISP_TOP_BED_CTRL_CNR2_EN_MASK			BIT(11)
143 #define ISP_TOP_BED_CTRL_CNR2_DIS			(0 << 11)
144 #define ISP_TOP_BED_CTRL_CNR2_EN			BIT(11)
145 #define ISP_TOP_BED_CTRL_CM1_EN_MASK			BIT(13)
146 #define ISP_TOP_BED_CTRL_CM1_DIS			(0 << 13)
147 #define ISP_TOP_BED_CTRL_CM1_EN				BIT(13)
148 #define ISP_TOP_BED_CTRL_CM0_EN_MASK			BIT(14)
149 #define ISP_TOP_BED_CTRL_CM0_DIS			(0 << 14)
150 #define ISP_TOP_BED_CTRL_CM0_EN				BIT(14)
151 #define ISP_TOP_BED_CTRL_PST_GAMMA_EN_MASK		BIT(16)
152 #define ISP_TOP_BED_CTRL_PST_GAMMA_DIS			(0 << 16)
153 #define ISP_TOP_BED_CTRL_PST_GAMMA_EN			BIT(16)
154 #define ISP_TOP_BED_CTRL_LUT3D_EN_MASK			BIT(17)
155 #define ISP_TOP_BED_CTRL_LUT3D_DIS			(0 << 17)
156 #define ISP_TOP_BED_CTRL_LUT3D_EN			BIT(17)
157 #define ISP_TOP_BED_CTRL_CCM_EN_MASK			BIT(18)
158 #define ISP_TOP_BED_CTRL_CCM_DIS			(0 << 18)
159 #define ISP_TOP_BED_CTRL_CCM_EN				BIT(18)
160 #define ISP_TOP_BED_CTRL_PST_TNR_LITE_EN_MASK		BIT(21)
161 #define ISP_TOP_BED_CTRL_PST_TNR_LITE_DIS		(0 << 21)
162 #define ISP_TOP_BED_CTRL_PST_TNR_LITE_EN		BIT(21)
163 #define ISP_TOP_BED_CTRL_AMCM_EN_MASK			BIT(25)
164 #define ISP_TOP_BED_CTRL_AMCM_DIS			(0 << 25)
165 #define ISP_TOP_BED_CTRL_AMCM_EN			BIT(25)
166 
167 #define ISP_TOP_3A_STAT_CRTL				0x0424
168 #define ISP_TOP_3A_STAT_CRTL_AE_STAT_EN_MASK		BIT(0)
169 #define ISP_TOP_3A_STAT_CRTL_AE_STAT_DIS		(0 << 0)
170 #define ISP_TOP_3A_STAT_CRTL_AE_STAT_EN			BIT(0)
171 #define ISP_TOP_3A_STAT_CRTL_AWB_STAT_EN_MASK		BIT(1)
172 #define ISP_TOP_3A_STAT_CRTL_AWB_STAT_DIS		(0 << 1)
173 #define ISP_TOP_3A_STAT_CRTL_AWB_STAT_EN		BIT(1)
174 #define ISP_TOP_3A_STAT_CRTL_AF_STAT_EN_MASK		BIT(2)
175 #define ISP_TOP_3A_STAT_CRTL_AF_STAT_DIS		(0 << 2)
176 #define ISP_TOP_3A_STAT_CRTL_AF_STAT_EN			BIT(2)
177 #define ISP_TOP_3A_STAT_CRTL_AWB_POINT_MASK		GENMASK(6, 4)
178 #define ISP_TOP_3A_STAT_CRTL_AWB_POINT(x)		((x) << 4)
179 #define ISP_TOP_3A_STAT_CRTL_AE_POINT_MASK		GENMASK(9, 8)
180 #define ISP_TOP_3A_STAT_CRTL_AE_POINT(x)		((x) << 8)
181 #define ISP_TOP_3A_STAT_CRTL_AF_POINT_MASK		GENMASK(13, 12)
182 #define ISP_TOP_3A_STAT_CRTL_AF_POINT(x)		((x) << 12)
183 
184 #define ISP_LSWB_BLC_OFST0				0x4028
185 #define ISP_LSWB_BLC_OFST0_R_OFST_MASK			GENMASK(15, 0)
186 #define ISP_LSWB_BLC_OFST0_R_OFST(x)			((x) << 0)
187 #define ISP_LSWB_BLC_OFST0_GR_OFST_MASK			GENMASK(31, 16)
188 #define ISP_LSWB_BLC_OFST0_GR_OFST(x)			((x) << 16)
189 
190 #define ISP_LSWB_BLC_OFST1				0x402c
191 #define ISP_LSWB_BLC_OFST1_GB_OFST_MASK			GENMASK(15, 0)
192 #define ISP_LSWB_BLC_OFST1_GB_OFST(x)			((x) << 0)
193 #define ISP_LSWB_BLC_OFST1_B_OFST_MASK			GENMASK(31, 16)
194 #define ISP_LSWB_BLC_OFST1_B_OFST(x)			((x) << 16)
195 
196 #define ISP_LSWB_BLC_PHSOFST				0x4034
197 #define ISP_LSWB_BLC_PHSOFST_VERT_OFST_MASK		GENMASK(1, 0)
198 #define ISP_LSWB_BLC_PHSOFST_VERT_OFST(x)		((x) << 0)
199 #define ISP_LSWB_BLC_PHSOFST_HORIZ_OFST_MASK		GENMASK(3, 2)
200 #define ISP_LSWB_BLC_PHSOFST_HORIZ_OFST(x)		((x) << 2)
201 
202 #define ISP_LSWB_WB_GAIN0				0x4038
203 #define ISP_LSWB_WB_GAIN0_R_GAIN_MASK			GENMASK(11, 0)
204 #define ISP_LSWB_WB_GAIN0_R_GAIN(x)			((x) << 0)
205 #define ISP_LSWB_WB_GAIN0_GR_GAIN_MASK			GENMASK(27, 16)
206 #define ISP_LSWB_WB_GAIN0_GR_GAIN(x)			((x) << 16)
207 
208 #define ISP_LSWB_WB_GAIN1				0x403c
209 #define ISP_LSWB_WB_GAIN1_GB_GAIN_MASK			GENMASK(11, 0)
210 #define ISP_LSWB_WB_GAIN1_GB_GAIN(x)			((x) << 0)
211 #define ISP_LSWB_WB_GAIN1_B_GAIN_MASK			GENMASK(27, 16)
212 #define ISP_LSWB_WB_GAIN1_B_GAIN(x)			((x) << 16)
213 
214 #define ISP_LSWB_WB_GAIN2				0x4040
215 #define ISP_LSWB_WB_GAIN2_IR_GAIN_MASK			GENMASK(11, 0)
216 #define ISP_LSWB_WB_GAIN2_IR_GAIN(x)			((x) << 0)
217 
218 #define ISP_LSWB_WB_LIMIT0				0x4044
219 #define ISP_LSWB_WB_LIMIT0_WB_LIMIT_R_MASK		GENMASK(15, 0)
220 #define ISP_LSWB_WB_LIMIT0_WB_LIMIT_R(x)		((x) << 0)
221 #define ISP_LSWB_WB_LIMIT0_WB_LIMIT_R_MAX		(0x8fff << 0)
222 #define ISP_LSWB_WB_LIMIT0_WB_LIMIT_GR_MASK		GENMASK(31, 16)
223 #define ISP_LSWB_WB_LIMIT0_WB_LIMIT_GR(x)		((x) << 16)
224 #define ISP_LSWB_WB_LIMIT0_WB_LIMIT_GR_MAX		(0x8fff << 16)
225 
226 #define ISP_LSWB_WB_LIMIT1				0x4048
227 #define ISP_LSWB_WB_LIMIT1_WB_LIMIT_GB_MASK		GENMASK(15, 0)
228 #define ISP_LSWB_WB_LIMIT1_WB_LIMIT_GB(x)		((x) << 0)
229 #define ISP_LSWB_WB_LIMIT1_WB_LIMIT_GB_MAX		(0x8fff << 0)
230 #define ISP_LSWB_WB_LIMIT1_WB_LIMIT_B_MASK		GENMASK(31, 16)
231 #define ISP_LSWB_WB_LIMIT1_WB_LIMIT_B(x)		((x) << 16)
232 #define ISP_LSWB_WB_LIMIT1_WB_LIMIT_B_MAX		(0x8fff << 16)
233 
234 #define ISP_LSWB_WB_PHSOFST				0x4050
235 #define ISP_LSWB_WB_PHSOFST_VERT_OFST_MASK		GENMASK(1, 0)
236 #define ISP_LSWB_WB_PHSOFST_VERT_OFST(x)		((x) << 0)
237 #define ISP_LSWB_WB_PHSOFST_HORIZ_OFST_MASK		GENMASK(3, 2)
238 #define ISP_LSWB_WB_PHSOFST_HORIZ_OFST(x)		((x) << 2)
239 
240 #define ISP_LSWB_LNS_PHSOFST				0x4054
241 #define ISP_LSWB_LNS_PHSOFST_VERT_OFST_MASK		GENMASK(1, 0)
242 #define ISP_LSWB_LNS_PHSOFST_VERT_OFST(x)		((x) << 0)
243 #define ISP_LSWB_LNS_PHSOFST_HORIZ_OFST_MASK		GENMASK(3, 2)
244 #define ISP_LSWB_LNS_PHSOFST_HORIZ_OFST(x)		((x) << 2)
245 
246 #define ISP_DMS_COMMON_PARAM0				0x5000
247 #define ISP_DMS_COMMON_PARAM0_VERT_PHS_OFST_MASK	GENMASK(1, 0)
248 #define ISP_DMS_COMMON_PARAM0_VERT_PHS_OFST(x)		((x) << 0)
249 #define ISP_DMS_COMMON_PARAM0_HORIZ_PHS_OFST_MASK	GENMASK(3, 2)
250 #define ISP_DMS_COMMON_PARAM0_HORIZ_PHS_OFST(x)		((x) << 2)
251 
252 #define ISP_CM0_COEF00_01				0x6048
253 #define ISP_CM0_COEF00_01_MTX_00_MASK			GENMASK(12, 0)
254 #define ISP_CM0_COEF00_01_MTX_00(x)			((x) << 0)
255 #define ISP_CM0_COEF00_01_MTX_01_MASK			GENMASK(28, 16)
256 #define ISP_CM0_COEF00_01_MTX_01(x)			((x) << 16)
257 
258 #define ISP_CM0_COEF02_10				0x604c
259 #define ISP_CM0_COEF02_10_MTX_02_MASK			GENMASK(12, 0)
260 #define ISP_CM0_COEF02_10_MTX_02(x)			((x) << 0)
261 #define ISP_CM0_COEF02_10_MTX_10_MASK			GENMASK(28, 16)
262 #define ISP_CM0_COEF02_10_MTX_10(x)			((x) << 16)
263 
264 #define ISP_CM0_COEF11_12				0x6050
265 #define ISP_CM0_COEF11_12_MTX_11_MASK			GENMASK(12, 0)
266 #define ISP_CM0_COEF11_12_MTX_11(x)			((x) << 0)
267 #define ISP_CM0_COEF11_12_MTX_12_MASK			GENMASK(28, 16)
268 #define ISP_CM0_COEF11_12_MTX_12(x)			((x) << 16)
269 
270 #define ISP_CM0_COEF20_21				0x6054
271 #define ISP_CM0_COEF20_21_MTX_20_MASK			GENMASK(12, 0)
272 #define ISP_CM0_COEF20_21_MTX_20(x)			((x) << 0)
273 #define ISP_CM0_COEF20_21_MTX_21_MASK			GENMASK(28, 16)
274 #define ISP_CM0_COEF20_21_MTX_21(x)			((x) << 16)
275 
276 #define ISP_CM0_COEF22_OUP_OFST0			0x6058
277 #define ISP_CM0_COEF22_OUP_OFST0_MTX_22_MASK		GENMASK(12, 0)
278 #define ISP_CM0_COEF22_OUP_OFST0_MTX_22(x)		((x) << 0)
279 
280 #define ISP_CCM_MTX_00_01				0x6098
281 #define ISP_CCM_MTX_00_01_MTX_00_MASK			GENMASK(12, 0)
282 #define ISP_CCM_MTX_00_01_MTX_00(x)			((x) << 0)
283 #define ISP_CCM_MTX_00_01_MTX_01_MASK			GENMASK(28, 16)
284 #define ISP_CCM_MTX_00_01_MTX_01(x)			((x) << 16)
285 
286 #define ISP_CCM_MTX_02_03				0x609c
287 #define ISP_CCM_MTX_02_03_MTX_02_MASK			GENMASK(12, 0)
288 #define ISP_CCM_MTX_02_03_MTX_02(x)			((x) << 0)
289 
290 #define ISP_CCM_MTX_10_11				0x60A0
291 #define ISP_CCM_MTX_10_11_MTX_10_MASK			GENMASK(12, 0)
292 #define ISP_CCM_MTX_10_11_MTX_10(x)			((x) << 0)
293 #define ISP_CCM_MTX_10_11_MTX_11_MASK			GENMASK(28, 16)
294 #define ISP_CCM_MTX_10_11_MTX_11(x)			((x) << 16)
295 
296 #define ISP_CCM_MTX_12_13				0x60A4
297 #define ISP_CCM_MTX_12_13_MTX_12_MASK			GENMASK(12, 0)
298 #define ISP_CCM_MTX_12_13_MTX_12(x)			((x) << 0)
299 
300 #define ISP_CCM_MTX_20_21				0x60A8
301 #define ISP_CCM_MTX_20_21_MTX_20_MASK			GENMASK(12, 0)
302 #define ISP_CCM_MTX_20_21_MTX_20(x)			((x) << 0)
303 #define ISP_CCM_MTX_20_21_MTX_21_MASK			GENMASK(28, 16)
304 #define ISP_CCM_MTX_20_21_MTX_21(x)			((x) << 16)
305 
306 #define ISP_CCM_MTX_22_23_RS				0x60Ac
307 #define ISP_CCM_MTX_22_23_RS_MTX_22_MASK		GENMASK(12, 0)
308 #define ISP_CCM_MTX_22_23_RS_MTX_22(x)			((x) << 0)
309 
310 #define ISP_PST_GAMMA_LUT_ADDR				0x60cc
311 #define ISP_PST_GAMMA_LUT_ADDR_IDX_ADDR(x)		((x) << 7)
312 
313 #define ISP_PST_GAMMA_LUT_DATA				0x60d0
314 #define ISP_PST_GM_LUT_DATA0(x)		(((x) & GENMASK(15, 0)) << 0)
315 #define ISP_PST_GM_LUT_DATA1(x)		(((x) & GENMASK(15, 0)) << 16)
316 
317 #define DISP0_TOP_TOP_CTRL				0x8000
318 #define DISP0_TOP_TOP_CTRL_CROP2_EN_MASK		BIT(5)
319 #define DISP0_TOP_TOP_CTRL_CROP2_EN			BIT(5)
320 #define DISP0_TOP_TOP_CTRL_CROP2_DIS			(0 << 5)
321 
322 #define DISP0_TOP_CRP2_START				0x8004
323 #define DISP0_TOP_CRP2_START_V_START_MASK		GENMASK(15, 0)
324 #define DISP0_TOP_CRP2_START_V_START(x)			((x) << 0)
325 #define DISP0_TOP_CRP2_START_H_START_MASK		GENMASK(31, 16)
326 #define DISP0_TOP_CRP2_START_H_START(x)			((x) << 16)
327 
328 #define DISP0_TOP_CRP2_SIZE				0x8008
329 #define DISP0_TOP_CRP2_SIZE_V_SIZE_MASK			GENMASK(15, 0)
330 #define DISP0_TOP_CRP2_SIZE_V_SIZE(x)			((x) << 0)
331 #define DISP0_TOP_CRP2_SIZE_H_SIZE_MASK			GENMASK(31, 16)
332 #define DISP0_TOP_CRP2_SIZE_H_SIZE(x)			((x) << 16)
333 
334 #define DISP0_TOP_OUT_SIZE				0x800c
335 #define DISP0_TOP_OUT_SIZE_SCL_OUT_HEIGHT_MASK		GENMASK(12, 0)
336 #define DISP0_TOP_OUT_SIZE_SCL_OUT_HEIGHT(x)		((x) << 0)
337 #define DISP0_TOP_OUT_SIZE_SCL_OUT_WIDTH_MASK		GENMASK(28, 16)
338 #define DISP0_TOP_OUT_SIZE_SCL_OUT_WIDTH(x)		((x) << 16)
339 
340 #define ISP_DISP0_TOP_IN_SIZE				0x804c
341 #define ISP_DISP0_TOP_IN_SIZE_VSIZE_MASK		GENMASK(12, 0)
342 #define ISP_DISP0_TOP_IN_SIZE_VSIZE(x)			((x) << 0)
343 #define ISP_DISP0_TOP_IN_SIZE_HSIZE_MASK		GENMASK(28, 16)
344 #define ISP_DISP0_TOP_IN_SIZE_HSIZE(x)			((x) << 16)
345 
346 #define DISP0_PPS_SCALE_EN				0x8200
347 #define DISP0_PPS_SCALE_EN_VSC_TAP_NUM_MASK		GENMASK(3, 0)
348 #define DISP0_PPS_SCALE_EN_VSC_TAP_NUM(x)		((x) << 0)
349 #define DISP0_PPS_SCALE_EN_HSC_TAP_NUM_MASK		GENMASK(7, 4)
350 #define DISP0_PPS_SCALE_EN_HSC_TAP_NUM(x)		((x) << 4)
351 #define DISP0_PPS_SCALE_EN_PREVSC_FLT_NUM_MASK		GENMASK(11, 8)
352 #define DISP0_PPS_SCALE_EN_PREVSC_FLT_NUM(x)		((x) << 8)
353 #define DISP0_PPS_SCALE_EN_PREHSC_FLT_NUM_MASK		GENMASK(15, 12)
354 #define DISP0_PPS_SCALE_EN_PREHSC_FLT_NUM(x)		((x) << 12)
355 #define DISP0_PPS_SCALE_EN_PREVSC_RATE_MASK		GENMASK(17, 16)
356 #define DISP0_PPS_SCALE_EN_PREVSC_RATE(x)		((x) << 16)
357 #define DISP0_PPS_SCALE_EN_PREHSC_RATE_MASK		GENMASK(19, 18)
358 #define DISP0_PPS_SCALE_EN_PREHSC_RATE(x)		((x) << 18)
359 #define DISP0_PPS_SCALE_EN_HSC_EN_MASK			BIT(20)
360 #define DISP0_PPS_SCALE_EN_HSC_EN(x)			((x) << 20)
361 #define DISP0_PPS_SCALE_EN_HSC_DIS			(0 << 20)
362 #define DISP0_PPS_SCALE_EN_VSC_EN_MASK			BIT(21)
363 #define DISP0_PPS_SCALE_EN_VSC_EN(x)			((x) << 21)
364 #define DISP0_PPS_SCALE_EN_VSC_DIS			(0 << 21)
365 #define DISP0_PPS_SCALE_EN_PREVSC_EN_MASK		BIT(22)
366 #define DISP0_PPS_SCALE_EN_PREVSC_EN(x)			((x) << 22)
367 #define DISP0_PPS_SCALE_EN_PREVSC_DIS			(0 << 22)
368 #define DISP0_PPS_SCALE_EN_PREHSC_EN_MASK		BIT(23)
369 #define DISP0_PPS_SCALE_EN_PREHSC_EN(x)			((x) << 23)
370 #define DISP0_PPS_SCALE_EN_PREHSC_DIS			(0 << 23)
371 #define DISP0_PPS_SCALE_EN_HSC_NOR_RS_BITS_MASK		GENMASK(27, 24)
372 #define DISP0_PPS_SCALE_EN_HSC_NOR_RS_BITS(x)		((x) << 24)
373 #define DISP0_PPS_SCALE_EN_VSC_NOR_RS_BITS_MASK		GENMASK(31, 28)
374 #define DISP0_PPS_SCALE_EN_VSC_NOR_RS_BITS(x)		((x) << 28)
375 
376 #define DISP0_PPS_VSC_START_PHASE_STEP			0x8224
377 #define DISP0_PPS_VSC_START_PHASE_STEP_VERT_FRAC_MASK	GENMASK(23, 0)
378 #define DISP0_PPS_VSC_START_PHASE_STEP_VERT_FRAC(x)	((x) << 0)
379 #define DISP0_PPS_VSC_START_PHASE_STEP_VERT_INTE_MASK	GENMASK(27, 24)
380 #define DISP0_PPS_VSC_START_PHASE_STEP_VERT_INTE(x)	((x) << 24)
381 
382 #define DISP0_PPS_HSC_START_PHASE_STEP			0x8230
383 #define DISP0_PPS_HSC_START_PHASE_STEP_HORIZ_FRAC_MASK	GENMASK(23, 0)
384 #define DISP0_PPS_HSC_START_PHASE_STEP_HORIZ_FRAC(x)	((x) << 0)
385 #define DISP0_PPS_HSC_START_PHASE_STEP_HORIZ_INTE_MASK	GENMASK(27, 24)
386 #define DISP0_PPS_HSC_START_PHASE_STEP_HORIZ_INTE(x)	((x) << 24)
387 
388 #define DISP0_PPS_444TO422				0x823c
389 #define DISP0_PPS_444TO422_EN_MASK			BIT(0)
390 #define DISP0_PPS_444TO422_EN(x)			((x) << 0)
391 
392 #define ISP_SCALE0_COEF_IDX_LUMA			0x8240
393 #define ISP_SCALE0_COEF_IDX_LUMA_COEF_S11_MODE_MASK	BIT(9)
394 #define ISP_SCALE0_COEF_IDX_LUMA_COEF_S11_MODE_EN	BIT(9)
395 #define ISP_SCALE0_COEF_IDX_LUMA_COEF_S11_MODE_DIS	(0 << 9)
396 #define ISP_SCALE0_COEF_IDX_LUMA_CTYPE_MASK		GENMASK(12, 10)
397 #define ISP_SCALE0_COEF_IDX_LUMA_CTYPE(x)		((x) << 10)
398 
399 #define ISP_SCALE0_COEF_LUMA				0x8244
400 #define ISP_SCALE0_COEF_LUMA_DATA1(x)		(((x) & GENMASK(10, 0)) << 0)
401 #define ISP_SCALE0_COEF_LUMA_DATA0(x)		(((x) & GENMASK(10, 0)) << 16)
402 
403 #define ISP_SCALE0_COEF_IDX_CHRO			0x8248
404 #define ISP_SCALE0_COEF_IDX_CHRO_COEF_S11_MODE_MASK	BIT(9)
405 #define ISP_SCALE0_COEF_IDX_CHRO_COEF_S11_MODE_EN	BIT(9)
406 #define ISP_SCALE0_COEF_IDX_CHRO_COEF_S11_MODE_DIS	(0 << 9)
407 #define ISP_SCALE0_COEF_IDX_CHRO_CTYPE_MASK		GENMASK(12, 10)
408 #define ISP_SCALE0_COEF_IDX_CHRO_CTYPE(x)		((x) << 10)
409 
410 #define ISP_SCALE0_COEF_CHRO				0x824c
411 #define ISP_SCALE0_COEF_CHRO_DATA1(x)		(((x) & GENMASK(10, 0)) << 0)
412 #define ISP_SCALE0_COEF_CHRO_DATA0(x)		(((x) & GENMASK(10, 0)) << 16)
413 
414 #define ISP_AF_CTRL					0xa044
415 #define ISP_AF_CTRL_VERT_OFST_MASK			GENMASK(15, 14)
416 #define ISP_AF_CTRL_VERT_OFST(x)			((x) << 14)
417 #define ISP_AF_CTRL_HORIZ_OFST_MASK			GENMASK(17, 16)
418 #define ISP_AF_CTRL_HORIZ_OFST(x)			((x) << 16)
419 
420 #define ISP_AF_HV_SIZE					0xa04c
421 #define ISP_AF_HV_SIZE_GLB_WIN_YSIZE_MASK		GENMASK(15, 0)
422 #define ISP_AF_HV_SIZE_GLB_WIN_YSIZE(x)			((x) << 0)
423 #define ISP_AF_HV_SIZE_GLB_WIN_XSIZE_MASK		GENMASK(31, 16)
424 #define ISP_AF_HV_SIZE_GLB_WIN_XSIZE(x)			((x) << 16)
425 
426 #define ISP_AF_HV_BLKNUM				0xa050
427 #define ISP_AF_HV_BLKNUM_V_NUM_MASK			GENMASK(5, 0)
428 #define ISP_AF_HV_BLKNUM_V_NUM(x)			((x) << 0)
429 #define ISP_AF_HV_BLKNUM_H_NUM_MASK			GENMASK(21, 16)
430 #define ISP_AF_HV_BLKNUM_H_NUM(x)			((x) << 16)
431 
432 #define ISP_AF_EN_CTRL					0xa054
433 #define ISP_AF_EN_CTRL_STAT_SEL_MASK			BIT(21)
434 #define ISP_AF_EN_CTRL_STAT_SEL_OLD			(0 << 21)
435 #define ISP_AF_EN_CTRL_STAT_SEL_NEW			BIT(21)
436 
437 #define ISP_AF_IDX_ADDR					0xa1c0
438 #define ISP_AF_IDX_DATA					0xa1c4
439 #define ISP_AF_IDX_DATA_VIDX_DATA(x)		(((x) & GENMASK(15, 0)) << 0)
440 #define ISP_AF_IDX_DATA_HIDX_DATA(x)		(((x) & GENMASK(15, 0)) << 16)
441 
442 #define ISP_AE_CTRL					0xa448
443 #define ISP_AE_CTRL_INPUT_2LINE_MASK			BIT(7)
444 #define ISP_AE_CTRL_INPUT_2LINE_EN			BIT(7)
445 #define ISP_AE_CTRL_INPUT_2LINE_DIS			(0 << 7)
446 #define ISP_AE_CTRL_LUMA_MODE_MASK			GENMASK(9, 8)
447 #define ISP_AE_CTRL_LUMA_MODE_CUR			(0 << 8)
448 #define ISP_AE_CTRL_LUMA_MODE_MAX			BIT(8)
449 #define ISP_AE_CTRL_LUMA_MODE_FILTER			(2 << 8)
450 #define ISP_AE_CTRL_VERT_OFST_MASK			GENMASK(25, 24)
451 #define ISP_AE_CTRL_VERT_OFST(x)			((x) << 24)
452 #define ISP_AE_CTRL_HORIZ_OFST_MASK			GENMASK(27, 26)
453 #define ISP_AE_CTRL_HORIZ_OFST(x)			((x) << 26)
454 
455 #define ISP_AE_HV_SIZE					0xa464
456 #define ISP_AE_HV_SIZE_VERT_SIZE_MASK			GENMASK(15, 0)
457 #define ISP_AE_HV_SIZE_VERT_SIZE(x)			((x) << 0)
458 #define ISP_AE_HV_SIZE_HORIZ_SIZE_MASK			GENMASK(31, 16)
459 #define ISP_AE_HV_SIZE_HORIZ_SIZE(x)			((x) << 16)
460 
461 #define ISP_AE_HV_BLKNUM				0xa468
462 #define ISP_AE_HV_BLKNUM_V_NUM_MASK			GENMASK(6, 0)
463 #define ISP_AE_HV_BLKNUM_V_NUM(x)			((x) << 0)
464 #define ISP_AE_HV_BLKNUM_H_NUM_MASK			GENMASK(22, 16)
465 #define ISP_AE_HV_BLKNUM_H_NUM(x)			((x) << 16)
466 
467 #define ISP_AE_IDX_ADDR					0xa600
468 #define ISP_AE_IDX_DATA					0xa604
469 #define ISP_AE_IDX_DATA_VIDX_DATA(x)		(((x) & GENMASK(15, 0)) << 0)
470 #define ISP_AE_IDX_DATA_HIDX_DATA(x)		(((x) & GENMASK(15, 0)) << 16)
471 
472 #define ISP_AE_BLK_WT_ADDR				0xa608
473 #define ISP_AE_BLK_WT_DATA				0xa60c
474 #define ISP_AE_BLK_WT_DATA_WT(i, x)	(((x) & GENMASK(3, 0)) << ((i) * 4))
475 
476 #define ISP_AWB_CTRL					0xa834
477 #define ISP_AWB_CTRL_VERT_OFST_MASK			GENMASK(1, 0)
478 #define ISP_AWB_CTRL_VERT_OFST(x)			((x) << 0)
479 #define ISP_AWB_CTRL_HORIZ_OFST_MASK			GENMASK(3, 2)
480 #define ISP_AWB_CTRL_HORIZ_OFST(x)			((x) << 2)
481 
482 #define ISP_AWB_HV_SIZE					0xa83c
483 #define ISP_AWB_HV_SIZE_VERT_SIZE_MASK			GENMASK(15, 0)
484 #define ISP_AWB_HV_SIZE_VERT_SIZE(x)			((x) << 0)
485 #define ISP_AWB_HV_SIZE_HORIZ_SIZE_MASK			GENMASK(31, 16)
486 #define ISP_AWB_HV_SIZE_HORIZ_SIZE(x)			((x) << 16)
487 
488 #define ISP_AWB_HV_BLKNUM				0xa840
489 #define ISP_AWB_HV_BLKNUM_V_NUM_MASK			GENMASK(5, 0)
490 #define ISP_AWB_HV_BLKNUM_V_NUM(x)			((x) << 0)
491 #define ISP_AWB_HV_BLKNUM_H_NUM_MASK			GENMASK(21, 16)
492 #define ISP_AWB_HV_BLKNUM_H_NUM(x)			((x) << 16)
493 
494 #define ISP_AWB_STAT_RG					0xa848
495 #define ISP_AWB_STAT_RG_MIN_VALUE_MASK			GENMASK(11, 0)
496 #define ISP_AWB_STAT_RG_MIN_VALUE(x)			((x) << 0)
497 #define ISP_AWB_STAT_RG_MAX_VALUE_MASK			GENMASK(27, 16)
498 #define ISP_AWB_STAT_RG_MAX_VALUE(x)			((x) << 16)
499 
500 #define ISP_AWB_STAT_BG					0xa84c
501 #define ISP_AWB_STAT_BG_MIN_VALUE_MASK			GENMASK(11, 0)
502 #define ISP_AWB_STAT_BG_MIN_VALUE(x)			((x) << 0)
503 #define ISP_AWB_STAT_BG_MAX_VALUE_MASK			GENMASK(27, 16)
504 #define ISP_AWB_STAT_BG_MAX_VALUE(x)			((x) << 16)
505 
506 #define ISP_AWB_STAT_RG_HL				0xa850
507 #define ISP_AWB_STAT_RG_HL_LOW_VALUE_MASK		GENMASK(11, 0)
508 #define ISP_AWB_STAT_RG_HL_LOW_VALUE(x)			((x) << 0)
509 #define ISP_AWB_STAT_RG_HL_HIGH_VALUE_MASK		GENMASK(27, 16)
510 #define ISP_AWB_STAT_RG_HL_HIGH_VALUE(x)		((x) << 16)
511 
512 #define ISP_AWB_STAT_BG_HL				0xa854
513 #define ISP_AWB_STAT_BG_HL_LOW_VALUE_MASK		GENMASK(11, 0)
514 #define ISP_AWB_STAT_BG_HL_LOW_VALUE(x)			((x) << 0)
515 #define ISP_AWB_STAT_BG_HL_HIGH_VALUE_MASK		GENMASK(27, 16)
516 #define ISP_AWB_STAT_BG_HL_HIGH_VALUE(x)		((x) << 16)
517 
518 #define ISP_AWB_STAT_CTRL2				0xa858
519 #define ISP_AWB_STAT_CTRL2_SATUR_CTRL_MASK		BIT(0)
520 #define ISP_AWB_STAT_CTRL2_SATUR_CTRL(x)		((x) << 0)
521 
522 #define ISP_AWB_IDX_ADDR				0xaa00
523 #define ISP_AWB_IDX_DATA				0xaa04
524 #define ISP_AWB_IDX_DATA_VIDX_DATA(x)		(((x) & GENMASK(15, 0)) << 0)
525 #define ISP_AWB_IDX_DATA_HIDX_DATA(x)		(((x) & GENMASK(15, 0)) << 16)
526 
527 #define ISP_AWB_BLK_WT_ADDR				0xaa08
528 #define ISP_AWB_BLK_WT_DATA				0xaa0c
529 #define ISP_AWB_BLK_WT_DATA_WT(i, x)	(((x) & GENMASK(3, 0)) << ((i) * 4))
530 
531 #define ISP_WRMIFX3_0_CH0_CTRL0				0xc400
532 #define ISP_WRMIFX3_0_CH0_CTRL0_STRIDE_MASK		GENMASK(28, 16)
533 #define ISP_WRMIFX3_0_CH0_CTRL0_STRIDE(x)		((x) << 16)
534 
535 #define ISP_WRMIFX3_0_CH0_CTRL1				0xc404
536 #define ISP_WRMIFX3_0_CH0_CTRL1_PIX_BITS_MODE_MASK	GENMASK(30, 27)
537 #define ISP_WRMIFX3_0_CH0_CTRL1_PIX_BITS_8BITS		BIT(27)
538 #define ISP_WRMIFX3_0_CH0_CTRL1_PIX_BITS_16BITS		(2 << 27)
539 
540 #define ISP_WRMIFX3_0_CH1_CTRL0				0xc408
541 #define ISP_WRMIFX3_0_CH1_CTRL0_STRIDE_MASK		GENMASK(28, 16)
542 #define ISP_WRMIFX3_0_CH1_CTRL0_STRIDE(x)		((x) << 16)
543 
544 #define ISP_WRMIFX3_0_CH1_CTRL1				0xc40c
545 #define ISP_WRMIFX3_0_CH1_CTRL1_PIX_BITS_MODE_MASK	GENMASK(30, 27)
546 #define ISP_WRMIFX3_0_CH1_CTRL1_PIX_BITS_8BITS		BIT(27)
547 #define ISP_WRMIFX3_0_CH1_CTRL1_PIX_BITS_16BITS		(2 << 27)
548 #define ISP_WRMIFX3_0_CH1_CTRL1_PIX_BITS_32BITS		(3 << 27)
549 
550 #define ISP_WRMIFX3_0_WIN_LUMA_H			0xc420
551 #define ISP_WRMIFX3_0_WIN_LUMA_H_LUMA_HEND_MASK		GENMASK(28, 16)
552 #define ISP_WRMIFX3_0_WIN_LUMA_H_LUMA_HEND(x)		(((x) - 1) << 16)
553 
554 #define ISP_WRMIFX3_0_WIN_LUMA_V			0xc424
555 #define ISP_WRMIFX3_0_WIN_LUMA_V_LUMA_VEND_MASK		GENMASK(28, 16)
556 #define ISP_WRMIFX3_0_WIN_LUMA_V_LUMA_VEND(x)		(((x) - 1) << 16)
557 
558 #define ISP_WRMIFX3_0_WIN_CHROM_H			0xc428
559 #define ISP_WRMIFX3_0_WIN_CHROM_H_CHROM_HEND_MASK	GENMASK(28, 16)
560 #define ISP_WRMIFX3_0_WIN_CHROM_H_CHROM_HEND(x)		(((x) - 1) << 16)
561 
562 #define ISP_WRMIFX3_0_WIN_CHROM_V			0xc42c
563 #define ISP_WRMIFX3_0_WIN_CHROM_V_CHROM_VEND_MASK	GENMASK(28, 16)
564 #define ISP_WRMIFX3_0_WIN_CHROM_V_CHROM_VEND(x)		(((x) - 1) << 16)
565 
566 #define ISP_WRMIFX3_0_CH0_BADDR				0xc440
567 #define ISP_WRMIFX3_0_CH0_BASE_ADDR(x)			((x) >> 4)
568 
569 #define ISP_WRMIFX3_0_CH1_BADDR				0xc444
570 #define ISP_WRMIFX3_0_CH1_BASE_ADDR(x)			((x) >> 4)
571 
572 #define ISP_WRMIFX3_0_FMT_SIZE				0xc464
573 #define ISP_WRMIFX3_0_FMT_SIZE_HSIZE_MASK		GENMASK(15, 0)
574 #define ISP_WRMIFX3_0_FMT_SIZE_HSIZE(x)			((x) << 0)
575 #define ISP_WRMIFX3_0_FMT_SIZE_VSIZE_MASK		GENMASK(31, 16)
576 #define ISP_WRMIFX3_0_FMT_SIZE_VSIZE(x)			((x) << 16)
577 
578 #define ISP_WRMIFX3_0_FMT_CTRL				0xc468
579 #define ISP_WRMIFX3_0_FMT_CTRL_MTX_IBITS_MASK		GENMASK(1, 0)
580 #define ISP_WRMIFX3_0_FMT_CTRL_MTX_IBITS_8BIT		(0 << 0)
581 #define ISP_WRMIFX3_0_FMT_CTRL_MTX_IBITS_10BIT		BIT(0)
582 #define ISP_WRMIFX3_0_FMT_CTRL_MTX_IBITS_12BIT		(2 << 0)
583 #define ISP_WRMIFX3_0_FMT_CTRL_MTX_IBITS_16BIT		(3 << 0)
584 #define ISP_WRMIFX3_0_FMT_CTRL_MTX_UV_SWAP_MASK		BIT(2)
585 #define ISP_WRMIFX3_0_FMT_CTRL_MTX_UV_SWAP_VU		(0 << 2)
586 #define ISP_WRMIFX3_0_FMT_CTRL_MTX_UV_SWAP_UV		BIT(2)
587 #define ISP_WRMIFX3_0_FMT_CTRL_MTX_PLANE_MASK		GENMASK(5, 4)
588 #define ISP_WRMIFX3_0_FMT_CTRL_MTX_PLANE_X1		(0 << 4)
589 #define ISP_WRMIFX3_0_FMT_CTRL_MTX_PLANE_X2		BIT(4)
590 #define ISP_WRMIFX3_0_FMT_CTRL_MODE_OUT_MASK		GENMASK(18, 16)
591 #define ISP_WRMIFX3_0_FMT_CTRL_MODE_OUT_YUV422		BIT(16)
592 #define ISP_WRMIFX3_0_FMT_CTRL_MODE_OUT_YUV420		(2 << 16)
593 #define ISP_WRMIFX3_0_FMT_CTRL_MODE_OUT_Y_ONLY		(3 << 16)
594 #define ISP_WRMIFX3_0_FMT_CTRL_MODE_OUT_RAW		(4 << 16)
595 
596 #define VIU_DMAWR_BADDR0				0xc840
597 #define VIU_DMAWR_BADDR0_AF_STATS_BASE_ADDR_MASK	GENMASK(27, 0)
598 #define VIU_DMAWR_BADDR0_AF_STATS_BASE_ADDR(x)		((x) >> 4)
599 
600 #define VIU_DMAWR_BADDR1				0xc844
601 #define VIU_DMAWR_BADDR1_AWB_STATS_BASE_ADDR_MASK	GENMASK(27, 0)
602 #define VIU_DMAWR_BADDR1_AWB_STATS_BASE_ADDR(x)		((x) >> 4)
603 
604 #define VIU_DMAWR_BADDR2				0xc848
605 #define VIU_DMAWR_BADDR2_AE_STATS_BASE_ADDR_MASK	GENMASK(27, 0)
606 #define VIU_DMAWR_BADDR2_AE_STATS_BASE_ADDR(x)		((x) >> 4)
607 
608 #define VIU_DMAWR_SIZE0					0xc854
609 #define VIU_DMAWR_SIZE0_AF_STATS_SIZE_MASK		GENMASK(15, 0)
610 #define VIU_DMAWR_SIZE0_AF_STATS_SIZE(x)		((x) << 0)
611 #define VIU_DMAWR_SIZE0_AWB_STATS_SIZE_MASK		GENMASK(31, 16)
612 #define VIU_DMAWR_SIZE0_AWB_STATS_SIZE(x)		((x) << 16)
613 
614 #define VIU_DMAWR_SIZE1					0xc858
615 #define VIU_DMAWR_SIZE1_AE_STATS_SIZE_MASK		GENMASK(15, 0)
616 #define VIU_DMAWR_SIZE1_AE_STATS_SIZE(x)		((x) << 0)
617 
618 #endif
619