1 /* 2 * Copyright (C) 2015 VanguardiaSur - www.vanguardiasur.com.ar 3 * 4 * Based on original driver by Krzysztof Ha?asa: 5 * Copyright (C) 2015 Industrial Research Institute for Automation 6 * and Measurements PIAP 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of version 2 of the GNU General Public License 10 * as published by the Free Software Foundation. 11 * 12 * Notes 13 * ----- 14 * 15 * 1. Under stress-testing, it has been observed that the PCIe link 16 * goes down, without reason. Therefore, the driver takes special care 17 * to allow device hot-unplugging. 18 * 19 * 2. TW686X devices are capable of setting a few different DMA modes, 20 * including: scatter-gather, field and frame modes. However, 21 * under stress testings it has been found that the machine can 22 * freeze completely if DMA registers are programmed while streaming 23 * is active. 24 * This driver tries to access hardware registers as infrequently 25 * as possible by: 26 * i. allocating fixed DMA buffers and memcpy'ing into 27 * vmalloc'ed buffers 28 * ii. using a timer to mitigate the rate of DMA reset operations, 29 * on DMA channels error. 30 */ 31 32 #include <linux/init.h> 33 #include <linux/interrupt.h> 34 #include <linux/delay.h> 35 #include <linux/kernel.h> 36 #include <linux/module.h> 37 #include <linux/pci_ids.h> 38 #include <linux/slab.h> 39 #include <linux/timer.h> 40 41 #include "tw686x.h" 42 #include "tw686x-regs.h" 43 44 /* 45 * This module parameter allows to control the DMA_TIMER_INTERVAL value. 46 * The DMA_TIMER_INTERVAL register controls the minimum DMA interrupt 47 * time span (iow, the maximum DMA interrupt rate) thus allowing for 48 * IRQ coalescing. 49 * 50 * The chip datasheet does not mention a time unit for this value, so 51 * users wanting fine-grain control over the interrupt rate should 52 * determine the desired value through testing. 53 */ 54 static u32 dma_interval = 0x00098968; 55 module_param(dma_interval, int, 0444); 56 MODULE_PARM_DESC(dma_interval, "Minimum time span for DMA interrupting host"); 57 58 void tw686x_disable_channel(struct tw686x_dev *dev, unsigned int channel) 59 { 60 u32 dma_en = reg_read(dev, DMA_CHANNEL_ENABLE); 61 u32 dma_cmd = reg_read(dev, DMA_CMD); 62 63 dma_en &= ~BIT(channel); 64 dma_cmd &= ~BIT(channel); 65 66 /* Must remove it from pending too */ 67 dev->pending_dma_en &= ~BIT(channel); 68 dev->pending_dma_cmd &= ~BIT(channel); 69 70 /* Stop DMA if no channels are enabled */ 71 if (!dma_en) 72 dma_cmd = 0; 73 reg_write(dev, DMA_CHANNEL_ENABLE, dma_en); 74 reg_write(dev, DMA_CMD, dma_cmd); 75 } 76 77 void tw686x_enable_channel(struct tw686x_dev *dev, unsigned int channel) 78 { 79 u32 dma_en = reg_read(dev, DMA_CHANNEL_ENABLE); 80 u32 dma_cmd = reg_read(dev, DMA_CMD); 81 82 dev->pending_dma_en |= dma_en | BIT(channel); 83 dev->pending_dma_cmd |= dma_cmd | DMA_CMD_ENABLE | BIT(channel); 84 } 85 86 /* 87 * The purpose of this awful hack is to avoid enabling the DMA 88 * channels "too fast" which makes some TW686x devices very 89 * angry and freeze the CPU (see note 1). 90 */ 91 static void tw686x_dma_delay(unsigned long data) 92 { 93 struct tw686x_dev *dev = (struct tw686x_dev *)data; 94 unsigned long flags; 95 96 spin_lock_irqsave(&dev->lock, flags); 97 98 reg_write(dev, DMA_CHANNEL_ENABLE, dev->pending_dma_en); 99 reg_write(dev, DMA_CMD, dev->pending_dma_cmd); 100 dev->pending_dma_en = 0; 101 dev->pending_dma_cmd = 0; 102 103 spin_unlock_irqrestore(&dev->lock, flags); 104 } 105 106 static void tw686x_reset_channels(struct tw686x_dev *dev, unsigned int ch_mask) 107 { 108 u32 dma_en, dma_cmd; 109 110 dma_en = reg_read(dev, DMA_CHANNEL_ENABLE); 111 dma_cmd = reg_read(dev, DMA_CMD); 112 113 /* 114 * Save pending register status, the timer will 115 * restore them. 116 */ 117 dev->pending_dma_en |= dma_en; 118 dev->pending_dma_cmd |= dma_cmd; 119 120 /* Disable the reset channels */ 121 reg_write(dev, DMA_CHANNEL_ENABLE, dma_en & ~ch_mask); 122 123 if ((dma_en & ~ch_mask) == 0) { 124 dev_dbg(&dev->pci_dev->dev, "reset: stopping DMA\n"); 125 dma_cmd &= ~DMA_CMD_ENABLE; 126 } 127 reg_write(dev, DMA_CMD, dma_cmd & ~ch_mask); 128 } 129 130 static irqreturn_t tw686x_irq(int irq, void *dev_id) 131 { 132 struct tw686x_dev *dev = (struct tw686x_dev *)dev_id; 133 unsigned int video_requests, audio_requests, reset_ch; 134 u32 fifo_status, fifo_signal, fifo_ov, fifo_bad, fifo_errors; 135 u32 int_status, dma_en, video_en, pb_status; 136 unsigned long flags; 137 138 int_status = reg_read(dev, INT_STATUS); /* cleared on read */ 139 fifo_status = reg_read(dev, VIDEO_FIFO_STATUS); 140 141 /* INT_STATUS does not include FIFO_STATUS errors! */ 142 if (!int_status && !TW686X_FIFO_ERROR(fifo_status)) 143 return IRQ_NONE; 144 145 if (int_status & INT_STATUS_DMA_TOUT) { 146 dev_dbg(&dev->pci_dev->dev, 147 "DMA timeout. Resetting DMA for all channels\n"); 148 reset_ch = ~0; 149 goto reset_channels; 150 } 151 152 spin_lock_irqsave(&dev->lock, flags); 153 dma_en = reg_read(dev, DMA_CHANNEL_ENABLE); 154 spin_unlock_irqrestore(&dev->lock, flags); 155 156 video_en = dma_en & 0xff; 157 fifo_signal = ~(fifo_status & 0xff) & video_en; 158 fifo_ov = fifo_status >> 24; 159 fifo_bad = fifo_status >> 16; 160 161 /* Mask of channels with signal and FIFO errors */ 162 fifo_errors = fifo_signal & (fifo_ov | fifo_bad); 163 164 reset_ch = 0; 165 pb_status = reg_read(dev, PB_STATUS); 166 167 /* Coalesce video frame/error events */ 168 video_requests = (int_status & video_en) | fifo_errors; 169 audio_requests = (int_status & dma_en) >> 8; 170 171 if (video_requests) 172 tw686x_video_irq(dev, video_requests, pb_status, 173 fifo_status, &reset_ch); 174 if (audio_requests) 175 tw686x_audio_irq(dev, audio_requests, pb_status); 176 177 reset_channels: 178 if (reset_ch) { 179 spin_lock_irqsave(&dev->lock, flags); 180 tw686x_reset_channels(dev, reset_ch); 181 spin_unlock_irqrestore(&dev->lock, flags); 182 mod_timer(&dev->dma_delay_timer, 183 jiffies + msecs_to_jiffies(100)); 184 } 185 186 return IRQ_HANDLED; 187 } 188 189 static void tw686x_dev_release(struct v4l2_device *v4l2_dev) 190 { 191 struct tw686x_dev *dev = container_of(v4l2_dev, struct tw686x_dev, 192 v4l2_dev); 193 unsigned int ch; 194 195 for (ch = 0; ch < max_channels(dev); ch++) 196 v4l2_ctrl_handler_free(&dev->video_channels[ch].ctrl_handler); 197 198 v4l2_device_unregister(&dev->v4l2_dev); 199 200 kfree(dev->audio_channels); 201 kfree(dev->video_channels); 202 kfree(dev); 203 } 204 205 static int tw686x_probe(struct pci_dev *pci_dev, 206 const struct pci_device_id *pci_id) 207 { 208 struct tw686x_dev *dev; 209 int err; 210 211 dev = kzalloc(sizeof(*dev), GFP_KERNEL); 212 if (!dev) 213 return -ENOMEM; 214 dev->type = pci_id->driver_data; 215 sprintf(dev->name, "tw%04X", pci_dev->device); 216 217 dev->video_channels = kcalloc(max_channels(dev), 218 sizeof(*dev->video_channels), GFP_KERNEL); 219 if (!dev->video_channels) { 220 err = -ENOMEM; 221 goto free_dev; 222 } 223 224 dev->audio_channels = kcalloc(max_channels(dev), 225 sizeof(*dev->audio_channels), GFP_KERNEL); 226 if (!dev->audio_channels) { 227 err = -ENOMEM; 228 goto free_video; 229 } 230 231 pr_info("%s: PCI %s, IRQ %d, MMIO 0x%lx\n", dev->name, 232 pci_name(pci_dev), pci_dev->irq, 233 (unsigned long)pci_resource_start(pci_dev, 0)); 234 235 dev->pci_dev = pci_dev; 236 if (pci_enable_device(pci_dev)) { 237 err = -EIO; 238 goto free_audio; 239 } 240 241 pci_set_master(pci_dev); 242 err = pci_set_dma_mask(pci_dev, DMA_BIT_MASK(32)); 243 if (err) { 244 dev_err(&pci_dev->dev, "32-bit PCI DMA not supported\n"); 245 err = -EIO; 246 goto disable_pci; 247 } 248 249 err = pci_request_regions(pci_dev, dev->name); 250 if (err) { 251 dev_err(&pci_dev->dev, "unable to request PCI region\n"); 252 goto disable_pci; 253 } 254 255 dev->mmio = pci_ioremap_bar(pci_dev, 0); 256 if (!dev->mmio) { 257 dev_err(&pci_dev->dev, "unable to remap PCI region\n"); 258 err = -ENOMEM; 259 goto free_region; 260 } 261 262 /* Reset all subsystems */ 263 reg_write(dev, SYS_SOFT_RST, 0x0f); 264 mdelay(1); 265 266 reg_write(dev, SRST[0], 0x3f); 267 if (max_channels(dev) > 4) 268 reg_write(dev, SRST[1], 0x3f); 269 270 /* Disable the DMA engine */ 271 reg_write(dev, DMA_CMD, 0); 272 reg_write(dev, DMA_CHANNEL_ENABLE, 0); 273 274 /* Enable DMA FIFO overflow and pointer check */ 275 reg_write(dev, DMA_CONFIG, 0xffffff04); 276 reg_write(dev, DMA_CHANNEL_TIMEOUT, 0x140c8584); 277 reg_write(dev, DMA_TIMER_INTERVAL, dma_interval); 278 279 spin_lock_init(&dev->lock); 280 281 err = request_irq(pci_dev->irq, tw686x_irq, IRQF_SHARED, 282 dev->name, dev); 283 if (err < 0) { 284 dev_err(&pci_dev->dev, "unable to request interrupt\n"); 285 goto iounmap; 286 } 287 288 setup_timer(&dev->dma_delay_timer, 289 tw686x_dma_delay, (unsigned long) dev); 290 291 /* 292 * This must be set right before initializing v4l2_dev. 293 * It's used to release resources after the last handle 294 * held is released. 295 */ 296 dev->v4l2_dev.release = tw686x_dev_release; 297 err = tw686x_video_init(dev); 298 if (err) { 299 dev_err(&pci_dev->dev, "can't register video\n"); 300 goto free_irq; 301 } 302 303 err = tw686x_audio_init(dev); 304 if (err) 305 dev_warn(&pci_dev->dev, "can't register audio\n"); 306 307 pci_set_drvdata(pci_dev, dev); 308 return 0; 309 310 free_irq: 311 free_irq(pci_dev->irq, dev); 312 iounmap: 313 pci_iounmap(pci_dev, dev->mmio); 314 free_region: 315 pci_release_regions(pci_dev); 316 disable_pci: 317 pci_disable_device(pci_dev); 318 free_audio: 319 kfree(dev->audio_channels); 320 free_video: 321 kfree(dev->video_channels); 322 free_dev: 323 kfree(dev); 324 return err; 325 } 326 327 static void tw686x_remove(struct pci_dev *pci_dev) 328 { 329 struct tw686x_dev *dev = pci_get_drvdata(pci_dev); 330 unsigned long flags; 331 332 /* This guarantees the IRQ handler is no longer running, 333 * which means we can kiss good-bye some resources. 334 */ 335 free_irq(pci_dev->irq, dev); 336 337 tw686x_video_free(dev); 338 tw686x_audio_free(dev); 339 del_timer_sync(&dev->dma_delay_timer); 340 341 pci_iounmap(pci_dev, dev->mmio); 342 pci_release_regions(pci_dev); 343 pci_disable_device(pci_dev); 344 345 /* 346 * Setting pci_dev to NULL allows to detect hardware is no longer 347 * available and will be used by vb2_ops. This is required because 348 * the device sometimes hot-unplugs itself as the result of a PCIe 349 * link down. 350 * The lock is really important here. 351 */ 352 spin_lock_irqsave(&dev->lock, flags); 353 dev->pci_dev = NULL; 354 spin_unlock_irqrestore(&dev->lock, flags); 355 356 /* 357 * This calls tw686x_dev_release if it's the last reference. 358 * Otherwise, release is postponed until there are no users left. 359 */ 360 v4l2_device_put(&dev->v4l2_dev); 361 } 362 363 /* 364 * On TW6864 and TW6868, all channels share the pair of video DMA SG tables, 365 * with 10-bit start_idx and end_idx determining start and end of frame buffer 366 * for particular channel. 367 * TW6868 with all its 8 channels would be problematic (only 127 SG entries per 368 * channel) but we support only 4 channels on this chip anyway (the first 369 * 4 channels are driven with internal video decoder, the other 4 would require 370 * an external TW286x part). 371 * 372 * On TW6865 and TW6869, each channel has its own DMA SG table, with indexes 373 * starting with 0. Both chips have complete sets of internal video decoders 374 * (respectively 4 or 8-channel). 375 * 376 * All chips have separate SG tables for two video frames. 377 */ 378 379 /* driver_data is number of A/V channels */ 380 static const struct pci_device_id tw686x_pci_tbl[] = { 381 { 382 PCI_DEVICE(PCI_VENDOR_ID_TECHWELL, 0x6864), 383 .driver_data = 4 384 }, 385 { 386 PCI_DEVICE(PCI_VENDOR_ID_TECHWELL, 0x6865), /* not tested */ 387 .driver_data = 4 | TYPE_SECOND_GEN 388 }, 389 /* 390 * TW6868 supports 8 A/V channels with an external TW2865 chip; 391 * not supported by the driver. 392 */ 393 { 394 PCI_DEVICE(PCI_VENDOR_ID_TECHWELL, 0x6868), /* not tested */ 395 .driver_data = 4 396 }, 397 { 398 PCI_DEVICE(PCI_VENDOR_ID_TECHWELL, 0x6869), 399 .driver_data = 8 | TYPE_SECOND_GEN}, 400 {} 401 }; 402 MODULE_DEVICE_TABLE(pci, tw686x_pci_tbl); 403 404 static struct pci_driver tw686x_pci_driver = { 405 .name = "tw686x", 406 .id_table = tw686x_pci_tbl, 407 .probe = tw686x_probe, 408 .remove = tw686x_remove, 409 }; 410 module_pci_driver(tw686x_pci_driver); 411 412 MODULE_DESCRIPTION("Driver for video frame grabber cards based on Intersil/Techwell TW686[4589]"); 413 MODULE_AUTHOR("Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>"); 414 MODULE_AUTHOR("Krzysztof Ha?asa <khalasa@piap.pl>"); 415 MODULE_LICENSE("GPL v2"); 416