1 /* 2 * 3 * device driver for philips saa7134 based TV cards 4 * video4linux video interface 5 * 6 * (c) 2001,02 Gerd Knorr <kraxel@bytesex.org> [SuSE Labs] 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #include "saa7134.h" 24 #include "saa7134-reg.h" 25 26 #include <linux/init.h> 27 #include <linux/list.h> 28 #include <linux/module.h> 29 #include <linux/kernel.h> 30 #include <linux/delay.h> 31 32 /* ------------------------------------------------------------------ */ 33 34 static unsigned int ts_debug; 35 module_param(ts_debug, int, 0644); 36 MODULE_PARM_DESC(ts_debug,"enable debug messages [ts]"); 37 38 #define ts_dbg(fmt, arg...) do { \ 39 if (ts_debug) \ 40 printk(KERN_DEBUG pr_fmt("ts: " fmt), ## arg); \ 41 } while (0) 42 43 /* ------------------------------------------------------------------ */ 44 static int buffer_activate(struct saa7134_dev *dev, 45 struct saa7134_buf *buf, 46 struct saa7134_buf *next) 47 { 48 49 ts_dbg("buffer_activate [%p]", buf); 50 buf->top_seen = 0; 51 52 if (!dev->ts_started) 53 dev->ts_field = V4L2_FIELD_TOP; 54 55 if (NULL == next) 56 next = buf; 57 if (V4L2_FIELD_TOP == dev->ts_field) { 58 ts_dbg("- [top] buf=%p next=%p\n", buf, next); 59 saa_writel(SAA7134_RS_BA1(5),saa7134_buffer_base(buf)); 60 saa_writel(SAA7134_RS_BA2(5),saa7134_buffer_base(next)); 61 dev->ts_field = V4L2_FIELD_BOTTOM; 62 } else { 63 ts_dbg("- [bottom] buf=%p next=%p\n", buf, next); 64 saa_writel(SAA7134_RS_BA1(5),saa7134_buffer_base(next)); 65 saa_writel(SAA7134_RS_BA2(5),saa7134_buffer_base(buf)); 66 dev->ts_field = V4L2_FIELD_TOP; 67 } 68 69 /* start DMA */ 70 saa7134_set_dmabits(dev); 71 72 mod_timer(&dev->ts_q.timeout, jiffies+TS_BUFFER_TIMEOUT); 73 74 if (!dev->ts_started) 75 saa7134_ts_start(dev); 76 77 return 0; 78 } 79 80 int saa7134_ts_buffer_init(struct vb2_buffer *vb2) 81 { 82 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb2); 83 struct saa7134_dmaqueue *dmaq = vb2->vb2_queue->drv_priv; 84 struct saa7134_buf *buf = container_of(vbuf, struct saa7134_buf, vb2); 85 86 dmaq->curr = NULL; 87 buf->activate = buffer_activate; 88 89 return 0; 90 } 91 EXPORT_SYMBOL_GPL(saa7134_ts_buffer_init); 92 93 int saa7134_ts_buffer_prepare(struct vb2_buffer *vb2) 94 { 95 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb2); 96 struct saa7134_dmaqueue *dmaq = vb2->vb2_queue->drv_priv; 97 struct saa7134_dev *dev = dmaq->dev; 98 struct saa7134_buf *buf = container_of(vbuf, struct saa7134_buf, vb2); 99 struct sg_table *dma = vb2_dma_sg_plane_desc(vb2, 0); 100 unsigned int lines, llength, size; 101 102 ts_dbg("buffer_prepare [%p]\n", buf); 103 104 llength = TS_PACKET_SIZE; 105 lines = dev->ts.nr_packets; 106 107 size = lines * llength; 108 if (vb2_plane_size(vb2, 0) < size) 109 return -EINVAL; 110 111 vb2_set_plane_payload(vb2, 0, size); 112 vbuf->field = dev->field; 113 114 return saa7134_pgtable_build(dev->pci, &dmaq->pt, dma->sgl, dma->nents, 115 saa7134_buffer_startpage(buf)); 116 } 117 EXPORT_SYMBOL_GPL(saa7134_ts_buffer_prepare); 118 119 int saa7134_ts_queue_setup(struct vb2_queue *q, 120 unsigned int *nbuffers, unsigned int *nplanes, 121 unsigned int sizes[], void *alloc_ctxs[]) 122 { 123 struct saa7134_dmaqueue *dmaq = q->drv_priv; 124 struct saa7134_dev *dev = dmaq->dev; 125 int size = TS_PACKET_SIZE * dev->ts.nr_packets; 126 127 if (0 == *nbuffers) 128 *nbuffers = dev->ts.nr_bufs; 129 *nbuffers = saa7134_buffer_count(size, *nbuffers); 130 if (*nbuffers < 3) 131 *nbuffers = 3; 132 *nplanes = 1; 133 sizes[0] = size; 134 alloc_ctxs[0] = dev->alloc_ctx; 135 return 0; 136 } 137 EXPORT_SYMBOL_GPL(saa7134_ts_queue_setup); 138 139 int saa7134_ts_start_streaming(struct vb2_queue *vq, unsigned int count) 140 { 141 struct saa7134_dmaqueue *dmaq = vq->drv_priv; 142 struct saa7134_dev *dev = dmaq->dev; 143 144 /* 145 * Planar video capture and TS share the same DMA channel, 146 * so only one can be active at a time. 147 */ 148 if (vb2_is_busy(&dev->video_vbq) && dev->fmt->planar) { 149 struct saa7134_buf *buf, *tmp; 150 151 list_for_each_entry_safe(buf, tmp, &dmaq->queue, entry) { 152 list_del(&buf->entry); 153 vb2_buffer_done(&buf->vb2.vb2_buf, 154 VB2_BUF_STATE_QUEUED); 155 } 156 if (dmaq->curr) { 157 vb2_buffer_done(&dmaq->curr->vb2.vb2_buf, 158 VB2_BUF_STATE_QUEUED); 159 dmaq->curr = NULL; 160 } 161 return -EBUSY; 162 } 163 dmaq->seq_nr = 0; 164 return 0; 165 } 166 EXPORT_SYMBOL_GPL(saa7134_ts_start_streaming); 167 168 void saa7134_ts_stop_streaming(struct vb2_queue *vq) 169 { 170 struct saa7134_dmaqueue *dmaq = vq->drv_priv; 171 struct saa7134_dev *dev = dmaq->dev; 172 173 saa7134_ts_stop(dev); 174 saa7134_stop_streaming(dev, dmaq); 175 } 176 EXPORT_SYMBOL_GPL(saa7134_ts_stop_streaming); 177 178 struct vb2_ops saa7134_ts_qops = { 179 .queue_setup = saa7134_ts_queue_setup, 180 .buf_init = saa7134_ts_buffer_init, 181 .buf_prepare = saa7134_ts_buffer_prepare, 182 .buf_queue = saa7134_vb2_buffer_queue, 183 .wait_prepare = vb2_ops_wait_prepare, 184 .wait_finish = vb2_ops_wait_finish, 185 .stop_streaming = saa7134_ts_stop_streaming, 186 }; 187 EXPORT_SYMBOL_GPL(saa7134_ts_qops); 188 189 /* ----------------------------------------------------------- */ 190 /* exported stuff */ 191 192 static unsigned int tsbufs = 8; 193 module_param(tsbufs, int, 0444); 194 MODULE_PARM_DESC(tsbufs, "number of ts buffers for read/write IO, range 2-32"); 195 196 static unsigned int ts_nr_packets = 64; 197 module_param(ts_nr_packets, int, 0444); 198 MODULE_PARM_DESC(ts_nr_packets,"size of a ts buffers (in ts packets)"); 199 200 int saa7134_ts_init_hw(struct saa7134_dev *dev) 201 { 202 /* deactivate TS softreset */ 203 saa_writeb(SAA7134_TS_SERIAL1, 0x00); 204 /* TSSOP high active, TSVAL high active, TSLOCK ignored */ 205 saa_writeb(SAA7134_TS_PARALLEL, 0x6c); 206 saa_writeb(SAA7134_TS_PARALLEL_SERIAL, (TS_PACKET_SIZE-1)); 207 saa_writeb(SAA7134_TS_DMA0, ((dev->ts.nr_packets-1)&0xff)); 208 saa_writeb(SAA7134_TS_DMA1, (((dev->ts.nr_packets-1)>>8)&0xff)); 209 /* TSNOPIT=0, TSCOLAP=0 */ 210 saa_writeb(SAA7134_TS_DMA2, 211 ((((dev->ts.nr_packets-1)>>16)&0x3f) | 0x00)); 212 213 return 0; 214 } 215 216 int saa7134_ts_init1(struct saa7134_dev *dev) 217 { 218 /* sanitycheck insmod options */ 219 if (tsbufs < 2) 220 tsbufs = 2; 221 if (tsbufs > VIDEO_MAX_FRAME) 222 tsbufs = VIDEO_MAX_FRAME; 223 if (ts_nr_packets < 4) 224 ts_nr_packets = 4; 225 if (ts_nr_packets > 312) 226 ts_nr_packets = 312; 227 dev->ts.nr_bufs = tsbufs; 228 dev->ts.nr_packets = ts_nr_packets; 229 230 INIT_LIST_HEAD(&dev->ts_q.queue); 231 init_timer(&dev->ts_q.timeout); 232 dev->ts_q.timeout.function = saa7134_buffer_timeout; 233 dev->ts_q.timeout.data = (unsigned long)(&dev->ts_q); 234 dev->ts_q.dev = dev; 235 dev->ts_q.need_two = 1; 236 dev->ts_started = 0; 237 saa7134_pgtable_alloc(dev->pci, &dev->ts_q.pt); 238 239 /* init TS hw */ 240 saa7134_ts_init_hw(dev); 241 242 return 0; 243 } 244 245 /* Function for stop TS */ 246 int saa7134_ts_stop(struct saa7134_dev *dev) 247 { 248 ts_dbg("TS stop\n"); 249 250 if (!dev->ts_started) 251 return 0; 252 253 /* Stop TS stream */ 254 switch (saa7134_boards[dev->board].ts_type) { 255 case SAA7134_MPEG_TS_PARALLEL: 256 saa_writeb(SAA7134_TS_PARALLEL, 0x6c); 257 dev->ts_started = 0; 258 break; 259 case SAA7134_MPEG_TS_SERIAL: 260 saa_writeb(SAA7134_TS_SERIAL0, 0x40); 261 dev->ts_started = 0; 262 break; 263 } 264 return 0; 265 } 266 267 /* Function for start TS */ 268 int saa7134_ts_start(struct saa7134_dev *dev) 269 { 270 ts_dbg("TS start\n"); 271 272 if (WARN_ON(dev->ts_started)) 273 return 0; 274 275 /* dma: setup channel 5 (= TS) */ 276 saa_writeb(SAA7134_TS_DMA0, (dev->ts.nr_packets - 1) & 0xff); 277 saa_writeb(SAA7134_TS_DMA1, 278 ((dev->ts.nr_packets - 1) >> 8) & 0xff); 279 /* TSNOPIT=0, TSCOLAP=0 */ 280 saa_writeb(SAA7134_TS_DMA2, 281 (((dev->ts.nr_packets - 1) >> 16) & 0x3f) | 0x00); 282 saa_writel(SAA7134_RS_PITCH(5), TS_PACKET_SIZE); 283 saa_writel(SAA7134_RS_CONTROL(5), SAA7134_RS_CONTROL_BURST_16 | 284 SAA7134_RS_CONTROL_ME | 285 (dev->ts_q.pt.dma >> 12)); 286 287 /* reset hardware TS buffers */ 288 saa_writeb(SAA7134_TS_SERIAL1, 0x00); 289 saa_writeb(SAA7134_TS_SERIAL1, 0x03); 290 saa_writeb(SAA7134_TS_SERIAL1, 0x00); 291 saa_writeb(SAA7134_TS_SERIAL1, 0x01); 292 293 /* TS clock non-inverted */ 294 saa_writeb(SAA7134_TS_SERIAL1, 0x00); 295 296 /* Start TS stream */ 297 switch (saa7134_boards[dev->board].ts_type) { 298 case SAA7134_MPEG_TS_PARALLEL: 299 saa_writeb(SAA7134_TS_SERIAL0, 0x40); 300 saa_writeb(SAA7134_TS_PARALLEL, 0xec | 301 (saa7134_boards[dev->board].ts_force_val << 4)); 302 break; 303 case SAA7134_MPEG_TS_SERIAL: 304 saa_writeb(SAA7134_TS_SERIAL0, 0xd8); 305 saa_writeb(SAA7134_TS_PARALLEL, 0x6c | 306 (saa7134_boards[dev->board].ts_force_val << 4)); 307 saa_writeb(SAA7134_TS_PARALLEL_SERIAL, 0xbc); 308 saa_writeb(SAA7134_TS_SERIAL1, 0x02); 309 break; 310 } 311 312 dev->ts_started = 1; 313 314 return 0; 315 } 316 317 int saa7134_ts_fini(struct saa7134_dev *dev) 318 { 319 saa7134_pgtable_free(dev->pci, &dev->ts_q.pt); 320 return 0; 321 } 322 323 void saa7134_irq_ts_done(struct saa7134_dev *dev, unsigned long status) 324 { 325 enum v4l2_field field; 326 327 spin_lock(&dev->slock); 328 if (dev->ts_q.curr) { 329 field = dev->ts_field; 330 if (field != V4L2_FIELD_TOP) { 331 if ((status & 0x100000) != 0x000000) 332 goto done; 333 } else { 334 if ((status & 0x100000) != 0x100000) 335 goto done; 336 } 337 saa7134_buffer_finish(dev, &dev->ts_q, VB2_BUF_STATE_DONE); 338 } 339 saa7134_buffer_next(dev,&dev->ts_q); 340 341 done: 342 spin_unlock(&dev->slock); 343 } 344