1*ba07fd2fSBen Hoff /* SPDX-License-Identifier: GPL-2.0-only */ 2*ba07fd2fSBen Hoff #ifndef HWS_PCIE_H 3*ba07fd2fSBen Hoff #define HWS_PCIE_H 4*ba07fd2fSBen Hoff 5*ba07fd2fSBen Hoff #include <linux/types.h> 6*ba07fd2fSBen Hoff #include <linux/compiler.h> 7*ba07fd2fSBen Hoff #include <linux/dma-mapping.h> 8*ba07fd2fSBen Hoff #include <linux/kthread.h> 9*ba07fd2fSBen Hoff #include <linux/pci.h> 10*ba07fd2fSBen Hoff #include <linux/list.h> 11*ba07fd2fSBen Hoff #include <linux/spinlock.h> 12*ba07fd2fSBen Hoff #include <linux/sizes.h> 13*ba07fd2fSBen Hoff #include <linux/atomic.h> 14*ba07fd2fSBen Hoff 15*ba07fd2fSBen Hoff #include <media/v4l2-ctrls.h> 16*ba07fd2fSBen Hoff #include <media/v4l2-device.h> 17*ba07fd2fSBen Hoff #include <media/v4l2-dv-timings.h> 18*ba07fd2fSBen Hoff #include <media/videobuf2-dma-sg.h> 19*ba07fd2fSBen Hoff 20*ba07fd2fSBen Hoff #include "hws_reg.h" 21*ba07fd2fSBen Hoff 22*ba07fd2fSBen Hoff struct hwsmem_param { 23*ba07fd2fSBen Hoff u32 index; 24*ba07fd2fSBen Hoff u32 type; 25*ba07fd2fSBen Hoff u32 status; 26*ba07fd2fSBen Hoff }; 27*ba07fd2fSBen Hoff 28*ba07fd2fSBen Hoff struct hws_pix_state { 29*ba07fd2fSBen Hoff u32 width; 30*ba07fd2fSBen Hoff u32 height; 31*ba07fd2fSBen Hoff u32 fourcc; /* V4L2_PIX_FMT_* (YUYV only here) */ 32*ba07fd2fSBen Hoff u32 bytesperline; /* stride */ 33*ba07fd2fSBen Hoff u32 sizeimage; /* full frame */ 34*ba07fd2fSBen Hoff enum v4l2_field field; /* V4L2_FIELD_NONE or INTERLACED */ 35*ba07fd2fSBen Hoff enum v4l2_colorspace colorspace; /* e.g., REC709 */ 36*ba07fd2fSBen Hoff enum v4l2_ycbcr_encoding ycbcr_enc; /* V4L2_YCBCR_ENC_DEFAULT */ 37*ba07fd2fSBen Hoff enum v4l2_quantization quantization; /* V4L2_QUANTIZATION_LIM_RANGE */ 38*ba07fd2fSBen Hoff enum v4l2_xfer_func xfer_func; /* V4L2_XFER_FUNC_DEFAULT */ 39*ba07fd2fSBen Hoff bool interlaced; /* cached hardware state */ 40*ba07fd2fSBen Hoff u32 half_size; /* hardware half-frame size */ 41*ba07fd2fSBen Hoff }; 42*ba07fd2fSBen Hoff 43*ba07fd2fSBen Hoff #define UNSET (-1U) 44*ba07fd2fSBen Hoff 45*ba07fd2fSBen Hoff struct hws_pcie_dev; 46*ba07fd2fSBen Hoff struct hws_adapter; 47*ba07fd2fSBen Hoff struct hws_video; 48*ba07fd2fSBen Hoff 49*ba07fd2fSBen Hoff struct hwsvideo_buffer { 50*ba07fd2fSBen Hoff struct vb2_v4l2_buffer vb; 51*ba07fd2fSBen Hoff struct list_head list; 52*ba07fd2fSBen Hoff int slot; 53*ba07fd2fSBen Hoff }; 54*ba07fd2fSBen Hoff 55*ba07fd2fSBen Hoff struct hws_video { 56*ba07fd2fSBen Hoff /* Linkage */ 57*ba07fd2fSBen Hoff struct hws_pcie_dev *parent; 58*ba07fd2fSBen Hoff struct video_device *video_device; 59*ba07fd2fSBen Hoff 60*ba07fd2fSBen Hoff struct vb2_queue buffer_queue; 61*ba07fd2fSBen Hoff struct list_head capture_queue; 62*ba07fd2fSBen Hoff struct hwsvideo_buffer *active; 63*ba07fd2fSBen Hoff struct hwsvideo_buffer *next_prepared; 64*ba07fd2fSBen Hoff 65*ba07fd2fSBen Hoff /* Locking */ 66*ba07fd2fSBen Hoff struct mutex state_lock; 67*ba07fd2fSBen Hoff spinlock_t irq_lock; /* Protects capture_queue and active buffers. */ 68*ba07fd2fSBen Hoff 69*ba07fd2fSBen Hoff /* Indices */ 70*ba07fd2fSBen Hoff int channel_index; 71*ba07fd2fSBen Hoff 72*ba07fd2fSBen Hoff /* Color controls */ 73*ba07fd2fSBen Hoff int current_brightness; 74*ba07fd2fSBen Hoff int current_contrast; 75*ba07fd2fSBen Hoff int current_saturation; 76*ba07fd2fSBen Hoff int current_hue; 77*ba07fd2fSBen Hoff 78*ba07fd2fSBen Hoff /* V4L2 controls */ 79*ba07fd2fSBen Hoff struct v4l2_ctrl_handler control_handler; 80*ba07fd2fSBen Hoff struct v4l2_ctrl *ctrl_brightness; 81*ba07fd2fSBen Hoff struct v4l2_ctrl *ctrl_contrast; 82*ba07fd2fSBen Hoff struct v4l2_ctrl *ctrl_saturation; 83*ba07fd2fSBen Hoff struct v4l2_ctrl *ctrl_hue; 84*ba07fd2fSBen Hoff 85*ba07fd2fSBen Hoff /* Capture queue status */ 86*ba07fd2fSBen Hoff struct hws_pix_state pix; 87*ba07fd2fSBen Hoff struct v4l2_dv_timings cur_dv_timings; /* last configured/notified DV timings */ 88*ba07fd2fSBen Hoff u32 current_fps; /* Hz, updated by mode changes, not by read-only queries */ 89*ba07fd2fSBen Hoff 90*ba07fd2fSBen Hoff /* Per-channel capture state */ 91*ba07fd2fSBen Hoff bool cap_active; 92*ba07fd2fSBen Hoff bool stop_requested; 93*ba07fd2fSBen Hoff u8 last_buf_half_toggle; 94*ba07fd2fSBen Hoff bool half_seen; 95*ba07fd2fSBen Hoff atomic_t sequence_number; 96*ba07fd2fSBen Hoff u32 queued_count; 97*ba07fd2fSBen Hoff 98*ba07fd2fSBen Hoff /* Timeout and error handling */ 99*ba07fd2fSBen Hoff u32 timeout_count; 100*ba07fd2fSBen Hoff u32 error_count; 101*ba07fd2fSBen Hoff 102*ba07fd2fSBen Hoff bool window_valid; 103*ba07fd2fSBen Hoff u32 last_dma_hi; 104*ba07fd2fSBen Hoff u32 last_dma_page; 105*ba07fd2fSBen Hoff u32 last_pci_addr; 106*ba07fd2fSBen Hoff u32 last_half16; 107*ba07fd2fSBen Hoff 108*ba07fd2fSBen Hoff /* Misc counters */ 109*ba07fd2fSBen Hoff int signal_loss_cnt; 110*ba07fd2fSBen Hoff }; 111*ba07fd2fSBen Hoff 112*ba07fd2fSBen Hoff static inline void hws_set_current_dv_timings(struct hws_video *vid, 113*ba07fd2fSBen Hoff u32 width, u32 height, 114*ba07fd2fSBen Hoff bool interlaced) 115*ba07fd2fSBen Hoff { 116*ba07fd2fSBen Hoff if (!vid) 117*ba07fd2fSBen Hoff return; 118*ba07fd2fSBen Hoff 119*ba07fd2fSBen Hoff vid->cur_dv_timings = (struct v4l2_dv_timings) { 120*ba07fd2fSBen Hoff .type = V4L2_DV_BT_656_1120, 121*ba07fd2fSBen Hoff .bt = { 122*ba07fd2fSBen Hoff .width = width, 123*ba07fd2fSBen Hoff .height = height, 124*ba07fd2fSBen Hoff .interlaced = interlaced, 125*ba07fd2fSBen Hoff }, 126*ba07fd2fSBen Hoff }; 127*ba07fd2fSBen Hoff } 128*ba07fd2fSBen Hoff 129*ba07fd2fSBen Hoff struct hws_scratch_dma { 130*ba07fd2fSBen Hoff void *cpu; 131*ba07fd2fSBen Hoff dma_addr_t dma; 132*ba07fd2fSBen Hoff size_t size; 133*ba07fd2fSBen Hoff }; 134*ba07fd2fSBen Hoff 135*ba07fd2fSBen Hoff struct hws_pcie_dev { 136*ba07fd2fSBen Hoff /* Core objects */ 137*ba07fd2fSBen Hoff struct pci_dev *pdev; 138*ba07fd2fSBen Hoff struct hws_video video[MAX_VID_CHANNELS]; 139*ba07fd2fSBen Hoff 140*ba07fd2fSBen Hoff /* BAR and workqueues */ 141*ba07fd2fSBen Hoff void __iomem *bar0_base; 142*ba07fd2fSBen Hoff 143*ba07fd2fSBen Hoff /* Device identity and capabilities */ 144*ba07fd2fSBen Hoff u16 vendor_id; 145*ba07fd2fSBen Hoff u16 device_id; 146*ba07fd2fSBen Hoff u16 device_ver; 147*ba07fd2fSBen Hoff u16 hw_ver; 148*ba07fd2fSBen Hoff u32 sub_ver; 149*ba07fd2fSBen Hoff u32 port_id; 150*ba07fd2fSBen Hoff /* Tri-state support flag used by set_video_format_size(). */ 151*ba07fd2fSBen Hoff u32 support_yv12; 152*ba07fd2fSBen Hoff u32 max_hw_video_buf_sz; 153*ba07fd2fSBen Hoff u8 max_channels; 154*ba07fd2fSBen Hoff u8 cur_max_video_ch; 155*ba07fd2fSBen Hoff bool start_run; 156*ba07fd2fSBen Hoff 157*ba07fd2fSBen Hoff bool buf_allocated; 158*ba07fd2fSBen Hoff 159*ba07fd2fSBen Hoff /* V4L2 framework objects */ 160*ba07fd2fSBen Hoff struct v4l2_device v4l2_device; 161*ba07fd2fSBen Hoff 162*ba07fd2fSBen Hoff /* Kernel thread */ 163*ba07fd2fSBen Hoff struct task_struct *main_task; 164*ba07fd2fSBen Hoff struct hws_scratch_dma scratch_vid[MAX_VID_CHANNELS]; 165*ba07fd2fSBen Hoff 166*ba07fd2fSBen Hoff bool suspended; 167*ba07fd2fSBen Hoff int irq; 168*ba07fd2fSBen Hoff 169*ba07fd2fSBen Hoff /* Error flags */ 170*ba07fd2fSBen Hoff int pci_lost; 171*ba07fd2fSBen Hoff }; 172*ba07fd2fSBen Hoff 173*ba07fd2fSBen Hoff #endif 174