1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /*************************************************************************** 3 * Copyright (C) 2006-2010 by Marin Mitov * 4 * mitov@issp.bas.bg * 5 * * 6 * * 7 ***************************************************************************/ 8 9 /* DT3155 header file */ 10 #ifndef _DT3155_H_ 11 #define _DT3155_H_ 12 13 #include <linux/pci.h> 14 #include <linux/interrupt.h> 15 #include <media/v4l2-device.h> 16 #include <media/v4l2-dev.h> 17 #include <media/videobuf2-v4l2.h> 18 19 #define DT3155_NAME "dt3155" 20 #define DT3155_VER_MAJ 2 21 #define DT3155_VER_MIN 0 22 #define DT3155_VER_EXT 0 23 #define DT3155_VERSION __stringify(DT3155_VER_MAJ) "." \ 24 __stringify(DT3155_VER_MIN) "." \ 25 __stringify(DT3155_VER_EXT) 26 27 /* DT3155 Base Register offsets (memory mapped) */ 28 #define EVEN_DMA_START 0x00 29 #define ODD_DMA_START 0x0C 30 #define EVEN_DMA_STRIDE 0x18 31 #define ODD_DMA_STRIDE 0x24 32 #define EVEN_PIXEL_FMT 0x30 33 #define ODD_PIXEL_FMT 0x34 34 #define FIFO_TRIGGER 0x38 35 #define XFER_MODE 0x3C 36 #define CSR1 0x40 37 #define RETRY_WAIT_CNT 0x44 38 #define INT_CSR 0x48 39 #define EVEN_FLD_MASK 0x4C 40 #define ODD_FLD_MASK 0x50 41 #define MASK_LENGTH 0x54 42 #define FIFO_FLAG_CNT 0x58 43 #define IIC_CLK_DUR 0x5C 44 #define IIC_CSR1 0x60 45 #define IIC_CSR2 0x64 46 47 /* DT3155 Internal Registers indexes (i2c/IIC mapped) */ 48 #define CSR2 0x10 49 #define EVEN_CSR 0x11 50 #define ODD_CSR 0x12 51 #define CONFIG 0x13 52 #define DT_ID 0x1F 53 #define X_CLIP_START 0x20 54 #define Y_CLIP_START 0x22 55 #define X_CLIP_END 0x24 56 #define Y_CLIP_END 0x26 57 #define AD_ADDR 0x30 58 #define AD_LUT 0x31 59 #define AD_CMD 0x32 60 #define DIG_OUT 0x40 61 #define PM_LUT_ADDR 0x50 62 #define PM_LUT_DATA 0x51 63 64 /* AD command register values */ 65 #define AD_CMD_REG 0x00 66 #define AD_POS_REF 0x01 67 #define AD_NEG_REF 0x02 68 69 /* CSR1 bit masks */ 70 #define RANGE_EN 0x00008000 71 #define CRPT_DIS 0x00004000 72 #define ADDR_ERR_ODD 0x00000800 73 #define ADDR_ERR_EVEN 0x00000400 74 #define FLD_CRPT_ODD 0x00000200 75 #define FLD_CRPT_EVEN 0x00000100 76 #define FIFO_EN 0x00000080 77 #define SRST 0x00000040 78 #define FLD_DN_ODD 0x00000020 79 #define FLD_DN_EVEN 0x00000010 80 /* These should not be used. 81 * Use CAP_CONT_ODD/EVEN instead 82 #define CAP_SNGL_ODD 0x00000008 83 #define CAP_SNGL_EVEN 0x00000004 84 */ 85 #define CAP_CONT_ODD 0x00000002 86 #define CAP_CONT_EVEN 0x00000001 87 88 /* INT_CSR bit masks */ 89 #define FLD_START_EN 0x00000400 90 #define FLD_END_ODD_EN 0x00000200 91 #define FLD_END_EVEN_EN 0x00000100 92 #define FLD_START 0x00000004 93 #define FLD_END_ODD 0x00000002 94 #define FLD_END_EVEN 0x00000001 95 96 /* IIC_CSR1 bit masks */ 97 #define DIRECT_ABORT 0x00000200 98 99 /* IIC_CSR2 bit masks */ 100 #define NEW_CYCLE 0x01000000 101 #define DIR_RD 0x00010000 102 #define IIC_READ 0x01010000 103 #define IIC_WRITE 0x01000000 104 105 /* CSR2 bit masks */ 106 #define DISP_PASS 0x40 107 #define BUSY_ODD 0x20 108 #define BUSY_EVEN 0x10 109 #define SYNC_PRESENT 0x08 110 #define VT_50HZ 0x04 111 #define SYNC_SNTL 0x02 112 #define CHROM_FILT 0x01 113 #define VT_60HZ 0x00 114 115 /* CSR_EVEN/ODD bit masks */ 116 #define CSR_ERROR 0x04 117 #define CSR_SNGL 0x02 118 #define CSR_DONE 0x01 119 120 /* CONFIG bit masks */ 121 #define PM_LUT_PGM 0x80 122 #define PM_LUT_SEL 0x40 123 #define CLIP_EN 0x20 124 #define HSCALE_EN 0x10 125 #define EXT_TRIG_UP 0x0C 126 #define EXT_TRIG_DOWN 0x04 127 #define ACQ_MODE_NEXT 0x02 128 #define ACQ_MODE_ODD 0x01 129 #define ACQ_MODE_EVEN 0x00 130 131 /* AD_CMD bit masks */ 132 #define VIDEO_CNL_1 0x00 133 #define VIDEO_CNL_2 0x40 134 #define VIDEO_CNL_3 0x80 135 #define VIDEO_CNL_4 0xC0 136 #define SYNC_CNL_1 0x00 137 #define SYNC_CNL_2 0x10 138 #define SYNC_CNL_3 0x20 139 #define SYNC_CNL_4 0x30 140 #define SYNC_LVL_1 0x00 141 #define SYNC_LVL_2 0x04 142 #define SYNC_LVL_3 0x08 143 #define SYNC_LVL_4 0x0C 144 145 /* DT3155 identificator */ 146 #define DT3155_ID 0x20 147 148 /* per board private data structure */ 149 /** 150 * struct dt3155_priv - private data structure 151 * 152 * @v4l2_dev: v4l2_device structure 153 * @vdev: video_device structure 154 * @pdev: pointer to pci_dev structure 155 * @vidq: vb2_queue structure 156 * @curr_buf: pointer to curren buffer 157 * @mux: mutex to protect the instance 158 * @dmaq: queue for dma buffers 159 * @lock: spinlock for dma queue 160 * @std: input standard 161 * @width: frame width 162 * @height: frame height 163 * @input: current input 164 * @sequence: frame counter 165 * @regs: local copy of mmio base register 166 * @csr2: local copy of csr2 register 167 * @config: local copy of config register 168 */ 169 struct dt3155_priv { 170 struct v4l2_device v4l2_dev; 171 struct video_device vdev; 172 struct pci_dev *pdev; 173 struct vb2_queue vidq; 174 struct vb2_v4l2_buffer *curr_buf; 175 struct mutex mux; 176 struct list_head dmaq; 177 spinlock_t lock; 178 v4l2_std_id std; 179 unsigned width, height; 180 unsigned input; 181 unsigned int sequence; 182 void __iomem *regs; 183 u8 csr2, config; 184 }; 185 186 #endif /* _DT3155_H_ */ 187