1 /*************************************************************************** 2 * Copyright (C) 2006-2010 by Marin Mitov * 3 * mitov@issp.bas.bg * 4 * * 5 * This program is free software; you can redistribute it and/or modify * 6 * it under the terms of the GNU General Public License as published by * 7 * the Free Software Foundation; either version 2 of the License, or * 8 * (at your option) any later version. * 9 * * 10 * This program is distributed in the hope that it will be useful, * 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of * 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * 13 * GNU General Public License for more details. * 14 * * 15 ***************************************************************************/ 16 17 #include <linux/module.h> 18 #include <linux/stringify.h> 19 #include <linux/delay.h> 20 #include <linux/kthread.h> 21 #include <linux/slab.h> 22 #include <media/v4l2-dev.h> 23 #include <media/v4l2-ioctl.h> 24 #include <media/v4l2-common.h> 25 #include <media/videobuf2-dma-contig.h> 26 27 #include "dt3155.h" 28 29 #define DT3155_DEVICE_ID 0x1223 30 31 /** 32 * read_i2c_reg - reads an internal i2c register 33 * 34 * @addr: dt3155 mmio base address 35 * @index: index (internal address) of register to read 36 * @data: pointer to byte the read data will be placed in 37 * 38 * returns: zero on success or error code 39 * 40 * This function starts reading the specified (by index) register 41 * and busy waits for the process to finish. The result is placed 42 * in a byte pointed by data. 43 */ 44 static int read_i2c_reg(void __iomem *addr, u8 index, u8 *data) 45 { 46 u32 tmp = index; 47 48 iowrite32((tmp << 17) | IIC_READ, addr + IIC_CSR2); 49 mmiowb(); 50 udelay(45); /* wait at least 43 usec for NEW_CYCLE to clear */ 51 if (ioread32(addr + IIC_CSR2) & NEW_CYCLE) 52 return -EIO; /* error: NEW_CYCLE not cleared */ 53 tmp = ioread32(addr + IIC_CSR1); 54 if (tmp & DIRECT_ABORT) { 55 /* reset DIRECT_ABORT bit */ 56 iowrite32(DIRECT_ABORT, addr + IIC_CSR1); 57 return -EIO; /* error: DIRECT_ABORT set */ 58 } 59 *data = tmp >> 24; 60 return 0; 61 } 62 63 /** 64 * write_i2c_reg - writes to an internal i2c register 65 * 66 * @addr: dt3155 mmio base address 67 * @index: index (internal address) of register to read 68 * @data: data to be written 69 * 70 * returns: zero on success or error code 71 * 72 * This function starts writing the specified (by index) register 73 * and busy waits for the process to finish. 74 */ 75 static int write_i2c_reg(void __iomem *addr, u8 index, u8 data) 76 { 77 u32 tmp = index; 78 79 iowrite32((tmp << 17) | IIC_WRITE | data, addr + IIC_CSR2); 80 mmiowb(); 81 udelay(65); /* wait at least 63 usec for NEW_CYCLE to clear */ 82 if (ioread32(addr + IIC_CSR2) & NEW_CYCLE) 83 return -EIO; /* error: NEW_CYCLE not cleared */ 84 if (ioread32(addr + IIC_CSR1) & DIRECT_ABORT) { 85 /* reset DIRECT_ABORT bit */ 86 iowrite32(DIRECT_ABORT, addr + IIC_CSR1); 87 return -EIO; /* error: DIRECT_ABORT set */ 88 } 89 return 0; 90 } 91 92 /** 93 * write_i2c_reg_nowait - writes to an internal i2c register 94 * 95 * @addr: dt3155 mmio base address 96 * @index: index (internal address) of register to read 97 * @data: data to be written 98 * 99 * This function starts writing the specified (by index) register 100 * and then returns. 101 */ 102 static void write_i2c_reg_nowait(void __iomem *addr, u8 index, u8 data) 103 { 104 u32 tmp = index; 105 106 iowrite32((tmp << 17) | IIC_WRITE | data, addr + IIC_CSR2); 107 mmiowb(); 108 } 109 110 /** 111 * wait_i2c_reg - waits the read/write to finish 112 * 113 * @addr: dt3155 mmio base address 114 * 115 * returns: zero on success or error code 116 * 117 * This function waits reading/writing to finish. 118 */ 119 static int wait_i2c_reg(void __iomem *addr) 120 { 121 if (ioread32(addr + IIC_CSR2) & NEW_CYCLE) 122 udelay(65); /* wait at least 63 usec for NEW_CYCLE to clear */ 123 if (ioread32(addr + IIC_CSR2) & NEW_CYCLE) 124 return -EIO; /* error: NEW_CYCLE not cleared */ 125 if (ioread32(addr + IIC_CSR1) & DIRECT_ABORT) { 126 /* reset DIRECT_ABORT bit */ 127 iowrite32(DIRECT_ABORT, addr + IIC_CSR1); 128 return -EIO; /* error: DIRECT_ABORT set */ 129 } 130 return 0; 131 } 132 133 static int 134 dt3155_queue_setup(struct vb2_queue *vq, 135 unsigned int *nbuffers, unsigned int *num_planes, 136 unsigned int sizes[], struct device *alloc_devs[]) 137 138 { 139 struct dt3155_priv *pd = vb2_get_drv_priv(vq); 140 unsigned size = pd->width * pd->height; 141 142 if (vq->num_buffers + *nbuffers < 2) 143 *nbuffers = 2 - vq->num_buffers; 144 if (*num_planes) 145 return sizes[0] < size ? -EINVAL : 0; 146 *num_planes = 1; 147 sizes[0] = size; 148 return 0; 149 } 150 151 static int dt3155_buf_prepare(struct vb2_buffer *vb) 152 { 153 struct dt3155_priv *pd = vb2_get_drv_priv(vb->vb2_queue); 154 155 vb2_set_plane_payload(vb, 0, pd->width * pd->height); 156 return 0; 157 } 158 159 static int dt3155_start_streaming(struct vb2_queue *q, unsigned count) 160 { 161 struct dt3155_priv *pd = vb2_get_drv_priv(q); 162 struct vb2_buffer *vb = &pd->curr_buf->vb2_buf; 163 dma_addr_t dma_addr; 164 165 pd->sequence = 0; 166 dma_addr = vb2_dma_contig_plane_dma_addr(vb, 0); 167 iowrite32(dma_addr, pd->regs + EVEN_DMA_START); 168 iowrite32(dma_addr + pd->width, pd->regs + ODD_DMA_START); 169 iowrite32(pd->width, pd->regs + EVEN_DMA_STRIDE); 170 iowrite32(pd->width, pd->regs + ODD_DMA_STRIDE); 171 /* enable interrupts, clear all irq flags */ 172 iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START | 173 FLD_END_EVEN | FLD_END_ODD, pd->regs + INT_CSR); 174 iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN | 175 FLD_DN_ODD | FLD_DN_EVEN | CAP_CONT_EVEN | CAP_CONT_ODD, 176 pd->regs + CSR1); 177 wait_i2c_reg(pd->regs); 178 write_i2c_reg(pd->regs, CONFIG, pd->config); 179 write_i2c_reg(pd->regs, EVEN_CSR, CSR_ERROR | CSR_DONE); 180 write_i2c_reg(pd->regs, ODD_CSR, CSR_ERROR | CSR_DONE); 181 182 /* start the board */ 183 write_i2c_reg(pd->regs, CSR2, pd->csr2 | BUSY_EVEN | BUSY_ODD); 184 return 0; 185 } 186 187 static void dt3155_stop_streaming(struct vb2_queue *q) 188 { 189 struct dt3155_priv *pd = vb2_get_drv_priv(q); 190 struct vb2_buffer *vb; 191 192 spin_lock_irq(&pd->lock); 193 /* stop the board */ 194 write_i2c_reg_nowait(pd->regs, CSR2, pd->csr2); 195 iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN | 196 FLD_DN_ODD | FLD_DN_EVEN, pd->regs + CSR1); 197 /* disable interrupts, clear all irq flags */ 198 iowrite32(FLD_START | FLD_END_EVEN | FLD_END_ODD, pd->regs + INT_CSR); 199 spin_unlock_irq(&pd->lock); 200 201 /* 202 * It is not clear whether the DMA stops at once or whether it 203 * will finish the current frame or field first. To be on the 204 * safe side we wait a bit. 205 */ 206 msleep(45); 207 208 spin_lock_irq(&pd->lock); 209 if (pd->curr_buf) { 210 vb2_buffer_done(&pd->curr_buf->vb2_buf, VB2_BUF_STATE_ERROR); 211 pd->curr_buf = NULL; 212 } 213 214 while (!list_empty(&pd->dmaq)) { 215 vb = list_first_entry(&pd->dmaq, typeof(*vb), done_entry); 216 list_del(&vb->done_entry); 217 vb2_buffer_done(vb, VB2_BUF_STATE_ERROR); 218 } 219 spin_unlock_irq(&pd->lock); 220 } 221 222 static void dt3155_buf_queue(struct vb2_buffer *vb) 223 { 224 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 225 struct dt3155_priv *pd = vb2_get_drv_priv(vb->vb2_queue); 226 227 /* pd->vidq.streaming = 1 when dt3155_buf_queue() is invoked */ 228 spin_lock_irq(&pd->lock); 229 if (pd->curr_buf) 230 list_add_tail(&vb->done_entry, &pd->dmaq); 231 else 232 pd->curr_buf = vbuf; 233 spin_unlock_irq(&pd->lock); 234 } 235 236 static const struct vb2_ops q_ops = { 237 .queue_setup = dt3155_queue_setup, 238 .wait_prepare = vb2_ops_wait_prepare, 239 .wait_finish = vb2_ops_wait_finish, 240 .buf_prepare = dt3155_buf_prepare, 241 .start_streaming = dt3155_start_streaming, 242 .stop_streaming = dt3155_stop_streaming, 243 .buf_queue = dt3155_buf_queue, 244 }; 245 246 static irqreturn_t dt3155_irq_handler_even(int irq, void *dev_id) 247 { 248 struct dt3155_priv *ipd = dev_id; 249 struct vb2_buffer *ivb; 250 dma_addr_t dma_addr; 251 u32 tmp; 252 253 tmp = ioread32(ipd->regs + INT_CSR) & (FLD_START | FLD_END_ODD); 254 if (!tmp) 255 return IRQ_NONE; /* not our irq */ 256 if ((tmp & FLD_START) && !(tmp & FLD_END_ODD)) { 257 iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START, 258 ipd->regs + INT_CSR); 259 return IRQ_HANDLED; /* start of field irq */ 260 } 261 tmp = ioread32(ipd->regs + CSR1) & (FLD_CRPT_EVEN | FLD_CRPT_ODD); 262 if (tmp) { 263 iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN | 264 FLD_DN_ODD | FLD_DN_EVEN | 265 CAP_CONT_EVEN | CAP_CONT_ODD, 266 ipd->regs + CSR1); 267 mmiowb(); 268 } 269 270 spin_lock(&ipd->lock); 271 if (ipd->curr_buf && !list_empty(&ipd->dmaq)) { 272 ipd->curr_buf->vb2_buf.timestamp = ktime_get_ns(); 273 ipd->curr_buf->sequence = ipd->sequence++; 274 ipd->curr_buf->field = V4L2_FIELD_NONE; 275 vb2_buffer_done(&ipd->curr_buf->vb2_buf, VB2_BUF_STATE_DONE); 276 277 ivb = list_first_entry(&ipd->dmaq, typeof(*ivb), done_entry); 278 list_del(&ivb->done_entry); 279 ipd->curr_buf = to_vb2_v4l2_buffer(ivb); 280 dma_addr = vb2_dma_contig_plane_dma_addr(ivb, 0); 281 iowrite32(dma_addr, ipd->regs + EVEN_DMA_START); 282 iowrite32(dma_addr + ipd->width, ipd->regs + ODD_DMA_START); 283 iowrite32(ipd->width, ipd->regs + EVEN_DMA_STRIDE); 284 iowrite32(ipd->width, ipd->regs + ODD_DMA_STRIDE); 285 mmiowb(); 286 } 287 288 /* enable interrupts, clear all irq flags */ 289 iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START | 290 FLD_END_EVEN | FLD_END_ODD, ipd->regs + INT_CSR); 291 spin_unlock(&ipd->lock); 292 return IRQ_HANDLED; 293 } 294 295 static const struct v4l2_file_operations dt3155_fops = { 296 .owner = THIS_MODULE, 297 .open = v4l2_fh_open, 298 .release = vb2_fop_release, 299 .unlocked_ioctl = video_ioctl2, 300 .read = vb2_fop_read, 301 .mmap = vb2_fop_mmap, 302 .poll = vb2_fop_poll 303 }; 304 305 static int dt3155_querycap(struct file *filp, void *p, 306 struct v4l2_capability *cap) 307 { 308 struct dt3155_priv *pd = video_drvdata(filp); 309 310 strscpy(cap->driver, DT3155_NAME, sizeof(cap->driver)); 311 strscpy(cap->card, DT3155_NAME " frame grabber", sizeof(cap->card)); 312 sprintf(cap->bus_info, "PCI:%s", pci_name(pd->pdev)); 313 cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | 314 V4L2_CAP_STREAMING | V4L2_CAP_READWRITE; 315 cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS; 316 return 0; 317 } 318 319 static int dt3155_enum_fmt_vid_cap(struct file *filp, 320 void *p, struct v4l2_fmtdesc *f) 321 { 322 if (f->index) 323 return -EINVAL; 324 f->pixelformat = V4L2_PIX_FMT_GREY; 325 strscpy(f->description, "8-bit Greyscale", sizeof(f->description)); 326 return 0; 327 } 328 329 static int dt3155_fmt_vid_cap(struct file *filp, void *p, struct v4l2_format *f) 330 { 331 struct dt3155_priv *pd = video_drvdata(filp); 332 333 f->fmt.pix.width = pd->width; 334 f->fmt.pix.height = pd->height; 335 f->fmt.pix.pixelformat = V4L2_PIX_FMT_GREY; 336 f->fmt.pix.field = V4L2_FIELD_NONE; 337 f->fmt.pix.bytesperline = f->fmt.pix.width; 338 f->fmt.pix.sizeimage = f->fmt.pix.width * f->fmt.pix.height; 339 f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M; 340 return 0; 341 } 342 343 static int dt3155_g_std(struct file *filp, void *p, v4l2_std_id *norm) 344 { 345 struct dt3155_priv *pd = video_drvdata(filp); 346 347 *norm = pd->std; 348 return 0; 349 } 350 351 static int dt3155_s_std(struct file *filp, void *p, v4l2_std_id norm) 352 { 353 struct dt3155_priv *pd = video_drvdata(filp); 354 355 if (pd->std == norm) 356 return 0; 357 if (vb2_is_busy(&pd->vidq)) 358 return -EBUSY; 359 pd->std = norm; 360 if (pd->std & V4L2_STD_525_60) { 361 pd->csr2 = VT_60HZ; 362 pd->width = 640; 363 pd->height = 480; 364 } else { 365 pd->csr2 = VT_50HZ; 366 pd->width = 768; 367 pd->height = 576; 368 } 369 return 0; 370 } 371 372 static int dt3155_enum_input(struct file *filp, void *p, 373 struct v4l2_input *input) 374 { 375 if (input->index > 3) 376 return -EINVAL; 377 if (input->index) 378 snprintf(input->name, sizeof(input->name), "VID%d", 379 input->index); 380 else 381 strscpy(input->name, "J2/VID0", sizeof(input->name)); 382 input->type = V4L2_INPUT_TYPE_CAMERA; 383 input->std = V4L2_STD_ALL; 384 input->status = 0; 385 return 0; 386 } 387 388 static int dt3155_g_input(struct file *filp, void *p, unsigned int *i) 389 { 390 struct dt3155_priv *pd = video_drvdata(filp); 391 392 *i = pd->input; 393 return 0; 394 } 395 396 static int dt3155_s_input(struct file *filp, void *p, unsigned int i) 397 { 398 struct dt3155_priv *pd = video_drvdata(filp); 399 400 if (i > 3) 401 return -EINVAL; 402 pd->input = i; 403 write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG); 404 write_i2c_reg(pd->regs, AD_CMD, (i << 6) | (i << 4) | SYNC_LVL_3); 405 return 0; 406 } 407 408 static const struct v4l2_ioctl_ops dt3155_ioctl_ops = { 409 .vidioc_querycap = dt3155_querycap, 410 .vidioc_enum_fmt_vid_cap = dt3155_enum_fmt_vid_cap, 411 .vidioc_try_fmt_vid_cap = dt3155_fmt_vid_cap, 412 .vidioc_g_fmt_vid_cap = dt3155_fmt_vid_cap, 413 .vidioc_s_fmt_vid_cap = dt3155_fmt_vid_cap, 414 .vidioc_reqbufs = vb2_ioctl_reqbufs, 415 .vidioc_create_bufs = vb2_ioctl_create_bufs, 416 .vidioc_querybuf = vb2_ioctl_querybuf, 417 .vidioc_expbuf = vb2_ioctl_expbuf, 418 .vidioc_qbuf = vb2_ioctl_qbuf, 419 .vidioc_dqbuf = vb2_ioctl_dqbuf, 420 .vidioc_streamon = vb2_ioctl_streamon, 421 .vidioc_streamoff = vb2_ioctl_streamoff, 422 .vidioc_g_std = dt3155_g_std, 423 .vidioc_s_std = dt3155_s_std, 424 .vidioc_enum_input = dt3155_enum_input, 425 .vidioc_g_input = dt3155_g_input, 426 .vidioc_s_input = dt3155_s_input, 427 }; 428 429 static int dt3155_init_board(struct dt3155_priv *pd) 430 { 431 struct pci_dev *pdev = pd->pdev; 432 int i; 433 u8 tmp = 0; 434 435 pci_set_master(pdev); /* dt3155 needs it */ 436 437 /* resetting the adapter */ 438 iowrite32(ADDR_ERR_ODD | ADDR_ERR_EVEN | FLD_CRPT_ODD | FLD_CRPT_EVEN | 439 FLD_DN_ODD | FLD_DN_EVEN, pd->regs + CSR1); 440 mmiowb(); 441 msleep(20); 442 443 /* initializing adapter registers */ 444 iowrite32(FIFO_EN | SRST, pd->regs + CSR1); 445 mmiowb(); 446 iowrite32(0xEEEEEE01, pd->regs + EVEN_PIXEL_FMT); 447 iowrite32(0xEEEEEE01, pd->regs + ODD_PIXEL_FMT); 448 iowrite32(0x00000020, pd->regs + FIFO_TRIGER); 449 iowrite32(0x00000103, pd->regs + XFER_MODE); 450 iowrite32(0, pd->regs + RETRY_WAIT_CNT); 451 iowrite32(0, pd->regs + INT_CSR); 452 iowrite32(1, pd->regs + EVEN_FLD_MASK); 453 iowrite32(1, pd->regs + ODD_FLD_MASK); 454 iowrite32(0, pd->regs + MASK_LENGTH); 455 iowrite32(0x0005007C, pd->regs + FIFO_FLAG_CNT); 456 iowrite32(0x01010101, pd->regs + IIC_CLK_DUR); 457 mmiowb(); 458 459 /* verifying that we have a DT3155 board (not just a SAA7116 chip) */ 460 read_i2c_reg(pd->regs, DT_ID, &tmp); 461 if (tmp != DT3155_ID) 462 return -ENODEV; 463 464 /* initialize AD LUT */ 465 write_i2c_reg(pd->regs, AD_ADDR, 0); 466 for (i = 0; i < 256; i++) 467 write_i2c_reg(pd->regs, AD_LUT, i); 468 469 /* initialize ADC references */ 470 /* FIXME: pos_ref & neg_ref depend on VT_50HZ */ 471 write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG); 472 write_i2c_reg(pd->regs, AD_CMD, VIDEO_CNL_1 | SYNC_CNL_1 | SYNC_LVL_3); 473 write_i2c_reg(pd->regs, AD_ADDR, AD_POS_REF); 474 write_i2c_reg(pd->regs, AD_CMD, 34); 475 write_i2c_reg(pd->regs, AD_ADDR, AD_NEG_REF); 476 write_i2c_reg(pd->regs, AD_CMD, 0); 477 478 /* initialize PM LUT */ 479 write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM); 480 for (i = 0; i < 256; i++) { 481 write_i2c_reg(pd->regs, PM_LUT_ADDR, i); 482 write_i2c_reg(pd->regs, PM_LUT_DATA, i); 483 } 484 write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM | PM_LUT_SEL); 485 for (i = 0; i < 256; i++) { 486 write_i2c_reg(pd->regs, PM_LUT_ADDR, i); 487 write_i2c_reg(pd->regs, PM_LUT_DATA, i); 488 } 489 write_i2c_reg(pd->regs, CONFIG, pd->config); /* ACQ_MODE_EVEN */ 490 491 /* select channel 1 for input and set sync level */ 492 write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG); 493 write_i2c_reg(pd->regs, AD_CMD, VIDEO_CNL_1 | SYNC_CNL_1 | SYNC_LVL_3); 494 495 /* disable all irqs, clear all irq flags */ 496 iowrite32(FLD_START | FLD_END_EVEN | FLD_END_ODD, 497 pd->regs + INT_CSR); 498 499 return 0; 500 } 501 502 static const struct video_device dt3155_vdev = { 503 .name = DT3155_NAME, 504 .fops = &dt3155_fops, 505 .ioctl_ops = &dt3155_ioctl_ops, 506 .minor = -1, 507 .release = video_device_release_empty, 508 .tvnorms = V4L2_STD_ALL, 509 }; 510 511 static int dt3155_probe(struct pci_dev *pdev, const struct pci_device_id *id) 512 { 513 int err; 514 struct dt3155_priv *pd; 515 516 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 517 if (err) 518 return -ENODEV; 519 pd = devm_kzalloc(&pdev->dev, sizeof(*pd), GFP_KERNEL); 520 if (!pd) 521 return -ENOMEM; 522 523 err = v4l2_device_register(&pdev->dev, &pd->v4l2_dev); 524 if (err) 525 return err; 526 pd->vdev = dt3155_vdev; 527 pd->vdev.v4l2_dev = &pd->v4l2_dev; 528 video_set_drvdata(&pd->vdev, pd); /* for use in video_fops */ 529 pd->pdev = pdev; 530 pd->std = V4L2_STD_625_50; 531 pd->csr2 = VT_50HZ; 532 pd->width = 768; 533 pd->height = 576; 534 INIT_LIST_HEAD(&pd->dmaq); 535 mutex_init(&pd->mux); 536 pd->vdev.lock = &pd->mux; /* for locking v4l2_file_operations */ 537 pd->vidq.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; 538 pd->vidq.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; 539 pd->vidq.io_modes = VB2_MMAP | VB2_DMABUF | VB2_READ; 540 pd->vidq.ops = &q_ops; 541 pd->vidq.mem_ops = &vb2_dma_contig_memops; 542 pd->vidq.drv_priv = pd; 543 pd->vidq.min_buffers_needed = 2; 544 pd->vidq.gfp_flags = GFP_DMA32; 545 pd->vidq.lock = &pd->mux; /* for locking v4l2_file_operations */ 546 pd->vidq.dev = &pdev->dev; 547 pd->vdev.queue = &pd->vidq; 548 err = vb2_queue_init(&pd->vidq); 549 if (err < 0) 550 goto err_v4l2_dev_unreg; 551 spin_lock_init(&pd->lock); 552 pd->config = ACQ_MODE_EVEN; 553 err = pci_enable_device(pdev); 554 if (err) 555 goto err_v4l2_dev_unreg; 556 err = pci_request_region(pdev, 0, pci_name(pdev)); 557 if (err) 558 goto err_pci_disable; 559 pd->regs = pci_iomap(pdev, 0, pci_resource_len(pd->pdev, 0)); 560 if (!pd->regs) { 561 err = -ENOMEM; 562 goto err_free_reg; 563 } 564 err = dt3155_init_board(pd); 565 if (err) 566 goto err_iounmap; 567 err = request_irq(pd->pdev->irq, dt3155_irq_handler_even, 568 IRQF_SHARED, DT3155_NAME, pd); 569 if (err) 570 goto err_iounmap; 571 err = video_register_device(&pd->vdev, VFL_TYPE_GRABBER, -1); 572 if (err) 573 goto err_free_irq; 574 dev_info(&pdev->dev, "/dev/video%i is ready\n", pd->vdev.minor); 575 return 0; /* success */ 576 577 err_free_irq: 578 free_irq(pd->pdev->irq, pd); 579 err_iounmap: 580 pci_iounmap(pdev, pd->regs); 581 err_free_reg: 582 pci_release_region(pdev, 0); 583 err_pci_disable: 584 pci_disable_device(pdev); 585 err_v4l2_dev_unreg: 586 v4l2_device_unregister(&pd->v4l2_dev); 587 return err; 588 } 589 590 static void dt3155_remove(struct pci_dev *pdev) 591 { 592 struct v4l2_device *v4l2_dev = pci_get_drvdata(pdev); 593 struct dt3155_priv *pd = container_of(v4l2_dev, struct dt3155_priv, 594 v4l2_dev); 595 596 video_unregister_device(&pd->vdev); 597 free_irq(pd->pdev->irq, pd); 598 vb2_queue_release(&pd->vidq); 599 v4l2_device_unregister(&pd->v4l2_dev); 600 pci_iounmap(pdev, pd->regs); 601 pci_release_region(pdev, 0); 602 pci_disable_device(pdev); 603 } 604 605 static const struct pci_device_id pci_ids[] = { 606 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, DT3155_DEVICE_ID) }, 607 { 0, /* zero marks the end */ }, 608 }; 609 MODULE_DEVICE_TABLE(pci, pci_ids); 610 611 static struct pci_driver pci_driver = { 612 .name = DT3155_NAME, 613 .id_table = pci_ids, 614 .probe = dt3155_probe, 615 .remove = dt3155_remove, 616 }; 617 618 module_pci_driver(pci_driver); 619 620 MODULE_DESCRIPTION("video4linux pci-driver for dt3155 frame grabber"); 621 MODULE_AUTHOR("Marin Mitov <mitov@issp.bas.bg>"); 622 MODULE_VERSION(DT3155_VERSION); 623 MODULE_LICENSE("GPL"); 624