1 /* 2 * ddbridge-regs.h: Digital Devices PCIe bridge driver 3 * 4 * Copyright (C) 2010-2017 Digital Devices GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * version 2 only, as published by the Free Software Foundation. 9 * 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * To obtain the license, point your browser to 17 * http://www.gnu.org/copyleft/gpl.html 18 */ 19 20 #ifndef __DDBRIDGE_REGS_H__ 21 #define __DDBRIDGE_REGS_H__ 22 23 /* ------------------------------------------------------------------------- */ 24 /* SPI Controller */ 25 26 #define SPI_CONTROL 0x10 27 #define SPI_DATA 0x14 28 29 /* ------------------------------------------------------------------------- */ 30 /* GPIO */ 31 32 #define GPIO_OUTPUT 0x20 33 #define GPIO_INPUT 0x24 34 #define GPIO_DIRECTION 0x28 35 36 /* ------------------------------------------------------------------------- */ 37 38 #define BOARD_CONTROL 0x30 39 40 /* ------------------------------------------------------------------------- */ 41 42 /* Interrupt controller 43 * How many MSI's are available depends on HW (Min 2 max 8) 44 * How many are usable also depends on Host platform 45 */ 46 47 #define INTERRUPT_BASE (0x40) 48 49 #define INTERRUPT_ENABLE (INTERRUPT_BASE + 0x00) 50 #define MSI1_ENABLE (INTERRUPT_BASE + 0x04) 51 #define MSI2_ENABLE (INTERRUPT_BASE + 0x08) 52 #define MSI3_ENABLE (INTERRUPT_BASE + 0x0C) 53 #define MSI4_ENABLE (INTERRUPT_BASE + 0x10) 54 #define MSI5_ENABLE (INTERRUPT_BASE + 0x14) 55 #define MSI6_ENABLE (INTERRUPT_BASE + 0x18) 56 #define MSI7_ENABLE (INTERRUPT_BASE + 0x1C) 57 58 #define INTERRUPT_STATUS (INTERRUPT_BASE + 0x20) 59 #define INTERRUPT_ACK (INTERRUPT_BASE + 0x20) 60 61 /* Temperature Monitor ( 2x LM75A @ 0x90,0x92 I2c ) */ 62 #define TEMPMON_BASE (0x1c0) 63 #define TEMPMON_CONTROL (TEMPMON_BASE + 0x00) 64 65 #define TEMPMON_CONTROL_AUTOSCAN (0x00000002) 66 #define TEMPMON_CONTROL_INTENABLE (0x00000004) 67 #define TEMPMON_CONTROL_OVERTEMP (0x00008000) 68 69 /* SHORT Temperature in Celsius x 256 */ 70 #define TEMPMON_SENSOR0 (TEMPMON_BASE + 0x04) 71 #define TEMPMON_SENSOR1 (TEMPMON_BASE + 0x08) 72 73 #define TEMPMON_FANCONTROL (TEMPMON_BASE + 0x10) 74 75 /* ------------------------------------------------------------------------- */ 76 /* I2C Master Controller */ 77 78 #define I2C_COMMAND (0x00) 79 #define I2C_TIMING (0x04) 80 #define I2C_TASKLENGTH (0x08) /* High read, low write */ 81 #define I2C_TASKADDRESS (0x0C) /* High read, low write */ 82 #define I2C_MONITOR (0x1C) 83 84 #define I2C_SPEED_400 (0x04030404) 85 #define I2C_SPEED_100 (0x13121313) 86 87 /* ------------------------------------------------------------------------- */ 88 /* DMA Controller */ 89 90 #define DMA_BASE_WRITE (0x100) 91 #define DMA_BASE_READ (0x140) 92 93 #define TS_CONTROL(_io) ((_io)->regs + 0x00) 94 #define TS_CONTROL2(_io) ((_io)->regs + 0x04) 95 96 /* ------------------------------------------------------------------------- */ 97 /* DMA Buffer */ 98 99 #define DMA_BUFFER_CONTROL(_dma) ((_dma)->regs + 0x00) 100 #define DMA_BUFFER_ACK(_dma) ((_dma)->regs + 0x04) 101 #define DMA_BUFFER_CURRENT(_dma) ((_dma)->regs + 0x08) 102 #define DMA_BUFFER_SIZE(_dma) ((_dma)->regs + 0x0c) 103 104 /* ------------------------------------------------------------------------- */ 105 /* CI Interface (only CI-Bridge) */ 106 107 #define CI_BASE (0x400) 108 #define CI_CONTROL(i) (CI_BASE + (i) * 32 + 0x00) 109 110 #define CI_DO_ATTRIBUTE_RW(i) (CI_BASE + (i) * 32 + 0x04) 111 #define CI_DO_IO_RW(i) (CI_BASE + (i) * 32 + 0x08) 112 #define CI_READDATA(i) (CI_BASE + (i) * 32 + 0x0c) 113 #define CI_DO_READ_ATTRIBUTES(i) (CI_BASE + (i) * 32 + 0x10) 114 115 #define CI_RESET_CAM (0x00000001) 116 #define CI_POWER_ON (0x00000002) 117 #define CI_ENABLE (0x00000004) 118 #define CI_BYPASS_DISABLE (0x00000010) 119 120 #define CI_CAM_READY (0x00010000) 121 #define CI_CAM_DETECT (0x00020000) 122 #define CI_READY (0x80000000) 123 124 #define CI_READ_CMD (0x40000000) 125 #define CI_WRITE_CMD (0x80000000) 126 127 #define CI_BUFFER_BASE (0x3000) 128 #define CI_BUFFER_SIZE (0x0800) 129 130 #define CI_BUFFER(i) (CI_BUFFER_BASE + (i) * CI_BUFFER_SIZE) 131 132 /* ------------------------------------------------------------------------- */ 133 /* LNB commands (mxl5xx / Max S8) */ 134 135 #define LNB_BASE (0x400) 136 #define LNB_CONTROL(i) (LNB_BASE + (i) * 0x20 + 0x00) 137 138 #define LNB_CMD (7ULL << 0) 139 #define LNB_CMD_NOP 0 140 #define LNB_CMD_INIT 1 141 #define LNB_CMD_LOW 3 142 #define LNB_CMD_HIGH 4 143 #define LNB_CMD_OFF 5 144 #define LNB_CMD_DISEQC 6 145 146 #define LNB_BUSY BIT_ULL(4) 147 #define LNB_TONE BIT_ULL(15) 148 149 #define LNB_BUF_LEVEL(i) (LNB_BASE + (i) * 0x20 + 0x10) 150 #define LNB_BUF_WRITE(i) (LNB_BASE + (i) * 0x20 + 0x14) 151 152 #endif /* __DDBRIDGE_REGS_H__ */ 153