1 /* 2 * ddbridge.c: Digital Devices PCIe bridge driver 3 * 4 * Copyright (C) 2010-2011 Digital Devices GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * version 2 only, as published by the Free Software Foundation. 9 * 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * To obtain the license, point your browser to 17 * http://www.gnu.org/copyleft/gpl.html 18 */ 19 20 #include <linux/module.h> 21 #include <linux/init.h> 22 #include <linux/interrupt.h> 23 #include <linux/delay.h> 24 #include <linux/slab.h> 25 #include <linux/poll.h> 26 #include <linux/io.h> 27 #include <linux/pci.h> 28 #include <linux/pci_ids.h> 29 #include <linux/timer.h> 30 #include <linux/i2c.h> 31 #include <linux/swab.h> 32 #include <linux/vmalloc.h> 33 #include "ddbridge.h" 34 35 #include "ddbridge-regs.h" 36 37 #include "tda18271c2dd.h" 38 #include "stv6110x.h" 39 #include "stv090x.h" 40 #include "lnbh24.h" 41 #include "drxk.h" 42 43 DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); 44 45 /* MSI had problems with lost interrupts, fixed but needs testing */ 46 #undef CONFIG_PCI_MSI 47 48 /******************************************************************************/ 49 50 static int i2c_read(struct i2c_adapter *adapter, u8 adr, u8 *val) 51 { 52 struct i2c_msg msgs[1] = {{.addr = adr, .flags = I2C_M_RD, 53 .buf = val, .len = 1 } }; 54 return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1; 55 } 56 57 static int i2c_read_reg(struct i2c_adapter *adapter, u8 adr, u8 reg, u8 *val) 58 { 59 struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, 60 .buf = ®, .len = 1 }, 61 {.addr = adr, .flags = I2C_M_RD, 62 .buf = val, .len = 1 } }; 63 return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1; 64 } 65 66 static int i2c_read_reg16(struct i2c_adapter *adapter, u8 adr, 67 u16 reg, u8 *val) 68 { 69 u8 msg[2] = {reg>>8, reg&0xff}; 70 struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, 71 .buf = msg, .len = 2}, 72 {.addr = adr, .flags = I2C_M_RD, 73 .buf = val, .len = 1} }; 74 return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1; 75 } 76 77 static int ddb_i2c_cmd(struct ddb_i2c *i2c, u32 adr, u32 cmd) 78 { 79 struct ddb *dev = i2c->dev; 80 long stat; 81 u32 val; 82 83 i2c->done = 0; 84 ddbwritel((adr << 9) | cmd, i2c->regs + I2C_COMMAND); 85 stat = wait_event_timeout(i2c->wq, i2c->done == 1, HZ); 86 if (stat == 0) { 87 printk(KERN_ERR "I2C timeout\n"); 88 { /* MSI debugging*/ 89 u32 istat = ddbreadl(INTERRUPT_STATUS); 90 printk(KERN_ERR "IRS %08x\n", istat); 91 ddbwritel(istat, INTERRUPT_ACK); 92 } 93 return -EIO; 94 } 95 val = ddbreadl(i2c->regs+I2C_COMMAND); 96 if (val & 0x70000) 97 return -EIO; 98 return 0; 99 } 100 101 static int ddb_i2c_master_xfer(struct i2c_adapter *adapter, 102 struct i2c_msg msg[], int num) 103 { 104 struct ddb_i2c *i2c = (struct ddb_i2c *)i2c_get_adapdata(adapter); 105 struct ddb *dev = i2c->dev; 106 u8 addr = 0; 107 108 if (num) 109 addr = msg[0].addr; 110 111 if (num == 2 && msg[1].flags & I2C_M_RD && 112 !(msg[0].flags & I2C_M_RD)) { 113 memcpy_toio(dev->regs + I2C_TASKMEM_BASE + i2c->wbuf, 114 msg[0].buf, msg[0].len); 115 ddbwritel(msg[0].len|(msg[1].len << 16), 116 i2c->regs+I2C_TASKLENGTH); 117 if (!ddb_i2c_cmd(i2c, addr, 1)) { 118 memcpy_fromio(msg[1].buf, 119 dev->regs + I2C_TASKMEM_BASE + i2c->rbuf, 120 msg[1].len); 121 return num; 122 } 123 } 124 125 if (num == 1 && !(msg[0].flags & I2C_M_RD)) { 126 ddbcpyto(I2C_TASKMEM_BASE + i2c->wbuf, msg[0].buf, msg[0].len); 127 ddbwritel(msg[0].len, i2c->regs + I2C_TASKLENGTH); 128 if (!ddb_i2c_cmd(i2c, addr, 2)) 129 return num; 130 } 131 if (num == 1 && (msg[0].flags & I2C_M_RD)) { 132 ddbwritel(msg[0].len << 16, i2c->regs + I2C_TASKLENGTH); 133 if (!ddb_i2c_cmd(i2c, addr, 3)) { 134 ddbcpyfrom(msg[0].buf, 135 I2C_TASKMEM_BASE + i2c->rbuf, msg[0].len); 136 return num; 137 } 138 } 139 return -EIO; 140 } 141 142 143 static u32 ddb_i2c_functionality(struct i2c_adapter *adap) 144 { 145 return I2C_FUNC_SMBUS_EMUL; 146 } 147 148 static struct i2c_algorithm ddb_i2c_algo = { 149 .master_xfer = ddb_i2c_master_xfer, 150 .functionality = ddb_i2c_functionality, 151 }; 152 153 static void ddb_i2c_release(struct ddb *dev) 154 { 155 int i; 156 struct ddb_i2c *i2c; 157 struct i2c_adapter *adap; 158 159 for (i = 0; i < dev->info->port_num; i++) { 160 i2c = &dev->i2c[i]; 161 adap = &i2c->adap; 162 i2c_del_adapter(adap); 163 } 164 } 165 166 static int ddb_i2c_init(struct ddb *dev) 167 { 168 int i, j, stat = 0; 169 struct ddb_i2c *i2c; 170 struct i2c_adapter *adap; 171 172 for (i = 0; i < dev->info->port_num; i++) { 173 i2c = &dev->i2c[i]; 174 i2c->dev = dev; 175 i2c->nr = i; 176 i2c->wbuf = i * (I2C_TASKMEM_SIZE / 4); 177 i2c->rbuf = i2c->wbuf + (I2C_TASKMEM_SIZE / 8); 178 i2c->regs = 0x80 + i * 0x20; 179 ddbwritel(I2C_SPEED_100, i2c->regs + I2C_TIMING); 180 ddbwritel((i2c->rbuf << 16) | i2c->wbuf, 181 i2c->regs + I2C_TASKADDRESS); 182 init_waitqueue_head(&i2c->wq); 183 184 adap = &i2c->adap; 185 i2c_set_adapdata(adap, i2c); 186 #ifdef I2C_ADAP_CLASS_TV_DIGITAL 187 adap->class = I2C_ADAP_CLASS_TV_DIGITAL|I2C_CLASS_TV_ANALOG; 188 #else 189 #ifdef I2C_CLASS_TV_ANALOG 190 adap->class = I2C_CLASS_TV_ANALOG; 191 #endif 192 #endif 193 strcpy(adap->name, "ddbridge"); 194 adap->algo = &ddb_i2c_algo; 195 adap->algo_data = (void *)i2c; 196 adap->dev.parent = &dev->pdev->dev; 197 stat = i2c_add_adapter(adap); 198 if (stat) 199 break; 200 } 201 if (stat) 202 for (j = 0; j < i; j++) { 203 i2c = &dev->i2c[j]; 204 adap = &i2c->adap; 205 i2c_del_adapter(adap); 206 } 207 return stat; 208 } 209 210 211 /******************************************************************************/ 212 /******************************************************************************/ 213 /******************************************************************************/ 214 215 #if 0 216 static void set_table(struct ddb *dev, u32 off, 217 dma_addr_t *pbuf, u32 num) 218 { 219 u32 i, base; 220 u64 mem; 221 222 base = DMA_BASE_ADDRESS_TABLE + off; 223 for (i = 0; i < num; i++) { 224 mem = pbuf[i]; 225 ddbwritel(mem & 0xffffffff, base + i * 8); 226 ddbwritel(mem >> 32, base + i * 8 + 4); 227 } 228 } 229 #endif 230 231 static void ddb_address_table(struct ddb *dev) 232 { 233 u32 i, j, base; 234 u64 mem; 235 dma_addr_t *pbuf; 236 237 for (i = 0; i < dev->info->port_num * 2; i++) { 238 base = DMA_BASE_ADDRESS_TABLE + i * 0x100; 239 pbuf = dev->input[i].pbuf; 240 for (j = 0; j < dev->input[i].dma_buf_num; j++) { 241 mem = pbuf[j]; 242 ddbwritel(mem & 0xffffffff, base + j * 8); 243 ddbwritel(mem >> 32, base + j * 8 + 4); 244 } 245 } 246 for (i = 0; i < dev->info->port_num; i++) { 247 base = DMA_BASE_ADDRESS_TABLE + 0x800 + i * 0x100; 248 pbuf = dev->output[i].pbuf; 249 for (j = 0; j < dev->output[i].dma_buf_num; j++) { 250 mem = pbuf[j]; 251 ddbwritel(mem & 0xffffffff, base + j * 8); 252 ddbwritel(mem >> 32, base + j * 8 + 4); 253 } 254 } 255 } 256 257 static void io_free(struct pci_dev *pdev, u8 **vbuf, 258 dma_addr_t *pbuf, u32 size, int num) 259 { 260 int i; 261 262 for (i = 0; i < num; i++) { 263 if (vbuf[i]) { 264 pci_free_consistent(pdev, size, vbuf[i], pbuf[i]); 265 vbuf[i] = NULL; 266 } 267 } 268 } 269 270 static int io_alloc(struct pci_dev *pdev, u8 **vbuf, 271 dma_addr_t *pbuf, u32 size, int num) 272 { 273 int i; 274 275 for (i = 0; i < num; i++) { 276 vbuf[i] = pci_alloc_consistent(pdev, size, &pbuf[i]); 277 if (!vbuf[i]) 278 return -ENOMEM; 279 } 280 return 0; 281 } 282 283 static int ddb_buffers_alloc(struct ddb *dev) 284 { 285 int i; 286 struct ddb_port *port; 287 288 for (i = 0; i < dev->info->port_num; i++) { 289 port = &dev->port[i]; 290 switch (port->class) { 291 case DDB_PORT_TUNER: 292 if (io_alloc(dev->pdev, port->input[0]->vbuf, 293 port->input[0]->pbuf, 294 port->input[0]->dma_buf_size, 295 port->input[0]->dma_buf_num) < 0) 296 return -1; 297 if (io_alloc(dev->pdev, port->input[1]->vbuf, 298 port->input[1]->pbuf, 299 port->input[1]->dma_buf_size, 300 port->input[1]->dma_buf_num) < 0) 301 return -1; 302 break; 303 case DDB_PORT_CI: 304 if (io_alloc(dev->pdev, port->input[0]->vbuf, 305 port->input[0]->pbuf, 306 port->input[0]->dma_buf_size, 307 port->input[0]->dma_buf_num) < 0) 308 return -1; 309 if (io_alloc(dev->pdev, port->output->vbuf, 310 port->output->pbuf, 311 port->output->dma_buf_size, 312 port->output->dma_buf_num) < 0) 313 return -1; 314 break; 315 default: 316 break; 317 } 318 } 319 ddb_address_table(dev); 320 return 0; 321 } 322 323 static void ddb_buffers_free(struct ddb *dev) 324 { 325 int i; 326 struct ddb_port *port; 327 328 for (i = 0; i < dev->info->port_num; i++) { 329 port = &dev->port[i]; 330 io_free(dev->pdev, port->input[0]->vbuf, 331 port->input[0]->pbuf, 332 port->input[0]->dma_buf_size, 333 port->input[0]->dma_buf_num); 334 io_free(dev->pdev, port->input[1]->vbuf, 335 port->input[1]->pbuf, 336 port->input[1]->dma_buf_size, 337 port->input[1]->dma_buf_num); 338 io_free(dev->pdev, port->output->vbuf, 339 port->output->pbuf, 340 port->output->dma_buf_size, 341 port->output->dma_buf_num); 342 } 343 } 344 345 static void ddb_input_start(struct ddb_input *input) 346 { 347 struct ddb *dev = input->port->dev; 348 349 spin_lock_irq(&input->lock); 350 input->cbuf = 0; 351 input->coff = 0; 352 353 /* reset */ 354 ddbwritel(0, TS_INPUT_CONTROL(input->nr)); 355 ddbwritel(2, TS_INPUT_CONTROL(input->nr)); 356 ddbwritel(0, TS_INPUT_CONTROL(input->nr)); 357 358 ddbwritel((1 << 16) | 359 (input->dma_buf_num << 11) | 360 (input->dma_buf_size >> 7), 361 DMA_BUFFER_SIZE(input->nr)); 362 ddbwritel(0, DMA_BUFFER_ACK(input->nr)); 363 364 ddbwritel(1, DMA_BASE_WRITE); 365 ddbwritel(3, DMA_BUFFER_CONTROL(input->nr)); 366 ddbwritel(9, TS_INPUT_CONTROL(input->nr)); 367 input->running = 1; 368 spin_unlock_irq(&input->lock); 369 } 370 371 static void ddb_input_stop(struct ddb_input *input) 372 { 373 struct ddb *dev = input->port->dev; 374 375 spin_lock_irq(&input->lock); 376 ddbwritel(0, TS_INPUT_CONTROL(input->nr)); 377 ddbwritel(0, DMA_BUFFER_CONTROL(input->nr)); 378 input->running = 0; 379 spin_unlock_irq(&input->lock); 380 } 381 382 static void ddb_output_start(struct ddb_output *output) 383 { 384 struct ddb *dev = output->port->dev; 385 386 spin_lock_irq(&output->lock); 387 output->cbuf = 0; 388 output->coff = 0; 389 ddbwritel(0, TS_OUTPUT_CONTROL(output->nr)); 390 ddbwritel(2, TS_OUTPUT_CONTROL(output->nr)); 391 ddbwritel(0, TS_OUTPUT_CONTROL(output->nr)); 392 ddbwritel(0x3c, TS_OUTPUT_CONTROL(output->nr)); 393 ddbwritel((1 << 16) | 394 (output->dma_buf_num << 11) | 395 (output->dma_buf_size >> 7), 396 DMA_BUFFER_SIZE(output->nr + 8)); 397 ddbwritel(0, DMA_BUFFER_ACK(output->nr + 8)); 398 399 ddbwritel(1, DMA_BASE_READ); 400 ddbwritel(3, DMA_BUFFER_CONTROL(output->nr + 8)); 401 /* ddbwritel(0xbd, TS_OUTPUT_CONTROL(output->nr)); */ 402 ddbwritel(0x1d, TS_OUTPUT_CONTROL(output->nr)); 403 output->running = 1; 404 spin_unlock_irq(&output->lock); 405 } 406 407 static void ddb_output_stop(struct ddb_output *output) 408 { 409 struct ddb *dev = output->port->dev; 410 411 spin_lock_irq(&output->lock); 412 ddbwritel(0, TS_OUTPUT_CONTROL(output->nr)); 413 ddbwritel(0, DMA_BUFFER_CONTROL(output->nr + 8)); 414 output->running = 0; 415 spin_unlock_irq(&output->lock); 416 } 417 418 static u32 ddb_output_free(struct ddb_output *output) 419 { 420 u32 idx, off, stat = output->stat; 421 s32 diff; 422 423 idx = (stat >> 11) & 0x1f; 424 off = (stat & 0x7ff) << 7; 425 426 if (output->cbuf != idx) { 427 if ((((output->cbuf + 1) % output->dma_buf_num) == idx) && 428 (output->dma_buf_size - output->coff <= 188)) 429 return 0; 430 return 188; 431 } 432 diff = off - output->coff; 433 if (diff <= 0 || diff > 188) 434 return 188; 435 return 0; 436 } 437 438 static ssize_t ddb_output_write(struct ddb_output *output, 439 const __user u8 *buf, size_t count) 440 { 441 struct ddb *dev = output->port->dev; 442 u32 idx, off, stat = output->stat; 443 u32 left = count, len; 444 445 idx = (stat >> 11) & 0x1f; 446 off = (stat & 0x7ff) << 7; 447 448 while (left) { 449 len = output->dma_buf_size - output->coff; 450 if ((((output->cbuf + 1) % output->dma_buf_num) == idx) && 451 (off == 0)) { 452 if (len <= 188) 453 break; 454 len -= 188; 455 } 456 if (output->cbuf == idx) { 457 if (off > output->coff) { 458 #if 1 459 len = off - output->coff; 460 len -= (len % 188); 461 if (len <= 188) 462 463 #endif 464 break; 465 len -= 188; 466 } 467 } 468 if (len > left) 469 len = left; 470 if (copy_from_user(output->vbuf[output->cbuf] + output->coff, 471 buf, len)) 472 return -EIO; 473 left -= len; 474 buf += len; 475 output->coff += len; 476 if (output->coff == output->dma_buf_size) { 477 output->coff = 0; 478 output->cbuf = ((output->cbuf + 1) % output->dma_buf_num); 479 } 480 ddbwritel((output->cbuf << 11) | (output->coff >> 7), 481 DMA_BUFFER_ACK(output->nr + 8)); 482 } 483 return count - left; 484 } 485 486 static u32 ddb_input_avail(struct ddb_input *input) 487 { 488 struct ddb *dev = input->port->dev; 489 u32 idx, off, stat = input->stat; 490 u32 ctrl = ddbreadl(DMA_BUFFER_CONTROL(input->nr)); 491 492 idx = (stat >> 11) & 0x1f; 493 off = (stat & 0x7ff) << 7; 494 495 if (ctrl & 4) { 496 printk(KERN_ERR "IA %d %d %08x\n", idx, off, ctrl); 497 ddbwritel(input->stat, DMA_BUFFER_ACK(input->nr)); 498 return 0; 499 } 500 if (input->cbuf != idx) 501 return 188; 502 return 0; 503 } 504 505 static ssize_t ddb_input_read(struct ddb_input *input, __user u8 *buf, size_t count) 506 { 507 struct ddb *dev = input->port->dev; 508 u32 left = count; 509 u32 idx, free, stat = input->stat; 510 int ret; 511 512 idx = (stat >> 11) & 0x1f; 513 514 while (left) { 515 if (input->cbuf == idx) 516 return count - left; 517 free = input->dma_buf_size - input->coff; 518 if (free > left) 519 free = left; 520 ret = copy_to_user(buf, input->vbuf[input->cbuf] + 521 input->coff, free); 522 if (ret) 523 return -EFAULT; 524 input->coff += free; 525 if (input->coff == input->dma_buf_size) { 526 input->coff = 0; 527 input->cbuf = (input->cbuf+1) % input->dma_buf_num; 528 } 529 left -= free; 530 ddbwritel((input->cbuf << 11) | (input->coff >> 7), 531 DMA_BUFFER_ACK(input->nr)); 532 } 533 return count; 534 } 535 536 /******************************************************************************/ 537 /******************************************************************************/ 538 /******************************************************************************/ 539 540 #if 0 541 static struct ddb_input *fe2input(struct ddb *dev, struct dvb_frontend *fe) 542 { 543 int i; 544 545 for (i = 0; i < dev->info->port_num * 2; i++) { 546 if (dev->input[i].fe == fe) 547 return &dev->input[i]; 548 } 549 return NULL; 550 } 551 #endif 552 553 static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable) 554 { 555 struct ddb_input *input = fe->sec_priv; 556 struct ddb_port *port = input->port; 557 int status; 558 559 if (enable) { 560 mutex_lock(&port->i2c_gate_lock); 561 status = input->gate_ctrl(fe, 1); 562 } else { 563 status = input->gate_ctrl(fe, 0); 564 mutex_unlock(&port->i2c_gate_lock); 565 } 566 return status; 567 } 568 569 static int demod_attach_drxk(struct ddb_input *input) 570 { 571 struct i2c_adapter *i2c = &input->port->i2c->adap; 572 struct dvb_frontend *fe; 573 struct drxk_config config; 574 575 memset(&config, 0, sizeof(config)); 576 config.microcode_name = "drxk_a3.mc"; 577 config.qam_demod_parameter_count = 4; 578 config.adr = 0x29 + (input->nr & 1); 579 580 fe = input->fe = dvb_attach(drxk_attach, &config, i2c); 581 if (!input->fe) { 582 printk(KERN_ERR "No DRXK found!\n"); 583 return -ENODEV; 584 } 585 fe->sec_priv = input; 586 input->gate_ctrl = fe->ops.i2c_gate_ctrl; 587 fe->ops.i2c_gate_ctrl = drxk_gate_ctrl; 588 return 0; 589 } 590 591 static int tuner_attach_tda18271(struct ddb_input *input) 592 { 593 struct i2c_adapter *i2c = &input->port->i2c->adap; 594 struct dvb_frontend *fe; 595 596 if (input->fe->ops.i2c_gate_ctrl) 597 input->fe->ops.i2c_gate_ctrl(input->fe, 1); 598 fe = dvb_attach(tda18271c2dd_attach, input->fe, i2c, 0x60); 599 if (!fe) { 600 printk(KERN_ERR "No TDA18271 found!\n"); 601 return -ENODEV; 602 } 603 if (input->fe->ops.i2c_gate_ctrl) 604 input->fe->ops.i2c_gate_ctrl(input->fe, 0); 605 return 0; 606 } 607 608 /******************************************************************************/ 609 /******************************************************************************/ 610 /******************************************************************************/ 611 612 static struct stv090x_config stv0900 = { 613 .device = STV0900, 614 .demod_mode = STV090x_DUAL, 615 .clk_mode = STV090x_CLK_EXT, 616 617 .xtal = 27000000, 618 .address = 0x69, 619 620 .ts1_mode = STV090x_TSMODE_SERIAL_PUNCTURED, 621 .ts2_mode = STV090x_TSMODE_SERIAL_PUNCTURED, 622 623 .repeater_level = STV090x_RPTLEVEL_16, 624 625 .adc1_range = STV090x_ADC_1Vpp, 626 .adc2_range = STV090x_ADC_1Vpp, 627 628 .diseqc_envelope_mode = true, 629 }; 630 631 static struct stv090x_config stv0900_aa = { 632 .device = STV0900, 633 .demod_mode = STV090x_DUAL, 634 .clk_mode = STV090x_CLK_EXT, 635 636 .xtal = 27000000, 637 .address = 0x68, 638 639 .ts1_mode = STV090x_TSMODE_SERIAL_PUNCTURED, 640 .ts2_mode = STV090x_TSMODE_SERIAL_PUNCTURED, 641 642 .repeater_level = STV090x_RPTLEVEL_16, 643 644 .adc1_range = STV090x_ADC_1Vpp, 645 .adc2_range = STV090x_ADC_1Vpp, 646 647 .diseqc_envelope_mode = true, 648 }; 649 650 static struct stv6110x_config stv6110a = { 651 .addr = 0x60, 652 .refclk = 27000000, 653 .clk_div = 1, 654 }; 655 656 static struct stv6110x_config stv6110b = { 657 .addr = 0x63, 658 .refclk = 27000000, 659 .clk_div = 1, 660 }; 661 662 static int demod_attach_stv0900(struct ddb_input *input, int type) 663 { 664 struct i2c_adapter *i2c = &input->port->i2c->adap; 665 struct stv090x_config *feconf = type ? &stv0900_aa : &stv0900; 666 667 input->fe = dvb_attach(stv090x_attach, feconf, i2c, 668 (input->nr & 1) ? STV090x_DEMODULATOR_1 669 : STV090x_DEMODULATOR_0); 670 if (!input->fe) { 671 printk(KERN_ERR "No STV0900 found!\n"); 672 return -ENODEV; 673 } 674 if (!dvb_attach(lnbh24_attach, input->fe, i2c, 0, 675 0, (input->nr & 1) ? 676 (0x09 - type) : (0x0b - type))) { 677 printk(KERN_ERR "No LNBH24 found!\n"); 678 return -ENODEV; 679 } 680 return 0; 681 } 682 683 static int tuner_attach_stv6110(struct ddb_input *input, int type) 684 { 685 struct i2c_adapter *i2c = &input->port->i2c->adap; 686 struct stv090x_config *feconf = type ? &stv0900_aa : &stv0900; 687 struct stv6110x_config *tunerconf = (input->nr & 1) ? 688 &stv6110b : &stv6110a; 689 const struct stv6110x_devctl *ctl; 690 691 ctl = dvb_attach(stv6110x_attach, input->fe, tunerconf, i2c); 692 if (!ctl) { 693 printk(KERN_ERR "No STV6110X found!\n"); 694 return -ENODEV; 695 } 696 printk(KERN_INFO "attach tuner input %d adr %02x\n", 697 input->nr, tunerconf->addr); 698 699 feconf->tuner_init = ctl->tuner_init; 700 feconf->tuner_sleep = ctl->tuner_sleep; 701 feconf->tuner_set_mode = ctl->tuner_set_mode; 702 feconf->tuner_set_frequency = ctl->tuner_set_frequency; 703 feconf->tuner_get_frequency = ctl->tuner_get_frequency; 704 feconf->tuner_set_bandwidth = ctl->tuner_set_bandwidth; 705 feconf->tuner_get_bandwidth = ctl->tuner_get_bandwidth; 706 feconf->tuner_set_bbgain = ctl->tuner_set_bbgain; 707 feconf->tuner_get_bbgain = ctl->tuner_get_bbgain; 708 feconf->tuner_set_refclk = ctl->tuner_set_refclk; 709 feconf->tuner_get_status = ctl->tuner_get_status; 710 711 return 0; 712 } 713 714 static int my_dvb_dmx_ts_card_init(struct dvb_demux *dvbdemux, char *id, 715 int (*start_feed)(struct dvb_demux_feed *), 716 int (*stop_feed)(struct dvb_demux_feed *), 717 void *priv) 718 { 719 dvbdemux->priv = priv; 720 721 dvbdemux->filternum = 256; 722 dvbdemux->feednum = 256; 723 dvbdemux->start_feed = start_feed; 724 dvbdemux->stop_feed = stop_feed; 725 dvbdemux->write_to_decoder = NULL; 726 dvbdemux->dmx.capabilities = (DMX_TS_FILTERING | 727 DMX_SECTION_FILTERING | 728 DMX_MEMORY_BASED_FILTERING); 729 return dvb_dmx_init(dvbdemux); 730 } 731 732 static int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev, 733 struct dvb_demux *dvbdemux, 734 struct dmx_frontend *hw_frontend, 735 struct dmx_frontend *mem_frontend, 736 struct dvb_adapter *dvb_adapter) 737 { 738 int ret; 739 740 dmxdev->filternum = 256; 741 dmxdev->demux = &dvbdemux->dmx; 742 dmxdev->capabilities = 0; 743 ret = dvb_dmxdev_init(dmxdev, dvb_adapter); 744 if (ret < 0) 745 return ret; 746 747 hw_frontend->source = DMX_FRONTEND_0; 748 dvbdemux->dmx.add_frontend(&dvbdemux->dmx, hw_frontend); 749 mem_frontend->source = DMX_MEMORY_FE; 750 dvbdemux->dmx.add_frontend(&dvbdemux->dmx, mem_frontend); 751 return dvbdemux->dmx.connect_frontend(&dvbdemux->dmx, hw_frontend); 752 } 753 754 static int start_feed(struct dvb_demux_feed *dvbdmxfeed) 755 { 756 struct dvb_demux *dvbdmx = dvbdmxfeed->demux; 757 struct ddb_input *input = dvbdmx->priv; 758 759 if (!input->users) 760 ddb_input_start(input); 761 762 return ++input->users; 763 } 764 765 static int stop_feed(struct dvb_demux_feed *dvbdmxfeed) 766 { 767 struct dvb_demux *dvbdmx = dvbdmxfeed->demux; 768 struct ddb_input *input = dvbdmx->priv; 769 770 if (--input->users) 771 return input->users; 772 773 ddb_input_stop(input); 774 return 0; 775 } 776 777 778 static void dvb_input_detach(struct ddb_input *input) 779 { 780 struct dvb_adapter *adap = &input->adap; 781 struct dvb_demux *dvbdemux = &input->demux; 782 783 switch (input->attached) { 784 case 5: 785 if (input->fe2) 786 dvb_unregister_frontend(input->fe2); 787 if (input->fe) { 788 dvb_unregister_frontend(input->fe); 789 dvb_frontend_detach(input->fe); 790 input->fe = NULL; 791 } 792 case 4: 793 dvb_net_release(&input->dvbnet); 794 795 case 3: 796 dvbdemux->dmx.close(&dvbdemux->dmx); 797 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, 798 &input->hw_frontend); 799 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, 800 &input->mem_frontend); 801 dvb_dmxdev_release(&input->dmxdev); 802 803 case 2: 804 dvb_dmx_release(&input->demux); 805 806 case 1: 807 dvb_unregister_adapter(adap); 808 } 809 input->attached = 0; 810 } 811 812 static int dvb_input_attach(struct ddb_input *input) 813 { 814 int ret; 815 struct ddb_port *port = input->port; 816 struct dvb_adapter *adap = &input->adap; 817 struct dvb_demux *dvbdemux = &input->demux; 818 819 ret = dvb_register_adapter(adap, "DDBridge", THIS_MODULE, 820 &input->port->dev->pdev->dev, 821 adapter_nr); 822 if (ret < 0) { 823 printk(KERN_ERR "ddbridge: Could not register adapter.Check if you enabled enough adapters in dvb-core!\n"); 824 return ret; 825 } 826 input->attached = 1; 827 828 ret = my_dvb_dmx_ts_card_init(dvbdemux, "SW demux", 829 start_feed, 830 stop_feed, input); 831 if (ret < 0) 832 return ret; 833 input->attached = 2; 834 835 ret = my_dvb_dmxdev_ts_card_init(&input->dmxdev, &input->demux, 836 &input->hw_frontend, 837 &input->mem_frontend, adap); 838 if (ret < 0) 839 return ret; 840 input->attached = 3; 841 842 ret = dvb_net_init(adap, &input->dvbnet, input->dmxdev.demux); 843 if (ret < 0) 844 return ret; 845 input->attached = 4; 846 847 input->fe = NULL; 848 switch (port->type) { 849 case DDB_TUNER_DVBS_ST: 850 if (demod_attach_stv0900(input, 0) < 0) 851 return -ENODEV; 852 if (tuner_attach_stv6110(input, 0) < 0) 853 return -ENODEV; 854 if (input->fe) { 855 if (dvb_register_frontend(adap, input->fe) < 0) 856 return -ENODEV; 857 } 858 break; 859 case DDB_TUNER_DVBS_ST_AA: 860 if (demod_attach_stv0900(input, 1) < 0) 861 return -ENODEV; 862 if (tuner_attach_stv6110(input, 1) < 0) 863 return -ENODEV; 864 if (input->fe) { 865 if (dvb_register_frontend(adap, input->fe) < 0) 866 return -ENODEV; 867 } 868 break; 869 case DDB_TUNER_DVBCT_TR: 870 if (demod_attach_drxk(input) < 0) 871 return -ENODEV; 872 if (tuner_attach_tda18271(input) < 0) 873 return -ENODEV; 874 if (dvb_register_frontend(adap, input->fe) < 0) 875 return -ENODEV; 876 if (input->fe2) { 877 if (dvb_register_frontend(adap, input->fe2) < 0) 878 return -ENODEV; 879 input->fe2->tuner_priv = input->fe->tuner_priv; 880 memcpy(&input->fe2->ops.tuner_ops, 881 &input->fe->ops.tuner_ops, 882 sizeof(struct dvb_tuner_ops)); 883 } 884 break; 885 } 886 input->attached = 5; 887 return 0; 888 } 889 890 /****************************************************************************/ 891 /****************************************************************************/ 892 893 static ssize_t ts_write(struct file *file, const __user char *buf, 894 size_t count, loff_t *ppos) 895 { 896 struct dvb_device *dvbdev = file->private_data; 897 struct ddb_output *output = dvbdev->priv; 898 size_t left = count; 899 int stat; 900 901 while (left) { 902 if (ddb_output_free(output) < 188) { 903 if (file->f_flags & O_NONBLOCK) 904 break; 905 if (wait_event_interruptible( 906 output->wq, ddb_output_free(output) >= 188) < 0) 907 break; 908 } 909 stat = ddb_output_write(output, buf, left); 910 if (stat < 0) 911 break; 912 buf += stat; 913 left -= stat; 914 } 915 return (left == count) ? -EAGAIN : (count - left); 916 } 917 918 static ssize_t ts_read(struct file *file, __user char *buf, 919 size_t count, loff_t *ppos) 920 { 921 struct dvb_device *dvbdev = file->private_data; 922 struct ddb_output *output = dvbdev->priv; 923 struct ddb_input *input = output->port->input[0]; 924 int left, read; 925 926 count -= count % 188; 927 left = count; 928 while (left) { 929 if (ddb_input_avail(input) < 188) { 930 if (file->f_flags & O_NONBLOCK) 931 break; 932 if (wait_event_interruptible( 933 input->wq, ddb_input_avail(input) >= 188) < 0) 934 break; 935 } 936 read = ddb_input_read(input, buf, left); 937 if (read < 0) 938 return read; 939 left -= read; 940 buf += read; 941 } 942 return (left == count) ? -EAGAIN : (count - left); 943 } 944 945 static unsigned int ts_poll(struct file *file, poll_table *wait) 946 { 947 /* 948 struct dvb_device *dvbdev = file->private_data; 949 struct ddb_output *output = dvbdev->priv; 950 struct ddb_input *input = output->port->input[0]; 951 */ 952 unsigned int mask = 0; 953 954 #if 0 955 if (data_avail_to_read) 956 mask |= POLLIN | POLLRDNORM; 957 if (data_avail_to_write) 958 mask |= POLLOUT | POLLWRNORM; 959 960 poll_wait(file, &read_queue, wait); 961 poll_wait(file, &write_queue, wait); 962 #endif 963 return mask; 964 } 965 966 static const struct file_operations ci_fops = { 967 .owner = THIS_MODULE, 968 .read = ts_read, 969 .write = ts_write, 970 .open = dvb_generic_open, 971 .release = dvb_generic_release, 972 .poll = ts_poll, 973 }; 974 975 static struct dvb_device dvbdev_ci = { 976 .readers = -1, 977 .writers = -1, 978 .users = -1, 979 .fops = &ci_fops, 980 }; 981 982 /****************************************************************************/ 983 /****************************************************************************/ 984 /****************************************************************************/ 985 986 static void input_tasklet(unsigned long data) 987 { 988 struct ddb_input *input = (struct ddb_input *) data; 989 struct ddb *dev = input->port->dev; 990 991 spin_lock(&input->lock); 992 if (!input->running) { 993 spin_unlock(&input->lock); 994 return; 995 } 996 input->stat = ddbreadl(DMA_BUFFER_CURRENT(input->nr)); 997 998 if (input->port->class == DDB_PORT_TUNER) { 999 if (4&ddbreadl(DMA_BUFFER_CONTROL(input->nr))) 1000 printk(KERN_ERR "Overflow input %d\n", input->nr); 1001 while (input->cbuf != ((input->stat >> 11) & 0x1f) 1002 || (4&ddbreadl(DMA_BUFFER_CONTROL(input->nr)))) { 1003 dvb_dmx_swfilter_packets(&input->demux, 1004 input->vbuf[input->cbuf], 1005 input->dma_buf_size / 188); 1006 1007 input->cbuf = (input->cbuf + 1) % input->dma_buf_num; 1008 ddbwritel((input->cbuf << 11), 1009 DMA_BUFFER_ACK(input->nr)); 1010 input->stat = ddbreadl(DMA_BUFFER_CURRENT(input->nr)); 1011 } 1012 } 1013 if (input->port->class == DDB_PORT_CI) 1014 wake_up(&input->wq); 1015 spin_unlock(&input->lock); 1016 } 1017 1018 static void output_tasklet(unsigned long data) 1019 { 1020 struct ddb_output *output = (struct ddb_output *) data; 1021 struct ddb *dev = output->port->dev; 1022 1023 spin_lock(&output->lock); 1024 if (!output->running) { 1025 spin_unlock(&output->lock); 1026 return; 1027 } 1028 output->stat = ddbreadl(DMA_BUFFER_CURRENT(output->nr + 8)); 1029 wake_up(&output->wq); 1030 spin_unlock(&output->lock); 1031 } 1032 1033 1034 static struct cxd2099_cfg cxd_cfg = { 1035 .bitrate = 62000, 1036 .adr = 0x40, 1037 .polarity = 1, 1038 .clock_mode = 1, 1039 }; 1040 1041 static int ddb_ci_attach(struct ddb_port *port) 1042 { 1043 int ret; 1044 1045 ret = dvb_register_adapter(&port->output->adap, 1046 "DDBridge", 1047 THIS_MODULE, 1048 &port->dev->pdev->dev, 1049 adapter_nr); 1050 if (ret < 0) 1051 return ret; 1052 port->en = cxd2099_attach(&cxd_cfg, port, &port->i2c->adap); 1053 if (!port->en) { 1054 dvb_unregister_adapter(&port->output->adap); 1055 return -ENODEV; 1056 } 1057 ddb_input_start(port->input[0]); 1058 ddb_output_start(port->output); 1059 dvb_ca_en50221_init(&port->output->adap, 1060 port->en, 0, 1); 1061 ret = dvb_register_device(&port->output->adap, &port->output->dev, 1062 &dvbdev_ci, (void *) port->output, 1063 DVB_DEVICE_SEC, 0); 1064 return ret; 1065 } 1066 1067 static int ddb_port_attach(struct ddb_port *port) 1068 { 1069 int ret = 0; 1070 1071 switch (port->class) { 1072 case DDB_PORT_TUNER: 1073 ret = dvb_input_attach(port->input[0]); 1074 if (ret < 0) 1075 break; 1076 ret = dvb_input_attach(port->input[1]); 1077 break; 1078 case DDB_PORT_CI: 1079 ret = ddb_ci_attach(port); 1080 break; 1081 default: 1082 break; 1083 } 1084 if (ret < 0) 1085 printk(KERN_ERR "port_attach on port %d failed\n", port->nr); 1086 return ret; 1087 } 1088 1089 static int ddb_ports_attach(struct ddb *dev) 1090 { 1091 int i, ret = 0; 1092 struct ddb_port *port; 1093 1094 for (i = 0; i < dev->info->port_num; i++) { 1095 port = &dev->port[i]; 1096 ret = ddb_port_attach(port); 1097 if (ret < 0) 1098 break; 1099 } 1100 return ret; 1101 } 1102 1103 static void ddb_ports_detach(struct ddb *dev) 1104 { 1105 int i; 1106 struct ddb_port *port; 1107 1108 for (i = 0; i < dev->info->port_num; i++) { 1109 port = &dev->port[i]; 1110 switch (port->class) { 1111 case DDB_PORT_TUNER: 1112 dvb_input_detach(port->input[0]); 1113 dvb_input_detach(port->input[1]); 1114 break; 1115 case DDB_PORT_CI: 1116 dvb_unregister_device(port->output->dev); 1117 if (port->en) { 1118 ddb_input_stop(port->input[0]); 1119 ddb_output_stop(port->output); 1120 dvb_ca_en50221_release(port->en); 1121 kfree(port->en); 1122 port->en = NULL; 1123 dvb_unregister_adapter(&port->output->adap); 1124 } 1125 break; 1126 } 1127 } 1128 } 1129 1130 /****************************************************************************/ 1131 /****************************************************************************/ 1132 1133 static int port_has_ci(struct ddb_port *port) 1134 { 1135 u8 val; 1136 return i2c_read_reg(&port->i2c->adap, 0x40, 0, &val) ? 0 : 1; 1137 } 1138 1139 static int port_has_stv0900(struct ddb_port *port) 1140 { 1141 u8 val; 1142 if (i2c_read_reg16(&port->i2c->adap, 0x69, 0xf100, &val) < 0) 1143 return 0; 1144 return 1; 1145 } 1146 1147 static int port_has_stv0900_aa(struct ddb_port *port) 1148 { 1149 u8 val; 1150 if (i2c_read_reg16(&port->i2c->adap, 0x68, 0xf100, &val) < 0) 1151 return 0; 1152 return 1; 1153 } 1154 1155 static int port_has_drxks(struct ddb_port *port) 1156 { 1157 u8 val; 1158 if (i2c_read(&port->i2c->adap, 0x29, &val) < 0) 1159 return 0; 1160 if (i2c_read(&port->i2c->adap, 0x2a, &val) < 0) 1161 return 0; 1162 return 1; 1163 } 1164 1165 static void ddb_port_probe(struct ddb_port *port) 1166 { 1167 struct ddb *dev = port->dev; 1168 char *modname = "NO MODULE"; 1169 1170 port->class = DDB_PORT_NONE; 1171 1172 if (port_has_ci(port)) { 1173 modname = "CI"; 1174 port->class = DDB_PORT_CI; 1175 ddbwritel(I2C_SPEED_400, port->i2c->regs + I2C_TIMING); 1176 } else if (port_has_stv0900(port)) { 1177 modname = "DUAL DVB-S2"; 1178 port->class = DDB_PORT_TUNER; 1179 port->type = DDB_TUNER_DVBS_ST; 1180 ddbwritel(I2C_SPEED_100, port->i2c->regs + I2C_TIMING); 1181 } else if (port_has_stv0900_aa(port)) { 1182 modname = "DUAL DVB-S2"; 1183 port->class = DDB_PORT_TUNER; 1184 port->type = DDB_TUNER_DVBS_ST_AA; 1185 ddbwritel(I2C_SPEED_100, port->i2c->regs + I2C_TIMING); 1186 } else if (port_has_drxks(port)) { 1187 modname = "DUAL DVB-C/T"; 1188 port->class = DDB_PORT_TUNER; 1189 port->type = DDB_TUNER_DVBCT_TR; 1190 ddbwritel(I2C_SPEED_400, port->i2c->regs + I2C_TIMING); 1191 } 1192 printk(KERN_INFO "Port %d (TAB %d): %s\n", 1193 port->nr, port->nr+1, modname); 1194 } 1195 1196 static void ddb_input_init(struct ddb_port *port, int nr) 1197 { 1198 struct ddb *dev = port->dev; 1199 struct ddb_input *input = &dev->input[nr]; 1200 1201 input->nr = nr; 1202 input->port = port; 1203 input->dma_buf_num = INPUT_DMA_BUFS; 1204 input->dma_buf_size = INPUT_DMA_SIZE; 1205 ddbwritel(0, TS_INPUT_CONTROL(nr)); 1206 ddbwritel(2, TS_INPUT_CONTROL(nr)); 1207 ddbwritel(0, TS_INPUT_CONTROL(nr)); 1208 ddbwritel(0, DMA_BUFFER_ACK(nr)); 1209 tasklet_init(&input->tasklet, input_tasklet, (unsigned long) input); 1210 spin_lock_init(&input->lock); 1211 init_waitqueue_head(&input->wq); 1212 } 1213 1214 static void ddb_output_init(struct ddb_port *port, int nr) 1215 { 1216 struct ddb *dev = port->dev; 1217 struct ddb_output *output = &dev->output[nr]; 1218 output->nr = nr; 1219 output->port = port; 1220 output->dma_buf_num = OUTPUT_DMA_BUFS; 1221 output->dma_buf_size = OUTPUT_DMA_SIZE; 1222 1223 ddbwritel(0, TS_OUTPUT_CONTROL(nr)); 1224 ddbwritel(2, TS_OUTPUT_CONTROL(nr)); 1225 ddbwritel(0, TS_OUTPUT_CONTROL(nr)); 1226 tasklet_init(&output->tasklet, output_tasklet, (unsigned long) output); 1227 init_waitqueue_head(&output->wq); 1228 } 1229 1230 static void ddb_ports_init(struct ddb *dev) 1231 { 1232 int i; 1233 struct ddb_port *port; 1234 1235 for (i = 0; i < dev->info->port_num; i++) { 1236 port = &dev->port[i]; 1237 port->dev = dev; 1238 port->nr = i; 1239 port->i2c = &dev->i2c[i]; 1240 port->input[0] = &dev->input[2 * i]; 1241 port->input[1] = &dev->input[2 * i + 1]; 1242 port->output = &dev->output[i]; 1243 1244 mutex_init(&port->i2c_gate_lock); 1245 ddb_port_probe(port); 1246 ddb_input_init(port, 2 * i); 1247 ddb_input_init(port, 2 * i + 1); 1248 ddb_output_init(port, i); 1249 } 1250 } 1251 1252 static void ddb_ports_release(struct ddb *dev) 1253 { 1254 int i; 1255 struct ddb_port *port; 1256 1257 for (i = 0; i < dev->info->port_num; i++) { 1258 port = &dev->port[i]; 1259 port->dev = dev; 1260 tasklet_kill(&port->input[0]->tasklet); 1261 tasklet_kill(&port->input[1]->tasklet); 1262 tasklet_kill(&port->output->tasklet); 1263 } 1264 } 1265 1266 /****************************************************************************/ 1267 /****************************************************************************/ 1268 /****************************************************************************/ 1269 1270 static void irq_handle_i2c(struct ddb *dev, int n) 1271 { 1272 struct ddb_i2c *i2c = &dev->i2c[n]; 1273 1274 i2c->done = 1; 1275 wake_up(&i2c->wq); 1276 } 1277 1278 static irqreturn_t irq_handler(int irq, void *dev_id) 1279 { 1280 struct ddb *dev = (struct ddb *) dev_id; 1281 u32 s = ddbreadl(INTERRUPT_STATUS); 1282 1283 if (!s) 1284 return IRQ_NONE; 1285 1286 do { 1287 ddbwritel(s, INTERRUPT_ACK); 1288 1289 if (s & 0x00000001) 1290 irq_handle_i2c(dev, 0); 1291 if (s & 0x00000002) 1292 irq_handle_i2c(dev, 1); 1293 if (s & 0x00000004) 1294 irq_handle_i2c(dev, 2); 1295 if (s & 0x00000008) 1296 irq_handle_i2c(dev, 3); 1297 1298 if (s & 0x00000100) 1299 tasklet_schedule(&dev->input[0].tasklet); 1300 if (s & 0x00000200) 1301 tasklet_schedule(&dev->input[1].tasklet); 1302 if (s & 0x00000400) 1303 tasklet_schedule(&dev->input[2].tasklet); 1304 if (s & 0x00000800) 1305 tasklet_schedule(&dev->input[3].tasklet); 1306 if (s & 0x00001000) 1307 tasklet_schedule(&dev->input[4].tasklet); 1308 if (s & 0x00002000) 1309 tasklet_schedule(&dev->input[5].tasklet); 1310 if (s & 0x00004000) 1311 tasklet_schedule(&dev->input[6].tasklet); 1312 if (s & 0x00008000) 1313 tasklet_schedule(&dev->input[7].tasklet); 1314 1315 if (s & 0x00010000) 1316 tasklet_schedule(&dev->output[0].tasklet); 1317 if (s & 0x00020000) 1318 tasklet_schedule(&dev->output[1].tasklet); 1319 if (s & 0x00040000) 1320 tasklet_schedule(&dev->output[2].tasklet); 1321 if (s & 0x00080000) 1322 tasklet_schedule(&dev->output[3].tasklet); 1323 1324 /* if (s & 0x000f0000) printk(KERN_DEBUG "%08x\n", istat); */ 1325 } while ((s = ddbreadl(INTERRUPT_STATUS))); 1326 1327 return IRQ_HANDLED; 1328 } 1329 1330 /******************************************************************************/ 1331 /******************************************************************************/ 1332 /******************************************************************************/ 1333 1334 static int flashio(struct ddb *dev, u8 *wbuf, u32 wlen, u8 *rbuf, u32 rlen) 1335 { 1336 u32 data, shift; 1337 1338 if (wlen > 4) 1339 ddbwritel(1, SPI_CONTROL); 1340 while (wlen > 4) { 1341 /* FIXME: check for big-endian */ 1342 data = swab32(*(u32 *)wbuf); 1343 wbuf += 4; 1344 wlen -= 4; 1345 ddbwritel(data, SPI_DATA); 1346 while (ddbreadl(SPI_CONTROL) & 0x0004) 1347 ; 1348 } 1349 1350 if (rlen) 1351 ddbwritel(0x0001 | ((wlen << (8 + 3)) & 0x1f00), SPI_CONTROL); 1352 else 1353 ddbwritel(0x0003 | ((wlen << (8 + 3)) & 0x1f00), SPI_CONTROL); 1354 1355 data = 0; 1356 shift = ((4 - wlen) * 8); 1357 while (wlen) { 1358 data <<= 8; 1359 data |= *wbuf; 1360 wlen--; 1361 wbuf++; 1362 } 1363 if (shift) 1364 data <<= shift; 1365 ddbwritel(data, SPI_DATA); 1366 while (ddbreadl(SPI_CONTROL) & 0x0004) 1367 ; 1368 1369 if (!rlen) { 1370 ddbwritel(0, SPI_CONTROL); 1371 return 0; 1372 } 1373 if (rlen > 4) 1374 ddbwritel(1, SPI_CONTROL); 1375 1376 while (rlen > 4) { 1377 ddbwritel(0xffffffff, SPI_DATA); 1378 while (ddbreadl(SPI_CONTROL) & 0x0004) 1379 ; 1380 data = ddbreadl(SPI_DATA); 1381 *(u32 *) rbuf = swab32(data); 1382 rbuf += 4; 1383 rlen -= 4; 1384 } 1385 ddbwritel(0x0003 | ((rlen << (8 + 3)) & 0x1F00), SPI_CONTROL); 1386 ddbwritel(0xffffffff, SPI_DATA); 1387 while (ddbreadl(SPI_CONTROL) & 0x0004) 1388 ; 1389 1390 data = ddbreadl(SPI_DATA); 1391 ddbwritel(0, SPI_CONTROL); 1392 1393 if (rlen < 4) 1394 data <<= ((4 - rlen) * 8); 1395 1396 while (rlen > 0) { 1397 *rbuf = ((data >> 24) & 0xff); 1398 data <<= 8; 1399 rbuf++; 1400 rlen--; 1401 } 1402 return 0; 1403 } 1404 1405 #define DDB_MAGIC 'd' 1406 1407 struct ddb_flashio { 1408 __user __u8 *write_buf; 1409 __u32 write_len; 1410 __user __u8 *read_buf; 1411 __u32 read_len; 1412 }; 1413 1414 #define IOCTL_DDB_FLASHIO _IOWR(DDB_MAGIC, 0x00, struct ddb_flashio) 1415 1416 #define DDB_NAME "ddbridge" 1417 1418 static u32 ddb_num; 1419 static struct ddb *ddbs[32]; 1420 static struct class *ddb_class; 1421 static int ddb_major; 1422 1423 static int ddb_open(struct inode *inode, struct file *file) 1424 { 1425 struct ddb *dev = ddbs[iminor(inode)]; 1426 1427 file->private_data = dev; 1428 return 0; 1429 } 1430 1431 static long ddb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) 1432 { 1433 struct ddb *dev = file->private_data; 1434 __user void *parg = (__user void *)arg; 1435 int res; 1436 1437 switch (cmd) { 1438 case IOCTL_DDB_FLASHIO: 1439 { 1440 struct ddb_flashio fio; 1441 u8 *rbuf, *wbuf; 1442 1443 if (copy_from_user(&fio, parg, sizeof(fio))) 1444 return -EFAULT; 1445 1446 if (fio.write_len > 1028 || fio.read_len > 1028) 1447 return -EINVAL; 1448 if (fio.write_len + fio.read_len > 1028) 1449 return -EINVAL; 1450 1451 wbuf = &dev->iobuf[0]; 1452 rbuf = wbuf + fio.write_len; 1453 1454 if (copy_from_user(wbuf, fio.write_buf, fio.write_len)) 1455 return -EFAULT; 1456 res = flashio(dev, wbuf, fio.write_len, rbuf, fio.read_len); 1457 if (res) 1458 return res; 1459 if (copy_to_user(fio.read_buf, rbuf, fio.read_len)) 1460 return -EFAULT; 1461 break; 1462 } 1463 default: 1464 return -ENOTTY; 1465 } 1466 return 0; 1467 } 1468 1469 static const struct file_operations ddb_fops = { 1470 .unlocked_ioctl = ddb_ioctl, 1471 .open = ddb_open, 1472 }; 1473 1474 static char *ddb_devnode(struct device *device, umode_t *mode) 1475 { 1476 struct ddb *dev = dev_get_drvdata(device); 1477 1478 return kasprintf(GFP_KERNEL, "ddbridge/card%d", dev->nr); 1479 } 1480 1481 static int ddb_class_create(void) 1482 { 1483 ddb_major = register_chrdev(0, DDB_NAME, &ddb_fops); 1484 if (ddb_major < 0) 1485 return ddb_major; 1486 1487 ddb_class = class_create(THIS_MODULE, DDB_NAME); 1488 if (IS_ERR(ddb_class)) { 1489 unregister_chrdev(ddb_major, DDB_NAME); 1490 return PTR_ERR(ddb_class); 1491 } 1492 ddb_class->devnode = ddb_devnode; 1493 return 0; 1494 } 1495 1496 static void ddb_class_destroy(void) 1497 { 1498 class_destroy(ddb_class); 1499 unregister_chrdev(ddb_major, DDB_NAME); 1500 } 1501 1502 static int ddb_device_create(struct ddb *dev) 1503 { 1504 dev->nr = ddb_num++; 1505 dev->ddb_dev = device_create(ddb_class, NULL, 1506 MKDEV(ddb_major, dev->nr), 1507 dev, "ddbridge%d", dev->nr); 1508 ddbs[dev->nr] = dev; 1509 if (IS_ERR(dev->ddb_dev)) 1510 return -1; 1511 return 0; 1512 } 1513 1514 static void ddb_device_destroy(struct ddb *dev) 1515 { 1516 ddb_num--; 1517 if (IS_ERR(dev->ddb_dev)) 1518 return; 1519 device_destroy(ddb_class, MKDEV(ddb_major, 0)); 1520 } 1521 1522 1523 /****************************************************************************/ 1524 /****************************************************************************/ 1525 /****************************************************************************/ 1526 1527 static void ddb_unmap(struct ddb *dev) 1528 { 1529 if (dev->regs) 1530 iounmap(dev->regs); 1531 vfree(dev); 1532 } 1533 1534 1535 static void ddb_remove(struct pci_dev *pdev) 1536 { 1537 struct ddb *dev = pci_get_drvdata(pdev); 1538 1539 ddb_ports_detach(dev); 1540 ddb_i2c_release(dev); 1541 1542 ddbwritel(0, INTERRUPT_ENABLE); 1543 free_irq(dev->pdev->irq, dev); 1544 #ifdef CONFIG_PCI_MSI 1545 if (dev->msi) 1546 pci_disable_msi(dev->pdev); 1547 #endif 1548 ddb_ports_release(dev); 1549 ddb_buffers_free(dev); 1550 ddb_device_destroy(dev); 1551 1552 ddb_unmap(dev); 1553 pci_set_drvdata(pdev, NULL); 1554 pci_disable_device(pdev); 1555 } 1556 1557 1558 static int ddb_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1559 { 1560 struct ddb *dev; 1561 int stat = 0; 1562 int irq_flag = IRQF_SHARED; 1563 1564 if (pci_enable_device(pdev) < 0) 1565 return -ENODEV; 1566 1567 dev = vzalloc(sizeof(struct ddb)); 1568 if (dev == NULL) 1569 return -ENOMEM; 1570 1571 dev->pdev = pdev; 1572 pci_set_drvdata(pdev, dev); 1573 dev->info = (struct ddb_info *) id->driver_data; 1574 printk(KERN_INFO "DDBridge driver detected: %s\n", dev->info->name); 1575 1576 dev->regs = ioremap(pci_resource_start(dev->pdev, 0), 1577 pci_resource_len(dev->pdev, 0)); 1578 if (!dev->regs) { 1579 stat = -ENOMEM; 1580 goto fail; 1581 } 1582 printk(KERN_INFO "HW %08x FW %08x\n", ddbreadl(0), ddbreadl(4)); 1583 1584 #ifdef CONFIG_PCI_MSI 1585 if (pci_msi_enabled()) 1586 stat = pci_enable_msi(dev->pdev); 1587 if (stat) { 1588 printk(KERN_INFO ": MSI not available.\n"); 1589 } else { 1590 irq_flag = 0; 1591 dev->msi = 1; 1592 } 1593 #endif 1594 stat = request_irq(dev->pdev->irq, irq_handler, 1595 irq_flag, "DDBridge", (void *) dev); 1596 if (stat < 0) 1597 goto fail1; 1598 ddbwritel(0, DMA_BASE_WRITE); 1599 ddbwritel(0, DMA_BASE_READ); 1600 ddbwritel(0xffffffff, INTERRUPT_ACK); 1601 ddbwritel(0xfff0f, INTERRUPT_ENABLE); 1602 ddbwritel(0, MSI1_ENABLE); 1603 1604 if (ddb_i2c_init(dev) < 0) 1605 goto fail1; 1606 ddb_ports_init(dev); 1607 if (ddb_buffers_alloc(dev) < 0) { 1608 printk(KERN_INFO ": Could not allocate buffer memory\n"); 1609 goto fail2; 1610 } 1611 if (ddb_ports_attach(dev) < 0) 1612 goto fail3; 1613 ddb_device_create(dev); 1614 return 0; 1615 1616 fail3: 1617 ddb_ports_detach(dev); 1618 printk(KERN_ERR "fail3\n"); 1619 ddb_ports_release(dev); 1620 fail2: 1621 printk(KERN_ERR "fail2\n"); 1622 ddb_buffers_free(dev); 1623 fail1: 1624 printk(KERN_ERR "fail1\n"); 1625 if (dev->msi) 1626 pci_disable_msi(dev->pdev); 1627 if (stat == 0) 1628 free_irq(dev->pdev->irq, dev); 1629 fail: 1630 printk(KERN_ERR "fail\n"); 1631 ddb_unmap(dev); 1632 pci_set_drvdata(pdev, NULL); 1633 pci_disable_device(pdev); 1634 return -1; 1635 } 1636 1637 /******************************************************************************/ 1638 /******************************************************************************/ 1639 /******************************************************************************/ 1640 1641 static const struct ddb_info ddb_none = { 1642 .type = DDB_NONE, 1643 .name = "Digital Devices PCIe bridge", 1644 }; 1645 1646 static const struct ddb_info ddb_octopus = { 1647 .type = DDB_OCTOPUS, 1648 .name = "Digital Devices Octopus DVB adapter", 1649 .port_num = 4, 1650 }; 1651 1652 static const struct ddb_info ddb_octopus_le = { 1653 .type = DDB_OCTOPUS, 1654 .name = "Digital Devices Octopus LE DVB adapter", 1655 .port_num = 2, 1656 }; 1657 1658 static const struct ddb_info ddb_octopus_mini = { 1659 .type = DDB_OCTOPUS, 1660 .name = "Digital Devices Octopus Mini", 1661 .port_num = 4, 1662 }; 1663 1664 static const struct ddb_info ddb_v6 = { 1665 .type = DDB_OCTOPUS, 1666 .name = "Digital Devices Cine S2 V6 DVB adapter", 1667 .port_num = 3, 1668 }; 1669 static const struct ddb_info ddb_v6_5 = { 1670 .type = DDB_OCTOPUS, 1671 .name = "Digital Devices Cine S2 V6.5 DVB adapter", 1672 .port_num = 4, 1673 }; 1674 1675 static const struct ddb_info ddb_dvbct = { 1676 .type = DDB_OCTOPUS, 1677 .name = "Digital Devices DVBCT V6.1 DVB adapter", 1678 .port_num = 3, 1679 }; 1680 1681 static const struct ddb_info ddb_satixS2v3 = { 1682 .type = DDB_OCTOPUS, 1683 .name = "Mystique SaTiX-S2 V3 DVB adapter", 1684 .port_num = 3, 1685 }; 1686 1687 static const struct ddb_info ddb_octopusv3 = { 1688 .type = DDB_OCTOPUS, 1689 .name = "Digital Devices Octopus V3 DVB adapter", 1690 .port_num = 4, 1691 }; 1692 1693 #define DDVID 0xdd01 /* Digital Devices Vendor ID */ 1694 1695 #define DDB_ID(_vend, _dev, _subvend, _subdev, _driverdata) { \ 1696 .vendor = _vend, .device = _dev, \ 1697 .subvendor = _subvend, .subdevice = _subdev, \ 1698 .driver_data = (unsigned long)&_driverdata } 1699 1700 static const struct pci_device_id ddb_id_tbl[] = { 1701 DDB_ID(DDVID, 0x0002, DDVID, 0x0001, ddb_octopus), 1702 DDB_ID(DDVID, 0x0003, DDVID, 0x0001, ddb_octopus), 1703 DDB_ID(DDVID, 0x0003, DDVID, 0x0002, ddb_octopus_le), 1704 DDB_ID(DDVID, 0x0003, DDVID, 0x0010, ddb_octopus_mini), 1705 DDB_ID(DDVID, 0x0003, DDVID, 0x0020, ddb_v6), 1706 DDB_ID(DDVID, 0x0003, DDVID, 0x0021, ddb_v6_5), 1707 DDB_ID(DDVID, 0x0003, DDVID, 0x0030, ddb_dvbct), 1708 DDB_ID(DDVID, 0x0003, DDVID, 0xdb03, ddb_satixS2v3), 1709 DDB_ID(DDVID, 0x0005, DDVID, 0x0004, ddb_octopusv3), 1710 /* in case sub-ids got deleted in flash */ 1711 DDB_ID(DDVID, 0x0003, PCI_ANY_ID, PCI_ANY_ID, ddb_none), 1712 {0} 1713 }; 1714 MODULE_DEVICE_TABLE(pci, ddb_id_tbl); 1715 1716 1717 static struct pci_driver ddb_pci_driver = { 1718 .name = "DDBridge", 1719 .id_table = ddb_id_tbl, 1720 .probe = ddb_probe, 1721 .remove = ddb_remove, 1722 }; 1723 1724 static __init int module_init_ddbridge(void) 1725 { 1726 int ret; 1727 1728 printk(KERN_INFO "Digital Devices PCIE bridge driver, Copyright (C) 2010-11 Digital Devices GmbH\n"); 1729 1730 ret = ddb_class_create(); 1731 if (ret < 0) 1732 return ret; 1733 ret = pci_register_driver(&ddb_pci_driver); 1734 if (ret < 0) 1735 ddb_class_destroy(); 1736 return ret; 1737 } 1738 1739 static __exit void module_exit_ddbridge(void) 1740 { 1741 pci_unregister_driver(&ddb_pci_driver); 1742 ddb_class_destroy(); 1743 } 1744 1745 module_init(module_init_ddbridge); 1746 module_exit(module_exit_ddbridge); 1747 1748 MODULE_DESCRIPTION("Digital Devices PCIe Bridge"); 1749 MODULE_AUTHOR("Ralph Metzler"); 1750 MODULE_LICENSE("GPL"); 1751 MODULE_VERSION("0.5"); 1752