1 /* 2 * 3 * device driver for Conexant 2388x based TV cards 4 * video4linux video interface 5 * 6 * (c) 2003-04 Gerd Knorr <kraxel@bytesex.org> [SuSE Labs] 7 * 8 * (c) 2005-2006 Mauro Carvalho Chehab <mchehab@infradead.org> 9 * - Multituner support 10 * - video_ioctl2 conversion 11 * - PAL/M fixes 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License as published by 15 * the Free Software Foundation; either version 2 of the License, or 16 * (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 */ 23 24 #include "cx88.h" 25 26 #include <linux/init.h> 27 #include <linux/list.h> 28 #include <linux/module.h> 29 #include <linux/kmod.h> 30 #include <linux/kernel.h> 31 #include <linux/slab.h> 32 #include <linux/interrupt.h> 33 #include <linux/dma-mapping.h> 34 #include <linux/delay.h> 35 #include <linux/kthread.h> 36 #include <asm/div64.h> 37 38 #include <media/v4l2-common.h> 39 #include <media/v4l2-ioctl.h> 40 #include <media/v4l2-event.h> 41 #include <media/i2c/wm8775.h> 42 43 MODULE_DESCRIPTION("v4l2 driver module for cx2388x based TV cards"); 44 MODULE_AUTHOR("Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]"); 45 MODULE_LICENSE("GPL"); 46 MODULE_VERSION(CX88_VERSION); 47 48 /* ------------------------------------------------------------------ */ 49 50 static unsigned int video_nr[] = {[0 ... (CX88_MAXBOARDS - 1)] = UNSET }; 51 static unsigned int vbi_nr[] = {[0 ... (CX88_MAXBOARDS - 1)] = UNSET }; 52 static unsigned int radio_nr[] = {[0 ... (CX88_MAXBOARDS - 1)] = UNSET }; 53 54 module_param_array(video_nr, int, NULL, 0444); 55 module_param_array(vbi_nr, int, NULL, 0444); 56 module_param_array(radio_nr, int, NULL, 0444); 57 58 MODULE_PARM_DESC(video_nr, "video device numbers"); 59 MODULE_PARM_DESC(vbi_nr, "vbi device numbers"); 60 MODULE_PARM_DESC(radio_nr, "radio device numbers"); 61 62 static unsigned int video_debug; 63 module_param(video_debug, int, 0644); 64 MODULE_PARM_DESC(video_debug, "enable debug messages [video]"); 65 66 static unsigned int irq_debug; 67 module_param(irq_debug, int, 0644); 68 MODULE_PARM_DESC(irq_debug, "enable debug messages [IRQ handler]"); 69 70 #define dprintk(level, fmt, arg...) do { \ 71 if (video_debug >= level) \ 72 printk(KERN_DEBUG pr_fmt("%s: video:" fmt), \ 73 __func__, ##arg); \ 74 } while (0) 75 76 /* ------------------------------------------------------------------- */ 77 /* static data */ 78 79 static const struct cx8800_fmt formats[] = { 80 { 81 .name = "8 bpp, gray", 82 .fourcc = V4L2_PIX_FMT_GREY, 83 .cxformat = ColorFormatY8, 84 .depth = 8, 85 .flags = FORMAT_FLAGS_PACKED, 86 }, { 87 .name = "15 bpp RGB, le", 88 .fourcc = V4L2_PIX_FMT_RGB555, 89 .cxformat = ColorFormatRGB15, 90 .depth = 16, 91 .flags = FORMAT_FLAGS_PACKED, 92 }, { 93 .name = "15 bpp RGB, be", 94 .fourcc = V4L2_PIX_FMT_RGB555X, 95 .cxformat = ColorFormatRGB15 | ColorFormatBSWAP, 96 .depth = 16, 97 .flags = FORMAT_FLAGS_PACKED, 98 }, { 99 .name = "16 bpp RGB, le", 100 .fourcc = V4L2_PIX_FMT_RGB565, 101 .cxformat = ColorFormatRGB16, 102 .depth = 16, 103 .flags = FORMAT_FLAGS_PACKED, 104 }, { 105 .name = "16 bpp RGB, be", 106 .fourcc = V4L2_PIX_FMT_RGB565X, 107 .cxformat = ColorFormatRGB16 | ColorFormatBSWAP, 108 .depth = 16, 109 .flags = FORMAT_FLAGS_PACKED, 110 }, { 111 .name = "24 bpp RGB, le", 112 .fourcc = V4L2_PIX_FMT_BGR24, 113 .cxformat = ColorFormatRGB24, 114 .depth = 24, 115 .flags = FORMAT_FLAGS_PACKED, 116 }, { 117 .name = "32 bpp RGB, le", 118 .fourcc = V4L2_PIX_FMT_BGR32, 119 .cxformat = ColorFormatRGB32, 120 .depth = 32, 121 .flags = FORMAT_FLAGS_PACKED, 122 }, { 123 .name = "32 bpp RGB, be", 124 .fourcc = V4L2_PIX_FMT_RGB32, 125 .cxformat = ColorFormatRGB32 | ColorFormatBSWAP | 126 ColorFormatWSWAP, 127 .depth = 32, 128 .flags = FORMAT_FLAGS_PACKED, 129 }, { 130 .name = "4:2:2, packed, YUYV", 131 .fourcc = V4L2_PIX_FMT_YUYV, 132 .cxformat = ColorFormatYUY2, 133 .depth = 16, 134 .flags = FORMAT_FLAGS_PACKED, 135 }, { 136 .name = "4:2:2, packed, UYVY", 137 .fourcc = V4L2_PIX_FMT_UYVY, 138 .cxformat = ColorFormatYUY2 | ColorFormatBSWAP, 139 .depth = 16, 140 .flags = FORMAT_FLAGS_PACKED, 141 }, 142 }; 143 144 static const struct cx8800_fmt *format_by_fourcc(unsigned int fourcc) 145 { 146 unsigned int i; 147 148 for (i = 0; i < ARRAY_SIZE(formats); i++) 149 if (formats[i].fourcc == fourcc) 150 return formats + i; 151 return NULL; 152 } 153 154 /* ------------------------------------------------------------------- */ 155 156 struct cx88_ctrl { 157 /* control information */ 158 u32 id; 159 s32 minimum; 160 s32 maximum; 161 u32 step; 162 s32 default_value; 163 164 /* control register information */ 165 u32 off; 166 u32 reg; 167 u32 sreg; 168 u32 mask; 169 u32 shift; 170 }; 171 172 static const struct cx88_ctrl cx8800_vid_ctls[] = { 173 /* --- video --- */ 174 { 175 .id = V4L2_CID_BRIGHTNESS, 176 .minimum = 0x00, 177 .maximum = 0xff, 178 .step = 1, 179 .default_value = 0x7f, 180 .off = 128, 181 .reg = MO_CONTR_BRIGHT, 182 .mask = 0x00ff, 183 .shift = 0, 184 }, { 185 .id = V4L2_CID_CONTRAST, 186 .minimum = 0, 187 .maximum = 0xff, 188 .step = 1, 189 .default_value = 0x3f, 190 .off = 0, 191 .reg = MO_CONTR_BRIGHT, 192 .mask = 0xff00, 193 .shift = 8, 194 }, { 195 .id = V4L2_CID_HUE, 196 .minimum = 0, 197 .maximum = 0xff, 198 .step = 1, 199 .default_value = 0x7f, 200 .off = 128, 201 .reg = MO_HUE, 202 .mask = 0x00ff, 203 .shift = 0, 204 }, { 205 /* strictly, this only describes only U saturation. 206 * V saturation is handled specially through code. 207 */ 208 .id = V4L2_CID_SATURATION, 209 .minimum = 0, 210 .maximum = 0xff, 211 .step = 1, 212 .default_value = 0x7f, 213 .off = 0, 214 .reg = MO_UV_SATURATION, 215 .mask = 0x00ff, 216 .shift = 0, 217 }, { 218 .id = V4L2_CID_SHARPNESS, 219 .minimum = 0, 220 .maximum = 4, 221 .step = 1, 222 .default_value = 0x0, 223 .off = 0, 224 /* 225 * NOTE: the value is converted and written to both even 226 * and odd registers in the code 227 */ 228 .reg = MO_FILTER_ODD, 229 .mask = 7 << 7, 230 .shift = 7, 231 }, { 232 .id = V4L2_CID_CHROMA_AGC, 233 .minimum = 0, 234 .maximum = 1, 235 .default_value = 0x1, 236 .reg = MO_INPUT_FORMAT, 237 .mask = 1 << 10, 238 .shift = 10, 239 }, { 240 .id = V4L2_CID_COLOR_KILLER, 241 .minimum = 0, 242 .maximum = 1, 243 .default_value = 0x1, 244 .reg = MO_INPUT_FORMAT, 245 .mask = 1 << 9, 246 .shift = 9, 247 }, { 248 .id = V4L2_CID_BAND_STOP_FILTER, 249 .minimum = 0, 250 .maximum = 1, 251 .step = 1, 252 .default_value = 0x0, 253 .off = 0, 254 .reg = MO_HTOTAL, 255 .mask = 3 << 11, 256 .shift = 11, 257 } 258 }; 259 260 static const struct cx88_ctrl cx8800_aud_ctls[] = { 261 { 262 /* --- audio --- */ 263 .id = V4L2_CID_AUDIO_MUTE, 264 .minimum = 0, 265 .maximum = 1, 266 .default_value = 1, 267 .reg = AUD_VOL_CTL, 268 .sreg = SHADOW_AUD_VOL_CTL, 269 .mask = (1 << 6), 270 .shift = 6, 271 }, { 272 .id = V4L2_CID_AUDIO_VOLUME, 273 .minimum = 0, 274 .maximum = 0x3f, 275 .step = 1, 276 .default_value = 0x3f, 277 .reg = AUD_VOL_CTL, 278 .sreg = SHADOW_AUD_VOL_CTL, 279 .mask = 0x3f, 280 .shift = 0, 281 }, { 282 .id = V4L2_CID_AUDIO_BALANCE, 283 .minimum = 0, 284 .maximum = 0x7f, 285 .step = 1, 286 .default_value = 0x40, 287 .reg = AUD_BAL_CTL, 288 .sreg = SHADOW_AUD_BAL_CTL, 289 .mask = 0x7f, 290 .shift = 0, 291 } 292 }; 293 294 enum { 295 CX8800_VID_CTLS = ARRAY_SIZE(cx8800_vid_ctls), 296 CX8800_AUD_CTLS = ARRAY_SIZE(cx8800_aud_ctls), 297 }; 298 299 /* ------------------------------------------------------------------ */ 300 301 int cx88_video_mux(struct cx88_core *core, unsigned int input) 302 { 303 /* struct cx88_core *core = dev->core; */ 304 305 dprintk(1, "video_mux: %d [vmux=%d,gpio=0x%x,0x%x,0x%x,0x%x]\n", 306 input, INPUT(input).vmux, 307 INPUT(input).gpio0, INPUT(input).gpio1, 308 INPUT(input).gpio2, INPUT(input).gpio3); 309 core->input = input; 310 cx_andor(MO_INPUT_FORMAT, 0x03 << 14, INPUT(input).vmux << 14); 311 cx_write(MO_GP3_IO, INPUT(input).gpio3); 312 cx_write(MO_GP0_IO, INPUT(input).gpio0); 313 cx_write(MO_GP1_IO, INPUT(input).gpio1); 314 cx_write(MO_GP2_IO, INPUT(input).gpio2); 315 316 switch (INPUT(input).type) { 317 case CX88_VMUX_SVIDEO: 318 cx_set(MO_AFECFG_IO, 0x00000001); 319 cx_set(MO_INPUT_FORMAT, 0x00010010); 320 cx_set(MO_FILTER_EVEN, 0x00002020); 321 cx_set(MO_FILTER_ODD, 0x00002020); 322 break; 323 default: 324 cx_clear(MO_AFECFG_IO, 0x00000001); 325 cx_clear(MO_INPUT_FORMAT, 0x00010010); 326 cx_clear(MO_FILTER_EVEN, 0x00002020); 327 cx_clear(MO_FILTER_ODD, 0x00002020); 328 break; 329 } 330 331 /* 332 * if there are audioroutes defined, we have an external 333 * ADC to deal with audio 334 */ 335 if (INPUT(input).audioroute) { 336 /* 337 * The wm8775 module has the "2" route hardwired into 338 * the initialization. Some boards may use different 339 * routes for different inputs. HVR-1300 surely does 340 */ 341 if (core->sd_wm8775) { 342 call_all(core, audio, s_routing, 343 INPUT(input).audioroute, 0, 0); 344 } 345 /* 346 * cx2388's C-ADC is connected to the tuner only. 347 * When used with S-Video, that ADC is busy dealing with 348 * chroma, so an external must be used for baseband audio 349 */ 350 if (INPUT(input).type != CX88_VMUX_TELEVISION && 351 INPUT(input).type != CX88_VMUX_CABLE) { 352 /* "I2S ADC mode" */ 353 core->tvaudio = WW_I2SADC; 354 cx88_set_tvaudio(core); 355 } else { 356 /* Normal mode */ 357 cx_write(AUD_I2SCNTL, 0x0); 358 cx_clear(AUD_CTL, EN_I2SIN_ENABLE); 359 } 360 } 361 362 return 0; 363 } 364 EXPORT_SYMBOL(cx88_video_mux); 365 366 /* ------------------------------------------------------------------ */ 367 368 static int start_video_dma(struct cx8800_dev *dev, 369 struct cx88_dmaqueue *q, 370 struct cx88_buffer *buf) 371 { 372 struct cx88_core *core = dev->core; 373 374 /* setup fifo + format */ 375 cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH21], 376 buf->bpl, buf->risc.dma); 377 cx88_set_scale(core, core->width, core->height, core->field); 378 cx_write(MO_COLOR_CTRL, dev->fmt->cxformat | ColorFormatGamma); 379 380 /* reset counter */ 381 cx_write(MO_VIDY_GPCNTRL, GP_COUNT_CONTROL_RESET); 382 q->count = 0; 383 384 /* enable irqs */ 385 cx_set(MO_PCI_INTMSK, core->pci_irqmask | PCI_INT_VIDINT); 386 387 /* 388 * Enables corresponding bits at PCI_INT_STAT: 389 * bits 0 to 4: video, audio, transport stream, VIP, Host 390 * bit 7: timer 391 * bits 8 and 9: DMA complete for: SRC, DST 392 * bits 10 and 11: BERR signal asserted for RISC: RD, WR 393 * bits 12 to 15: BERR signal asserted for: BRDG, SRC, DST, IPB 394 */ 395 cx_set(MO_VID_INTMSK, 0x0f0011); 396 397 /* enable capture */ 398 cx_set(VID_CAPTURE_CONTROL, 0x06); 399 400 /* start dma */ 401 cx_set(MO_DEV_CNTRL2, (1 << 5)); 402 cx_set(MO_VID_DMACNTRL, 0x11); /* Planar Y and packed FIFO and RISC enable */ 403 404 return 0; 405 } 406 407 #ifdef CONFIG_PM 408 static int stop_video_dma(struct cx8800_dev *dev) 409 { 410 struct cx88_core *core = dev->core; 411 412 /* stop dma */ 413 cx_clear(MO_VID_DMACNTRL, 0x11); 414 415 /* disable capture */ 416 cx_clear(VID_CAPTURE_CONTROL, 0x06); 417 418 /* disable irqs */ 419 cx_clear(MO_PCI_INTMSK, PCI_INT_VIDINT); 420 cx_clear(MO_VID_INTMSK, 0x0f0011); 421 return 0; 422 } 423 424 static int restart_video_queue(struct cx8800_dev *dev, 425 struct cx88_dmaqueue *q) 426 { 427 struct cx88_buffer *buf; 428 429 if (!list_empty(&q->active)) { 430 buf = list_entry(q->active.next, struct cx88_buffer, list); 431 dprintk(2, "restart_queue [%p/%d]: restart dma\n", 432 buf, buf->vb.vb2_buf.index); 433 start_video_dma(dev, q, buf); 434 } 435 return 0; 436 } 437 #endif 438 439 /* ------------------------------------------------------------------ */ 440 441 static int queue_setup(struct vb2_queue *q, 442 unsigned int *num_buffers, unsigned int *num_planes, 443 unsigned int sizes[], struct device *alloc_devs[]) 444 { 445 struct cx8800_dev *dev = q->drv_priv; 446 struct cx88_core *core = dev->core; 447 448 *num_planes = 1; 449 sizes[0] = (dev->fmt->depth * core->width * core->height) >> 3; 450 return 0; 451 } 452 453 static int buffer_prepare(struct vb2_buffer *vb) 454 { 455 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 456 struct cx8800_dev *dev = vb->vb2_queue->drv_priv; 457 struct cx88_core *core = dev->core; 458 struct cx88_buffer *buf = container_of(vbuf, struct cx88_buffer, vb); 459 struct sg_table *sgt = vb2_dma_sg_plane_desc(vb, 0); 460 461 buf->bpl = core->width * dev->fmt->depth >> 3; 462 463 if (vb2_plane_size(vb, 0) < core->height * buf->bpl) 464 return -EINVAL; 465 vb2_set_plane_payload(vb, 0, core->height * buf->bpl); 466 467 switch (core->field) { 468 case V4L2_FIELD_TOP: 469 cx88_risc_buffer(dev->pci, &buf->risc, 470 sgt->sgl, 0, UNSET, 471 buf->bpl, 0, core->height); 472 break; 473 case V4L2_FIELD_BOTTOM: 474 cx88_risc_buffer(dev->pci, &buf->risc, 475 sgt->sgl, UNSET, 0, 476 buf->bpl, 0, core->height); 477 break; 478 case V4L2_FIELD_SEQ_TB: 479 cx88_risc_buffer(dev->pci, &buf->risc, 480 sgt->sgl, 481 0, buf->bpl * (core->height >> 1), 482 buf->bpl, 0, 483 core->height >> 1); 484 break; 485 case V4L2_FIELD_SEQ_BT: 486 cx88_risc_buffer(dev->pci, &buf->risc, 487 sgt->sgl, 488 buf->bpl * (core->height >> 1), 0, 489 buf->bpl, 0, 490 core->height >> 1); 491 break; 492 case V4L2_FIELD_INTERLACED: 493 default: 494 cx88_risc_buffer(dev->pci, &buf->risc, 495 sgt->sgl, 0, buf->bpl, 496 buf->bpl, buf->bpl, 497 core->height >> 1); 498 break; 499 } 500 dprintk(2, 501 "[%p/%d] buffer_prepare - %dx%d %dbpp \"%s\" - dma=0x%08lx\n", 502 buf, buf->vb.vb2_buf.index, 503 core->width, core->height, dev->fmt->depth, dev->fmt->name, 504 (unsigned long)buf->risc.dma); 505 return 0; 506 } 507 508 static void buffer_finish(struct vb2_buffer *vb) 509 { 510 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 511 struct cx8800_dev *dev = vb->vb2_queue->drv_priv; 512 struct cx88_buffer *buf = container_of(vbuf, struct cx88_buffer, vb); 513 struct cx88_riscmem *risc = &buf->risc; 514 515 if (risc->cpu) 516 pci_free_consistent(dev->pci, risc->size, risc->cpu, risc->dma); 517 memset(risc, 0, sizeof(*risc)); 518 } 519 520 static void buffer_queue(struct vb2_buffer *vb) 521 { 522 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 523 struct cx8800_dev *dev = vb->vb2_queue->drv_priv; 524 struct cx88_buffer *buf = container_of(vbuf, struct cx88_buffer, vb); 525 struct cx88_buffer *prev; 526 struct cx88_dmaqueue *q = &dev->vidq; 527 528 /* add jump to start */ 529 buf->risc.cpu[1] = cpu_to_le32(buf->risc.dma + 8); 530 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_CNT_INC); 531 buf->risc.jmp[1] = cpu_to_le32(buf->risc.dma + 8); 532 533 if (list_empty(&q->active)) { 534 list_add_tail(&buf->list, &q->active); 535 dprintk(2, "[%p/%d] buffer_queue - first active\n", 536 buf, buf->vb.vb2_buf.index); 537 538 } else { 539 buf->risc.cpu[0] |= cpu_to_le32(RISC_IRQ1); 540 prev = list_entry(q->active.prev, struct cx88_buffer, list); 541 list_add_tail(&buf->list, &q->active); 542 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma); 543 dprintk(2, "[%p/%d] buffer_queue - append to active\n", 544 buf, buf->vb.vb2_buf.index); 545 } 546 } 547 548 static int start_streaming(struct vb2_queue *q, unsigned int count) 549 { 550 struct cx8800_dev *dev = q->drv_priv; 551 struct cx88_dmaqueue *dmaq = &dev->vidq; 552 struct cx88_buffer *buf = list_entry(dmaq->active.next, 553 struct cx88_buffer, list); 554 555 start_video_dma(dev, dmaq, buf); 556 return 0; 557 } 558 559 static void stop_streaming(struct vb2_queue *q) 560 { 561 struct cx8800_dev *dev = q->drv_priv; 562 struct cx88_core *core = dev->core; 563 struct cx88_dmaqueue *dmaq = &dev->vidq; 564 unsigned long flags; 565 566 cx_clear(MO_VID_DMACNTRL, 0x11); 567 cx_clear(VID_CAPTURE_CONTROL, 0x06); 568 spin_lock_irqsave(&dev->slock, flags); 569 while (!list_empty(&dmaq->active)) { 570 struct cx88_buffer *buf = list_entry(dmaq->active.next, 571 struct cx88_buffer, list); 572 573 list_del(&buf->list); 574 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); 575 } 576 spin_unlock_irqrestore(&dev->slock, flags); 577 } 578 579 static const struct vb2_ops cx8800_video_qops = { 580 .queue_setup = queue_setup, 581 .buf_prepare = buffer_prepare, 582 .buf_finish = buffer_finish, 583 .buf_queue = buffer_queue, 584 .wait_prepare = vb2_ops_wait_prepare, 585 .wait_finish = vb2_ops_wait_finish, 586 .start_streaming = start_streaming, 587 .stop_streaming = stop_streaming, 588 }; 589 590 /* ------------------------------------------------------------------ */ 591 592 static int radio_open(struct file *file) 593 { 594 struct cx8800_dev *dev = video_drvdata(file); 595 struct cx88_core *core = dev->core; 596 int ret = v4l2_fh_open(file); 597 598 if (ret) 599 return ret; 600 601 cx_write(MO_GP3_IO, core->board.radio.gpio3); 602 cx_write(MO_GP0_IO, core->board.radio.gpio0); 603 cx_write(MO_GP1_IO, core->board.radio.gpio1); 604 cx_write(MO_GP2_IO, core->board.radio.gpio2); 605 if (core->board.radio.audioroute) { 606 if (core->sd_wm8775) { 607 call_all(core, audio, s_routing, 608 core->board.radio.audioroute, 0, 0); 609 } 610 /* "I2S ADC mode" */ 611 core->tvaudio = WW_I2SADC; 612 cx88_set_tvaudio(core); 613 } else { 614 /* FM Mode */ 615 core->tvaudio = WW_FM; 616 cx88_set_tvaudio(core); 617 cx88_set_stereo(core, V4L2_TUNER_MODE_STEREO, 1); 618 } 619 call_all(core, tuner, s_radio); 620 return 0; 621 } 622 623 /* ------------------------------------------------------------------ */ 624 /* VIDEO CTRL IOCTLS */ 625 626 static int cx8800_s_vid_ctrl(struct v4l2_ctrl *ctrl) 627 { 628 struct cx88_core *core = 629 container_of(ctrl->handler, struct cx88_core, video_hdl); 630 const struct cx88_ctrl *cc = ctrl->priv; 631 u32 value, mask; 632 633 mask = cc->mask; 634 switch (ctrl->id) { 635 case V4L2_CID_SATURATION: 636 /* special v_sat handling */ 637 638 value = ((ctrl->val - cc->off) << cc->shift) & cc->mask; 639 640 if (core->tvnorm & V4L2_STD_SECAM) { 641 /* For SECAM, both U and V sat should be equal */ 642 value = value << 8 | value; 643 } else { 644 /* Keeps U Saturation proportional to V Sat */ 645 value = (value * 0x5a) / 0x7f << 8 | value; 646 } 647 mask = 0xffff; 648 break; 649 case V4L2_CID_SHARPNESS: 650 /* 0b000, 0b100, 0b101, 0b110, or 0b111 */ 651 value = (ctrl->val < 1 ? 0 : ((ctrl->val + 3) << 7)); 652 /* needs to be set for both fields */ 653 cx_andor(MO_FILTER_EVEN, mask, value); 654 break; 655 case V4L2_CID_CHROMA_AGC: 656 value = ((ctrl->val - cc->off) << cc->shift) & cc->mask; 657 break; 658 default: 659 value = ((ctrl->val - cc->off) << cc->shift) & cc->mask; 660 break; 661 } 662 dprintk(1, 663 "set_control id=0x%X(%s) ctrl=0x%02x, reg=0x%02x val=0x%02x (mask 0x%02x)%s\n", 664 ctrl->id, ctrl->name, ctrl->val, cc->reg, value, 665 mask, cc->sreg ? " [shadowed]" : ""); 666 if (cc->sreg) 667 cx_sandor(cc->sreg, cc->reg, mask, value); 668 else 669 cx_andor(cc->reg, mask, value); 670 return 0; 671 } 672 673 static int cx8800_s_aud_ctrl(struct v4l2_ctrl *ctrl) 674 { 675 struct cx88_core *core = 676 container_of(ctrl->handler, struct cx88_core, audio_hdl); 677 const struct cx88_ctrl *cc = ctrl->priv; 678 u32 value, mask; 679 680 /* Pass changes onto any WM8775 */ 681 if (core->sd_wm8775) { 682 switch (ctrl->id) { 683 case V4L2_CID_AUDIO_MUTE: 684 wm8775_s_ctrl(core, ctrl->id, ctrl->val); 685 break; 686 case V4L2_CID_AUDIO_VOLUME: 687 wm8775_s_ctrl(core, ctrl->id, (ctrl->val) ? 688 (0x90 + ctrl->val) << 8 : 0); 689 break; 690 case V4L2_CID_AUDIO_BALANCE: 691 wm8775_s_ctrl(core, ctrl->id, ctrl->val << 9); 692 break; 693 default: 694 break; 695 } 696 } 697 698 mask = cc->mask; 699 switch (ctrl->id) { 700 case V4L2_CID_AUDIO_BALANCE: 701 value = (ctrl->val < 0x40) ? 702 (0x7f - ctrl->val) : (ctrl->val - 0x40); 703 break; 704 case V4L2_CID_AUDIO_VOLUME: 705 value = 0x3f - (ctrl->val & 0x3f); 706 break; 707 default: 708 value = ((ctrl->val - cc->off) << cc->shift) & cc->mask; 709 break; 710 } 711 dprintk(1, 712 "set_control id=0x%X(%s) ctrl=0x%02x, reg=0x%02x val=0x%02x (mask 0x%02x)%s\n", 713 ctrl->id, ctrl->name, ctrl->val, cc->reg, value, 714 mask, cc->sreg ? " [shadowed]" : ""); 715 if (cc->sreg) 716 cx_sandor(cc->sreg, cc->reg, mask, value); 717 else 718 cx_andor(cc->reg, mask, value); 719 return 0; 720 } 721 722 /* ------------------------------------------------------------------ */ 723 /* VIDEO IOCTLS */ 724 725 static int vidioc_g_fmt_vid_cap(struct file *file, void *priv, 726 struct v4l2_format *f) 727 { 728 struct cx8800_dev *dev = video_drvdata(file); 729 struct cx88_core *core = dev->core; 730 731 f->fmt.pix.width = core->width; 732 f->fmt.pix.height = core->height; 733 f->fmt.pix.field = core->field; 734 f->fmt.pix.pixelformat = dev->fmt->fourcc; 735 f->fmt.pix.bytesperline = 736 (f->fmt.pix.width * dev->fmt->depth) >> 3; 737 f->fmt.pix.sizeimage = 738 f->fmt.pix.height * f->fmt.pix.bytesperline; 739 f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M; 740 return 0; 741 } 742 743 static int vidioc_try_fmt_vid_cap(struct file *file, void *priv, 744 struct v4l2_format *f) 745 { 746 struct cx8800_dev *dev = video_drvdata(file); 747 struct cx88_core *core = dev->core; 748 const struct cx8800_fmt *fmt; 749 enum v4l2_field field; 750 unsigned int maxw, maxh; 751 752 fmt = format_by_fourcc(f->fmt.pix.pixelformat); 753 if (!fmt) 754 return -EINVAL; 755 756 maxw = norm_maxw(core->tvnorm); 757 maxh = norm_maxh(core->tvnorm); 758 759 field = f->fmt.pix.field; 760 761 switch (field) { 762 case V4L2_FIELD_TOP: 763 case V4L2_FIELD_BOTTOM: 764 case V4L2_FIELD_INTERLACED: 765 case V4L2_FIELD_SEQ_BT: 766 case V4L2_FIELD_SEQ_TB: 767 break; 768 default: 769 field = (f->fmt.pix.height > maxh / 2) 770 ? V4L2_FIELD_INTERLACED 771 : V4L2_FIELD_BOTTOM; 772 break; 773 } 774 if (V4L2_FIELD_HAS_T_OR_B(field)) 775 maxh /= 2; 776 777 v4l_bound_align_image(&f->fmt.pix.width, 48, maxw, 2, 778 &f->fmt.pix.height, 32, maxh, 0, 0); 779 f->fmt.pix.field = field; 780 f->fmt.pix.bytesperline = 781 (f->fmt.pix.width * fmt->depth) >> 3; 782 f->fmt.pix.sizeimage = 783 f->fmt.pix.height * f->fmt.pix.bytesperline; 784 f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M; 785 786 return 0; 787 } 788 789 static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, 790 struct v4l2_format *f) 791 { 792 struct cx8800_dev *dev = video_drvdata(file); 793 struct cx88_core *core = dev->core; 794 int err = vidioc_try_fmt_vid_cap(file, priv, f); 795 796 if (err != 0) 797 return err; 798 if (vb2_is_busy(&dev->vb2_vidq) || vb2_is_busy(&dev->vb2_vbiq)) 799 return -EBUSY; 800 if (core->dvbdev && vb2_is_busy(&core->dvbdev->vb2_mpegq)) 801 return -EBUSY; 802 dev->fmt = format_by_fourcc(f->fmt.pix.pixelformat); 803 core->width = f->fmt.pix.width; 804 core->height = f->fmt.pix.height; 805 core->field = f->fmt.pix.field; 806 return 0; 807 } 808 809 void cx88_querycap(struct file *file, struct cx88_core *core, 810 struct v4l2_capability *cap) 811 { 812 struct video_device *vdev = video_devdata(file); 813 814 strlcpy(cap->card, core->board.name, sizeof(cap->card)); 815 cap->device_caps = V4L2_CAP_READWRITE | V4L2_CAP_STREAMING; 816 if (core->board.tuner_type != UNSET) 817 cap->device_caps |= V4L2_CAP_TUNER; 818 switch (vdev->vfl_type) { 819 case VFL_TYPE_RADIO: 820 cap->device_caps = V4L2_CAP_RADIO | V4L2_CAP_TUNER; 821 break; 822 case VFL_TYPE_GRABBER: 823 cap->device_caps |= V4L2_CAP_VIDEO_CAPTURE; 824 break; 825 case VFL_TYPE_VBI: 826 cap->device_caps |= V4L2_CAP_VBI_CAPTURE; 827 break; 828 } 829 cap->capabilities = cap->device_caps | V4L2_CAP_VIDEO_CAPTURE | 830 V4L2_CAP_VBI_CAPTURE | V4L2_CAP_DEVICE_CAPS; 831 if (core->board.radio.type == CX88_RADIO) 832 cap->capabilities |= V4L2_CAP_RADIO; 833 } 834 EXPORT_SYMBOL(cx88_querycap); 835 836 static int vidioc_querycap(struct file *file, void *priv, 837 struct v4l2_capability *cap) 838 { 839 struct cx8800_dev *dev = video_drvdata(file); 840 struct cx88_core *core = dev->core; 841 842 strcpy(cap->driver, "cx8800"); 843 sprintf(cap->bus_info, "PCI:%s", pci_name(dev->pci)); 844 cx88_querycap(file, core, cap); 845 return 0; 846 } 847 848 static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv, 849 struct v4l2_fmtdesc *f) 850 { 851 if (unlikely(f->index >= ARRAY_SIZE(formats))) 852 return -EINVAL; 853 854 strlcpy(f->description, formats[f->index].name, sizeof(f->description)); 855 f->pixelformat = formats[f->index].fourcc; 856 857 return 0; 858 } 859 860 static int vidioc_g_std(struct file *file, void *priv, v4l2_std_id *tvnorm) 861 { 862 struct cx8800_dev *dev = video_drvdata(file); 863 struct cx88_core *core = dev->core; 864 865 *tvnorm = core->tvnorm; 866 return 0; 867 } 868 869 static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id tvnorms) 870 { 871 struct cx8800_dev *dev = video_drvdata(file); 872 struct cx88_core *core = dev->core; 873 874 return cx88_set_tvnorm(core, tvnorms); 875 } 876 877 /* only one input in this sample driver */ 878 int cx88_enum_input(struct cx88_core *core, struct v4l2_input *i) 879 { 880 static const char * const iname[] = { 881 [CX88_VMUX_COMPOSITE1] = "Composite1", 882 [CX88_VMUX_COMPOSITE2] = "Composite2", 883 [CX88_VMUX_COMPOSITE3] = "Composite3", 884 [CX88_VMUX_COMPOSITE4] = "Composite4", 885 [CX88_VMUX_SVIDEO] = "S-Video", 886 [CX88_VMUX_TELEVISION] = "Television", 887 [CX88_VMUX_CABLE] = "Cable TV", 888 [CX88_VMUX_DVB] = "DVB", 889 [CX88_VMUX_DEBUG] = "for debug only", 890 }; 891 unsigned int n = i->index; 892 893 if (n >= 4) 894 return -EINVAL; 895 if (!INPUT(n).type) 896 return -EINVAL; 897 i->type = V4L2_INPUT_TYPE_CAMERA; 898 strcpy(i->name, iname[INPUT(n).type]); 899 if ((INPUT(n).type == CX88_VMUX_TELEVISION) || 900 (INPUT(n).type == CX88_VMUX_CABLE)) 901 i->type = V4L2_INPUT_TYPE_TUNER; 902 903 i->std = CX88_NORMS; 904 return 0; 905 } 906 EXPORT_SYMBOL(cx88_enum_input); 907 908 static int vidioc_enum_input(struct file *file, void *priv, 909 struct v4l2_input *i) 910 { 911 struct cx8800_dev *dev = video_drvdata(file); 912 struct cx88_core *core = dev->core; 913 914 return cx88_enum_input(core, i); 915 } 916 917 static int vidioc_g_input(struct file *file, void *priv, unsigned int *i) 918 { 919 struct cx8800_dev *dev = video_drvdata(file); 920 struct cx88_core *core = dev->core; 921 922 *i = core->input; 923 return 0; 924 } 925 926 static int vidioc_s_input(struct file *file, void *priv, unsigned int i) 927 { 928 struct cx8800_dev *dev = video_drvdata(file); 929 struct cx88_core *core = dev->core; 930 931 if (i >= 4) 932 return -EINVAL; 933 if (!INPUT(i).type) 934 return -EINVAL; 935 936 cx88_newstation(core); 937 cx88_video_mux(core, i); 938 return 0; 939 } 940 941 static int vidioc_g_tuner(struct file *file, void *priv, 942 struct v4l2_tuner *t) 943 { 944 struct cx8800_dev *dev = video_drvdata(file); 945 struct cx88_core *core = dev->core; 946 u32 reg; 947 948 if (unlikely(core->board.tuner_type == UNSET)) 949 return -EINVAL; 950 if (t->index != 0) 951 return -EINVAL; 952 953 strcpy(t->name, "Television"); 954 t->capability = V4L2_TUNER_CAP_NORM; 955 t->rangehigh = 0xffffffffUL; 956 call_all(core, tuner, g_tuner, t); 957 958 cx88_get_stereo(core, t); 959 reg = cx_read(MO_DEVICE_STATUS); 960 t->signal = (reg & (1 << 5)) ? 0xffff : 0x0000; 961 return 0; 962 } 963 964 static int vidioc_s_tuner(struct file *file, void *priv, 965 const struct v4l2_tuner *t) 966 { 967 struct cx8800_dev *dev = video_drvdata(file); 968 struct cx88_core *core = dev->core; 969 970 if (core->board.tuner_type == UNSET) 971 return -EINVAL; 972 if (t->index != 0) 973 return -EINVAL; 974 975 cx88_set_stereo(core, t->audmode, 1); 976 return 0; 977 } 978 979 static int vidioc_g_frequency(struct file *file, void *priv, 980 struct v4l2_frequency *f) 981 { 982 struct cx8800_dev *dev = video_drvdata(file); 983 struct cx88_core *core = dev->core; 984 985 if (unlikely(core->board.tuner_type == UNSET)) 986 return -EINVAL; 987 if (f->tuner) 988 return -EINVAL; 989 990 f->frequency = core->freq; 991 992 call_all(core, tuner, g_frequency, f); 993 994 return 0; 995 } 996 997 int cx88_set_freq(struct cx88_core *core, 998 const struct v4l2_frequency *f) 999 { 1000 struct v4l2_frequency new_freq = *f; 1001 1002 if (unlikely(core->board.tuner_type == UNSET)) 1003 return -EINVAL; 1004 if (unlikely(f->tuner != 0)) 1005 return -EINVAL; 1006 1007 cx88_newstation(core); 1008 call_all(core, tuner, s_frequency, f); 1009 call_all(core, tuner, g_frequency, &new_freq); 1010 core->freq = new_freq.frequency; 1011 1012 /* When changing channels it is required to reset TVAUDIO */ 1013 usleep_range(10000, 20000); 1014 cx88_set_tvaudio(core); 1015 1016 return 0; 1017 } 1018 EXPORT_SYMBOL(cx88_set_freq); 1019 1020 static int vidioc_s_frequency(struct file *file, void *priv, 1021 const struct v4l2_frequency *f) 1022 { 1023 struct cx8800_dev *dev = video_drvdata(file); 1024 struct cx88_core *core = dev->core; 1025 1026 return cx88_set_freq(core, f); 1027 } 1028 1029 #ifdef CONFIG_VIDEO_ADV_DEBUG 1030 static int vidioc_g_register(struct file *file, void *fh, 1031 struct v4l2_dbg_register *reg) 1032 { 1033 struct cx8800_dev *dev = video_drvdata(file); 1034 struct cx88_core *core = dev->core; 1035 1036 /* cx2388x has a 24-bit register space */ 1037 reg->val = cx_read(reg->reg & 0xfffffc); 1038 reg->size = 4; 1039 return 0; 1040 } 1041 1042 static int vidioc_s_register(struct file *file, void *fh, 1043 const struct v4l2_dbg_register *reg) 1044 { 1045 struct cx8800_dev *dev = video_drvdata(file); 1046 struct cx88_core *core = dev->core; 1047 1048 cx_write(reg->reg & 0xfffffc, reg->val); 1049 return 0; 1050 } 1051 #endif 1052 1053 /* ----------------------------------------------------------- */ 1054 /* RADIO ESPECIFIC IOCTLS */ 1055 /* ----------------------------------------------------------- */ 1056 1057 static int radio_g_tuner(struct file *file, void *priv, 1058 struct v4l2_tuner *t) 1059 { 1060 struct cx8800_dev *dev = video_drvdata(file); 1061 struct cx88_core *core = dev->core; 1062 1063 if (unlikely(t->index > 0)) 1064 return -EINVAL; 1065 1066 strcpy(t->name, "Radio"); 1067 1068 call_all(core, tuner, g_tuner, t); 1069 return 0; 1070 } 1071 1072 static int radio_s_tuner(struct file *file, void *priv, 1073 const struct v4l2_tuner *t) 1074 { 1075 struct cx8800_dev *dev = video_drvdata(file); 1076 struct cx88_core *core = dev->core; 1077 1078 if (t->index != 0) 1079 return -EINVAL; 1080 1081 call_all(core, tuner, s_tuner, t); 1082 return 0; 1083 } 1084 1085 /* ----------------------------------------------------------- */ 1086 1087 static const char *cx88_vid_irqs[32] = { 1088 "y_risci1", "u_risci1", "v_risci1", "vbi_risc1", 1089 "y_risci2", "u_risci2", "v_risci2", "vbi_risc2", 1090 "y_oflow", "u_oflow", "v_oflow", "vbi_oflow", 1091 "y_sync", "u_sync", "v_sync", "vbi_sync", 1092 "opc_err", "par_err", "rip_err", "pci_abort", 1093 }; 1094 1095 static void cx8800_vid_irq(struct cx8800_dev *dev) 1096 { 1097 struct cx88_core *core = dev->core; 1098 u32 status, mask, count; 1099 1100 status = cx_read(MO_VID_INTSTAT); 1101 mask = cx_read(MO_VID_INTMSK); 1102 if (0 == (status & mask)) 1103 return; 1104 cx_write(MO_VID_INTSTAT, status); 1105 if (irq_debug || (status & mask & ~0xff)) 1106 cx88_print_irqbits("irq vid", 1107 cx88_vid_irqs, ARRAY_SIZE(cx88_vid_irqs), 1108 status, mask); 1109 1110 /* risc op code error */ 1111 if (status & (1 << 16)) { 1112 pr_warn("video risc op code error\n"); 1113 cx_clear(MO_VID_DMACNTRL, 0x11); 1114 cx_clear(VID_CAPTURE_CONTROL, 0x06); 1115 cx88_sram_channel_dump(core, &cx88_sram_channels[SRAM_CH21]); 1116 } 1117 1118 /* risc1 y */ 1119 if (status & 0x01) { 1120 spin_lock(&dev->slock); 1121 count = cx_read(MO_VIDY_GPCNT); 1122 cx88_wakeup(core, &dev->vidq, count); 1123 spin_unlock(&dev->slock); 1124 } 1125 1126 /* risc1 vbi */ 1127 if (status & 0x08) { 1128 spin_lock(&dev->slock); 1129 count = cx_read(MO_VBI_GPCNT); 1130 cx88_wakeup(core, &dev->vbiq, count); 1131 spin_unlock(&dev->slock); 1132 } 1133 } 1134 1135 static irqreturn_t cx8800_irq(int irq, void *dev_id) 1136 { 1137 struct cx8800_dev *dev = dev_id; 1138 struct cx88_core *core = dev->core; 1139 u32 status; 1140 int loop, handled = 0; 1141 1142 for (loop = 0; loop < 10; loop++) { 1143 status = cx_read(MO_PCI_INTSTAT) & 1144 (core->pci_irqmask | PCI_INT_VIDINT); 1145 if (status == 0) 1146 goto out; 1147 cx_write(MO_PCI_INTSTAT, status); 1148 handled = 1; 1149 1150 if (status & core->pci_irqmask) 1151 cx88_core_irq(core, status); 1152 if (status & PCI_INT_VIDINT) 1153 cx8800_vid_irq(dev); 1154 } 1155 if (loop == 10) { 1156 pr_warn("irq loop -- clearing mask\n"); 1157 cx_write(MO_PCI_INTMSK, 0); 1158 } 1159 1160 out: 1161 return IRQ_RETVAL(handled); 1162 } 1163 1164 /* ----------------------------------------------------------- */ 1165 /* exported stuff */ 1166 1167 static const struct v4l2_file_operations video_fops = { 1168 .owner = THIS_MODULE, 1169 .open = v4l2_fh_open, 1170 .release = vb2_fop_release, 1171 .read = vb2_fop_read, 1172 .poll = vb2_fop_poll, 1173 .mmap = vb2_fop_mmap, 1174 .unlocked_ioctl = video_ioctl2, 1175 }; 1176 1177 static const struct v4l2_ioctl_ops video_ioctl_ops = { 1178 .vidioc_querycap = vidioc_querycap, 1179 .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap, 1180 .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap, 1181 .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap, 1182 .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap, 1183 .vidioc_reqbufs = vb2_ioctl_reqbufs, 1184 .vidioc_querybuf = vb2_ioctl_querybuf, 1185 .vidioc_qbuf = vb2_ioctl_qbuf, 1186 .vidioc_dqbuf = vb2_ioctl_dqbuf, 1187 .vidioc_g_std = vidioc_g_std, 1188 .vidioc_s_std = vidioc_s_std, 1189 .vidioc_enum_input = vidioc_enum_input, 1190 .vidioc_g_input = vidioc_g_input, 1191 .vidioc_s_input = vidioc_s_input, 1192 .vidioc_streamon = vb2_ioctl_streamon, 1193 .vidioc_streamoff = vb2_ioctl_streamoff, 1194 .vidioc_g_tuner = vidioc_g_tuner, 1195 .vidioc_s_tuner = vidioc_s_tuner, 1196 .vidioc_g_frequency = vidioc_g_frequency, 1197 .vidioc_s_frequency = vidioc_s_frequency, 1198 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, 1199 .vidioc_unsubscribe_event = v4l2_event_unsubscribe, 1200 #ifdef CONFIG_VIDEO_ADV_DEBUG 1201 .vidioc_g_register = vidioc_g_register, 1202 .vidioc_s_register = vidioc_s_register, 1203 #endif 1204 }; 1205 1206 static const struct video_device cx8800_video_template = { 1207 .name = "cx8800-video", 1208 .fops = &video_fops, 1209 .ioctl_ops = &video_ioctl_ops, 1210 .tvnorms = CX88_NORMS, 1211 }; 1212 1213 static const struct v4l2_ioctl_ops vbi_ioctl_ops = { 1214 .vidioc_querycap = vidioc_querycap, 1215 .vidioc_g_fmt_vbi_cap = cx8800_vbi_fmt, 1216 .vidioc_try_fmt_vbi_cap = cx8800_vbi_fmt, 1217 .vidioc_s_fmt_vbi_cap = cx8800_vbi_fmt, 1218 .vidioc_reqbufs = vb2_ioctl_reqbufs, 1219 .vidioc_querybuf = vb2_ioctl_querybuf, 1220 .vidioc_qbuf = vb2_ioctl_qbuf, 1221 .vidioc_dqbuf = vb2_ioctl_dqbuf, 1222 .vidioc_g_std = vidioc_g_std, 1223 .vidioc_s_std = vidioc_s_std, 1224 .vidioc_enum_input = vidioc_enum_input, 1225 .vidioc_g_input = vidioc_g_input, 1226 .vidioc_s_input = vidioc_s_input, 1227 .vidioc_streamon = vb2_ioctl_streamon, 1228 .vidioc_streamoff = vb2_ioctl_streamoff, 1229 .vidioc_g_tuner = vidioc_g_tuner, 1230 .vidioc_s_tuner = vidioc_s_tuner, 1231 .vidioc_g_frequency = vidioc_g_frequency, 1232 .vidioc_s_frequency = vidioc_s_frequency, 1233 #ifdef CONFIG_VIDEO_ADV_DEBUG 1234 .vidioc_g_register = vidioc_g_register, 1235 .vidioc_s_register = vidioc_s_register, 1236 #endif 1237 }; 1238 1239 static const struct video_device cx8800_vbi_template = { 1240 .name = "cx8800-vbi", 1241 .fops = &video_fops, 1242 .ioctl_ops = &vbi_ioctl_ops, 1243 .tvnorms = CX88_NORMS, 1244 }; 1245 1246 static const struct v4l2_file_operations radio_fops = { 1247 .owner = THIS_MODULE, 1248 .open = radio_open, 1249 .poll = v4l2_ctrl_poll, 1250 .release = v4l2_fh_release, 1251 .unlocked_ioctl = video_ioctl2, 1252 }; 1253 1254 static const struct v4l2_ioctl_ops radio_ioctl_ops = { 1255 .vidioc_querycap = vidioc_querycap, 1256 .vidioc_g_tuner = radio_g_tuner, 1257 .vidioc_s_tuner = radio_s_tuner, 1258 .vidioc_g_frequency = vidioc_g_frequency, 1259 .vidioc_s_frequency = vidioc_s_frequency, 1260 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, 1261 .vidioc_unsubscribe_event = v4l2_event_unsubscribe, 1262 #ifdef CONFIG_VIDEO_ADV_DEBUG 1263 .vidioc_g_register = vidioc_g_register, 1264 .vidioc_s_register = vidioc_s_register, 1265 #endif 1266 }; 1267 1268 static const struct video_device cx8800_radio_template = { 1269 .name = "cx8800-radio", 1270 .fops = &radio_fops, 1271 .ioctl_ops = &radio_ioctl_ops, 1272 }; 1273 1274 static const struct v4l2_ctrl_ops cx8800_ctrl_vid_ops = { 1275 .s_ctrl = cx8800_s_vid_ctrl, 1276 }; 1277 1278 static const struct v4l2_ctrl_ops cx8800_ctrl_aud_ops = { 1279 .s_ctrl = cx8800_s_aud_ctrl, 1280 }; 1281 1282 /* ----------------------------------------------------------- */ 1283 1284 static void cx8800_unregister_video(struct cx8800_dev *dev) 1285 { 1286 video_unregister_device(&dev->radio_dev); 1287 video_unregister_device(&dev->vbi_dev); 1288 video_unregister_device(&dev->video_dev); 1289 } 1290 1291 static int cx8800_initdev(struct pci_dev *pci_dev, 1292 const struct pci_device_id *pci_id) 1293 { 1294 struct cx8800_dev *dev; 1295 struct cx88_core *core; 1296 struct vb2_queue *q; 1297 int err; 1298 int i; 1299 1300 dev = kzalloc(sizeof(*dev), GFP_KERNEL); 1301 if (!dev) 1302 return -ENOMEM; 1303 1304 /* pci init */ 1305 dev->pci = pci_dev; 1306 if (pci_enable_device(pci_dev)) { 1307 err = -EIO; 1308 goto fail_free; 1309 } 1310 core = cx88_core_get(dev->pci); 1311 if (!core) { 1312 err = -EINVAL; 1313 goto fail_free; 1314 } 1315 dev->core = core; 1316 1317 /* print pci info */ 1318 dev->pci_rev = pci_dev->revision; 1319 pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat); 1320 pr_info("found at %s, rev: %d, irq: %d, latency: %d, mmio: 0x%llx\n", 1321 pci_name(pci_dev), dev->pci_rev, pci_dev->irq, 1322 dev->pci_lat, 1323 (unsigned long long)pci_resource_start(pci_dev, 0)); 1324 1325 pci_set_master(pci_dev); 1326 err = pci_set_dma_mask(pci_dev, DMA_BIT_MASK(32)); 1327 if (err) { 1328 pr_err("Oops: no 32bit PCI DMA ???\n"); 1329 goto fail_core; 1330 } 1331 1332 /* initialize driver struct */ 1333 spin_lock_init(&dev->slock); 1334 1335 /* init video dma queues */ 1336 INIT_LIST_HEAD(&dev->vidq.active); 1337 1338 /* init vbi dma queues */ 1339 INIT_LIST_HEAD(&dev->vbiq.active); 1340 1341 /* get irq */ 1342 err = request_irq(pci_dev->irq, cx8800_irq, 1343 IRQF_SHARED, core->name, dev); 1344 if (err < 0) { 1345 pr_err("can't get IRQ %d\n", pci_dev->irq); 1346 goto fail_core; 1347 } 1348 cx_set(MO_PCI_INTMSK, core->pci_irqmask); 1349 1350 for (i = 0; i < CX8800_AUD_CTLS; i++) { 1351 const struct cx88_ctrl *cc = &cx8800_aud_ctls[i]; 1352 struct v4l2_ctrl *vc; 1353 1354 vc = v4l2_ctrl_new_std(&core->audio_hdl, &cx8800_ctrl_aud_ops, 1355 cc->id, cc->minimum, cc->maximum, 1356 cc->step, cc->default_value); 1357 if (!vc) { 1358 err = core->audio_hdl.error; 1359 goto fail_core; 1360 } 1361 vc->priv = (void *)cc; 1362 } 1363 1364 for (i = 0; i < CX8800_VID_CTLS; i++) { 1365 const struct cx88_ctrl *cc = &cx8800_vid_ctls[i]; 1366 struct v4l2_ctrl *vc; 1367 1368 vc = v4l2_ctrl_new_std(&core->video_hdl, &cx8800_ctrl_vid_ops, 1369 cc->id, cc->minimum, cc->maximum, 1370 cc->step, cc->default_value); 1371 if (!vc) { 1372 err = core->video_hdl.error; 1373 goto fail_core; 1374 } 1375 vc->priv = (void *)cc; 1376 if (vc->id == V4L2_CID_CHROMA_AGC) 1377 core->chroma_agc = vc; 1378 } 1379 v4l2_ctrl_add_handler(&core->video_hdl, &core->audio_hdl, NULL); 1380 1381 /* load and configure helper modules */ 1382 1383 if (core->board.audio_chip == CX88_AUDIO_WM8775) { 1384 struct i2c_board_info wm8775_info = { 1385 .type = "wm8775", 1386 .addr = 0x36 >> 1, 1387 .platform_data = &core->wm8775_data, 1388 }; 1389 struct v4l2_subdev *sd; 1390 1391 if (core->boardnr == CX88_BOARD_HAUPPAUGE_NOVASPLUS_S1) 1392 core->wm8775_data.is_nova_s = true; 1393 else 1394 core->wm8775_data.is_nova_s = false; 1395 1396 sd = v4l2_i2c_new_subdev_board(&core->v4l2_dev, &core->i2c_adap, 1397 &wm8775_info, NULL); 1398 if (sd) { 1399 core->sd_wm8775 = sd; 1400 sd->grp_id = WM8775_GID; 1401 } 1402 } 1403 1404 if (core->board.audio_chip == CX88_AUDIO_TVAUDIO) { 1405 /* 1406 * This probes for a tda9874 as is used on some 1407 * Pixelview Ultra boards. 1408 */ 1409 v4l2_i2c_new_subdev(&core->v4l2_dev, &core->i2c_adap, 1410 "tvaudio", 0, I2C_ADDRS(0xb0 >> 1)); 1411 } 1412 1413 switch (core->boardnr) { 1414 case CX88_BOARD_DVICO_FUSIONHDTV_5_GOLD: 1415 case CX88_BOARD_DVICO_FUSIONHDTV_7_GOLD: { 1416 static const struct i2c_board_info rtc_info = { 1417 I2C_BOARD_INFO("isl1208", 0x6f) 1418 }; 1419 1420 request_module("rtc-isl1208"); 1421 core->i2c_rtc = i2c_new_device(&core->i2c_adap, &rtc_info); 1422 } 1423 /* break intentionally omitted */ 1424 case CX88_BOARD_DVICO_FUSIONHDTV_5_PCI_NANO: 1425 request_module("ir-kbd-i2c"); 1426 } 1427 1428 /* Sets device info at pci_dev */ 1429 pci_set_drvdata(pci_dev, dev); 1430 1431 dev->fmt = format_by_fourcc(V4L2_PIX_FMT_BGR24); 1432 1433 /* Maintain a reference so cx88-blackbird can query the 8800 device. */ 1434 core->v4ldev = dev; 1435 1436 /* initial device configuration */ 1437 mutex_lock(&core->lock); 1438 cx88_set_tvnorm(core, core->tvnorm); 1439 v4l2_ctrl_handler_setup(&core->video_hdl); 1440 v4l2_ctrl_handler_setup(&core->audio_hdl); 1441 cx88_video_mux(core, 0); 1442 1443 q = &dev->vb2_vidq; 1444 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; 1445 q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF | VB2_READ; 1446 q->gfp_flags = GFP_DMA32; 1447 q->min_buffers_needed = 2; 1448 q->drv_priv = dev; 1449 q->buf_struct_size = sizeof(struct cx88_buffer); 1450 q->ops = &cx8800_video_qops; 1451 q->mem_ops = &vb2_dma_sg_memops; 1452 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; 1453 q->lock = &core->lock; 1454 q->dev = &dev->pci->dev; 1455 1456 err = vb2_queue_init(q); 1457 if (err < 0) 1458 goto fail_unreg; 1459 1460 q = &dev->vb2_vbiq; 1461 q->type = V4L2_BUF_TYPE_VBI_CAPTURE; 1462 q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF | VB2_READ; 1463 q->gfp_flags = GFP_DMA32; 1464 q->min_buffers_needed = 2; 1465 q->drv_priv = dev; 1466 q->buf_struct_size = sizeof(struct cx88_buffer); 1467 q->ops = &cx8800_vbi_qops; 1468 q->mem_ops = &vb2_dma_sg_memops; 1469 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; 1470 q->lock = &core->lock; 1471 q->dev = &dev->pci->dev; 1472 1473 err = vb2_queue_init(q); 1474 if (err < 0) 1475 goto fail_unreg; 1476 1477 /* register v4l devices */ 1478 cx88_vdev_init(core, dev->pci, &dev->video_dev, 1479 &cx8800_video_template, "video"); 1480 video_set_drvdata(&dev->video_dev, dev); 1481 dev->video_dev.ctrl_handler = &core->video_hdl; 1482 dev->video_dev.queue = &dev->vb2_vidq; 1483 err = video_register_device(&dev->video_dev, VFL_TYPE_GRABBER, 1484 video_nr[core->nr]); 1485 if (err < 0) { 1486 pr_err("can't register video device\n"); 1487 goto fail_unreg; 1488 } 1489 pr_info("registered device %s [v4l2]\n", 1490 video_device_node_name(&dev->video_dev)); 1491 1492 cx88_vdev_init(core, dev->pci, &dev->vbi_dev, 1493 &cx8800_vbi_template, "vbi"); 1494 video_set_drvdata(&dev->vbi_dev, dev); 1495 dev->vbi_dev.queue = &dev->vb2_vbiq; 1496 err = video_register_device(&dev->vbi_dev, VFL_TYPE_VBI, 1497 vbi_nr[core->nr]); 1498 if (err < 0) { 1499 pr_err("can't register vbi device\n"); 1500 goto fail_unreg; 1501 } 1502 pr_info("registered device %s\n", 1503 video_device_node_name(&dev->vbi_dev)); 1504 1505 if (core->board.radio.type == CX88_RADIO) { 1506 cx88_vdev_init(core, dev->pci, &dev->radio_dev, 1507 &cx8800_radio_template, "radio"); 1508 video_set_drvdata(&dev->radio_dev, dev); 1509 dev->radio_dev.ctrl_handler = &core->audio_hdl; 1510 err = video_register_device(&dev->radio_dev, VFL_TYPE_RADIO, 1511 radio_nr[core->nr]); 1512 if (err < 0) { 1513 pr_err("can't register radio device\n"); 1514 goto fail_unreg; 1515 } 1516 pr_info("registered device %s\n", 1517 video_device_node_name(&dev->radio_dev)); 1518 } 1519 1520 /* start tvaudio thread */ 1521 if (core->board.tuner_type != UNSET) { 1522 core->kthread = kthread_run(cx88_audio_thread, 1523 core, "cx88 tvaudio"); 1524 if (IS_ERR(core->kthread)) { 1525 err = PTR_ERR(core->kthread); 1526 pr_err("failed to create cx88 audio thread, err=%d\n", 1527 err); 1528 } 1529 } 1530 mutex_unlock(&core->lock); 1531 1532 return 0; 1533 1534 fail_unreg: 1535 cx8800_unregister_video(dev); 1536 free_irq(pci_dev->irq, dev); 1537 mutex_unlock(&core->lock); 1538 fail_core: 1539 core->v4ldev = NULL; 1540 cx88_core_put(core, dev->pci); 1541 fail_free: 1542 kfree(dev); 1543 return err; 1544 } 1545 1546 static void cx8800_finidev(struct pci_dev *pci_dev) 1547 { 1548 struct cx8800_dev *dev = pci_get_drvdata(pci_dev); 1549 struct cx88_core *core = dev->core; 1550 1551 /* stop thread */ 1552 if (core->kthread) { 1553 kthread_stop(core->kthread); 1554 core->kthread = NULL; 1555 } 1556 1557 if (core->ir) 1558 cx88_ir_stop(core); 1559 1560 cx88_shutdown(core); /* FIXME */ 1561 1562 /* unregister stuff */ 1563 1564 free_irq(pci_dev->irq, dev); 1565 cx8800_unregister_video(dev); 1566 pci_disable_device(pci_dev); 1567 1568 core->v4ldev = NULL; 1569 1570 /* free memory */ 1571 cx88_core_put(core, dev->pci); 1572 kfree(dev); 1573 } 1574 1575 #ifdef CONFIG_PM 1576 static int cx8800_suspend(struct pci_dev *pci_dev, pm_message_t state) 1577 { 1578 struct cx8800_dev *dev = pci_get_drvdata(pci_dev); 1579 struct cx88_core *core = dev->core; 1580 unsigned long flags; 1581 1582 /* stop video+vbi capture */ 1583 spin_lock_irqsave(&dev->slock, flags); 1584 if (!list_empty(&dev->vidq.active)) { 1585 pr_info("suspend video\n"); 1586 stop_video_dma(dev); 1587 } 1588 if (!list_empty(&dev->vbiq.active)) { 1589 pr_info("suspend vbi\n"); 1590 cx8800_stop_vbi_dma(dev); 1591 } 1592 spin_unlock_irqrestore(&dev->slock, flags); 1593 1594 if (core->ir) 1595 cx88_ir_stop(core); 1596 /* FIXME -- shutdown device */ 1597 cx88_shutdown(core); 1598 1599 pci_save_state(pci_dev); 1600 if (pci_set_power_state(pci_dev, 1601 pci_choose_state(pci_dev, state)) != 0) { 1602 pci_disable_device(pci_dev); 1603 dev->state.disabled = 1; 1604 } 1605 return 0; 1606 } 1607 1608 static int cx8800_resume(struct pci_dev *pci_dev) 1609 { 1610 struct cx8800_dev *dev = pci_get_drvdata(pci_dev); 1611 struct cx88_core *core = dev->core; 1612 unsigned long flags; 1613 int err; 1614 1615 if (dev->state.disabled) { 1616 err = pci_enable_device(pci_dev); 1617 if (err) { 1618 pr_err("can't enable device\n"); 1619 return err; 1620 } 1621 1622 dev->state.disabled = 0; 1623 } 1624 err = pci_set_power_state(pci_dev, PCI_D0); 1625 if (err) { 1626 pr_err("can't set power state\n"); 1627 pci_disable_device(pci_dev); 1628 dev->state.disabled = 1; 1629 1630 return err; 1631 } 1632 pci_restore_state(pci_dev); 1633 1634 /* FIXME: re-initialize hardware */ 1635 cx88_reset(core); 1636 if (core->ir) 1637 cx88_ir_start(core); 1638 1639 cx_set(MO_PCI_INTMSK, core->pci_irqmask); 1640 1641 /* restart video+vbi capture */ 1642 spin_lock_irqsave(&dev->slock, flags); 1643 if (!list_empty(&dev->vidq.active)) { 1644 pr_info("resume video\n"); 1645 restart_video_queue(dev, &dev->vidq); 1646 } 1647 if (!list_empty(&dev->vbiq.active)) { 1648 pr_info("resume vbi\n"); 1649 cx8800_restart_vbi_queue(dev, &dev->vbiq); 1650 } 1651 spin_unlock_irqrestore(&dev->slock, flags); 1652 1653 return 0; 1654 } 1655 #endif 1656 1657 /* ----------------------------------------------------------- */ 1658 1659 static const struct pci_device_id cx8800_pci_tbl[] = { 1660 { 1661 .vendor = 0x14f1, 1662 .device = 0x8800, 1663 .subvendor = PCI_ANY_ID, 1664 .subdevice = PCI_ANY_ID, 1665 }, { 1666 /* --- end of list --- */ 1667 } 1668 }; 1669 MODULE_DEVICE_TABLE(pci, cx8800_pci_tbl); 1670 1671 static struct pci_driver cx8800_pci_driver = { 1672 .name = "cx8800", 1673 .id_table = cx8800_pci_tbl, 1674 .probe = cx8800_initdev, 1675 .remove = cx8800_finidev, 1676 #ifdef CONFIG_PM 1677 .suspend = cx8800_suspend, 1678 .resume = cx8800_resume, 1679 #endif 1680 }; 1681 1682 module_pci_driver(cx8800_pci_driver); 1683