xref: /linux/drivers/media/pci/cx25821/cx25821.h (revision 8be98d2f2a0a262f8bf8a0bc1fdf522b3c7aab17)
1*c942fddfSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */
2b285192aSMauro Carvalho Chehab /*
3b285192aSMauro Carvalho Chehab  *  Driver for the Conexant CX25821 PCIe bridge
4b285192aSMauro Carvalho Chehab  *
5b285192aSMauro Carvalho Chehab  *  Copyright (C) 2009 Conexant Systems Inc.
6b285192aSMauro Carvalho Chehab  *  Authors  <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
7b285192aSMauro Carvalho Chehab  *  Based on Steven Toth <stoth@linuxtv.org> cx23885 driver
8b285192aSMauro Carvalho Chehab  */
9b285192aSMauro Carvalho Chehab 
10b285192aSMauro Carvalho Chehab #ifndef CX25821_H_
11b285192aSMauro Carvalho Chehab #define CX25821_H_
12b285192aSMauro Carvalho Chehab 
13b285192aSMauro Carvalho Chehab #include <linux/pci.h>
14b285192aSMauro Carvalho Chehab #include <linux/i2c.h>
15b285192aSMauro Carvalho Chehab #include <linux/interrupt.h>
16b285192aSMauro Carvalho Chehab #include <linux/delay.h>
17b285192aSMauro Carvalho Chehab #include <linux/sched.h>
18b285192aSMauro Carvalho Chehab #include <linux/kdev_t.h>
19b285192aSMauro Carvalho Chehab 
20b285192aSMauro Carvalho Chehab #include <media/v4l2-common.h>
21b285192aSMauro Carvalho Chehab #include <media/v4l2-device.h>
22f8d7ee70SHans Verkuil #include <media/v4l2-ctrls.h>
232d700715SJunghak Sung #include <media/videobuf2-v4l2.h>
24b671ae6bSHans Verkuil #include <media/videobuf2-dma-sg.h>
25b285192aSMauro Carvalho Chehab 
26b285192aSMauro Carvalho Chehab #include "cx25821-reg.h"
27b285192aSMauro Carvalho Chehab #include "cx25821-medusa-reg.h"
28b285192aSMauro Carvalho Chehab #include "cx25821-sram.h"
29b285192aSMauro Carvalho Chehab #include "cx25821-audio.h"
30b285192aSMauro Carvalho Chehab 
31b285192aSMauro Carvalho Chehab #include <linux/mutex.h>
32b285192aSMauro Carvalho Chehab 
33b285192aSMauro Carvalho Chehab #define UNSET (-1U)
34b285192aSMauro Carvalho Chehab #define NO_SYNC_LINE (-1U)
35b285192aSMauro Carvalho Chehab 
36b285192aSMauro Carvalho Chehab #define CX25821_MAXBOARDS 2
37b285192aSMauro Carvalho Chehab 
38b285192aSMauro Carvalho Chehab #define LINE_SIZE_D1    1440
39b285192aSMauro Carvalho Chehab 
40b285192aSMauro Carvalho Chehab /* Number of decoders and encoders */
41b285192aSMauro Carvalho Chehab #define MAX_DECODERS            8
42b285192aSMauro Carvalho Chehab #define MAX_ENCODERS            2
43b285192aSMauro Carvalho Chehab #define QUAD_DECODERS           4
44b285192aSMauro Carvalho Chehab #define MAX_CAMERAS             16
45b285192aSMauro Carvalho Chehab 
46b285192aSMauro Carvalho Chehab /* Max number of inputs by card */
47b285192aSMauro Carvalho Chehab #define MAX_CX25821_INPUT     8
48b285192aSMauro Carvalho Chehab #define RESOURCE_VIDEO0       1
49b285192aSMauro Carvalho Chehab #define RESOURCE_VIDEO1       2
50b285192aSMauro Carvalho Chehab #define RESOURCE_VIDEO2       4
51b285192aSMauro Carvalho Chehab #define RESOURCE_VIDEO3       8
52b285192aSMauro Carvalho Chehab #define RESOURCE_VIDEO4       16
53b285192aSMauro Carvalho Chehab #define RESOURCE_VIDEO5       32
54b285192aSMauro Carvalho Chehab #define RESOURCE_VIDEO6       64
55b285192aSMauro Carvalho Chehab #define RESOURCE_VIDEO7       128
56b285192aSMauro Carvalho Chehab #define RESOURCE_VIDEO8       256
57b285192aSMauro Carvalho Chehab #define RESOURCE_VIDEO9       512
58b285192aSMauro Carvalho Chehab #define RESOURCE_VIDEO10      1024
59b285192aSMauro Carvalho Chehab #define RESOURCE_VIDEO11      2048
60b285192aSMauro Carvalho Chehab 
61b285192aSMauro Carvalho Chehab #define BUFFER_TIMEOUT     (HZ)	/* 0.5 seconds */
62b285192aSMauro Carvalho Chehab 
63b285192aSMauro Carvalho Chehab #define UNKNOWN_BOARD        0
64b285192aSMauro Carvalho Chehab #define CX25821_BOARD        1
65b285192aSMauro Carvalho Chehab 
66b285192aSMauro Carvalho Chehab /* Currently supported by the driver */
67b285192aSMauro Carvalho Chehab #define CX25821_NORMS (\
68b285192aSMauro Carvalho Chehab 	V4L2_STD_NTSC_M |  V4L2_STD_NTSC_M_JP | V4L2_STD_NTSC_M_KR | \
69b285192aSMauro Carvalho Chehab 	V4L2_STD_PAL_BG |  V4L2_STD_PAL_DK    |  V4L2_STD_PAL_I    | \
70b285192aSMauro Carvalho Chehab 	V4L2_STD_PAL_M  |  V4L2_STD_PAL_N     |  V4L2_STD_PAL_H    | \
71b285192aSMauro Carvalho Chehab 	V4L2_STD_PAL_Nc)
72b285192aSMauro Carvalho Chehab 
73b285192aSMauro Carvalho Chehab #define CX25821_BOARD_CONEXANT_ATHENA10 1
74b285192aSMauro Carvalho Chehab #define MAX_VID_CHANNEL_NUM     12
75b6f21dc3SHans Verkuil 
76b6f21dc3SHans Verkuil /*
77b6f21dc3SHans Verkuil  * Maximum capture-only channels. This can go away once video/audio output
78b6f21dc3SHans Verkuil  * is fully supported in this driver.
79b6f21dc3SHans Verkuil  */
80b6f21dc3SHans Verkuil #define MAX_VID_CAP_CHANNEL_NUM     10
81b6f21dc3SHans Verkuil 
82b285192aSMauro Carvalho Chehab #define VID_CHANNEL_NUM 8
83b285192aSMauro Carvalho Chehab 
84b285192aSMauro Carvalho Chehab struct cx25821_fmt {
85b285192aSMauro Carvalho Chehab 	u32 fourcc;		/* v4l2 format id */
86b285192aSMauro Carvalho Chehab 	int depth;
87b285192aSMauro Carvalho Chehab 	int flags;
88b285192aSMauro Carvalho Chehab 	u32 cxformat;
89b285192aSMauro Carvalho Chehab };
90b285192aSMauro Carvalho Chehab 
91b285192aSMauro Carvalho Chehab struct cx25821_tvnorm {
92b285192aSMauro Carvalho Chehab 	char *name;
93b285192aSMauro Carvalho Chehab 	v4l2_std_id id;
94b285192aSMauro Carvalho Chehab 	u32 cxiformat;
95b285192aSMauro Carvalho Chehab 	u32 cxoformat;
96b285192aSMauro Carvalho Chehab };
97b285192aSMauro Carvalho Chehab 
98b285192aSMauro Carvalho Chehab enum cx25821_src_sel_type {
99b285192aSMauro Carvalho Chehab 	CX25821_SRC_SEL_EXT_656_VIDEO = 0,
100b285192aSMauro Carvalho Chehab 	CX25821_SRC_SEL_PARALLEL_MPEG_VIDEO
101b285192aSMauro Carvalho Chehab };
102b285192aSMauro Carvalho Chehab 
1035ede94c7SHans Verkuil struct cx25821_riscmem {
1045ede94c7SHans Verkuil 	unsigned int   size;
1055ede94c7SHans Verkuil 	__le32         *cpu;
1065ede94c7SHans Verkuil 	__le32         *jmp;
1075ede94c7SHans Verkuil 	dma_addr_t     dma;
1085ede94c7SHans Verkuil };
1095ede94c7SHans Verkuil 
110b285192aSMauro Carvalho Chehab /* buffer for one video frame */
111b285192aSMauro Carvalho Chehab struct cx25821_buffer {
112b285192aSMauro Carvalho Chehab 	/* common v4l buffer stuff -- must be first */
1132d700715SJunghak Sung 	struct vb2_v4l2_buffer vb;
114b671ae6bSHans Verkuil 	struct list_head queue;
115b285192aSMauro Carvalho Chehab 
116b285192aSMauro Carvalho Chehab 	/* cx25821 specific */
117b285192aSMauro Carvalho Chehab 	unsigned int bpl;
1185ede94c7SHans Verkuil 	struct cx25821_riscmem risc;
11995c232a2SHans Verkuil 	const struct cx25821_fmt *fmt;
120b285192aSMauro Carvalho Chehab };
121b285192aSMauro Carvalho Chehab 
122b285192aSMauro Carvalho Chehab enum port {
123b285192aSMauro Carvalho Chehab 	CX25821_UNDEFINED = 0,
124b285192aSMauro Carvalho Chehab 	CX25821_RAW,
125b285192aSMauro Carvalho Chehab 	CX25821_264
126b285192aSMauro Carvalho Chehab };
127b285192aSMauro Carvalho Chehab 
128b285192aSMauro Carvalho Chehab struct cx25821_board {
129b285192aSMauro Carvalho Chehab 	const char *name;
130b285192aSMauro Carvalho Chehab 	enum port porta;
131b285192aSMauro Carvalho Chehab 	enum port portb;
132b285192aSMauro Carvalho Chehab 	enum port portc;
133b285192aSMauro Carvalho Chehab 
134b285192aSMauro Carvalho Chehab 	u32 clk_freq;
135b285192aSMauro Carvalho Chehab };
136b285192aSMauro Carvalho Chehab 
137b285192aSMauro Carvalho Chehab struct cx25821_i2c {
138b285192aSMauro Carvalho Chehab 	struct cx25821_dev *dev;
139b285192aSMauro Carvalho Chehab 
140b285192aSMauro Carvalho Chehab 	int nr;
141b285192aSMauro Carvalho Chehab 
142b285192aSMauro Carvalho Chehab 	/* i2c i/o */
143b285192aSMauro Carvalho Chehab 	struct i2c_adapter i2c_adap;
144b285192aSMauro Carvalho Chehab 	struct i2c_client i2c_client;
145b285192aSMauro Carvalho Chehab 	u32 i2c_rc;
146b285192aSMauro Carvalho Chehab 
14716790554SMauro Carvalho Chehab 	/* cx25821 registers used for raw address */
148b285192aSMauro Carvalho Chehab 	u32 i2c_period;
149b285192aSMauro Carvalho Chehab 	u32 reg_ctrl;
150b285192aSMauro Carvalho Chehab 	u32 reg_stat;
151b285192aSMauro Carvalho Chehab 	u32 reg_addr;
152b285192aSMauro Carvalho Chehab 	u32 reg_rdata;
153b285192aSMauro Carvalho Chehab 	u32 reg_wdata;
154b285192aSMauro Carvalho Chehab };
155b285192aSMauro Carvalho Chehab 
156b285192aSMauro Carvalho Chehab struct cx25821_dmaqueue {
157b285192aSMauro Carvalho Chehab 	struct list_head active;
158b285192aSMauro Carvalho Chehab 	u32 count;
159b285192aSMauro Carvalho Chehab };
160b285192aSMauro Carvalho Chehab 
161f8d7ee70SHans Verkuil struct cx25821_dev;
162f8d7ee70SHans Verkuil 
1637087d31bSHans Verkuil struct cx25821_channel;
1647087d31bSHans Verkuil 
1657087d31bSHans Verkuil struct cx25821_video_out_data {
1667087d31bSHans Verkuil 	struct cx25821_channel *chan;
1677087d31bSHans Verkuil 	int _line_size;
1687087d31bSHans Verkuil 	int _prog_cnt;
1697087d31bSHans Verkuil 	int _pixel_format;
1707087d31bSHans Verkuil 	int _is_first_frame;
1717087d31bSHans Verkuil 	int _is_running;
1727087d31bSHans Verkuil 	int _file_status;
1737087d31bSHans Verkuil 	int _lines_count;
1747087d31bSHans Verkuil 	int _frame_count;
1757087d31bSHans Verkuil 	unsigned int _risc_size;
1767087d31bSHans Verkuil 
1777087d31bSHans Verkuil 	__le32 *_dma_virt_start_addr;
1787087d31bSHans Verkuil 	__le32 *_dma_virt_addr;
1797087d31bSHans Verkuil 	dma_addr_t _dma_phys_addr;
1807087d31bSHans Verkuil 	dma_addr_t _dma_phys_start_addr;
1817087d31bSHans Verkuil 
1827087d31bSHans Verkuil 	unsigned int _data_buf_size;
1837087d31bSHans Verkuil 	__le32 *_data_buf_virt_addr;
1847087d31bSHans Verkuil 	dma_addr_t _data_buf_phys_addr;
1857087d31bSHans Verkuil 
1867087d31bSHans Verkuil 	u32 upstream_riscbuf_size;
1877087d31bSHans Verkuil 	u32 upstream_databuf_size;
1887087d31bSHans Verkuil 	int is_60hz;
1897087d31bSHans Verkuil 	int _frame_index;
190ea3f7ac6SHans Verkuil 	int cur_frame_index;
191ea3f7ac6SHans Verkuil 	int curpos;
192ea3f7ac6SHans Verkuil 	wait_queue_head_t waitq;
1937087d31bSHans Verkuil };
1947087d31bSHans Verkuil 
195b285192aSMauro Carvalho Chehab struct cx25821_channel {
196f8d7ee70SHans Verkuil 	unsigned id;
197f8d7ee70SHans Verkuil 	struct cx25821_dev *dev;
198b285192aSMauro Carvalho Chehab 
199f8d7ee70SHans Verkuil 	struct v4l2_ctrl_handler hdl;
200b285192aSMauro Carvalho Chehab 
201467870caSHans Verkuil 	struct video_device vdev;
2022efe2cc4SHans Verkuil 	struct cx25821_dmaqueue dma_vidq;
203b671ae6bSHans Verkuil 	struct vb2_queue vidq;
204b285192aSMauro Carvalho Chehab 
205bfef0d35SHans Verkuil 	const struct sram_channel *sram_channels;
206b285192aSMauro Carvalho Chehab 
2072efe2cc4SHans Verkuil 	const struct cx25821_fmt *fmt;
208b671ae6bSHans Verkuil 	unsigned field;
2092efe2cc4SHans Verkuil 	unsigned int width, height;
210b285192aSMauro Carvalho Chehab 	int pixel_formats;
211b285192aSMauro Carvalho Chehab 	int use_cif_resolution;
212b285192aSMauro Carvalho Chehab 	int cif_width;
2137087d31bSHans Verkuil 
2147087d31bSHans Verkuil 	/* video output data for the video output channel */
2157087d31bSHans Verkuil 	struct cx25821_video_out_data *out;
216b285192aSMauro Carvalho Chehab };
217b285192aSMauro Carvalho Chehab 
218a8f35ce3SHans Verkuil struct snd_card;
219a8f35ce3SHans Verkuil 
220b285192aSMauro Carvalho Chehab struct cx25821_dev {
221b285192aSMauro Carvalho Chehab 	struct v4l2_device v4l2_dev;
222b285192aSMauro Carvalho Chehab 
223b285192aSMauro Carvalho Chehab 	/* pci stuff */
224b285192aSMauro Carvalho Chehab 	struct pci_dev *pci;
225b285192aSMauro Carvalho Chehab 	unsigned char pci_rev, pci_lat;
226b285192aSMauro Carvalho Chehab 	int pci_bus, pci_slot;
227b285192aSMauro Carvalho Chehab 	u32 base_io_addr;
228b285192aSMauro Carvalho Chehab 	u32 __iomem *lmmio;
229b285192aSMauro Carvalho Chehab 	u8 __iomem *bmmio;
230b285192aSMauro Carvalho Chehab 	int pci_irqmask;
231b285192aSMauro Carvalho Chehab 	int hwrevision;
232a8f35ce3SHans Verkuil 	/* used by cx25821-alsa */
233a8f35ce3SHans Verkuil 	struct snd_card *card;
234b285192aSMauro Carvalho Chehab 
235b285192aSMauro Carvalho Chehab 	u32 clk_freq;
236b285192aSMauro Carvalho Chehab 
237b285192aSMauro Carvalho Chehab 	/* I2C adapters: Master 1 & 2 (External) & Master 3 (Internal only) */
238b285192aSMauro Carvalho Chehab 	struct cx25821_i2c i2c_bus[3];
239b285192aSMauro Carvalho Chehab 
240b285192aSMauro Carvalho Chehab 	int nr;
241b285192aSMauro Carvalho Chehab 	struct mutex lock;
242b285192aSMauro Carvalho Chehab 
243b285192aSMauro Carvalho Chehab 	struct cx25821_channel channels[MAX_VID_CHANNEL_NUM];
244b285192aSMauro Carvalho Chehab 
245b285192aSMauro Carvalho Chehab 	/* board details */
246b285192aSMauro Carvalho Chehab 	unsigned int board;
247b285192aSMauro Carvalho Chehab 	char name[32];
248b285192aSMauro Carvalho Chehab 
249b285192aSMauro Carvalho Chehab 	/* Analog video */
250b285192aSMauro Carvalho Chehab 	unsigned int input;
251b285192aSMauro Carvalho Chehab 	v4l2_std_id tvnorm;
252b285192aSMauro Carvalho Chehab 	unsigned short _max_num_decoders;
253b285192aSMauro Carvalho Chehab 
254b285192aSMauro Carvalho Chehab 	/* Analog Audio Upstream */
255b285192aSMauro Carvalho Chehab 	int _audio_is_running;
256b285192aSMauro Carvalho Chehab 	int _audiopixel_format;
257b285192aSMauro Carvalho Chehab 	int _is_first_audio_frame;
258b285192aSMauro Carvalho Chehab 	int _audiofile_status;
259b285192aSMauro Carvalho Chehab 	int _audio_lines_count;
260b285192aSMauro Carvalho Chehab 	int _audioframe_count;
261b285192aSMauro Carvalho Chehab 	int _audio_upstream_channel;
262b285192aSMauro Carvalho Chehab 	int _last_index_irq;    /* The last interrupt index processed. */
263b285192aSMauro Carvalho Chehab 
264b285192aSMauro Carvalho Chehab 	__le32 *_risc_audio_jmp_addr;
265b285192aSMauro Carvalho Chehab 	__le32 *_risc_virt_start_addr;
266b285192aSMauro Carvalho Chehab 	__le32 *_risc_virt_addr;
267b285192aSMauro Carvalho Chehab 	dma_addr_t _risc_phys_addr;
268b285192aSMauro Carvalho Chehab 	dma_addr_t _risc_phys_start_addr;
269b285192aSMauro Carvalho Chehab 
270b285192aSMauro Carvalho Chehab 	unsigned int _audiorisc_size;
271b285192aSMauro Carvalho Chehab 	unsigned int _audiodata_buf_size;
272b285192aSMauro Carvalho Chehab 	__le32 *_audiodata_buf_virt_addr;
273b285192aSMauro Carvalho Chehab 	dma_addr_t _audiodata_buf_phys_addr;
274b285192aSMauro Carvalho Chehab 	char *_audiofilename;
2757087d31bSHans Verkuil 	u32 audio_upstream_riscbuf_size;
2767087d31bSHans Verkuil 	u32 audio_upstream_databuf_size;
2777087d31bSHans Verkuil 	int _audioframe_index;
2787087d31bSHans Verkuil 	struct work_struct _audio_work_entry;
2797087d31bSHans Verkuil 	char *input_audiofilename;
280b285192aSMauro Carvalho Chehab 
281b285192aSMauro Carvalho Chehab 	/* V4l */
282b285192aSMauro Carvalho Chehab 	spinlock_t slock;
283b285192aSMauro Carvalho Chehab 
284b285192aSMauro Carvalho Chehab 	/* Video Upstream */
2857087d31bSHans Verkuil 	struct cx25821_video_out_data vid_out_data[2];
286b285192aSMauro Carvalho Chehab };
287b285192aSMauro Carvalho Chehab 
get_cx25821(struct v4l2_device * v4l2_dev)288b285192aSMauro Carvalho Chehab static inline struct cx25821_dev *get_cx25821(struct v4l2_device *v4l2_dev)
289b285192aSMauro Carvalho Chehab {
290b285192aSMauro Carvalho Chehab 	return container_of(v4l2_dev, struct cx25821_dev, v4l2_dev);
291b285192aSMauro Carvalho Chehab }
292b285192aSMauro Carvalho Chehab 
293b285192aSMauro Carvalho Chehab extern struct cx25821_board cx25821_boards[];
294b285192aSMauro Carvalho Chehab 
295b285192aSMauro Carvalho Chehab #define SRAM_CH00  0		/* Video A */
296b285192aSMauro Carvalho Chehab #define SRAM_CH01  1		/* Video B */
297b285192aSMauro Carvalho Chehab #define SRAM_CH02  2		/* Video C */
298b285192aSMauro Carvalho Chehab #define SRAM_CH03  3		/* Video D */
299b285192aSMauro Carvalho Chehab #define SRAM_CH04  4		/* Video E */
300b285192aSMauro Carvalho Chehab #define SRAM_CH05  5		/* Video F */
301b285192aSMauro Carvalho Chehab #define SRAM_CH06  6		/* Video G */
302b285192aSMauro Carvalho Chehab #define SRAM_CH07  7		/* Video H */
303b285192aSMauro Carvalho Chehab 
304b285192aSMauro Carvalho Chehab #define SRAM_CH08  8		/* Audio A */
305b285192aSMauro Carvalho Chehab #define SRAM_CH09  9		/* Video Upstream I */
306b285192aSMauro Carvalho Chehab #define SRAM_CH10  10		/* Video Upstream J */
307b285192aSMauro Carvalho Chehab #define SRAM_CH11  11		/* Audio Upstream AUD_CHANNEL_B */
308b285192aSMauro Carvalho Chehab 
309b285192aSMauro Carvalho Chehab #define VID_UPSTREAM_SRAM_CHANNEL_I     SRAM_CH09
310b285192aSMauro Carvalho Chehab #define VID_UPSTREAM_SRAM_CHANNEL_J     SRAM_CH10
311b285192aSMauro Carvalho Chehab #define AUDIO_UPSTREAM_SRAM_CHANNEL_B   SRAM_CH11
312b285192aSMauro Carvalho Chehab 
313b285192aSMauro Carvalho Chehab struct sram_channel {
314b285192aSMauro Carvalho Chehab 	char *name;
315b285192aSMauro Carvalho Chehab 	u32 i;
316b285192aSMauro Carvalho Chehab 	u32 cmds_start;
317b285192aSMauro Carvalho Chehab 	u32 ctrl_start;
318b285192aSMauro Carvalho Chehab 	u32 cdt;
319b285192aSMauro Carvalho Chehab 	u32 fifo_start;
320b285192aSMauro Carvalho Chehab 	u32 fifo_size;
321b285192aSMauro Carvalho Chehab 	u32 ptr1_reg;
322b285192aSMauro Carvalho Chehab 	u32 ptr2_reg;
323b285192aSMauro Carvalho Chehab 	u32 cnt1_reg;
324b285192aSMauro Carvalho Chehab 	u32 cnt2_reg;
325b285192aSMauro Carvalho Chehab 	u32 int_msk;
326b285192aSMauro Carvalho Chehab 	u32 int_stat;
327b285192aSMauro Carvalho Chehab 	u32 int_mstat;
328b285192aSMauro Carvalho Chehab 	u32 dma_ctl;
329b285192aSMauro Carvalho Chehab 	u32 gpcnt_ctl;
330b285192aSMauro Carvalho Chehab 	u32 gpcnt;
331b285192aSMauro Carvalho Chehab 	u32 aud_length;
332b285192aSMauro Carvalho Chehab 	u32 aud_cfg;
333b285192aSMauro Carvalho Chehab 	u32 fld_aud_fifo_en;
334b285192aSMauro Carvalho Chehab 	u32 fld_aud_risc_en;
335b285192aSMauro Carvalho Chehab 
336b285192aSMauro Carvalho Chehab 	/* For Upstream Video */
337b285192aSMauro Carvalho Chehab 	u32 vid_fmt_ctl;
338b285192aSMauro Carvalho Chehab 	u32 vid_active_ctl1;
339b285192aSMauro Carvalho Chehab 	u32 vid_active_ctl2;
340b285192aSMauro Carvalho Chehab 	u32 vid_cdt_size;
341b285192aSMauro Carvalho Chehab 
342b285192aSMauro Carvalho Chehab 	u32 vip_ctl;
343b285192aSMauro Carvalho Chehab 	u32 pix_frmt;
344b285192aSMauro Carvalho Chehab 	u32 jumponly;
345b285192aSMauro Carvalho Chehab 	u32 irq_bit;
346b285192aSMauro Carvalho Chehab };
347bfef0d35SHans Verkuil 
348bfef0d35SHans Verkuil extern const struct sram_channel cx25821_sram_channels[];
349b285192aSMauro Carvalho Chehab 
350b285192aSMauro Carvalho Chehab #define cx_read(reg)             readl(dev->lmmio + ((reg)>>2))
351b285192aSMauro Carvalho Chehab #define cx_write(reg, value)     writel((value), dev->lmmio + ((reg)>>2))
352b285192aSMauro Carvalho Chehab 
353b285192aSMauro Carvalho Chehab #define cx_andor(reg, mask, value) \
354b285192aSMauro Carvalho Chehab 	writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) |\
355b285192aSMauro Carvalho Chehab 	((value) & (mask)), dev->lmmio+((reg)>>2))
356b285192aSMauro Carvalho Chehab 
357b285192aSMauro Carvalho Chehab #define cx_set(reg, bit)          cx_andor((reg), (bit), (bit))
358b285192aSMauro Carvalho Chehab #define cx_clear(reg, bit)        cx_andor((reg), (bit), 0)
359b285192aSMauro Carvalho Chehab 
360b285192aSMauro Carvalho Chehab #define Set_GPIO_Bit(Bit)                       (1 << Bit)
361b285192aSMauro Carvalho Chehab #define Clear_GPIO_Bit(Bit)                     (~(1 << Bit))
362b285192aSMauro Carvalho Chehab 
363b285192aSMauro Carvalho Chehab #define CX25821_ERR(fmt, args...)			\
364b285192aSMauro Carvalho Chehab 	pr_err("(%d): " fmt, dev->board, ##args)
365b285192aSMauro Carvalho Chehab #define CX25821_WARN(fmt, args...)			\
366b285192aSMauro Carvalho Chehab 	pr_warn("(%d): " fmt, dev->board, ##args)
367b285192aSMauro Carvalho Chehab #define CX25821_INFO(fmt, args...)			\
368b285192aSMauro Carvalho Chehab 	pr_info("(%d): " fmt, dev->board, ##args)
369b285192aSMauro Carvalho Chehab 
370b285192aSMauro Carvalho Chehab extern int cx25821_i2c_register(struct cx25821_i2c *bus);
371b285192aSMauro Carvalho Chehab extern int cx25821_i2c_read(struct cx25821_i2c *bus, u16 reg_addr, int *value);
372b285192aSMauro Carvalho Chehab extern int cx25821_i2c_write(struct cx25821_i2c *bus, u16 reg_addr, int value);
373b285192aSMauro Carvalho Chehab extern int cx25821_i2c_unregister(struct cx25821_i2c *bus);
374b285192aSMauro Carvalho Chehab extern void cx25821_gpio_init(struct cx25821_dev *dev);
375b285192aSMauro Carvalho Chehab extern void cx25821_set_gpiopin_direction(struct cx25821_dev *dev,
376b285192aSMauro Carvalho Chehab 					  int pin_number, int pin_logic_value);
377b285192aSMauro Carvalho Chehab 
378b285192aSMauro Carvalho Chehab extern int medusa_video_init(struct cx25821_dev *dev);
379b285192aSMauro Carvalho Chehab extern int medusa_set_videostandard(struct cx25821_dev *dev);
380b285192aSMauro Carvalho Chehab extern void medusa_set_resolution(struct cx25821_dev *dev, int width,
381b285192aSMauro Carvalho Chehab 				  int decoder_select);
382b285192aSMauro Carvalho Chehab extern int medusa_set_brightness(struct cx25821_dev *dev, int brightness,
383b285192aSMauro Carvalho Chehab 				 int decoder);
384b285192aSMauro Carvalho Chehab extern int medusa_set_contrast(struct cx25821_dev *dev, int contrast,
385b285192aSMauro Carvalho Chehab 			       int decoder);
386b285192aSMauro Carvalho Chehab extern int medusa_set_hue(struct cx25821_dev *dev, int hue, int decoder);
387b285192aSMauro Carvalho Chehab extern int medusa_set_saturation(struct cx25821_dev *dev, int saturation,
388b285192aSMauro Carvalho Chehab 				 int decoder);
389b285192aSMauro Carvalho Chehab 
390b285192aSMauro Carvalho Chehab extern int cx25821_sram_channel_setup(struct cx25821_dev *dev,
391bfef0d35SHans Verkuil 				      const struct sram_channel *ch, unsigned int bpl,
392b285192aSMauro Carvalho Chehab 				      u32 risc);
393b285192aSMauro Carvalho Chehab 
3945ede94c7SHans Verkuil extern int cx25821_riscmem_alloc(struct pci_dev *pci,
3955ede94c7SHans Verkuil 				 struct cx25821_riscmem *risc,
3965ede94c7SHans Verkuil 				 unsigned int size);
3975ede94c7SHans Verkuil extern int cx25821_risc_buffer(struct pci_dev *pci, struct cx25821_riscmem *risc,
398b285192aSMauro Carvalho Chehab 			       struct scatterlist *sglist,
399b285192aSMauro Carvalho Chehab 			       unsigned int top_offset,
400b285192aSMauro Carvalho Chehab 			       unsigned int bottom_offset,
401b285192aSMauro Carvalho Chehab 			       unsigned int bpl,
402b285192aSMauro Carvalho Chehab 			       unsigned int padding, unsigned int lines);
403b285192aSMauro Carvalho Chehab extern int cx25821_risc_databuffer_audio(struct pci_dev *pci,
4045ede94c7SHans Verkuil 					 struct cx25821_riscmem *risc,
405b285192aSMauro Carvalho Chehab 					 struct scatterlist *sglist,
406b285192aSMauro Carvalho Chehab 					 unsigned int bpl,
407b285192aSMauro Carvalho Chehab 					 unsigned int lines, unsigned int lpi);
408b671ae6bSHans Verkuil extern void cx25821_free_buffer(struct cx25821_dev *dev,
409b285192aSMauro Carvalho Chehab 				struct cx25821_buffer *buf);
410b285192aSMauro Carvalho Chehab extern void cx25821_sram_channel_dump(struct cx25821_dev *dev,
411bfef0d35SHans Verkuil 				      const struct sram_channel *ch);
412b285192aSMauro Carvalho Chehab extern void cx25821_sram_channel_dump_audio(struct cx25821_dev *dev,
413bfef0d35SHans Verkuil 					    const struct sram_channel *ch);
414b285192aSMauro Carvalho Chehab 
415b285192aSMauro Carvalho Chehab extern struct cx25821_dev *cx25821_dev_get(struct pci_dev *pci);
416b285192aSMauro Carvalho Chehab extern void cx25821_print_irqbits(char *name, char *tag, char **strings,
417b285192aSMauro Carvalho Chehab 				  int len, u32 bits, u32 mask);
418b285192aSMauro Carvalho Chehab extern void cx25821_dev_unregister(struct cx25821_dev *dev);
419b285192aSMauro Carvalho Chehab extern int cx25821_sram_channel_setup_audio(struct cx25821_dev *dev,
420bfef0d35SHans Verkuil 					    const struct sram_channel *ch,
421b285192aSMauro Carvalho Chehab 					    unsigned int bpl, u32 risc);
422b285192aSMauro Carvalho Chehab 
423b285192aSMauro Carvalho Chehab extern void cx25821_set_pixel_format(struct cx25821_dev *dev, int channel,
424b285192aSMauro Carvalho Chehab 				     u32 format);
42595c232a2SHans Verkuil 
426b285192aSMauro Carvalho Chehab #endif
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