1 /* 2 * Driver for the Conexant CX25821 PCIe bridge 3 * 4 * Copyright (C) 2009 Conexant Systems Inc. 5 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * 16 * GNU General Public License for more details. 17 */ 18 19 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 20 21 #include "cx25821.h" 22 #include "cx25821-medusa-video.h" 23 #include "cx25821-biffuncs.h" 24 25 /* 26 * medusa_enable_bluefield_output() 27 * 28 * Enable the generation of blue filed output if no video 29 * 30 */ 31 static void medusa_enable_bluefield_output(struct cx25821_dev *dev, int channel, 32 int enable) 33 { 34 u32 value = 0; 35 u32 tmp = 0; 36 int out_ctrl = OUT_CTRL1; 37 int out_ctrl_ns = OUT_CTRL_NS; 38 39 switch (channel) { 40 default: 41 case VDEC_A: 42 break; 43 case VDEC_B: 44 out_ctrl = VDEC_B_OUT_CTRL1; 45 out_ctrl_ns = VDEC_B_OUT_CTRL_NS; 46 break; 47 case VDEC_C: 48 out_ctrl = VDEC_C_OUT_CTRL1; 49 out_ctrl_ns = VDEC_C_OUT_CTRL_NS; 50 break; 51 case VDEC_D: 52 out_ctrl = VDEC_D_OUT_CTRL1; 53 out_ctrl_ns = VDEC_D_OUT_CTRL_NS; 54 break; 55 case VDEC_E: 56 out_ctrl = VDEC_E_OUT_CTRL1; 57 out_ctrl_ns = VDEC_E_OUT_CTRL_NS; 58 return; 59 case VDEC_F: 60 out_ctrl = VDEC_F_OUT_CTRL1; 61 out_ctrl_ns = VDEC_F_OUT_CTRL_NS; 62 return; 63 case VDEC_G: 64 out_ctrl = VDEC_G_OUT_CTRL1; 65 out_ctrl_ns = VDEC_G_OUT_CTRL_NS; 66 return; 67 case VDEC_H: 68 out_ctrl = VDEC_H_OUT_CTRL1; 69 out_ctrl_ns = VDEC_H_OUT_CTRL_NS; 70 return; 71 } 72 73 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl, &tmp); 74 value &= 0xFFFFFF7F; /* clear BLUE_FIELD_EN */ 75 if (enable) 76 value |= 0x00000080; /* set BLUE_FIELD_EN */ 77 cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl, value); 78 79 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl_ns, &tmp); 80 value &= 0xFFFFFF7F; 81 if (enable) 82 value |= 0x00000080; /* set BLUE_FIELD_EN */ 83 cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl_ns, value); 84 } 85 86 static int medusa_initialize_ntsc(struct cx25821_dev *dev) 87 { 88 int ret_val = 0; 89 int i = 0; 90 u32 value = 0; 91 u32 tmp = 0; 92 93 for (i = 0; i < MAX_DECODERS; i++) { 94 /* set video format NTSC-M */ 95 value = cx25821_i2c_read(&dev->i2c_bus[0], 96 MODE_CTRL + (0x200 * i), &tmp); 97 value &= 0xFFFFFFF0; 98 /* enable the fast locking mode bit[16] */ 99 value |= 0x10001; 100 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 101 MODE_CTRL + (0x200 * i), value); 102 103 /* resolution NTSC 720x480 */ 104 value = cx25821_i2c_read(&dev->i2c_bus[0], 105 HORIZ_TIM_CTRL + (0x200 * i), &tmp); 106 value &= 0x00C00C00; 107 value |= 0x612D0074; 108 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 109 HORIZ_TIM_CTRL + (0x200 * i), value); 110 111 value = cx25821_i2c_read(&dev->i2c_bus[0], 112 VERT_TIM_CTRL + (0x200 * i), &tmp); 113 value &= 0x00C00C00; 114 value |= 0x1C1E001A; /* vblank_cnt + 2 to get camera ID */ 115 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 116 VERT_TIM_CTRL + (0x200 * i), value); 117 118 /* chroma subcarrier step size */ 119 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 120 SC_STEP_SIZE + (0x200 * i), 0x43E00000); 121 122 /* enable VIP optional active */ 123 value = cx25821_i2c_read(&dev->i2c_bus[0], 124 OUT_CTRL_NS + (0x200 * i), &tmp); 125 value &= 0xFFFBFFFF; 126 value |= 0x00040000; 127 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 128 OUT_CTRL_NS + (0x200 * i), value); 129 130 /* enable VIP optional active (VIP_OPT_AL) for direct output. */ 131 value = cx25821_i2c_read(&dev->i2c_bus[0], 132 OUT_CTRL1 + (0x200 * i), &tmp); 133 value &= 0xFFFBFFFF; 134 value |= 0x00040000; 135 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 136 OUT_CTRL1 + (0x200 * i), value); 137 138 /* 139 * clear VPRES_VERT_EN bit, fixes the chroma run away problem 140 * when the input switching rate < 16 fields 141 */ 142 value = cx25821_i2c_read(&dev->i2c_bus[0], 143 MISC_TIM_CTRL + (0x200 * i), &tmp); 144 /* disable special play detection */ 145 value = setBitAtPos(value, 14); 146 value = clearBitAtPos(value, 15); 147 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 148 MISC_TIM_CTRL + (0x200 * i), value); 149 150 /* set vbi_gate_en to 0 */ 151 value = cx25821_i2c_read(&dev->i2c_bus[0], 152 DFE_CTRL1 + (0x200 * i), &tmp); 153 value = clearBitAtPos(value, 29); 154 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 155 DFE_CTRL1 + (0x200 * i), value); 156 157 /* Enable the generation of blue field output if no video */ 158 medusa_enable_bluefield_output(dev, i, 1); 159 } 160 161 for (i = 0; i < MAX_ENCODERS; i++) { 162 /* NTSC hclock */ 163 value = cx25821_i2c_read(&dev->i2c_bus[0], 164 DENC_A_REG_1 + (0x100 * i), &tmp); 165 value &= 0xF000FC00; 166 value |= 0x06B402D0; 167 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 168 DENC_A_REG_1 + (0x100 * i), value); 169 170 /* burst begin and burst end */ 171 value = cx25821_i2c_read(&dev->i2c_bus[0], 172 DENC_A_REG_2 + (0x100 * i), &tmp); 173 value &= 0xFF000000; 174 value |= 0x007E9054; 175 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 176 DENC_A_REG_2 + (0x100 * i), value); 177 178 value = cx25821_i2c_read(&dev->i2c_bus[0], 179 DENC_A_REG_3 + (0x100 * i), &tmp); 180 value &= 0xFC00FE00; 181 value |= 0x00EC00F0; 182 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 183 DENC_A_REG_3 + (0x100 * i), value); 184 185 /* set NTSC vblank, no phase alternation, 7.5 IRE pedestal */ 186 value = cx25821_i2c_read(&dev->i2c_bus[0], 187 DENC_A_REG_4 + (0x100 * i), &tmp); 188 value &= 0x00FCFFFF; 189 value |= 0x13020000; 190 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 191 DENC_A_REG_4 + (0x100 * i), value); 192 193 value = cx25821_i2c_read(&dev->i2c_bus[0], 194 DENC_A_REG_5 + (0x100 * i), &tmp); 195 value &= 0xFFFF0000; 196 value |= 0x0000E575; 197 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 198 DENC_A_REG_5 + (0x100 * i), value); 199 200 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 201 DENC_A_REG_6 + (0x100 * i), 0x009A89C1); 202 203 /* Subcarrier Increment */ 204 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 205 DENC_A_REG_7 + (0x100 * i), 0x21F07C1F); 206 } 207 208 /* set picture resolutions */ 209 /* 0 - 720 */ 210 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], HSCALE_CTRL, 0x0); 211 /* 0 - 480 */ 212 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], VSCALE_CTRL, 0x0); 213 214 /* set Bypass input format to NTSC 525 lines */ 215 value = cx25821_i2c_read(&dev->i2c_bus[0], BYP_AB_CTRL, &tmp); 216 value |= 0x00080200; 217 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], BYP_AB_CTRL, value); 218 219 return ret_val; 220 } 221 222 static int medusa_PALCombInit(struct cx25821_dev *dev, int dec) 223 { 224 int ret_val = -1; 225 u32 value = 0, tmp = 0; 226 227 /* Setup for 2D threshold */ 228 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 229 COMB_2D_HFS_CFG + (0x200 * dec), 0x20002861); 230 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 231 COMB_2D_HFD_CFG + (0x200 * dec), 0x20002861); 232 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 233 COMB_2D_LF_CFG + (0x200 * dec), 0x200A1023); 234 235 /* Setup flat chroma and luma thresholds */ 236 value = cx25821_i2c_read(&dev->i2c_bus[0], 237 COMB_FLAT_THRESH_CTRL + (0x200 * dec), &tmp); 238 value &= 0x06230000; 239 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 240 COMB_FLAT_THRESH_CTRL + (0x200 * dec), value); 241 242 /* set comb 2D blend */ 243 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 244 COMB_2D_BLEND + (0x200 * dec), 0x210F0F0F); 245 246 /* COMB MISC CONTROL */ 247 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 248 COMB_MISC_CTRL + (0x200 * dec), 0x41120A7F); 249 250 return ret_val; 251 } 252 253 static int medusa_initialize_pal(struct cx25821_dev *dev) 254 { 255 int ret_val = 0; 256 int i = 0; 257 u32 value = 0; 258 u32 tmp = 0; 259 260 for (i = 0; i < MAX_DECODERS; i++) { 261 /* set video format PAL-BDGHI */ 262 value = cx25821_i2c_read(&dev->i2c_bus[0], 263 MODE_CTRL + (0x200 * i), &tmp); 264 value &= 0xFFFFFFF0; 265 /* enable the fast locking mode bit[16] */ 266 value |= 0x10004; 267 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 268 MODE_CTRL + (0x200 * i), value); 269 270 /* resolution PAL 720x576 */ 271 value = cx25821_i2c_read(&dev->i2c_bus[0], 272 HORIZ_TIM_CTRL + (0x200 * i), &tmp); 273 value &= 0x00C00C00; 274 value |= 0x632D007D; 275 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 276 HORIZ_TIM_CTRL + (0x200 * i), value); 277 278 /* vblank656_cnt=x26, vactive_cnt=240h, vblank_cnt=x24 */ 279 value = cx25821_i2c_read(&dev->i2c_bus[0], 280 VERT_TIM_CTRL + (0x200 * i), &tmp); 281 value &= 0x00C00C00; 282 value |= 0x28240026; /* vblank_cnt + 2 to get camera ID */ 283 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 284 VERT_TIM_CTRL + (0x200 * i), value); 285 286 /* chroma subcarrier step size */ 287 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 288 SC_STEP_SIZE + (0x200 * i), 0x5411E2D0); 289 290 /* enable VIP optional active */ 291 value = cx25821_i2c_read(&dev->i2c_bus[0], 292 OUT_CTRL_NS + (0x200 * i), &tmp); 293 value &= 0xFFFBFFFF; 294 value |= 0x00040000; 295 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 296 OUT_CTRL_NS + (0x200 * i), value); 297 298 /* enable VIP optional active (VIP_OPT_AL) for direct output. */ 299 value = cx25821_i2c_read(&dev->i2c_bus[0], 300 OUT_CTRL1 + (0x200 * i), &tmp); 301 value &= 0xFFFBFFFF; 302 value |= 0x00040000; 303 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 304 OUT_CTRL1 + (0x200 * i), value); 305 306 /* 307 * clear VPRES_VERT_EN bit, fixes the chroma run away problem 308 * when the input switching rate < 16 fields 309 */ 310 value = cx25821_i2c_read(&dev->i2c_bus[0], 311 MISC_TIM_CTRL + (0x200 * i), &tmp); 312 /* disable special play detection */ 313 value = setBitAtPos(value, 14); 314 value = clearBitAtPos(value, 15); 315 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 316 MISC_TIM_CTRL + (0x200 * i), value); 317 318 /* set vbi_gate_en to 0 */ 319 value = cx25821_i2c_read(&dev->i2c_bus[0], 320 DFE_CTRL1 + (0x200 * i), &tmp); 321 value = clearBitAtPos(value, 29); 322 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 323 DFE_CTRL1 + (0x200 * i), value); 324 325 medusa_PALCombInit(dev, i); 326 327 /* Enable the generation of blue field output if no video */ 328 medusa_enable_bluefield_output(dev, i, 1); 329 } 330 331 for (i = 0; i < MAX_ENCODERS; i++) { 332 /* PAL hclock */ 333 value = cx25821_i2c_read(&dev->i2c_bus[0], 334 DENC_A_REG_1 + (0x100 * i), &tmp); 335 value &= 0xF000FC00; 336 value |= 0x06C002D0; 337 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 338 DENC_A_REG_1 + (0x100 * i), value); 339 340 /* burst begin and burst end */ 341 value = cx25821_i2c_read(&dev->i2c_bus[0], 342 DENC_A_REG_2 + (0x100 * i), &tmp); 343 value &= 0xFF000000; 344 value |= 0x007E9754; 345 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 346 DENC_A_REG_2 + (0x100 * i), value); 347 348 /* hblank and vactive */ 349 value = cx25821_i2c_read(&dev->i2c_bus[0], 350 DENC_A_REG_3 + (0x100 * i), &tmp); 351 value &= 0xFC00FE00; 352 value |= 0x00FC0120; 353 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 354 DENC_A_REG_3 + (0x100 * i), value); 355 356 /* set PAL vblank, phase alternation, 0 IRE pedestal */ 357 value = cx25821_i2c_read(&dev->i2c_bus[0], 358 DENC_A_REG_4 + (0x100 * i), &tmp); 359 value &= 0x00FCFFFF; 360 value |= 0x14010000; 361 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 362 DENC_A_REG_4 + (0x100 * i), value); 363 364 value = cx25821_i2c_read(&dev->i2c_bus[0], 365 DENC_A_REG_5 + (0x100 * i), &tmp); 366 value &= 0xFFFF0000; 367 value |= 0x0000F078; 368 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 369 DENC_A_REG_5 + (0x100 * i), value); 370 371 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 372 DENC_A_REG_6 + (0x100 * i), 0x00A493CF); 373 374 /* Subcarrier Increment */ 375 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], 376 DENC_A_REG_7 + (0x100 * i), 0x2A098ACB); 377 } 378 379 /* set picture resolutions */ 380 /* 0 - 720 */ 381 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], HSCALE_CTRL, 0x0); 382 /* 0 - 576 */ 383 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], VSCALE_CTRL, 0x0); 384 385 /* set Bypass input format to PAL 625 lines */ 386 value = cx25821_i2c_read(&dev->i2c_bus[0], BYP_AB_CTRL, &tmp); 387 value &= 0xFFF7FDFF; 388 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], BYP_AB_CTRL, value); 389 390 return ret_val; 391 } 392 393 int medusa_set_videostandard(struct cx25821_dev *dev) 394 { 395 int status = 0; 396 u32 value = 0, tmp = 0; 397 398 if (dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK) 399 status = medusa_initialize_pal(dev); 400 else 401 status = medusa_initialize_ntsc(dev); 402 403 /* Enable DENC_A output */ 404 value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_A_REG_4, &tmp); 405 value = setBitAtPos(value, 4); 406 status = cx25821_i2c_write(&dev->i2c_bus[0], DENC_A_REG_4, value); 407 408 /* Enable DENC_B output */ 409 value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_B_REG_4, &tmp); 410 value = setBitAtPos(value, 4); 411 status = cx25821_i2c_write(&dev->i2c_bus[0], DENC_B_REG_4, value); 412 413 return status; 414 } 415 416 void medusa_set_resolution(struct cx25821_dev *dev, int width, 417 int decoder_select) 418 { 419 int decoder = 0; 420 int decoder_count = 0; 421 u32 hscale = 0x0; 422 u32 vscale = 0x0; 423 const int MAX_WIDTH = 720; 424 425 /* validate the width */ 426 if (width > MAX_WIDTH) { 427 pr_info("%s(): width %d > MAX_WIDTH %d ! resetting to MAX_WIDTH\n", 428 __func__, width, MAX_WIDTH); 429 width = MAX_WIDTH; 430 } 431 432 if (decoder_select <= 7 && decoder_select >= 0) { 433 decoder = decoder_select; 434 decoder_count = decoder_select + 1; 435 } else { 436 decoder = 0; 437 decoder_count = dev->_max_num_decoders; 438 } 439 440 switch (width) { 441 case 320: 442 hscale = 0x13E34B; 443 vscale = 0x0; 444 break; 445 446 case 352: 447 hscale = 0x10A273; 448 vscale = 0x0; 449 break; 450 451 case 176: 452 hscale = 0x3115B2; 453 vscale = 0x1E00; 454 break; 455 456 case 160: 457 hscale = 0x378D84; 458 vscale = 0x1E00; 459 break; 460 461 default: /* 720 */ 462 hscale = 0x0; 463 vscale = 0x0; 464 break; 465 } 466 467 for (; decoder < decoder_count; decoder++) { 468 /* write scaling values for each decoder */ 469 cx25821_i2c_write(&dev->i2c_bus[0], 470 HSCALE_CTRL + (0x200 * decoder), hscale); 471 cx25821_i2c_write(&dev->i2c_bus[0], 472 VSCALE_CTRL + (0x200 * decoder), vscale); 473 } 474 } 475 476 static void medusa_set_decoderduration(struct cx25821_dev *dev, int decoder, 477 int duration) 478 { 479 u32 fld_cnt = 0; 480 u32 tmp = 0; 481 u32 disp_cnt_reg = DISP_AB_CNT; 482 483 /* no support */ 484 if (decoder < VDEC_A || decoder > VDEC_H) { 485 return; 486 } 487 488 switch (decoder) { 489 default: 490 break; 491 case VDEC_C: 492 case VDEC_D: 493 disp_cnt_reg = DISP_CD_CNT; 494 break; 495 case VDEC_E: 496 case VDEC_F: 497 disp_cnt_reg = DISP_EF_CNT; 498 break; 499 case VDEC_G: 500 case VDEC_H: 501 disp_cnt_reg = DISP_GH_CNT; 502 break; 503 } 504 505 /* update hardware */ 506 fld_cnt = cx25821_i2c_read(&dev->i2c_bus[0], disp_cnt_reg, &tmp); 507 508 if (!(decoder % 2)) { /* EVEN decoder */ 509 fld_cnt &= 0xFFFF0000; 510 fld_cnt |= duration; 511 } else { 512 fld_cnt &= 0x0000FFFF; 513 fld_cnt |= ((u32) duration) << 16; 514 } 515 516 cx25821_i2c_write(&dev->i2c_bus[0], disp_cnt_reg, fld_cnt); 517 } 518 519 /* Map to Medusa register setting */ 520 static int mapM(int srcMin, int srcMax, int srcVal, int dstMin, int dstMax, 521 int *dstVal) 522 { 523 int numerator; 524 int denominator; 525 int quotient; 526 527 if ((srcMin == srcMax) || (srcVal < srcMin) || (srcVal > srcMax)) 528 return -1; 529 /* 530 * This is the overall expression used: 531 * *dstVal = 532 * (srcVal - srcMin)*(dstMax - dstMin) / (srcMax - srcMin) + dstMin; 533 * but we need to account for rounding so below we use the modulus 534 * operator to find the remainder and increment if necessary. 535 */ 536 numerator = (srcVal - srcMin) * (dstMax - dstMin); 537 denominator = srcMax - srcMin; 538 quotient = numerator / denominator; 539 540 if (2 * (numerator % denominator) >= denominator) 541 quotient++; 542 543 *dstVal = quotient + dstMin; 544 545 return 0; 546 } 547 548 static unsigned long convert_to_twos(long numeric, unsigned long bits_len) 549 { 550 unsigned char temp; 551 552 if (numeric >= 0) 553 return numeric; 554 else { 555 temp = ~(abs(numeric) & 0xFF); 556 temp += 1; 557 return temp; 558 } 559 } 560 561 int medusa_set_brightness(struct cx25821_dev *dev, int brightness, int decoder) 562 { 563 int ret_val = 0; 564 int value = 0; 565 u32 val = 0, tmp = 0; 566 567 if ((brightness > VIDEO_PROCAMP_MAX) || 568 (brightness < VIDEO_PROCAMP_MIN)) { 569 return -1; 570 } 571 ret_val = mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, brightness, 572 SIGNED_BYTE_MIN, SIGNED_BYTE_MAX, &value); 573 value = convert_to_twos(value, 8); 574 val = cx25821_i2c_read(&dev->i2c_bus[0], 575 VDEC_A_BRITE_CTRL + (0x200 * decoder), &tmp); 576 val &= 0xFFFFFF00; 577 ret_val |= cx25821_i2c_write(&dev->i2c_bus[0], 578 VDEC_A_BRITE_CTRL + (0x200 * decoder), val | value); 579 return ret_val; 580 } 581 582 int medusa_set_contrast(struct cx25821_dev *dev, int contrast, int decoder) 583 { 584 int ret_val = 0; 585 int value = 0; 586 u32 val = 0, tmp = 0; 587 588 if ((contrast > VIDEO_PROCAMP_MAX) || (contrast < VIDEO_PROCAMP_MIN)) { 589 return -1; 590 } 591 592 ret_val = mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, contrast, 593 UNSIGNED_BYTE_MIN, UNSIGNED_BYTE_MAX, &value); 594 val = cx25821_i2c_read(&dev->i2c_bus[0], 595 VDEC_A_CNTRST_CTRL + (0x200 * decoder), &tmp); 596 val &= 0xFFFFFF00; 597 ret_val |= cx25821_i2c_write(&dev->i2c_bus[0], 598 VDEC_A_CNTRST_CTRL + (0x200 * decoder), val | value); 599 600 return ret_val; 601 } 602 603 int medusa_set_hue(struct cx25821_dev *dev, int hue, int decoder) 604 { 605 int ret_val = 0; 606 int value = 0; 607 u32 val = 0, tmp = 0; 608 609 if ((hue > VIDEO_PROCAMP_MAX) || (hue < VIDEO_PROCAMP_MIN)) { 610 return -1; 611 } 612 613 ret_val = mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, hue, 614 SIGNED_BYTE_MIN, SIGNED_BYTE_MAX, &value); 615 616 value = convert_to_twos(value, 8); 617 val = cx25821_i2c_read(&dev->i2c_bus[0], 618 VDEC_A_HUE_CTRL + (0x200 * decoder), &tmp); 619 val &= 0xFFFFFF00; 620 621 ret_val |= cx25821_i2c_write(&dev->i2c_bus[0], 622 VDEC_A_HUE_CTRL + (0x200 * decoder), val | value); 623 624 return ret_val; 625 } 626 627 int medusa_set_saturation(struct cx25821_dev *dev, int saturation, int decoder) 628 { 629 int ret_val = 0; 630 int value = 0; 631 u32 val = 0, tmp = 0; 632 633 if ((saturation > VIDEO_PROCAMP_MAX) || 634 (saturation < VIDEO_PROCAMP_MIN)) { 635 return -1; 636 } 637 638 ret_val = mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, saturation, 639 UNSIGNED_BYTE_MIN, UNSIGNED_BYTE_MAX, &value); 640 641 val = cx25821_i2c_read(&dev->i2c_bus[0], 642 VDEC_A_USAT_CTRL + (0x200 * decoder), &tmp); 643 val &= 0xFFFFFF00; 644 ret_val |= cx25821_i2c_write(&dev->i2c_bus[0], 645 VDEC_A_USAT_CTRL + (0x200 * decoder), val | value); 646 647 val = cx25821_i2c_read(&dev->i2c_bus[0], 648 VDEC_A_VSAT_CTRL + (0x200 * decoder), &tmp); 649 val &= 0xFFFFFF00; 650 ret_val |= cx25821_i2c_write(&dev->i2c_bus[0], 651 VDEC_A_VSAT_CTRL + (0x200 * decoder), val | value); 652 653 return ret_val; 654 } 655 656 /* Program the display sequence and monitor output. */ 657 658 int medusa_video_init(struct cx25821_dev *dev) 659 { 660 u32 value = 0, tmp = 0; 661 int ret_val = 0; 662 int i = 0; 663 664 /* disable Auto source selection on all video decoders */ 665 value = cx25821_i2c_read(&dev->i2c_bus[0], MON_A_CTRL, &tmp); 666 value &= 0xFFFFF0FF; 667 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], MON_A_CTRL, value); 668 669 if (ret_val < 0) 670 goto error; 671 672 /* Turn off Master source switch enable */ 673 value = cx25821_i2c_read(&dev->i2c_bus[0], MON_A_CTRL, &tmp); 674 value &= 0xFFFFFFDF; 675 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], MON_A_CTRL, value); 676 677 if (ret_val < 0) 678 goto error; 679 680 /* 681 * FIXME: due to a coding bug the duration was always 0. It's 682 * likely that it really should be something else, but due to the 683 * lack of documentation I have no idea what it should be. For 684 * now just fill in 0 as the duration. 685 */ 686 for (i = 0; i < dev->_max_num_decoders; i++) 687 medusa_set_decoderduration(dev, i, 0); 688 689 /* Select monitor as DENC A input, power up the DAC */ 690 value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_AB_CTRL, &tmp); 691 value &= 0xFF70FF70; 692 value |= 0x00090008; /* set en_active */ 693 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], DENC_AB_CTRL, value); 694 695 if (ret_val < 0) 696 goto error; 697 698 /* enable input is VIP/656 */ 699 value = cx25821_i2c_read(&dev->i2c_bus[0], BYP_AB_CTRL, &tmp); 700 value |= 0x00040100; /* enable VIP */ 701 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], BYP_AB_CTRL, value); 702 703 if (ret_val < 0) 704 goto error; 705 706 /* select AFE clock to output mode */ 707 value = cx25821_i2c_read(&dev->i2c_bus[0], AFE_AB_DIAG_CTRL, &tmp); 708 value &= 0x83FFFFFF; 709 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], AFE_AB_DIAG_CTRL, 710 value | 0x10000000); 711 712 if (ret_val < 0) 713 goto error; 714 715 /* Turn on all of the data out and control output pins. */ 716 value = cx25821_i2c_read(&dev->i2c_bus[0], PIN_OE_CTRL, &tmp); 717 value &= 0xFEF0FE00; 718 if (dev->_max_num_decoders == MAX_DECODERS) { 719 /* 720 * Note: The octal board does not support control pins(bit16-19) 721 * These bits are ignored in the octal board. 722 * 723 * disable VDEC A-C port, default to Mobilygen Interface 724 */ 725 value |= 0x010001F8; 726 } else { 727 /* disable VDEC A-C port, default to Mobilygen Interface */ 728 value |= 0x010F0108; 729 } 730 731 value |= 7; 732 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], PIN_OE_CTRL, value); 733 734 if (ret_val < 0) 735 goto error; 736 737 ret_val = medusa_set_videostandard(dev); 738 739 error: 740 return ret_val; 741 } 742