1 /* 2 * Driver for the Conexant CX25821 PCIe bridge 3 * 4 * Copyright (C) 2009 Conexant Systems Inc. 5 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com> 6 * Based on Steven Toth <stoth@linuxtv.org> cx23885 driver 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * 17 * GNU General Public License for more details. 18 */ 19 20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 21 22 #include <linux/i2c.h> 23 #include <linux/slab.h> 24 #include "cx25821.h" 25 #include "cx25821-sram.h" 26 #include "cx25821-video.h" 27 28 MODULE_DESCRIPTION("Driver for Athena cards"); 29 MODULE_AUTHOR("Shu Lin - Hiep Huynh"); 30 MODULE_LICENSE("GPL"); 31 32 static unsigned int debug; 33 module_param(debug, int, 0644); 34 MODULE_PARM_DESC(debug, "enable debug messages"); 35 36 static unsigned int card[] = {[0 ... (CX25821_MAXBOARDS - 1)] = UNSET }; 37 module_param_array(card, int, NULL, 0444); 38 MODULE_PARM_DESC(card, "card type"); 39 40 const struct sram_channel cx25821_sram_channels[] = { 41 [SRAM_CH00] = { 42 .i = SRAM_CH00, 43 .name = "VID A", 44 .cmds_start = VID_A_DOWN_CMDS, 45 .ctrl_start = VID_A_IQ, 46 .cdt = VID_A_CDT, 47 .fifo_start = VID_A_DOWN_CLUSTER_1, 48 .fifo_size = (VID_CLUSTER_SIZE << 2), 49 .ptr1_reg = DMA1_PTR1, 50 .ptr2_reg = DMA1_PTR2, 51 .cnt1_reg = DMA1_CNT1, 52 .cnt2_reg = DMA1_CNT2, 53 .int_msk = VID_A_INT_MSK, 54 .int_stat = VID_A_INT_STAT, 55 .int_mstat = VID_A_INT_MSTAT, 56 .dma_ctl = VID_DST_A_DMA_CTL, 57 .gpcnt_ctl = VID_DST_A_GPCNT_CTL, 58 .gpcnt = VID_DST_A_GPCNT, 59 .vip_ctl = VID_DST_A_VIP_CTL, 60 .pix_frmt = VID_DST_A_PIX_FRMT, 61 }, 62 63 [SRAM_CH01] = { 64 .i = SRAM_CH01, 65 .name = "VID B", 66 .cmds_start = VID_B_DOWN_CMDS, 67 .ctrl_start = VID_B_IQ, 68 .cdt = VID_B_CDT, 69 .fifo_start = VID_B_DOWN_CLUSTER_1, 70 .fifo_size = (VID_CLUSTER_SIZE << 2), 71 .ptr1_reg = DMA2_PTR1, 72 .ptr2_reg = DMA2_PTR2, 73 .cnt1_reg = DMA2_CNT1, 74 .cnt2_reg = DMA2_CNT2, 75 .int_msk = VID_B_INT_MSK, 76 .int_stat = VID_B_INT_STAT, 77 .int_mstat = VID_B_INT_MSTAT, 78 .dma_ctl = VID_DST_B_DMA_CTL, 79 .gpcnt_ctl = VID_DST_B_GPCNT_CTL, 80 .gpcnt = VID_DST_B_GPCNT, 81 .vip_ctl = VID_DST_B_VIP_CTL, 82 .pix_frmt = VID_DST_B_PIX_FRMT, 83 }, 84 85 [SRAM_CH02] = { 86 .i = SRAM_CH02, 87 .name = "VID C", 88 .cmds_start = VID_C_DOWN_CMDS, 89 .ctrl_start = VID_C_IQ, 90 .cdt = VID_C_CDT, 91 .fifo_start = VID_C_DOWN_CLUSTER_1, 92 .fifo_size = (VID_CLUSTER_SIZE << 2), 93 .ptr1_reg = DMA3_PTR1, 94 .ptr2_reg = DMA3_PTR2, 95 .cnt1_reg = DMA3_CNT1, 96 .cnt2_reg = DMA3_CNT2, 97 .int_msk = VID_C_INT_MSK, 98 .int_stat = VID_C_INT_STAT, 99 .int_mstat = VID_C_INT_MSTAT, 100 .dma_ctl = VID_DST_C_DMA_CTL, 101 .gpcnt_ctl = VID_DST_C_GPCNT_CTL, 102 .gpcnt = VID_DST_C_GPCNT, 103 .vip_ctl = VID_DST_C_VIP_CTL, 104 .pix_frmt = VID_DST_C_PIX_FRMT, 105 }, 106 107 [SRAM_CH03] = { 108 .i = SRAM_CH03, 109 .name = "VID D", 110 .cmds_start = VID_D_DOWN_CMDS, 111 .ctrl_start = VID_D_IQ, 112 .cdt = VID_D_CDT, 113 .fifo_start = VID_D_DOWN_CLUSTER_1, 114 .fifo_size = (VID_CLUSTER_SIZE << 2), 115 .ptr1_reg = DMA4_PTR1, 116 .ptr2_reg = DMA4_PTR2, 117 .cnt1_reg = DMA4_CNT1, 118 .cnt2_reg = DMA4_CNT2, 119 .int_msk = VID_D_INT_MSK, 120 .int_stat = VID_D_INT_STAT, 121 .int_mstat = VID_D_INT_MSTAT, 122 .dma_ctl = VID_DST_D_DMA_CTL, 123 .gpcnt_ctl = VID_DST_D_GPCNT_CTL, 124 .gpcnt = VID_DST_D_GPCNT, 125 .vip_ctl = VID_DST_D_VIP_CTL, 126 .pix_frmt = VID_DST_D_PIX_FRMT, 127 }, 128 129 [SRAM_CH04] = { 130 .i = SRAM_CH04, 131 .name = "VID E", 132 .cmds_start = VID_E_DOWN_CMDS, 133 .ctrl_start = VID_E_IQ, 134 .cdt = VID_E_CDT, 135 .fifo_start = VID_E_DOWN_CLUSTER_1, 136 .fifo_size = (VID_CLUSTER_SIZE << 2), 137 .ptr1_reg = DMA5_PTR1, 138 .ptr2_reg = DMA5_PTR2, 139 .cnt1_reg = DMA5_CNT1, 140 .cnt2_reg = DMA5_CNT2, 141 .int_msk = VID_E_INT_MSK, 142 .int_stat = VID_E_INT_STAT, 143 .int_mstat = VID_E_INT_MSTAT, 144 .dma_ctl = VID_DST_E_DMA_CTL, 145 .gpcnt_ctl = VID_DST_E_GPCNT_CTL, 146 .gpcnt = VID_DST_E_GPCNT, 147 .vip_ctl = VID_DST_E_VIP_CTL, 148 .pix_frmt = VID_DST_E_PIX_FRMT, 149 }, 150 151 [SRAM_CH05] = { 152 .i = SRAM_CH05, 153 .name = "VID F", 154 .cmds_start = VID_F_DOWN_CMDS, 155 .ctrl_start = VID_F_IQ, 156 .cdt = VID_F_CDT, 157 .fifo_start = VID_F_DOWN_CLUSTER_1, 158 .fifo_size = (VID_CLUSTER_SIZE << 2), 159 .ptr1_reg = DMA6_PTR1, 160 .ptr2_reg = DMA6_PTR2, 161 .cnt1_reg = DMA6_CNT1, 162 .cnt2_reg = DMA6_CNT2, 163 .int_msk = VID_F_INT_MSK, 164 .int_stat = VID_F_INT_STAT, 165 .int_mstat = VID_F_INT_MSTAT, 166 .dma_ctl = VID_DST_F_DMA_CTL, 167 .gpcnt_ctl = VID_DST_F_GPCNT_CTL, 168 .gpcnt = VID_DST_F_GPCNT, 169 .vip_ctl = VID_DST_F_VIP_CTL, 170 .pix_frmt = VID_DST_F_PIX_FRMT, 171 }, 172 173 [SRAM_CH06] = { 174 .i = SRAM_CH06, 175 .name = "VID G", 176 .cmds_start = VID_G_DOWN_CMDS, 177 .ctrl_start = VID_G_IQ, 178 .cdt = VID_G_CDT, 179 .fifo_start = VID_G_DOWN_CLUSTER_1, 180 .fifo_size = (VID_CLUSTER_SIZE << 2), 181 .ptr1_reg = DMA7_PTR1, 182 .ptr2_reg = DMA7_PTR2, 183 .cnt1_reg = DMA7_CNT1, 184 .cnt2_reg = DMA7_CNT2, 185 .int_msk = VID_G_INT_MSK, 186 .int_stat = VID_G_INT_STAT, 187 .int_mstat = VID_G_INT_MSTAT, 188 .dma_ctl = VID_DST_G_DMA_CTL, 189 .gpcnt_ctl = VID_DST_G_GPCNT_CTL, 190 .gpcnt = VID_DST_G_GPCNT, 191 .vip_ctl = VID_DST_G_VIP_CTL, 192 .pix_frmt = VID_DST_G_PIX_FRMT, 193 }, 194 195 [SRAM_CH07] = { 196 .i = SRAM_CH07, 197 .name = "VID H", 198 .cmds_start = VID_H_DOWN_CMDS, 199 .ctrl_start = VID_H_IQ, 200 .cdt = VID_H_CDT, 201 .fifo_start = VID_H_DOWN_CLUSTER_1, 202 .fifo_size = (VID_CLUSTER_SIZE << 2), 203 .ptr1_reg = DMA8_PTR1, 204 .ptr2_reg = DMA8_PTR2, 205 .cnt1_reg = DMA8_CNT1, 206 .cnt2_reg = DMA8_CNT2, 207 .int_msk = VID_H_INT_MSK, 208 .int_stat = VID_H_INT_STAT, 209 .int_mstat = VID_H_INT_MSTAT, 210 .dma_ctl = VID_DST_H_DMA_CTL, 211 .gpcnt_ctl = VID_DST_H_GPCNT_CTL, 212 .gpcnt = VID_DST_H_GPCNT, 213 .vip_ctl = VID_DST_H_VIP_CTL, 214 .pix_frmt = VID_DST_H_PIX_FRMT, 215 }, 216 217 [SRAM_CH08] = { 218 .name = "audio from", 219 .cmds_start = AUD_A_DOWN_CMDS, 220 .ctrl_start = AUD_A_IQ, 221 .cdt = AUD_A_CDT, 222 .fifo_start = AUD_A_DOWN_CLUSTER_1, 223 .fifo_size = AUDIO_CLUSTER_SIZE * 3, 224 .ptr1_reg = DMA17_PTR1, 225 .ptr2_reg = DMA17_PTR2, 226 .cnt1_reg = DMA17_CNT1, 227 .cnt2_reg = DMA17_CNT2, 228 }, 229 230 [SRAM_CH09] = { 231 .i = SRAM_CH09, 232 .name = "VID Upstream I", 233 .cmds_start = VID_I_UP_CMDS, 234 .ctrl_start = VID_I_IQ, 235 .cdt = VID_I_CDT, 236 .fifo_start = VID_I_UP_CLUSTER_1, 237 .fifo_size = (VID_CLUSTER_SIZE << 2), 238 .ptr1_reg = DMA15_PTR1, 239 .ptr2_reg = DMA15_PTR2, 240 .cnt1_reg = DMA15_CNT1, 241 .cnt2_reg = DMA15_CNT2, 242 .int_msk = VID_I_INT_MSK, 243 .int_stat = VID_I_INT_STAT, 244 .int_mstat = VID_I_INT_MSTAT, 245 .dma_ctl = VID_SRC_I_DMA_CTL, 246 .gpcnt_ctl = VID_SRC_I_GPCNT_CTL, 247 .gpcnt = VID_SRC_I_GPCNT, 248 249 .vid_fmt_ctl = VID_SRC_I_FMT_CTL, 250 .vid_active_ctl1 = VID_SRC_I_ACTIVE_CTL1, 251 .vid_active_ctl2 = VID_SRC_I_ACTIVE_CTL2, 252 .vid_cdt_size = VID_SRC_I_CDT_SZ, 253 .irq_bit = 8, 254 }, 255 256 [SRAM_CH10] = { 257 .i = SRAM_CH10, 258 .name = "VID Upstream J", 259 .cmds_start = VID_J_UP_CMDS, 260 .ctrl_start = VID_J_IQ, 261 .cdt = VID_J_CDT, 262 .fifo_start = VID_J_UP_CLUSTER_1, 263 .fifo_size = (VID_CLUSTER_SIZE << 2), 264 .ptr1_reg = DMA16_PTR1, 265 .ptr2_reg = DMA16_PTR2, 266 .cnt1_reg = DMA16_CNT1, 267 .cnt2_reg = DMA16_CNT2, 268 .int_msk = VID_J_INT_MSK, 269 .int_stat = VID_J_INT_STAT, 270 .int_mstat = VID_J_INT_MSTAT, 271 .dma_ctl = VID_SRC_J_DMA_CTL, 272 .gpcnt_ctl = VID_SRC_J_GPCNT_CTL, 273 .gpcnt = VID_SRC_J_GPCNT, 274 275 .vid_fmt_ctl = VID_SRC_J_FMT_CTL, 276 .vid_active_ctl1 = VID_SRC_J_ACTIVE_CTL1, 277 .vid_active_ctl2 = VID_SRC_J_ACTIVE_CTL2, 278 .vid_cdt_size = VID_SRC_J_CDT_SZ, 279 .irq_bit = 9, 280 }, 281 282 [SRAM_CH11] = { 283 .i = SRAM_CH11, 284 .name = "Audio Upstream Channel B", 285 .cmds_start = AUD_B_UP_CMDS, 286 .ctrl_start = AUD_B_IQ, 287 .cdt = AUD_B_CDT, 288 .fifo_start = AUD_B_UP_CLUSTER_1, 289 .fifo_size = (AUDIO_CLUSTER_SIZE * 3), 290 .ptr1_reg = DMA22_PTR1, 291 .ptr2_reg = DMA22_PTR2, 292 .cnt1_reg = DMA22_CNT1, 293 .cnt2_reg = DMA22_CNT2, 294 .int_msk = AUD_B_INT_MSK, 295 .int_stat = AUD_B_INT_STAT, 296 .int_mstat = AUD_B_INT_MSTAT, 297 .dma_ctl = AUD_INT_DMA_CTL, 298 .gpcnt_ctl = AUD_B_GPCNT_CTL, 299 .gpcnt = AUD_B_GPCNT, 300 .aud_length = AUD_B_LNGTH, 301 .aud_cfg = AUD_B_CFG, 302 .fld_aud_fifo_en = FLD_AUD_SRC_B_FIFO_EN, 303 .fld_aud_risc_en = FLD_AUD_SRC_B_RISC_EN, 304 .irq_bit = 11, 305 }, 306 }; 307 EXPORT_SYMBOL(cx25821_sram_channels); 308 309 static int cx25821_risc_decode(u32 risc) 310 { 311 static const char * const instr[16] = { 312 [RISC_SYNC >> 28] = "sync", 313 [RISC_WRITE >> 28] = "write", 314 [RISC_WRITEC >> 28] = "writec", 315 [RISC_READ >> 28] = "read", 316 [RISC_READC >> 28] = "readc", 317 [RISC_JUMP >> 28] = "jump", 318 [RISC_SKIP >> 28] = "skip", 319 [RISC_WRITERM >> 28] = "writerm", 320 [RISC_WRITECM >> 28] = "writecm", 321 [RISC_WRITECR >> 28] = "writecr", 322 }; 323 static const int incr[16] = { 324 [RISC_WRITE >> 28] = 3, 325 [RISC_JUMP >> 28] = 3, 326 [RISC_SKIP >> 28] = 1, 327 [RISC_SYNC >> 28] = 1, 328 [RISC_WRITERM >> 28] = 3, 329 [RISC_WRITECM >> 28] = 3, 330 [RISC_WRITECR >> 28] = 4, 331 }; 332 static const char * const bits[] = { 333 "12", "13", "14", "resync", 334 "cnt0", "cnt1", "18", "19", 335 "20", "21", "22", "23", 336 "irq1", "irq2", "eol", "sol", 337 }; 338 int i; 339 340 pr_cont("0x%08x [ %s", 341 risc, instr[risc >> 28] ? instr[risc >> 28] : "INVALID"); 342 for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--) { 343 if (risc & (1 << (i + 12))) 344 pr_cont(" %s", bits[i]); 345 } 346 pr_cont(" count=%d ]\n", risc & 0xfff); 347 return incr[risc >> 28] ? incr[risc >> 28] : 1; 348 } 349 350 static inline int i2c_slave_did_ack(struct i2c_adapter *i2c_adap) 351 { 352 struct cx25821_i2c *bus = i2c_adap->algo_data; 353 struct cx25821_dev *dev = bus->dev; 354 return cx_read(bus->reg_stat) & 0x01; 355 } 356 357 static void cx25821_registers_init(struct cx25821_dev *dev) 358 { 359 u32 tmp; 360 361 /* enable RUN_RISC in Pecos */ 362 cx_write(DEV_CNTRL2, 0x20); 363 364 /* Set the master PCI interrupt masks to enable video, audio, MBIF, 365 * and GPIO interrupts 366 * I2C interrupt masking is handled by the I2C objects themselves. */ 367 cx_write(PCI_INT_MSK, 0x2001FFFF); 368 369 tmp = cx_read(RDR_TLCTL0); 370 tmp &= ~FLD_CFG_RCB_CK_EN; /* Clear the RCB_CK_EN bit */ 371 cx_write(RDR_TLCTL0, tmp); 372 373 /* PLL-A setting for the Audio Master Clock */ 374 cx_write(PLL_A_INT_FRAC, 0x9807A58B); 375 376 /* PLL_A_POST = 0x1C, PLL_A_OUT_TO_PIN = 0x1 */ 377 cx_write(PLL_A_POST_STAT_BIST, 0x8000019C); 378 379 /* clear reset bit [31] */ 380 tmp = cx_read(PLL_A_INT_FRAC); 381 cx_write(PLL_A_INT_FRAC, tmp & 0x7FFFFFFF); 382 383 /* PLL-B setting for Mobilygen Host Bus Interface */ 384 cx_write(PLL_B_INT_FRAC, 0x9883A86F); 385 386 /* PLL_B_POST = 0xD, PLL_B_OUT_TO_PIN = 0x0 */ 387 cx_write(PLL_B_POST_STAT_BIST, 0x8000018D); 388 389 /* clear reset bit [31] */ 390 tmp = cx_read(PLL_B_INT_FRAC); 391 cx_write(PLL_B_INT_FRAC, tmp & 0x7FFFFFFF); 392 393 /* PLL-C setting for video upstream channel */ 394 cx_write(PLL_C_INT_FRAC, 0x96A0EA3F); 395 396 /* PLL_C_POST = 0x3, PLL_C_OUT_TO_PIN = 0x0 */ 397 cx_write(PLL_C_POST_STAT_BIST, 0x80000103); 398 399 /* clear reset bit [31] */ 400 tmp = cx_read(PLL_C_INT_FRAC); 401 cx_write(PLL_C_INT_FRAC, tmp & 0x7FFFFFFF); 402 403 /* PLL-D setting for audio upstream channel */ 404 cx_write(PLL_D_INT_FRAC, 0x98757F5B); 405 406 /* PLL_D_POST = 0x13, PLL_D_OUT_TO_PIN = 0x0 */ 407 cx_write(PLL_D_POST_STAT_BIST, 0x80000113); 408 409 /* clear reset bit [31] */ 410 tmp = cx_read(PLL_D_INT_FRAC); 411 cx_write(PLL_D_INT_FRAC, tmp & 0x7FFFFFFF); 412 413 /* This selects the PLL C clock source for the video upstream channel 414 * I and J */ 415 tmp = cx_read(VID_CH_CLK_SEL); 416 cx_write(VID_CH_CLK_SEL, (tmp & 0x00FFFFFF) | 0x24000000); 417 418 /* 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for 419 * channel A-C 420 * select 656/VIP DST for downstream Channel A - C */ 421 tmp = cx_read(VID_CH_MODE_SEL); 422 /* cx_write( VID_CH_MODE_SEL, tmp | 0x1B0001FF); */ 423 cx_write(VID_CH_MODE_SEL, tmp & 0xFFFFFE00); 424 425 /* enables 656 port I and J as output */ 426 tmp = cx_read(CLK_RST); 427 /* use external ALT_PLL_REF pin as its reference clock instead */ 428 tmp |= FLD_USE_ALT_PLL_REF; 429 cx_write(CLK_RST, tmp & ~(FLD_VID_I_CLK_NOE | FLD_VID_J_CLK_NOE)); 430 431 msleep(100); 432 } 433 434 int cx25821_sram_channel_setup(struct cx25821_dev *dev, 435 const struct sram_channel *ch, 436 unsigned int bpl, u32 risc) 437 { 438 unsigned int i, lines; 439 u32 cdt; 440 441 if (ch->cmds_start == 0) { 442 cx_write(ch->ptr1_reg, 0); 443 cx_write(ch->ptr2_reg, 0); 444 cx_write(ch->cnt2_reg, 0); 445 cx_write(ch->cnt1_reg, 0); 446 return 0; 447 } 448 449 bpl = (bpl + 7) & ~7; /* alignment */ 450 cdt = ch->cdt; 451 lines = ch->fifo_size / bpl; 452 453 if (lines > 4) 454 lines = 4; 455 456 BUG_ON(lines < 2); 457 458 cx_write(8 + 0, RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC); 459 cx_write(8 + 4, 8); 460 cx_write(8 + 8, 0); 461 462 /* write CDT */ 463 for (i = 0; i < lines; i++) { 464 cx_write(cdt + 16 * i, ch->fifo_start + bpl * i); 465 cx_write(cdt + 16 * i + 4, 0); 466 cx_write(cdt + 16 * i + 8, 0); 467 cx_write(cdt + 16 * i + 12, 0); 468 } 469 470 /* init the first cdt buffer */ 471 for (i = 0; i < 128; i++) 472 cx_write(ch->fifo_start + 4 * i, i); 473 474 /* write CMDS */ 475 if (ch->jumponly) 476 cx_write(ch->cmds_start + 0, 8); 477 else 478 cx_write(ch->cmds_start + 0, risc); 479 480 cx_write(ch->cmds_start + 4, 0); /* 64 bits 63-32 */ 481 cx_write(ch->cmds_start + 8, cdt); 482 cx_write(ch->cmds_start + 12, (lines * 16) >> 3); 483 cx_write(ch->cmds_start + 16, ch->ctrl_start); 484 485 if (ch->jumponly) 486 cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2)); 487 else 488 cx_write(ch->cmds_start + 20, 64 >> 2); 489 490 for (i = 24; i < 80; i += 4) 491 cx_write(ch->cmds_start + i, 0); 492 493 /* fill registers */ 494 cx_write(ch->ptr1_reg, ch->fifo_start); 495 cx_write(ch->ptr2_reg, cdt); 496 cx_write(ch->cnt2_reg, (lines * 16) >> 3); 497 cx_write(ch->cnt1_reg, (bpl >> 3) - 1); 498 499 return 0; 500 } 501 502 int cx25821_sram_channel_setup_audio(struct cx25821_dev *dev, 503 const struct sram_channel *ch, 504 unsigned int bpl, u32 risc) 505 { 506 unsigned int i, lines; 507 u32 cdt; 508 509 if (ch->cmds_start == 0) { 510 cx_write(ch->ptr1_reg, 0); 511 cx_write(ch->ptr2_reg, 0); 512 cx_write(ch->cnt2_reg, 0); 513 cx_write(ch->cnt1_reg, 0); 514 return 0; 515 } 516 517 bpl = (bpl + 7) & ~7; /* alignment */ 518 cdt = ch->cdt; 519 lines = ch->fifo_size / bpl; 520 521 if (lines > 3) 522 lines = 3; /* for AUDIO */ 523 524 BUG_ON(lines < 2); 525 526 cx_write(8 + 0, RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC); 527 cx_write(8 + 4, 8); 528 cx_write(8 + 8, 0); 529 530 /* write CDT */ 531 for (i = 0; i < lines; i++) { 532 cx_write(cdt + 16 * i, ch->fifo_start + bpl * i); 533 cx_write(cdt + 16 * i + 4, 0); 534 cx_write(cdt + 16 * i + 8, 0); 535 cx_write(cdt + 16 * i + 12, 0); 536 } 537 538 /* write CMDS */ 539 if (ch->jumponly) 540 cx_write(ch->cmds_start + 0, 8); 541 else 542 cx_write(ch->cmds_start + 0, risc); 543 544 cx_write(ch->cmds_start + 4, 0); /* 64 bits 63-32 */ 545 cx_write(ch->cmds_start + 8, cdt); 546 cx_write(ch->cmds_start + 12, (lines * 16) >> 3); 547 cx_write(ch->cmds_start + 16, ch->ctrl_start); 548 549 /* IQ size */ 550 if (ch->jumponly) 551 cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2)); 552 else 553 cx_write(ch->cmds_start + 20, 64 >> 2); 554 555 /* zero out */ 556 for (i = 24; i < 80; i += 4) 557 cx_write(ch->cmds_start + i, 0); 558 559 /* fill registers */ 560 cx_write(ch->ptr1_reg, ch->fifo_start); 561 cx_write(ch->ptr2_reg, cdt); 562 cx_write(ch->cnt2_reg, (lines * 16) >> 3); 563 cx_write(ch->cnt1_reg, (bpl >> 3) - 1); 564 565 return 0; 566 } 567 EXPORT_SYMBOL(cx25821_sram_channel_setup_audio); 568 569 void cx25821_sram_channel_dump(struct cx25821_dev *dev, const struct sram_channel *ch) 570 { 571 static char *name[] = { 572 "init risc lo", 573 "init risc hi", 574 "cdt base", 575 "cdt size", 576 "iq base", 577 "iq size", 578 "risc pc lo", 579 "risc pc hi", 580 "iq wr ptr", 581 "iq rd ptr", 582 "cdt current", 583 "pci target lo", 584 "pci target hi", 585 "line / byte", 586 }; 587 u32 risc; 588 unsigned int i, j, n; 589 590 pr_warn("%s: %s - dma channel status dump\n", dev->name, ch->name); 591 for (i = 0; i < ARRAY_SIZE(name); i++) 592 pr_warn("cmds + 0x%2x: %-15s: 0x%08x\n", 593 i * 4, name[i], cx_read(ch->cmds_start + 4 * i)); 594 595 j = i * 4; 596 for (i = 0; i < 4;) { 597 risc = cx_read(ch->cmds_start + 4 * (i + 14)); 598 pr_warn("cmds + 0x%2x: risc%d: ", j + i * 4, i); 599 i += cx25821_risc_decode(risc); 600 } 601 602 for (i = 0; i < (64 >> 2); i += n) { 603 risc = cx_read(ch->ctrl_start + 4 * i); 604 /* No consideration for bits 63-32 */ 605 606 pr_warn("ctrl + 0x%2x (0x%08x): iq %x: ", 607 i * 4, ch->ctrl_start + 4 * i, i); 608 n = cx25821_risc_decode(risc); 609 for (j = 1; j < n; j++) { 610 risc = cx_read(ch->ctrl_start + 4 * (i + j)); 611 pr_warn("ctrl + 0x%2x : iq %x: 0x%08x [ arg #%d ]\n", 612 4 * (i + j), i + j, risc, j); 613 } 614 } 615 616 pr_warn(" : fifo: 0x%08x -> 0x%x\n", 617 ch->fifo_start, ch->fifo_start + ch->fifo_size); 618 pr_warn(" : ctrl: 0x%08x -> 0x%x\n", 619 ch->ctrl_start, ch->ctrl_start + 6 * 16); 620 pr_warn(" : ptr1_reg: 0x%08x\n", 621 cx_read(ch->ptr1_reg)); 622 pr_warn(" : ptr2_reg: 0x%08x\n", 623 cx_read(ch->ptr2_reg)); 624 pr_warn(" : cnt1_reg: 0x%08x\n", 625 cx_read(ch->cnt1_reg)); 626 pr_warn(" : cnt2_reg: 0x%08x\n", 627 cx_read(ch->cnt2_reg)); 628 } 629 630 void cx25821_sram_channel_dump_audio(struct cx25821_dev *dev, 631 const struct sram_channel *ch) 632 { 633 static const char * const name[] = { 634 "init risc lo", 635 "init risc hi", 636 "cdt base", 637 "cdt size", 638 "iq base", 639 "iq size", 640 "risc pc lo", 641 "risc pc hi", 642 "iq wr ptr", 643 "iq rd ptr", 644 "cdt current", 645 "pci target lo", 646 "pci target hi", 647 "line / byte", 648 }; 649 650 u32 risc, value, tmp; 651 unsigned int i, j, n; 652 653 pr_info("\n%s: %s - dma Audio channel status dump\n", 654 dev->name, ch->name); 655 656 for (i = 0; i < ARRAY_SIZE(name); i++) 657 pr_info("%s: cmds + 0x%2x: %-15s: 0x%08x\n", 658 dev->name, i * 4, name[i], 659 cx_read(ch->cmds_start + 4 * i)); 660 661 j = i * 4; 662 for (i = 0; i < 4;) { 663 risc = cx_read(ch->cmds_start + 4 * (i + 14)); 664 pr_warn("cmds + 0x%2x: risc%d: ", j + i * 4, i); 665 i += cx25821_risc_decode(risc); 666 } 667 668 for (i = 0; i < (64 >> 2); i += n) { 669 risc = cx_read(ch->ctrl_start + 4 * i); 670 /* No consideration for bits 63-32 */ 671 672 pr_warn("ctrl + 0x%2x (0x%08x): iq %x: ", 673 i * 4, ch->ctrl_start + 4 * i, i); 674 n = cx25821_risc_decode(risc); 675 676 for (j = 1; j < n; j++) { 677 risc = cx_read(ch->ctrl_start + 4 * (i + j)); 678 pr_warn("ctrl + 0x%2x : iq %x: 0x%08x [ arg #%d ]\n", 679 4 * (i + j), i + j, risc, j); 680 } 681 } 682 683 pr_warn(" : fifo: 0x%08x -> 0x%x\n", 684 ch->fifo_start, ch->fifo_start + ch->fifo_size); 685 pr_warn(" : ctrl: 0x%08x -> 0x%x\n", 686 ch->ctrl_start, ch->ctrl_start + 6 * 16); 687 pr_warn(" : ptr1_reg: 0x%08x\n", 688 cx_read(ch->ptr1_reg)); 689 pr_warn(" : ptr2_reg: 0x%08x\n", 690 cx_read(ch->ptr2_reg)); 691 pr_warn(" : cnt1_reg: 0x%08x\n", 692 cx_read(ch->cnt1_reg)); 693 pr_warn(" : cnt2_reg: 0x%08x\n", 694 cx_read(ch->cnt2_reg)); 695 696 for (i = 0; i < 4; i++) { 697 risc = cx_read(ch->cmds_start + 56 + (i * 4)); 698 pr_warn("instruction %d = 0x%x\n", i, risc); 699 } 700 701 /* read data from the first cdt buffer */ 702 risc = cx_read(AUD_A_CDT); 703 pr_warn("\nread cdt loc=0x%x\n", risc); 704 for (i = 0; i < 8; i++) { 705 n = cx_read(risc + i * 4); 706 pr_cont("0x%x ", n); 707 } 708 pr_cont("\n\n"); 709 710 value = cx_read(CLK_RST); 711 CX25821_INFO(" CLK_RST = 0x%x\n\n", value); 712 713 value = cx_read(PLL_A_POST_STAT_BIST); 714 CX25821_INFO(" PLL_A_POST_STAT_BIST = 0x%x\n\n", value); 715 value = cx_read(PLL_A_INT_FRAC); 716 CX25821_INFO(" PLL_A_INT_FRAC = 0x%x\n\n", value); 717 718 value = cx_read(PLL_B_POST_STAT_BIST); 719 CX25821_INFO(" PLL_B_POST_STAT_BIST = 0x%x\n\n", value); 720 value = cx_read(PLL_B_INT_FRAC); 721 CX25821_INFO(" PLL_B_INT_FRAC = 0x%x\n\n", value); 722 723 value = cx_read(PLL_C_POST_STAT_BIST); 724 CX25821_INFO(" PLL_C_POST_STAT_BIST = 0x%x\n\n", value); 725 value = cx_read(PLL_C_INT_FRAC); 726 CX25821_INFO(" PLL_C_INT_FRAC = 0x%x\n\n", value); 727 728 value = cx_read(PLL_D_POST_STAT_BIST); 729 CX25821_INFO(" PLL_D_POST_STAT_BIST = 0x%x\n\n", value); 730 value = cx_read(PLL_D_INT_FRAC); 731 CX25821_INFO(" PLL_D_INT_FRAC = 0x%x\n\n", value); 732 733 value = cx25821_i2c_read(&dev->i2c_bus[0], AFE_AB_DIAG_CTRL, &tmp); 734 CX25821_INFO(" AFE_AB_DIAG_CTRL (0x10900090) = 0x%x\n\n", value); 735 } 736 EXPORT_SYMBOL(cx25821_sram_channel_dump_audio); 737 738 static void cx25821_shutdown(struct cx25821_dev *dev) 739 { 740 int i; 741 742 /* disable RISC controller */ 743 cx_write(DEV_CNTRL2, 0); 744 745 /* Disable Video A/B activity */ 746 for (i = 0; i < VID_CHANNEL_NUM; i++) { 747 cx_write(dev->channels[i].sram_channels->dma_ctl, 0); 748 cx_write(dev->channels[i].sram_channels->int_msk, 0); 749 } 750 751 for (i = VID_UPSTREAM_SRAM_CHANNEL_I; 752 i <= VID_UPSTREAM_SRAM_CHANNEL_J; i++) { 753 cx_write(dev->channels[i].sram_channels->dma_ctl, 0); 754 cx_write(dev->channels[i].sram_channels->int_msk, 0); 755 } 756 757 /* Disable Audio activity */ 758 cx_write(AUD_INT_DMA_CTL, 0); 759 760 /* Disable Serial port */ 761 cx_write(UART_CTL, 0); 762 763 /* Disable Interrupts */ 764 cx_write(PCI_INT_MSK, 0); 765 cx_write(AUD_A_INT_MSK, 0); 766 } 767 768 void cx25821_set_pixel_format(struct cx25821_dev *dev, int channel_select, 769 u32 format) 770 { 771 if (channel_select <= 7 && channel_select >= 0) { 772 cx_write(dev->channels[channel_select].sram_channels->pix_frmt, 773 format); 774 } 775 dev->channels[channel_select].pixel_formats = format; 776 } 777 778 static void cx25821_set_vip_mode(struct cx25821_dev *dev, 779 const struct sram_channel *ch) 780 { 781 cx_write(ch->pix_frmt, PIXEL_FRMT_422); 782 cx_write(ch->vip_ctl, PIXEL_ENGINE_VIP1); 783 } 784 785 static void cx25821_initialize(struct cx25821_dev *dev) 786 { 787 int i; 788 789 dprintk(1, "%s()\n", __func__); 790 791 cx25821_shutdown(dev); 792 cx_write(PCI_INT_STAT, 0xffffffff); 793 794 for (i = 0; i < VID_CHANNEL_NUM; i++) 795 cx_write(dev->channels[i].sram_channels->int_stat, 0xffffffff); 796 797 cx_write(AUD_A_INT_STAT, 0xffffffff); 798 cx_write(AUD_B_INT_STAT, 0xffffffff); 799 cx_write(AUD_C_INT_STAT, 0xffffffff); 800 cx_write(AUD_D_INT_STAT, 0xffffffff); 801 cx_write(AUD_E_INT_STAT, 0xffffffff); 802 803 cx_write(CLK_DELAY, cx_read(CLK_DELAY) & 0x80000000); 804 cx_write(PAD_CTRL, 0x12); /* for I2C */ 805 cx25821_registers_init(dev); /* init Pecos registers */ 806 msleep(100); 807 808 for (i = 0; i < VID_CHANNEL_NUM; i++) { 809 cx25821_set_vip_mode(dev, dev->channels[i].sram_channels); 810 cx25821_sram_channel_setup(dev, dev->channels[i].sram_channels, 811 1440, 0); 812 dev->channels[i].pixel_formats = PIXEL_FRMT_422; 813 dev->channels[i].use_cif_resolution = 0; 814 } 815 816 /* Probably only affect Downstream */ 817 for (i = VID_UPSTREAM_SRAM_CHANNEL_I; 818 i <= VID_UPSTREAM_SRAM_CHANNEL_J; i++) { 819 dev->channels[i].pixel_formats = PIXEL_FRMT_422; 820 cx25821_set_vip_mode(dev, dev->channels[i].sram_channels); 821 } 822 823 cx25821_sram_channel_setup_audio(dev, 824 dev->channels[SRAM_CH08].sram_channels, 128, 0); 825 826 cx25821_gpio_init(dev); 827 } 828 829 static int cx25821_get_resources(struct cx25821_dev *dev) 830 { 831 if (request_mem_region(pci_resource_start(dev->pci, 0), 832 pci_resource_len(dev->pci, 0), dev->name)) 833 return 0; 834 835 pr_err("%s: can't get MMIO memory @ 0x%llx\n", 836 dev->name, (unsigned long long)pci_resource_start(dev->pci, 0)); 837 838 return -EBUSY; 839 } 840 841 static void cx25821_dev_checkrevision(struct cx25821_dev *dev) 842 { 843 dev->hwrevision = cx_read(RDR_CFG2) & 0xff; 844 845 pr_info("Hardware revision = 0x%02x\n", dev->hwrevision); 846 } 847 848 static void cx25821_iounmap(struct cx25821_dev *dev) 849 { 850 if (dev == NULL) 851 return; 852 853 /* Releasing IO memory */ 854 if (dev->lmmio != NULL) { 855 iounmap(dev->lmmio); 856 dev->lmmio = NULL; 857 } 858 } 859 860 static int cx25821_dev_setup(struct cx25821_dev *dev) 861 { 862 static unsigned int cx25821_devcount; 863 int i; 864 865 mutex_init(&dev->lock); 866 867 dev->nr = ++cx25821_devcount; 868 sprintf(dev->name, "cx25821[%d]", dev->nr); 869 870 if (dev->nr >= ARRAY_SIZE(card)) { 871 CX25821_INFO("dev->nr >= %zd", ARRAY_SIZE(card)); 872 return -ENODEV; 873 } 874 if (dev->pci->device != 0x8210) { 875 pr_info("%s(): Exiting. Incorrect Hardware device = 0x%02x\n", 876 __func__, dev->pci->device); 877 return -ENODEV; 878 } 879 pr_info("Athena Hardware device = 0x%02x\n", dev->pci->device); 880 881 /* Apply a sensible clock frequency for the PCIe bridge */ 882 dev->clk_freq = 28000000; 883 for (i = 0; i < MAX_VID_CHANNEL_NUM; i++) { 884 dev->channels[i].dev = dev; 885 dev->channels[i].id = i; 886 dev->channels[i].sram_channels = &cx25821_sram_channels[i]; 887 } 888 889 /* board config */ 890 dev->board = 1; /* card[dev->nr]; */ 891 dev->_max_num_decoders = MAX_DECODERS; 892 893 dev->pci_bus = dev->pci->bus->number; 894 dev->pci_slot = PCI_SLOT(dev->pci->devfn); 895 dev->pci_irqmask = 0x001f00; 896 897 /* External Master 1 Bus */ 898 dev->i2c_bus[0].nr = 0; 899 dev->i2c_bus[0].dev = dev; 900 dev->i2c_bus[0].reg_stat = I2C1_STAT; 901 dev->i2c_bus[0].reg_ctrl = I2C1_CTRL; 902 dev->i2c_bus[0].reg_addr = I2C1_ADDR; 903 dev->i2c_bus[0].reg_rdata = I2C1_RDATA; 904 dev->i2c_bus[0].reg_wdata = I2C1_WDATA; 905 dev->i2c_bus[0].i2c_period = (0x07 << 24); /* 1.95MHz */ 906 907 if (cx25821_get_resources(dev) < 0) { 908 pr_err("%s: No more PCIe resources for subsystem: %04x:%04x\n", 909 dev->name, dev->pci->subsystem_vendor, 910 dev->pci->subsystem_device); 911 912 cx25821_devcount--; 913 return -EBUSY; 914 } 915 916 /* PCIe stuff */ 917 dev->base_io_addr = pci_resource_start(dev->pci, 0); 918 919 if (!dev->base_io_addr) { 920 CX25821_ERR("No PCI Memory resources, exiting!\n"); 921 return -ENODEV; 922 } 923 924 dev->lmmio = ioremap(dev->base_io_addr, pci_resource_len(dev->pci, 0)); 925 926 if (!dev->lmmio) { 927 CX25821_ERR("ioremap failed, maybe increasing __VMALLOC_RESERVE in page.h\n"); 928 cx25821_iounmap(dev); 929 return -ENOMEM; 930 } 931 932 dev->bmmio = (u8 __iomem *) dev->lmmio; 933 934 pr_info("%s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n", 935 dev->name, dev->pci->subsystem_vendor, 936 dev->pci->subsystem_device, cx25821_boards[dev->board].name, 937 dev->board, card[dev->nr] == dev->board ? 938 "insmod option" : "autodetected"); 939 940 /* init hardware */ 941 cx25821_initialize(dev); 942 943 cx25821_i2c_register(&dev->i2c_bus[0]); 944 /* cx25821_i2c_register(&dev->i2c_bus[1]); 945 * cx25821_i2c_register(&dev->i2c_bus[2]); */ 946 947 if (medusa_video_init(dev) < 0) 948 CX25821_ERR("%s(): Failed to initialize medusa!\n", __func__); 949 950 cx25821_video_register(dev); 951 952 cx25821_dev_checkrevision(dev); 953 return 0; 954 } 955 956 void cx25821_dev_unregister(struct cx25821_dev *dev) 957 { 958 int i; 959 960 if (!dev->base_io_addr) 961 return; 962 963 release_mem_region(dev->base_io_addr, pci_resource_len(dev->pci, 0)); 964 965 for (i = 0; i < MAX_VID_CAP_CHANNEL_NUM - 1; i++) { 966 if (i == SRAM_CH08) /* audio channel */ 967 continue; 968 /* 969 * TODO: enable when video output is properly 970 * supported. 971 if (i == SRAM_CH09 || i == SRAM_CH10) 972 cx25821_free_mem_upstream(&dev->channels[i]); 973 */ 974 cx25821_video_unregister(dev, i); 975 } 976 977 cx25821_i2c_unregister(&dev->i2c_bus[0]); 978 cx25821_iounmap(dev); 979 } 980 EXPORT_SYMBOL(cx25821_dev_unregister); 981 982 int cx25821_riscmem_alloc(struct pci_dev *pci, 983 struct cx25821_riscmem *risc, 984 unsigned int size) 985 { 986 __le32 *cpu; 987 dma_addr_t dma = 0; 988 989 if (NULL != risc->cpu && risc->size < size) 990 pci_free_consistent(pci, risc->size, risc->cpu, risc->dma); 991 if (NULL == risc->cpu) { 992 cpu = pci_zalloc_consistent(pci, size, &dma); 993 if (NULL == cpu) 994 return -ENOMEM; 995 risc->cpu = cpu; 996 risc->dma = dma; 997 risc->size = size; 998 } 999 return 0; 1000 } 1001 EXPORT_SYMBOL(cx25821_riscmem_alloc); 1002 1003 static __le32 *cx25821_risc_field(__le32 * rp, struct scatterlist *sglist, 1004 unsigned int offset, u32 sync_line, 1005 unsigned int bpl, unsigned int padding, 1006 unsigned int lines, bool jump) 1007 { 1008 struct scatterlist *sg; 1009 unsigned int line, todo; 1010 1011 if (jump) { 1012 *(rp++) = cpu_to_le32(RISC_JUMP); 1013 *(rp++) = cpu_to_le32(0); 1014 *(rp++) = cpu_to_le32(0); /* bits 63-32 */ 1015 } 1016 1017 /* sync instruction */ 1018 if (sync_line != NO_SYNC_LINE) 1019 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line); 1020 1021 /* scan lines */ 1022 sg = sglist; 1023 for (line = 0; line < lines; line++) { 1024 while (offset && offset >= sg_dma_len(sg)) { 1025 offset -= sg_dma_len(sg); 1026 sg = sg_next(sg); 1027 } 1028 if (bpl <= sg_dma_len(sg) - offset) { 1029 /* fits into current chunk */ 1030 *(rp++) = cpu_to_le32(RISC_WRITE | RISC_SOL | RISC_EOL | 1031 bpl); 1032 *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset); 1033 *(rp++) = cpu_to_le32(0); /* bits 63-32 */ 1034 offset += bpl; 1035 } else { 1036 /* scanline needs to be split */ 1037 todo = bpl; 1038 *(rp++) = cpu_to_le32(RISC_WRITE | RISC_SOL | 1039 (sg_dma_len(sg) - offset)); 1040 *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset); 1041 *(rp++) = cpu_to_le32(0); /* bits 63-32 */ 1042 todo -= (sg_dma_len(sg) - offset); 1043 offset = 0; 1044 sg = sg_next(sg); 1045 while (todo > sg_dma_len(sg)) { 1046 *(rp++) = cpu_to_le32(RISC_WRITE | 1047 sg_dma_len(sg)); 1048 *(rp++) = cpu_to_le32(sg_dma_address(sg)); 1049 *(rp++) = cpu_to_le32(0); /* bits 63-32 */ 1050 todo -= sg_dma_len(sg); 1051 sg = sg_next(sg); 1052 } 1053 *(rp++) = cpu_to_le32(RISC_WRITE | RISC_EOL | todo); 1054 *(rp++) = cpu_to_le32(sg_dma_address(sg)); 1055 *(rp++) = cpu_to_le32(0); /* bits 63-32 */ 1056 offset += todo; 1057 } 1058 1059 offset += padding; 1060 } 1061 1062 return rp; 1063 } 1064 1065 int cx25821_risc_buffer(struct pci_dev *pci, struct cx25821_riscmem *risc, 1066 struct scatterlist *sglist, unsigned int top_offset, 1067 unsigned int bottom_offset, unsigned int bpl, 1068 unsigned int padding, unsigned int lines) 1069 { 1070 u32 instructions; 1071 u32 fields; 1072 __le32 *rp; 1073 int rc; 1074 1075 fields = 0; 1076 if (UNSET != top_offset) 1077 fields++; 1078 if (UNSET != bottom_offset) 1079 fields++; 1080 1081 /* estimate risc mem: worst case is one write per page border + 1082 one write per scan line + syncs + jump (all 3 dwords). Padding 1083 can cause next bpl to start close to a page border. First DMA 1084 region may be smaller than PAGE_SIZE */ 1085 /* write and jump need and extra dword */ 1086 instructions = fields * (1 + ((bpl + padding) * lines) / PAGE_SIZE + 1087 lines); 1088 instructions += 5; 1089 rc = cx25821_riscmem_alloc(pci, risc, instructions * 12); 1090 1091 if (rc < 0) 1092 return rc; 1093 1094 /* write risc instructions */ 1095 rp = risc->cpu; 1096 1097 if (UNSET != top_offset) { 1098 rp = cx25821_risc_field(rp, sglist, top_offset, 0, bpl, padding, 1099 lines, true); 1100 } 1101 1102 if (UNSET != bottom_offset) { 1103 rp = cx25821_risc_field(rp, sglist, bottom_offset, 0x200, bpl, 1104 padding, lines, UNSET == top_offset); 1105 } 1106 1107 /* save pointer to jmp instruction address */ 1108 risc->jmp = rp; 1109 BUG_ON((risc->jmp - risc->cpu + 3) * sizeof(*risc->cpu) > risc->size); 1110 1111 return 0; 1112 } 1113 1114 static __le32 *cx25821_risc_field_audio(__le32 * rp, struct scatterlist *sglist, 1115 unsigned int offset, u32 sync_line, 1116 unsigned int bpl, unsigned int padding, 1117 unsigned int lines, unsigned int lpi) 1118 { 1119 struct scatterlist *sg; 1120 unsigned int line, todo, sol; 1121 1122 /* sync instruction */ 1123 if (sync_line != NO_SYNC_LINE) 1124 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line); 1125 1126 /* scan lines */ 1127 sg = sglist; 1128 for (line = 0; line < lines; line++) { 1129 while (offset && offset >= sg_dma_len(sg)) { 1130 offset -= sg_dma_len(sg); 1131 sg = sg_next(sg); 1132 } 1133 1134 if (lpi && line > 0 && !(line % lpi)) 1135 sol = RISC_SOL | RISC_IRQ1 | RISC_CNT_INC; 1136 else 1137 sol = RISC_SOL; 1138 1139 if (bpl <= sg_dma_len(sg) - offset) { 1140 /* fits into current chunk */ 1141 *(rp++) = cpu_to_le32(RISC_WRITE | sol | RISC_EOL | 1142 bpl); 1143 *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset); 1144 *(rp++) = cpu_to_le32(0); /* bits 63-32 */ 1145 offset += bpl; 1146 } else { 1147 /* scanline needs to be split */ 1148 todo = bpl; 1149 *(rp++) = cpu_to_le32(RISC_WRITE | sol | 1150 (sg_dma_len(sg) - offset)); 1151 *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset); 1152 *(rp++) = cpu_to_le32(0); /* bits 63-32 */ 1153 todo -= (sg_dma_len(sg) - offset); 1154 offset = 0; 1155 sg = sg_next(sg); 1156 while (todo > sg_dma_len(sg)) { 1157 *(rp++) = cpu_to_le32(RISC_WRITE | 1158 sg_dma_len(sg)); 1159 *(rp++) = cpu_to_le32(sg_dma_address(sg)); 1160 *(rp++) = cpu_to_le32(0); /* bits 63-32 */ 1161 todo -= sg_dma_len(sg); 1162 sg = sg_next(sg); 1163 } 1164 *(rp++) = cpu_to_le32(RISC_WRITE | RISC_EOL | todo); 1165 *(rp++) = cpu_to_le32(sg_dma_address(sg)); 1166 *(rp++) = cpu_to_le32(0); /* bits 63-32 */ 1167 offset += todo; 1168 } 1169 offset += padding; 1170 } 1171 1172 return rp; 1173 } 1174 1175 int cx25821_risc_databuffer_audio(struct pci_dev *pci, 1176 struct cx25821_riscmem *risc, 1177 struct scatterlist *sglist, 1178 unsigned int bpl, 1179 unsigned int lines, unsigned int lpi) 1180 { 1181 u32 instructions; 1182 __le32 *rp; 1183 int rc; 1184 1185 /* estimate risc mem: worst case is one write per page border + 1186 one write per scan line + syncs + jump (all 2 dwords). Here 1187 there is no padding and no sync. First DMA region may be smaller 1188 than PAGE_SIZE */ 1189 /* Jump and write need an extra dword */ 1190 instructions = 1 + (bpl * lines) / PAGE_SIZE + lines; 1191 instructions += 1; 1192 1193 rc = cx25821_riscmem_alloc(pci, risc, instructions * 12); 1194 if (rc < 0) 1195 return rc; 1196 1197 /* write risc instructions */ 1198 rp = risc->cpu; 1199 rp = cx25821_risc_field_audio(rp, sglist, 0, NO_SYNC_LINE, bpl, 0, 1200 lines, lpi); 1201 1202 /* save pointer to jmp instruction address */ 1203 risc->jmp = rp; 1204 BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size); 1205 return 0; 1206 } 1207 EXPORT_SYMBOL(cx25821_risc_databuffer_audio); 1208 1209 void cx25821_free_buffer(struct cx25821_dev *dev, struct cx25821_buffer *buf) 1210 { 1211 BUG_ON(in_interrupt()); 1212 if (WARN_ON(buf->risc.size == 0)) 1213 return; 1214 pci_free_consistent(dev->pci, 1215 buf->risc.size, buf->risc.cpu, buf->risc.dma); 1216 memset(&buf->risc, 0, sizeof(buf->risc)); 1217 } 1218 1219 static irqreturn_t cx25821_irq(int irq, void *dev_id) 1220 { 1221 struct cx25821_dev *dev = dev_id; 1222 u32 pci_status; 1223 u32 vid_status; 1224 int i, handled = 0; 1225 u32 mask[8] = { 1, 2, 4, 8, 16, 32, 64, 128 }; 1226 1227 pci_status = cx_read(PCI_INT_STAT); 1228 1229 if (pci_status == 0) 1230 goto out; 1231 1232 for (i = 0; i < VID_CHANNEL_NUM; i++) { 1233 if (pci_status & mask[i]) { 1234 vid_status = cx_read(dev->channels[i]. 1235 sram_channels->int_stat); 1236 1237 if (vid_status) 1238 handled += cx25821_video_irq(dev, i, 1239 vid_status); 1240 1241 cx_write(PCI_INT_STAT, mask[i]); 1242 } 1243 } 1244 1245 out: 1246 return IRQ_RETVAL(handled); 1247 } 1248 1249 void cx25821_print_irqbits(char *name, char *tag, char **strings, 1250 int len, u32 bits, u32 mask) 1251 { 1252 unsigned int i; 1253 1254 printk(KERN_DEBUG pr_fmt("%s: %s [0x%x]"), name, tag, bits); 1255 1256 for (i = 0; i < len; i++) { 1257 if (!(bits & (1 << i))) 1258 continue; 1259 if (strings[i]) 1260 pr_cont(" %s", strings[i]); 1261 else 1262 pr_cont(" %d", i); 1263 if (!(mask & (1 << i))) 1264 continue; 1265 pr_cont("*"); 1266 } 1267 pr_cont("\n"); 1268 } 1269 EXPORT_SYMBOL(cx25821_print_irqbits); 1270 1271 struct cx25821_dev *cx25821_dev_get(struct pci_dev *pci) 1272 { 1273 struct cx25821_dev *dev = pci_get_drvdata(pci); 1274 return dev; 1275 } 1276 EXPORT_SYMBOL(cx25821_dev_get); 1277 1278 static int cx25821_initdev(struct pci_dev *pci_dev, 1279 const struct pci_device_id *pci_id) 1280 { 1281 struct cx25821_dev *dev; 1282 int err = 0; 1283 1284 dev = kzalloc(sizeof(*dev), GFP_KERNEL); 1285 if (NULL == dev) 1286 return -ENOMEM; 1287 1288 err = v4l2_device_register(&pci_dev->dev, &dev->v4l2_dev); 1289 if (err < 0) 1290 goto fail_free; 1291 1292 /* pci init */ 1293 dev->pci = pci_dev; 1294 if (pci_enable_device(pci_dev)) { 1295 err = -EIO; 1296 1297 pr_info("pci enable failed!\n"); 1298 1299 goto fail_unregister_device; 1300 } 1301 1302 err = cx25821_dev_setup(dev); 1303 if (err) 1304 goto fail_unregister_pci; 1305 1306 /* print pci info */ 1307 pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev); 1308 pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat); 1309 pr_info("%s/0: found at %s, rev: %d, irq: %d, latency: %d, mmio: 0x%llx\n", 1310 dev->name, pci_name(pci_dev), dev->pci_rev, pci_dev->irq, 1311 dev->pci_lat, (unsigned long long)dev->base_io_addr); 1312 1313 pci_set_master(pci_dev); 1314 err = pci_set_dma_mask(pci_dev, 0xffffffff); 1315 if (err) { 1316 pr_err("%s/0: Oops: no 32bit PCI DMA ???\n", dev->name); 1317 err = -EIO; 1318 goto fail_irq; 1319 } 1320 1321 err = request_irq(pci_dev->irq, cx25821_irq, 1322 IRQF_SHARED, dev->name, dev); 1323 1324 if (err < 0) { 1325 pr_err("%s: can't get IRQ %d\n", dev->name, pci_dev->irq); 1326 goto fail_irq; 1327 } 1328 1329 return 0; 1330 1331 fail_irq: 1332 pr_info("cx25821_initdev() can't get IRQ !\n"); 1333 cx25821_dev_unregister(dev); 1334 1335 fail_unregister_pci: 1336 pci_disable_device(pci_dev); 1337 fail_unregister_device: 1338 v4l2_device_unregister(&dev->v4l2_dev); 1339 1340 fail_free: 1341 kfree(dev); 1342 return err; 1343 } 1344 1345 static void cx25821_finidev(struct pci_dev *pci_dev) 1346 { 1347 struct v4l2_device *v4l2_dev = pci_get_drvdata(pci_dev); 1348 struct cx25821_dev *dev = get_cx25821(v4l2_dev); 1349 1350 cx25821_shutdown(dev); 1351 pci_disable_device(pci_dev); 1352 1353 /* unregister stuff */ 1354 if (pci_dev->irq) 1355 free_irq(pci_dev->irq, dev); 1356 1357 cx25821_dev_unregister(dev); 1358 v4l2_device_unregister(v4l2_dev); 1359 kfree(dev); 1360 } 1361 1362 static const struct pci_device_id cx25821_pci_tbl[] = { 1363 { 1364 /* CX25821 Athena */ 1365 .vendor = 0x14f1, 1366 .device = 0x8210, 1367 .subvendor = 0x14f1, 1368 .subdevice = 0x0920, 1369 }, { 1370 /* CX25821 No Brand */ 1371 .vendor = 0x14f1, 1372 .device = 0x8210, 1373 .subvendor = 0x0000, 1374 .subdevice = 0x0000, 1375 }, { 1376 /* --- end of list --- */ 1377 } 1378 }; 1379 1380 MODULE_DEVICE_TABLE(pci, cx25821_pci_tbl); 1381 1382 static struct pci_driver cx25821_pci_driver = { 1383 .name = "cx25821", 1384 .id_table = cx25821_pci_tbl, 1385 .probe = cx25821_initdev, 1386 .remove = cx25821_finidev, 1387 /* TODO */ 1388 .suspend = NULL, 1389 .resume = NULL, 1390 }; 1391 1392 static int __init cx25821_init(void) 1393 { 1394 pr_info("driver loaded\n"); 1395 return pci_register_driver(&cx25821_pci_driver); 1396 } 1397 1398 static void __exit cx25821_fini(void) 1399 { 1400 pci_unregister_driver(&cx25821_pci_driver); 1401 } 1402 1403 module_init(cx25821_init); 1404 module_exit(cx25821_fini); 1405