1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Driver for the Conexant CX23885/7/8 PCIe bridge 4 * 5 * CX23888 Integrated Consumer Infrared Controller 6 * 7 * Copyright (C) 2009 Andy Walls <awalls@md.metrocast.net> 8 */ 9 10 #include "cx23885.h" 11 #include "cx23888-ir.h" 12 13 #include <linux/kfifo.h> 14 #include <linux/slab.h> 15 16 #include <media/v4l2-device.h> 17 #include <media/rc-core.h> 18 19 static unsigned int ir_888_debug; 20 module_param(ir_888_debug, int, 0644); 21 MODULE_PARM_DESC(ir_888_debug, "enable debug messages [CX23888 IR controller]"); 22 23 #define CX23888_IR_REG_BASE 0x170000 24 /* 25 * These CX23888 register offsets have a straightforward one to one mapping 26 * to the CX23885 register offsets of 0x200 through 0x218 27 */ 28 #define CX23888_IR_CNTRL_REG 0x170000 29 #define CNTRL_WIN_3_3 0x00000000 30 #define CNTRL_WIN_4_3 0x00000001 31 #define CNTRL_WIN_3_4 0x00000002 32 #define CNTRL_WIN_4_4 0x00000003 33 #define CNTRL_WIN 0x00000003 34 #define CNTRL_EDG_NONE 0x00000000 35 #define CNTRL_EDG_FALL 0x00000004 36 #define CNTRL_EDG_RISE 0x00000008 37 #define CNTRL_EDG_BOTH 0x0000000C 38 #define CNTRL_EDG 0x0000000C 39 #define CNTRL_DMD 0x00000010 40 #define CNTRL_MOD 0x00000020 41 #define CNTRL_RFE 0x00000040 42 #define CNTRL_TFE 0x00000080 43 #define CNTRL_RXE 0x00000100 44 #define CNTRL_TXE 0x00000200 45 #define CNTRL_RIC 0x00000400 46 #define CNTRL_TIC 0x00000800 47 #define CNTRL_CPL 0x00001000 48 #define CNTRL_LBM 0x00002000 49 #define CNTRL_R 0x00004000 50 /* CX23888 specific control flag */ 51 #define CNTRL_IVO 0x00008000 52 53 #define CX23888_IR_TXCLK_REG 0x170004 54 #define TXCLK_TCD 0x0000FFFF 55 56 #define CX23888_IR_RXCLK_REG 0x170008 57 #define RXCLK_RCD 0x0000FFFF 58 59 #define CX23888_IR_CDUTY_REG 0x17000C 60 #define CDUTY_CDC 0x0000000F 61 62 #define CX23888_IR_STATS_REG 0x170010 63 #define STATS_RTO 0x00000001 64 #define STATS_ROR 0x00000002 65 #define STATS_RBY 0x00000004 66 #define STATS_TBY 0x00000008 67 #define STATS_RSR 0x00000010 68 #define STATS_TSR 0x00000020 69 70 #define CX23888_IR_IRQEN_REG 0x170014 71 #define IRQEN_RTE 0x00000001 72 #define IRQEN_ROE 0x00000002 73 #define IRQEN_RSE 0x00000010 74 #define IRQEN_TSE 0x00000020 75 76 #define CX23888_IR_FILTR_REG 0x170018 77 #define FILTR_LPF 0x0000FFFF 78 79 /* This register doesn't follow the pattern; it's 0x23C on a CX23885 */ 80 #define CX23888_IR_FIFO_REG 0x170040 81 #define FIFO_RXTX 0x0000FFFF 82 #define FIFO_RXTX_LVL 0x00010000 83 #define FIFO_RXTX_RTO 0x0001FFFF 84 #define FIFO_RX_NDV 0x00020000 85 #define FIFO_RX_DEPTH 8 86 #define FIFO_TX_DEPTH 8 87 88 /* CX23888 unique registers */ 89 #define CX23888_IR_SEEDP_REG 0x17001C 90 #define CX23888_IR_TIMOL_REG 0x170020 91 #define CX23888_IR_WAKE0_REG 0x170024 92 #define CX23888_IR_WAKE1_REG 0x170028 93 #define CX23888_IR_WAKE2_REG 0x17002C 94 #define CX23888_IR_MASK0_REG 0x170030 95 #define CX23888_IR_MASK1_REG 0x170034 96 #define CX23888_IR_MAKS2_REG 0x170038 97 #define CX23888_IR_DPIPG_REG 0x17003C 98 #define CX23888_IR_LEARN_REG 0x170044 99 100 #define CX23888_VIDCLK_FREQ 108000000 /* 108 MHz, BT.656 */ 101 #define CX23888_IR_REFCLK_FREQ (CX23888_VIDCLK_FREQ / 2) 102 103 /* 104 * We use this union internally for convenience, but callers to tx_write 105 * and rx_read will be expecting records of type struct ir_raw_event. 106 * Always ensure the size of this union is dictated by struct ir_raw_event. 107 */ 108 union cx23888_ir_fifo_rec { 109 u32 hw_fifo_data; 110 struct ir_raw_event ir_core_data; 111 }; 112 113 #define CX23888_IR_RX_KFIFO_SIZE (256 * sizeof(union cx23888_ir_fifo_rec)) 114 #define CX23888_IR_TX_KFIFO_SIZE (256 * sizeof(union cx23888_ir_fifo_rec)) 115 116 struct cx23888_ir_state { 117 struct v4l2_subdev sd; 118 struct cx23885_dev *dev; 119 120 struct v4l2_subdev_ir_parameters rx_params; 121 struct mutex rx_params_lock; 122 atomic_t rxclk_divider; 123 atomic_t rx_invert; 124 125 struct kfifo rx_kfifo; 126 spinlock_t rx_kfifo_lock; 127 128 struct v4l2_subdev_ir_parameters tx_params; 129 struct mutex tx_params_lock; 130 atomic_t txclk_divider; 131 }; 132 133 static inline struct cx23888_ir_state *to_state(struct v4l2_subdev *sd) 134 { 135 return v4l2_get_subdevdata(sd); 136 } 137 138 /* 139 * IR register block read and write functions 140 */ 141 static 142 inline int cx23888_ir_write4(struct cx23885_dev *dev, u32 addr, u32 value) 143 { 144 cx_write(addr, value); 145 return 0; 146 } 147 148 static inline u32 cx23888_ir_read4(struct cx23885_dev *dev, u32 addr) 149 { 150 return cx_read(addr); 151 } 152 153 static inline int cx23888_ir_and_or4(struct cx23885_dev *dev, u32 addr, 154 u32 and_mask, u32 or_value) 155 { 156 cx_andor(addr, ~and_mask, or_value); 157 return 0; 158 } 159 160 /* 161 * Rx and Tx Clock Divider register computations 162 * 163 * Note the largest clock divider value of 0xffff corresponds to: 164 * (0xffff + 1) * 1000 / 108/2 MHz = 1,213,629.629... ns 165 * which fits in 21 bits, so we'll use unsigned int for time arguments. 166 */ 167 static inline u16 count_to_clock_divider(unsigned int d) 168 { 169 if (d > RXCLK_RCD + 1) 170 d = RXCLK_RCD; 171 else if (d < 2) 172 d = 1; 173 else 174 d--; 175 return (u16) d; 176 } 177 178 static inline u16 carrier_freq_to_clock_divider(unsigned int freq) 179 { 180 return count_to_clock_divider( 181 DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, freq * 16)); 182 } 183 184 static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider) 185 { 186 return DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, (divider + 1) * 16); 187 } 188 189 static inline unsigned int clock_divider_to_freq(unsigned int divider, 190 unsigned int rollovers) 191 { 192 return DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, 193 (divider + 1) * rollovers); 194 } 195 196 /* 197 * Low Pass Filter register calculations 198 * 199 * Note the largest count value of 0xffff corresponds to: 200 * 0xffff * 1000 / 108/2 MHz = 1,213,611.11... ns 201 * which fits in 21 bits, so we'll use unsigned int for time arguments. 202 */ 203 static inline u16 count_to_lpf_count(unsigned int d) 204 { 205 if (d > FILTR_LPF) 206 d = FILTR_LPF; 207 else if (d < 4) 208 d = 0; 209 return (u16) d; 210 } 211 212 static inline u16 ns_to_lpf_count(unsigned int ns) 213 { 214 return count_to_lpf_count( 215 DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ / 1000000 * ns, 1000)); 216 } 217 218 static inline unsigned int lpf_count_to_ns(unsigned int count) 219 { 220 /* Duration of the Low Pass Filter rejection window in ns */ 221 return DIV_ROUND_CLOSEST(count * 1000, 222 CX23888_IR_REFCLK_FREQ / 1000000); 223 } 224 225 static inline unsigned int lpf_count_to_us(unsigned int count) 226 { 227 /* Duration of the Low Pass Filter rejection window in us */ 228 return DIV_ROUND_CLOSEST(count, CX23888_IR_REFCLK_FREQ / 1000000); 229 } 230 231 /* 232 * FIFO register pulse width count computations 233 */ 234 static u32 clock_divider_to_resolution(u16 divider) 235 { 236 /* 237 * Resolution is the duration of 1 tick of the readable portion of 238 * the pulse width counter as read from the FIFO. The two lsb's are 239 * not readable, hence the << 2. This function returns ns. 240 */ 241 return DIV_ROUND_CLOSEST((1 << 2) * ((u32) divider + 1) * 1000, 242 CX23888_IR_REFCLK_FREQ / 1000000); 243 } 244 245 static u64 pulse_width_count_to_ns(u16 count, u16 divider) 246 { 247 u64 n; 248 u32 rem; 249 250 /* 251 * The 2 lsb's of the pulse width timer count are not readable, hence 252 * the (count << 2) | 0x3 253 */ 254 n = (((u64) count << 2) | 0x3) * (divider + 1) * 1000; /* millicycles */ 255 rem = do_div(n, CX23888_IR_REFCLK_FREQ / 1000000); /* / MHz => ns */ 256 if (rem >= CX23888_IR_REFCLK_FREQ / 1000000 / 2) 257 n++; 258 return n; 259 } 260 261 static unsigned int pulse_width_count_to_us(u16 count, u16 divider) 262 { 263 u64 n; 264 u32 rem; 265 266 /* 267 * The 2 lsb's of the pulse width timer count are not readable, hence 268 * the (count << 2) | 0x3 269 */ 270 n = (((u64) count << 2) | 0x3) * (divider + 1); /* cycles */ 271 rem = do_div(n, CX23888_IR_REFCLK_FREQ / 1000000); /* / MHz => us */ 272 if (rem >= CX23888_IR_REFCLK_FREQ / 1000000 / 2) 273 n++; 274 return (unsigned int) n; 275 } 276 277 /* 278 * Pulse Clocks computations: Combined Pulse Width Count & Rx Clock Counts 279 * 280 * The total pulse clock count is an 18 bit pulse width timer count as the most 281 * significant part and (up to) 16 bit clock divider count as a modulus. 282 * When the Rx clock divider ticks down to 0, it increments the 18 bit pulse 283 * width timer count's least significant bit. 284 */ 285 static u64 ns_to_pulse_clocks(u32 ns) 286 { 287 u64 clocks; 288 u32 rem; 289 clocks = CX23888_IR_REFCLK_FREQ / 1000000 * (u64) ns; /* millicycles */ 290 rem = do_div(clocks, 1000); /* /1000 = cycles */ 291 if (rem >= 1000 / 2) 292 clocks++; 293 return clocks; 294 } 295 296 static u16 pulse_clocks_to_clock_divider(u64 count) 297 { 298 do_div(count, (FIFO_RXTX << 2) | 0x3); 299 300 /* net result needs to be rounded down and decremented by 1 */ 301 if (count > RXCLK_RCD + 1) 302 count = RXCLK_RCD; 303 else if (count < 2) 304 count = 1; 305 else 306 count--; 307 return (u16) count; 308 } 309 310 /* 311 * IR Control Register helpers 312 */ 313 enum tx_fifo_watermark { 314 TX_FIFO_HALF_EMPTY = 0, 315 TX_FIFO_EMPTY = CNTRL_TIC, 316 }; 317 318 enum rx_fifo_watermark { 319 RX_FIFO_HALF_FULL = 0, 320 RX_FIFO_NOT_EMPTY = CNTRL_RIC, 321 }; 322 323 static inline void control_tx_irq_watermark(struct cx23885_dev *dev, 324 enum tx_fifo_watermark level) 325 { 326 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_TIC, level); 327 } 328 329 static inline void control_rx_irq_watermark(struct cx23885_dev *dev, 330 enum rx_fifo_watermark level) 331 { 332 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_RIC, level); 333 } 334 335 static inline void control_tx_enable(struct cx23885_dev *dev, bool enable) 336 { 337 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~(CNTRL_TXE | CNTRL_TFE), 338 enable ? (CNTRL_TXE | CNTRL_TFE) : 0); 339 } 340 341 static inline void control_rx_enable(struct cx23885_dev *dev, bool enable) 342 { 343 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~(CNTRL_RXE | CNTRL_RFE), 344 enable ? (CNTRL_RXE | CNTRL_RFE) : 0); 345 } 346 347 static inline void control_tx_modulation_enable(struct cx23885_dev *dev, 348 bool enable) 349 { 350 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_MOD, 351 enable ? CNTRL_MOD : 0); 352 } 353 354 static inline void control_rx_demodulation_enable(struct cx23885_dev *dev, 355 bool enable) 356 { 357 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_DMD, 358 enable ? CNTRL_DMD : 0); 359 } 360 361 static inline void control_rx_s_edge_detection(struct cx23885_dev *dev, 362 u32 edge_types) 363 { 364 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_EDG_BOTH, 365 edge_types & CNTRL_EDG_BOTH); 366 } 367 368 static void control_rx_s_carrier_window(struct cx23885_dev *dev, 369 unsigned int carrier, 370 unsigned int *carrier_range_low, 371 unsigned int *carrier_range_high) 372 { 373 u32 v; 374 unsigned int c16 = carrier * 16; 375 376 if (*carrier_range_low < DIV_ROUND_CLOSEST(c16, 16 + 3)) { 377 v = CNTRL_WIN_3_4; 378 *carrier_range_low = DIV_ROUND_CLOSEST(c16, 16 + 4); 379 } else { 380 v = CNTRL_WIN_3_3; 381 *carrier_range_low = DIV_ROUND_CLOSEST(c16, 16 + 3); 382 } 383 384 if (*carrier_range_high > DIV_ROUND_CLOSEST(c16, 16 - 3)) { 385 v |= CNTRL_WIN_4_3; 386 *carrier_range_high = DIV_ROUND_CLOSEST(c16, 16 - 4); 387 } else { 388 v |= CNTRL_WIN_3_3; 389 *carrier_range_high = DIV_ROUND_CLOSEST(c16, 16 - 3); 390 } 391 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_WIN, v); 392 } 393 394 static inline void control_tx_polarity_invert(struct cx23885_dev *dev, 395 bool invert) 396 { 397 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_CPL, 398 invert ? CNTRL_CPL : 0); 399 } 400 401 static inline void control_tx_level_invert(struct cx23885_dev *dev, 402 bool invert) 403 { 404 cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_IVO, 405 invert ? CNTRL_IVO : 0); 406 } 407 408 /* 409 * IR Rx & Tx Clock Register helpers 410 */ 411 static unsigned int txclk_tx_s_carrier(struct cx23885_dev *dev, 412 unsigned int freq, 413 u16 *divider) 414 { 415 *divider = carrier_freq_to_clock_divider(freq); 416 cx23888_ir_write4(dev, CX23888_IR_TXCLK_REG, *divider); 417 return clock_divider_to_carrier_freq(*divider); 418 } 419 420 static unsigned int rxclk_rx_s_carrier(struct cx23885_dev *dev, 421 unsigned int freq, 422 u16 *divider) 423 { 424 *divider = carrier_freq_to_clock_divider(freq); 425 cx23888_ir_write4(dev, CX23888_IR_RXCLK_REG, *divider); 426 return clock_divider_to_carrier_freq(*divider); 427 } 428 429 static u32 txclk_tx_s_max_pulse_width(struct cx23885_dev *dev, u32 ns, 430 u16 *divider) 431 { 432 u64 pulse_clocks; 433 434 if (ns > IR_MAX_DURATION) 435 ns = IR_MAX_DURATION; 436 pulse_clocks = ns_to_pulse_clocks(ns); 437 *divider = pulse_clocks_to_clock_divider(pulse_clocks); 438 cx23888_ir_write4(dev, CX23888_IR_TXCLK_REG, *divider); 439 return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider); 440 } 441 442 static u32 rxclk_rx_s_max_pulse_width(struct cx23885_dev *dev, u32 ns, 443 u16 *divider) 444 { 445 u64 pulse_clocks; 446 447 if (ns > IR_MAX_DURATION) 448 ns = IR_MAX_DURATION; 449 pulse_clocks = ns_to_pulse_clocks(ns); 450 *divider = pulse_clocks_to_clock_divider(pulse_clocks); 451 cx23888_ir_write4(dev, CX23888_IR_RXCLK_REG, *divider); 452 return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider); 453 } 454 455 /* 456 * IR Tx Carrier Duty Cycle register helpers 457 */ 458 static unsigned int cduty_tx_s_duty_cycle(struct cx23885_dev *dev, 459 unsigned int duty_cycle) 460 { 461 u32 n; 462 n = DIV_ROUND_CLOSEST(duty_cycle * 100, 625); /* 16ths of 100% */ 463 if (n != 0) 464 n--; 465 if (n > 15) 466 n = 15; 467 cx23888_ir_write4(dev, CX23888_IR_CDUTY_REG, n); 468 return DIV_ROUND_CLOSEST((n + 1) * 100, 16); 469 } 470 471 /* 472 * IR Filter Register helpers 473 */ 474 static u32 filter_rx_s_min_width(struct cx23885_dev *dev, u32 min_width_ns) 475 { 476 u32 count = ns_to_lpf_count(min_width_ns); 477 cx23888_ir_write4(dev, CX23888_IR_FILTR_REG, count); 478 return lpf_count_to_ns(count); 479 } 480 481 /* 482 * IR IRQ Enable Register helpers 483 */ 484 static inline void irqenable_rx(struct cx23885_dev *dev, u32 mask) 485 { 486 mask &= (IRQEN_RTE | IRQEN_ROE | IRQEN_RSE); 487 cx23888_ir_and_or4(dev, CX23888_IR_IRQEN_REG, 488 ~(IRQEN_RTE | IRQEN_ROE | IRQEN_RSE), mask); 489 } 490 491 static inline void irqenable_tx(struct cx23885_dev *dev, u32 mask) 492 { 493 mask &= IRQEN_TSE; 494 cx23888_ir_and_or4(dev, CX23888_IR_IRQEN_REG, ~IRQEN_TSE, mask); 495 } 496 497 /* 498 * V4L2 Subdevice IR Ops 499 */ 500 static int cx23888_ir_irq_handler(struct v4l2_subdev *sd, u32 status, 501 bool *handled) 502 { 503 struct cx23888_ir_state *state = to_state(sd); 504 struct cx23885_dev *dev = state->dev; 505 unsigned long flags; 506 507 u32 cntrl = cx23888_ir_read4(dev, CX23888_IR_CNTRL_REG); 508 u32 irqen = cx23888_ir_read4(dev, CX23888_IR_IRQEN_REG); 509 u32 stats = cx23888_ir_read4(dev, CX23888_IR_STATS_REG); 510 511 union cx23888_ir_fifo_rec rx_data[FIFO_RX_DEPTH]; 512 unsigned int i, j, k; 513 u32 events, v; 514 int tsr, rsr, rto, ror, tse, rse, rte, roe, kror; 515 516 tsr = stats & STATS_TSR; /* Tx FIFO Service Request */ 517 rsr = stats & STATS_RSR; /* Rx FIFO Service Request */ 518 rto = stats & STATS_RTO; /* Rx Pulse Width Timer Time Out */ 519 ror = stats & STATS_ROR; /* Rx FIFO Over Run */ 520 521 tse = irqen & IRQEN_TSE; /* Tx FIFO Service Request IRQ Enable */ 522 rse = irqen & IRQEN_RSE; /* Rx FIFO Service Request IRQ Enable */ 523 rte = irqen & IRQEN_RTE; /* Rx Pulse Width Timer Time Out IRQ Enable */ 524 roe = irqen & IRQEN_ROE; /* Rx FIFO Over Run IRQ Enable */ 525 526 *handled = false; 527 v4l2_dbg(2, ir_888_debug, sd, "IRQ Status: %s %s %s %s %s %s\n", 528 tsr ? "tsr" : " ", rsr ? "rsr" : " ", 529 rto ? "rto" : " ", ror ? "ror" : " ", 530 stats & STATS_TBY ? "tby" : " ", 531 stats & STATS_RBY ? "rby" : " "); 532 533 v4l2_dbg(2, ir_888_debug, sd, "IRQ Enables: %s %s %s %s\n", 534 tse ? "tse" : " ", rse ? "rse" : " ", 535 rte ? "rte" : " ", roe ? "roe" : " "); 536 537 /* 538 * Transmitter interrupt service 539 */ 540 if (tse && tsr) { 541 /* 542 * TODO: 543 * Check the watermark threshold setting 544 * Pull FIFO_TX_DEPTH or FIFO_TX_DEPTH/2 entries from tx_kfifo 545 * Push the data to the hardware FIFO. 546 * If there was nothing more to send in the tx_kfifo, disable 547 * the TSR IRQ and notify the v4l2_device. 548 * If there was something in the tx_kfifo, check the tx_kfifo 549 * level and notify the v4l2_device, if it is low. 550 */ 551 /* For now, inhibit TSR interrupt until Tx is implemented */ 552 irqenable_tx(dev, 0); 553 events = V4L2_SUBDEV_IR_TX_FIFO_SERVICE_REQ; 554 v4l2_subdev_notify(sd, V4L2_SUBDEV_IR_TX_NOTIFY, &events); 555 *handled = true; 556 } 557 558 /* 559 * Receiver interrupt service 560 */ 561 kror = 0; 562 if ((rse && rsr) || (rte && rto)) { 563 /* 564 * Receive data on RSR to clear the STATS_RSR. 565 * Receive data on RTO, since we may not have yet hit the RSR 566 * watermark when we receive the RTO. 567 */ 568 for (i = 0, v = FIFO_RX_NDV; 569 (v & FIFO_RX_NDV) && !kror; i = 0) { 570 for (j = 0; 571 (v & FIFO_RX_NDV) && j < FIFO_RX_DEPTH; j++) { 572 v = cx23888_ir_read4(dev, CX23888_IR_FIFO_REG); 573 rx_data[i].hw_fifo_data = v & ~FIFO_RX_NDV; 574 i++; 575 } 576 if (i == 0) 577 break; 578 j = i * sizeof(union cx23888_ir_fifo_rec); 579 k = kfifo_in_locked(&state->rx_kfifo, 580 (unsigned char *) rx_data, j, 581 &state->rx_kfifo_lock); 582 if (k != j) 583 kror++; /* rx_kfifo over run */ 584 } 585 *handled = true; 586 } 587 588 events = 0; 589 v = 0; 590 if (kror) { 591 events |= V4L2_SUBDEV_IR_RX_SW_FIFO_OVERRUN; 592 v4l2_err(sd, "IR receiver software FIFO overrun\n"); 593 } 594 if (roe && ror) { 595 /* 596 * The RX FIFO Enable (CNTRL_RFE) must be toggled to clear 597 * the Rx FIFO Over Run status (STATS_ROR) 598 */ 599 v |= CNTRL_RFE; 600 events |= V4L2_SUBDEV_IR_RX_HW_FIFO_OVERRUN; 601 v4l2_err(sd, "IR receiver hardware FIFO overrun\n"); 602 } 603 if (rte && rto) { 604 /* 605 * The IR Receiver Enable (CNTRL_RXE) must be toggled to clear 606 * the Rx Pulse Width Timer Time Out (STATS_RTO) 607 */ 608 v |= CNTRL_RXE; 609 events |= V4L2_SUBDEV_IR_RX_END_OF_RX_DETECTED; 610 } 611 if (v) { 612 /* Clear STATS_ROR & STATS_RTO as needed by resetting hardware */ 613 cx23888_ir_write4(dev, CX23888_IR_CNTRL_REG, cntrl & ~v); 614 cx23888_ir_write4(dev, CX23888_IR_CNTRL_REG, cntrl); 615 *handled = true; 616 } 617 618 spin_lock_irqsave(&state->rx_kfifo_lock, flags); 619 if (kfifo_len(&state->rx_kfifo) >= CX23888_IR_RX_KFIFO_SIZE / 2) 620 events |= V4L2_SUBDEV_IR_RX_FIFO_SERVICE_REQ; 621 spin_unlock_irqrestore(&state->rx_kfifo_lock, flags); 622 623 if (events) 624 v4l2_subdev_notify(sd, V4L2_SUBDEV_IR_RX_NOTIFY, &events); 625 return 0; 626 } 627 628 /* Receiver */ 629 static int cx23888_ir_rx_read(struct v4l2_subdev *sd, u8 *buf, size_t count, 630 ssize_t *num) 631 { 632 struct cx23888_ir_state *state = to_state(sd); 633 bool invert = (bool) atomic_read(&state->rx_invert); 634 u16 divider = (u16) atomic_read(&state->rxclk_divider); 635 636 unsigned int i, n; 637 union cx23888_ir_fifo_rec *p; 638 unsigned u, v, w; 639 640 n = count / sizeof(union cx23888_ir_fifo_rec) 641 * sizeof(union cx23888_ir_fifo_rec); 642 if (n == 0) { 643 *num = 0; 644 return 0; 645 } 646 647 n = kfifo_out_locked(&state->rx_kfifo, buf, n, &state->rx_kfifo_lock); 648 649 n /= sizeof(union cx23888_ir_fifo_rec); 650 *num = n * sizeof(union cx23888_ir_fifo_rec); 651 652 for (p = (union cx23888_ir_fifo_rec *) buf, i = 0; i < n; p++, i++) { 653 654 if ((p->hw_fifo_data & FIFO_RXTX_RTO) == FIFO_RXTX_RTO) { 655 /* Assume RTO was because of no IR light input */ 656 u = 0; 657 w = 1; 658 } else { 659 u = (p->hw_fifo_data & FIFO_RXTX_LVL) ? 1 : 0; 660 if (invert) 661 u = u ? 0 : 1; 662 w = 0; 663 } 664 665 v = (unsigned) pulse_width_count_to_ns( 666 (u16)(p->hw_fifo_data & FIFO_RXTX), divider) / 1000; 667 if (v > IR_MAX_DURATION) 668 v = IR_MAX_DURATION; 669 670 p->ir_core_data = (struct ir_raw_event) 671 { .pulse = u, .duration = v, .timeout = w }; 672 673 v4l2_dbg(2, ir_888_debug, sd, "rx read: %10u ns %s %s\n", 674 v, u ? "mark" : "space", w ? "(timed out)" : ""); 675 if (w) 676 v4l2_dbg(2, ir_888_debug, sd, "rx read: end of rx\n"); 677 } 678 return 0; 679 } 680 681 static int cx23888_ir_rx_g_parameters(struct v4l2_subdev *sd, 682 struct v4l2_subdev_ir_parameters *p) 683 { 684 struct cx23888_ir_state *state = to_state(sd); 685 mutex_lock(&state->rx_params_lock); 686 memcpy(p, &state->rx_params, sizeof(struct v4l2_subdev_ir_parameters)); 687 mutex_unlock(&state->rx_params_lock); 688 return 0; 689 } 690 691 static int cx23888_ir_rx_shutdown(struct v4l2_subdev *sd) 692 { 693 struct cx23888_ir_state *state = to_state(sd); 694 struct cx23885_dev *dev = state->dev; 695 696 mutex_lock(&state->rx_params_lock); 697 698 /* Disable or slow down all IR Rx circuits and counters */ 699 irqenable_rx(dev, 0); 700 control_rx_enable(dev, false); 701 control_rx_demodulation_enable(dev, false); 702 control_rx_s_edge_detection(dev, CNTRL_EDG_NONE); 703 filter_rx_s_min_width(dev, 0); 704 cx23888_ir_write4(dev, CX23888_IR_RXCLK_REG, RXCLK_RCD); 705 706 state->rx_params.shutdown = true; 707 708 mutex_unlock(&state->rx_params_lock); 709 return 0; 710 } 711 712 static int cx23888_ir_rx_s_parameters(struct v4l2_subdev *sd, 713 struct v4l2_subdev_ir_parameters *p) 714 { 715 struct cx23888_ir_state *state = to_state(sd); 716 struct cx23885_dev *dev = state->dev; 717 struct v4l2_subdev_ir_parameters *o = &state->rx_params; 718 u16 rxclk_divider; 719 720 if (p->shutdown) 721 return cx23888_ir_rx_shutdown(sd); 722 723 if (p->mode != V4L2_SUBDEV_IR_MODE_PULSE_WIDTH) 724 return -ENOSYS; 725 726 mutex_lock(&state->rx_params_lock); 727 728 o->shutdown = p->shutdown; 729 730 o->mode = p->mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH; 731 732 o->bytes_per_data_element = p->bytes_per_data_element 733 = sizeof(union cx23888_ir_fifo_rec); 734 735 /* Before we tweak the hardware, we have to disable the receiver */ 736 irqenable_rx(dev, 0); 737 control_rx_enable(dev, false); 738 739 control_rx_demodulation_enable(dev, p->modulation); 740 o->modulation = p->modulation; 741 742 if (p->modulation) { 743 p->carrier_freq = rxclk_rx_s_carrier(dev, p->carrier_freq, 744 &rxclk_divider); 745 746 o->carrier_freq = p->carrier_freq; 747 748 o->duty_cycle = p->duty_cycle = 50; 749 750 control_rx_s_carrier_window(dev, p->carrier_freq, 751 &p->carrier_range_lower, 752 &p->carrier_range_upper); 753 o->carrier_range_lower = p->carrier_range_lower; 754 o->carrier_range_upper = p->carrier_range_upper; 755 756 p->max_pulse_width = 757 (u32) pulse_width_count_to_ns(FIFO_RXTX, rxclk_divider); 758 } else { 759 p->max_pulse_width = 760 rxclk_rx_s_max_pulse_width(dev, p->max_pulse_width, 761 &rxclk_divider); 762 } 763 o->max_pulse_width = p->max_pulse_width; 764 atomic_set(&state->rxclk_divider, rxclk_divider); 765 766 p->noise_filter_min_width = 767 filter_rx_s_min_width(dev, p->noise_filter_min_width); 768 o->noise_filter_min_width = p->noise_filter_min_width; 769 770 p->resolution = clock_divider_to_resolution(rxclk_divider); 771 o->resolution = p->resolution; 772 773 /* FIXME - make this dependent on resolution for better performance */ 774 control_rx_irq_watermark(dev, RX_FIFO_HALF_FULL); 775 776 control_rx_s_edge_detection(dev, CNTRL_EDG_BOTH); 777 778 o->invert_level = p->invert_level; 779 atomic_set(&state->rx_invert, p->invert_level); 780 781 o->interrupt_enable = p->interrupt_enable; 782 o->enable = p->enable; 783 if (p->enable) { 784 unsigned long flags; 785 786 spin_lock_irqsave(&state->rx_kfifo_lock, flags); 787 kfifo_reset(&state->rx_kfifo); 788 /* reset tx_fifo too if there is one... */ 789 spin_unlock_irqrestore(&state->rx_kfifo_lock, flags); 790 if (p->interrupt_enable) 791 irqenable_rx(dev, IRQEN_RSE | IRQEN_RTE | IRQEN_ROE); 792 control_rx_enable(dev, p->enable); 793 } 794 795 mutex_unlock(&state->rx_params_lock); 796 return 0; 797 } 798 799 /* Transmitter */ 800 static int cx23888_ir_tx_write(struct v4l2_subdev *sd, u8 *buf, size_t count, 801 ssize_t *num) 802 { 803 struct cx23888_ir_state *state = to_state(sd); 804 struct cx23885_dev *dev = state->dev; 805 /* For now enable the Tx FIFO Service interrupt & pretend we did work */ 806 irqenable_tx(dev, IRQEN_TSE); 807 *num = count; 808 return 0; 809 } 810 811 static int cx23888_ir_tx_g_parameters(struct v4l2_subdev *sd, 812 struct v4l2_subdev_ir_parameters *p) 813 { 814 struct cx23888_ir_state *state = to_state(sd); 815 mutex_lock(&state->tx_params_lock); 816 memcpy(p, &state->tx_params, sizeof(struct v4l2_subdev_ir_parameters)); 817 mutex_unlock(&state->tx_params_lock); 818 return 0; 819 } 820 821 static int cx23888_ir_tx_shutdown(struct v4l2_subdev *sd) 822 { 823 struct cx23888_ir_state *state = to_state(sd); 824 struct cx23885_dev *dev = state->dev; 825 826 mutex_lock(&state->tx_params_lock); 827 828 /* Disable or slow down all IR Tx circuits and counters */ 829 irqenable_tx(dev, 0); 830 control_tx_enable(dev, false); 831 control_tx_modulation_enable(dev, false); 832 cx23888_ir_write4(dev, CX23888_IR_TXCLK_REG, TXCLK_TCD); 833 834 state->tx_params.shutdown = true; 835 836 mutex_unlock(&state->tx_params_lock); 837 return 0; 838 } 839 840 static int cx23888_ir_tx_s_parameters(struct v4l2_subdev *sd, 841 struct v4l2_subdev_ir_parameters *p) 842 { 843 struct cx23888_ir_state *state = to_state(sd); 844 struct cx23885_dev *dev = state->dev; 845 struct v4l2_subdev_ir_parameters *o = &state->tx_params; 846 u16 txclk_divider; 847 848 if (p->shutdown) 849 return cx23888_ir_tx_shutdown(sd); 850 851 if (p->mode != V4L2_SUBDEV_IR_MODE_PULSE_WIDTH) 852 return -ENOSYS; 853 854 mutex_lock(&state->tx_params_lock); 855 856 o->shutdown = p->shutdown; 857 858 o->mode = p->mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH; 859 860 o->bytes_per_data_element = p->bytes_per_data_element 861 = sizeof(union cx23888_ir_fifo_rec); 862 863 /* Before we tweak the hardware, we have to disable the transmitter */ 864 irqenable_tx(dev, 0); 865 control_tx_enable(dev, false); 866 867 control_tx_modulation_enable(dev, p->modulation); 868 o->modulation = p->modulation; 869 870 if (p->modulation) { 871 p->carrier_freq = txclk_tx_s_carrier(dev, p->carrier_freq, 872 &txclk_divider); 873 o->carrier_freq = p->carrier_freq; 874 875 p->duty_cycle = cduty_tx_s_duty_cycle(dev, p->duty_cycle); 876 o->duty_cycle = p->duty_cycle; 877 878 p->max_pulse_width = 879 (u32) pulse_width_count_to_ns(FIFO_RXTX, txclk_divider); 880 } else { 881 p->max_pulse_width = 882 txclk_tx_s_max_pulse_width(dev, p->max_pulse_width, 883 &txclk_divider); 884 } 885 o->max_pulse_width = p->max_pulse_width; 886 atomic_set(&state->txclk_divider, txclk_divider); 887 888 p->resolution = clock_divider_to_resolution(txclk_divider); 889 o->resolution = p->resolution; 890 891 /* FIXME - make this dependent on resolution for better performance */ 892 control_tx_irq_watermark(dev, TX_FIFO_HALF_EMPTY); 893 894 control_tx_polarity_invert(dev, p->invert_carrier_sense); 895 o->invert_carrier_sense = p->invert_carrier_sense; 896 897 control_tx_level_invert(dev, p->invert_level); 898 o->invert_level = p->invert_level; 899 900 o->interrupt_enable = p->interrupt_enable; 901 o->enable = p->enable; 902 if (p->enable) { 903 if (p->interrupt_enable) 904 irqenable_tx(dev, IRQEN_TSE); 905 control_tx_enable(dev, p->enable); 906 } 907 908 mutex_unlock(&state->tx_params_lock); 909 return 0; 910 } 911 912 913 /* 914 * V4L2 Subdevice Core Ops 915 */ 916 static int cx23888_ir_log_status(struct v4l2_subdev *sd) 917 { 918 struct cx23888_ir_state *state = to_state(sd); 919 struct cx23885_dev *dev = state->dev; 920 char *s; 921 int i, j; 922 923 u32 cntrl = cx23888_ir_read4(dev, CX23888_IR_CNTRL_REG); 924 u32 txclk = cx23888_ir_read4(dev, CX23888_IR_TXCLK_REG) & TXCLK_TCD; 925 u32 rxclk = cx23888_ir_read4(dev, CX23888_IR_RXCLK_REG) & RXCLK_RCD; 926 u32 cduty = cx23888_ir_read4(dev, CX23888_IR_CDUTY_REG) & CDUTY_CDC; 927 u32 stats = cx23888_ir_read4(dev, CX23888_IR_STATS_REG); 928 u32 irqen = cx23888_ir_read4(dev, CX23888_IR_IRQEN_REG); 929 u32 filtr = cx23888_ir_read4(dev, CX23888_IR_FILTR_REG) & FILTR_LPF; 930 931 v4l2_info(sd, "IR Receiver:\n"); 932 v4l2_info(sd, "\tEnabled: %s\n", 933 cntrl & CNTRL_RXE ? "yes" : "no"); 934 v4l2_info(sd, "\tDemodulation from a carrier: %s\n", 935 cntrl & CNTRL_DMD ? "enabled" : "disabled"); 936 v4l2_info(sd, "\tFIFO: %s\n", 937 cntrl & CNTRL_RFE ? "enabled" : "disabled"); 938 switch (cntrl & CNTRL_EDG) { 939 case CNTRL_EDG_NONE: 940 s = "disabled"; 941 break; 942 case CNTRL_EDG_FALL: 943 s = "falling edge"; 944 break; 945 case CNTRL_EDG_RISE: 946 s = "rising edge"; 947 break; 948 case CNTRL_EDG_BOTH: 949 s = "rising & falling edges"; 950 break; 951 default: 952 s = "??? edge"; 953 break; 954 } 955 v4l2_info(sd, "\tPulse timers' start/stop trigger: %s\n", s); 956 v4l2_info(sd, "\tFIFO data on pulse timer overflow: %s\n", 957 cntrl & CNTRL_R ? "not loaded" : "overflow marker"); 958 v4l2_info(sd, "\tFIFO interrupt watermark: %s\n", 959 cntrl & CNTRL_RIC ? "not empty" : "half full or greater"); 960 v4l2_info(sd, "\tLoopback mode: %s\n", 961 cntrl & CNTRL_LBM ? "loopback active" : "normal receive"); 962 if (cntrl & CNTRL_DMD) { 963 v4l2_info(sd, "\tExpected carrier (16 clocks): %u Hz\n", 964 clock_divider_to_carrier_freq(rxclk)); 965 switch (cntrl & CNTRL_WIN) { 966 case CNTRL_WIN_3_3: 967 i = 3; 968 j = 3; 969 break; 970 case CNTRL_WIN_4_3: 971 i = 4; 972 j = 3; 973 break; 974 case CNTRL_WIN_3_4: 975 i = 3; 976 j = 4; 977 break; 978 case CNTRL_WIN_4_4: 979 i = 4; 980 j = 4; 981 break; 982 default: 983 i = 0; 984 j = 0; 985 break; 986 } 987 v4l2_info(sd, "\tNext carrier edge window: 16 clocks -%1d/+%1d, %u to %u Hz\n", 988 i, j, 989 clock_divider_to_freq(rxclk, 16 + j), 990 clock_divider_to_freq(rxclk, 16 - i)); 991 } 992 v4l2_info(sd, "\tMax measurable pulse width: %u us, %llu ns\n", 993 pulse_width_count_to_us(FIFO_RXTX, rxclk), 994 pulse_width_count_to_ns(FIFO_RXTX, rxclk)); 995 v4l2_info(sd, "\tLow pass filter: %s\n", 996 filtr ? "enabled" : "disabled"); 997 if (filtr) 998 v4l2_info(sd, "\tMin acceptable pulse width (LPF): %u us, %u ns\n", 999 lpf_count_to_us(filtr), 1000 lpf_count_to_ns(filtr)); 1001 v4l2_info(sd, "\tPulse width timer timed-out: %s\n", 1002 stats & STATS_RTO ? "yes" : "no"); 1003 v4l2_info(sd, "\tPulse width timer time-out intr: %s\n", 1004 irqen & IRQEN_RTE ? "enabled" : "disabled"); 1005 v4l2_info(sd, "\tFIFO overrun: %s\n", 1006 stats & STATS_ROR ? "yes" : "no"); 1007 v4l2_info(sd, "\tFIFO overrun interrupt: %s\n", 1008 irqen & IRQEN_ROE ? "enabled" : "disabled"); 1009 v4l2_info(sd, "\tBusy: %s\n", 1010 stats & STATS_RBY ? "yes" : "no"); 1011 v4l2_info(sd, "\tFIFO service requested: %s\n", 1012 stats & STATS_RSR ? "yes" : "no"); 1013 v4l2_info(sd, "\tFIFO service request interrupt: %s\n", 1014 irqen & IRQEN_RSE ? "enabled" : "disabled"); 1015 1016 v4l2_info(sd, "IR Transmitter:\n"); 1017 v4l2_info(sd, "\tEnabled: %s\n", 1018 cntrl & CNTRL_TXE ? "yes" : "no"); 1019 v4l2_info(sd, "\tModulation onto a carrier: %s\n", 1020 cntrl & CNTRL_MOD ? "enabled" : "disabled"); 1021 v4l2_info(sd, "\tFIFO: %s\n", 1022 cntrl & CNTRL_TFE ? "enabled" : "disabled"); 1023 v4l2_info(sd, "\tFIFO interrupt watermark: %s\n", 1024 cntrl & CNTRL_TIC ? "not empty" : "half full or less"); 1025 v4l2_info(sd, "\tOutput pin level inversion %s\n", 1026 cntrl & CNTRL_IVO ? "yes" : "no"); 1027 v4l2_info(sd, "\tCarrier polarity: %s\n", 1028 cntrl & CNTRL_CPL ? "space:burst mark:noburst" 1029 : "space:noburst mark:burst"); 1030 if (cntrl & CNTRL_MOD) { 1031 v4l2_info(sd, "\tCarrier (16 clocks): %u Hz\n", 1032 clock_divider_to_carrier_freq(txclk)); 1033 v4l2_info(sd, "\tCarrier duty cycle: %2u/16\n", 1034 cduty + 1); 1035 } 1036 v4l2_info(sd, "\tMax pulse width: %u us, %llu ns\n", 1037 pulse_width_count_to_us(FIFO_RXTX, txclk), 1038 pulse_width_count_to_ns(FIFO_RXTX, txclk)); 1039 v4l2_info(sd, "\tBusy: %s\n", 1040 stats & STATS_TBY ? "yes" : "no"); 1041 v4l2_info(sd, "\tFIFO service requested: %s\n", 1042 stats & STATS_TSR ? "yes" : "no"); 1043 v4l2_info(sd, "\tFIFO service request interrupt: %s\n", 1044 irqen & IRQEN_TSE ? "enabled" : "disabled"); 1045 1046 return 0; 1047 } 1048 1049 #ifdef CONFIG_VIDEO_ADV_DEBUG 1050 static int cx23888_ir_g_register(struct v4l2_subdev *sd, 1051 struct v4l2_dbg_register *reg) 1052 { 1053 struct cx23888_ir_state *state = to_state(sd); 1054 u32 addr = CX23888_IR_REG_BASE + (u32) reg->reg; 1055 1056 if ((addr & 0x3) != 0) 1057 return -EINVAL; 1058 if (addr < CX23888_IR_CNTRL_REG || addr > CX23888_IR_LEARN_REG) 1059 return -EINVAL; 1060 reg->size = 4; 1061 reg->val = cx23888_ir_read4(state->dev, addr); 1062 return 0; 1063 } 1064 1065 static int cx23888_ir_s_register(struct v4l2_subdev *sd, 1066 const struct v4l2_dbg_register *reg) 1067 { 1068 struct cx23888_ir_state *state = to_state(sd); 1069 u32 addr = CX23888_IR_REG_BASE + (u32) reg->reg; 1070 1071 if ((addr & 0x3) != 0) 1072 return -EINVAL; 1073 if (addr < CX23888_IR_CNTRL_REG || addr > CX23888_IR_LEARN_REG) 1074 return -EINVAL; 1075 cx23888_ir_write4(state->dev, addr, reg->val); 1076 return 0; 1077 } 1078 #endif 1079 1080 static const struct v4l2_subdev_core_ops cx23888_ir_core_ops = { 1081 .log_status = cx23888_ir_log_status, 1082 #ifdef CONFIG_VIDEO_ADV_DEBUG 1083 .g_register = cx23888_ir_g_register, 1084 .s_register = cx23888_ir_s_register, 1085 #endif 1086 .interrupt_service_routine = cx23888_ir_irq_handler, 1087 }; 1088 1089 static const struct v4l2_subdev_ir_ops cx23888_ir_ir_ops = { 1090 .rx_read = cx23888_ir_rx_read, 1091 .rx_g_parameters = cx23888_ir_rx_g_parameters, 1092 .rx_s_parameters = cx23888_ir_rx_s_parameters, 1093 1094 .tx_write = cx23888_ir_tx_write, 1095 .tx_g_parameters = cx23888_ir_tx_g_parameters, 1096 .tx_s_parameters = cx23888_ir_tx_s_parameters, 1097 }; 1098 1099 static const struct v4l2_subdev_ops cx23888_ir_controller_ops = { 1100 .core = &cx23888_ir_core_ops, 1101 .ir = &cx23888_ir_ir_ops, 1102 }; 1103 1104 static const struct v4l2_subdev_ir_parameters default_rx_params = { 1105 .bytes_per_data_element = sizeof(union cx23888_ir_fifo_rec), 1106 .mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH, 1107 1108 .enable = false, 1109 .interrupt_enable = false, 1110 .shutdown = true, 1111 1112 .modulation = true, 1113 .carrier_freq = 36000, /* 36 kHz - RC-5, RC-6, and RC-6A carrier */ 1114 1115 /* RC-5: 666,667 ns = 1/36 kHz * 32 cycles * 1 mark * 0.75 */ 1116 /* RC-6A: 333,333 ns = 1/36 kHz * 16 cycles * 1 mark * 0.75 */ 1117 .noise_filter_min_width = 333333, /* ns */ 1118 .carrier_range_lower = 35000, 1119 .carrier_range_upper = 37000, 1120 .invert_level = false, 1121 }; 1122 1123 static const struct v4l2_subdev_ir_parameters default_tx_params = { 1124 .bytes_per_data_element = sizeof(union cx23888_ir_fifo_rec), 1125 .mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH, 1126 1127 .enable = false, 1128 .interrupt_enable = false, 1129 .shutdown = true, 1130 1131 .modulation = true, 1132 .carrier_freq = 36000, /* 36 kHz - RC-5 carrier */ 1133 .duty_cycle = 25, /* 25 % - RC-5 carrier */ 1134 .invert_level = false, 1135 .invert_carrier_sense = false, 1136 }; 1137 1138 int cx23888_ir_probe(struct cx23885_dev *dev) 1139 { 1140 struct cx23888_ir_state *state; 1141 struct v4l2_subdev *sd; 1142 struct v4l2_subdev_ir_parameters default_params; 1143 int ret; 1144 1145 state = kzalloc(sizeof(struct cx23888_ir_state), GFP_KERNEL); 1146 if (state == NULL) 1147 return -ENOMEM; 1148 1149 spin_lock_init(&state->rx_kfifo_lock); 1150 if (kfifo_alloc(&state->rx_kfifo, CX23888_IR_RX_KFIFO_SIZE, 1151 GFP_KERNEL)) { 1152 kfree(state); 1153 return -ENOMEM; 1154 } 1155 1156 state->dev = dev; 1157 sd = &state->sd; 1158 1159 v4l2_subdev_init(sd, &cx23888_ir_controller_ops); 1160 v4l2_set_subdevdata(sd, state); 1161 /* FIXME - fix the formatting of dev->v4l2_dev.name and use it */ 1162 snprintf(sd->name, sizeof(sd->name), "%s/888-ir", dev->name); 1163 sd->grp_id = CX23885_HW_888_IR; 1164 1165 ret = v4l2_device_register_subdev(&dev->v4l2_dev, sd); 1166 if (ret == 0) { 1167 /* 1168 * Ensure no interrupts arrive from '888 specific conditions, 1169 * since we ignore them in this driver to have commonality with 1170 * similar IR controller cores. 1171 */ 1172 cx23888_ir_write4(dev, CX23888_IR_IRQEN_REG, 0); 1173 1174 mutex_init(&state->rx_params_lock); 1175 default_params = default_rx_params; 1176 v4l2_subdev_call(sd, ir, rx_s_parameters, &default_params); 1177 1178 mutex_init(&state->tx_params_lock); 1179 default_params = default_tx_params; 1180 v4l2_subdev_call(sd, ir, tx_s_parameters, &default_params); 1181 } else { 1182 kfifo_free(&state->rx_kfifo); 1183 } 1184 return ret; 1185 } 1186 1187 int cx23888_ir_remove(struct cx23885_dev *dev) 1188 { 1189 struct v4l2_subdev *sd; 1190 struct cx23888_ir_state *state; 1191 1192 sd = cx23885_find_hw(dev, CX23885_HW_888_IR); 1193 if (sd == NULL) 1194 return -ENODEV; 1195 1196 cx23888_ir_rx_shutdown(sd); 1197 cx23888_ir_tx_shutdown(sd); 1198 1199 state = to_state(sd); 1200 v4l2_device_unregister_subdev(sd); 1201 kfifo_free(&state->rx_kfifo); 1202 kfree(state); 1203 /* Nothing more to free() as state held the actual v4l2_subdev object */ 1204 return 0; 1205 } 1206