1 /* 2 * Driver for the Conexant CX23885 PCIe bridge 3 * 4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 */ 21 22 #include <linux/module.h> 23 #include <linux/init.h> 24 #include <linux/device.h> 25 #include <linux/fs.h> 26 #include <linux/kthread.h> 27 #include <linux/file.h> 28 #include <linux/suspend.h> 29 30 #include "cx23885.h" 31 #include <media/v4l2-common.h> 32 33 #include "dvb_ca_en50221.h" 34 #include "s5h1409.h" 35 #include "s5h1411.h" 36 #include "mt2131.h" 37 #include "tda8290.h" 38 #include "tda18271.h" 39 #include "lgdt330x.h" 40 #include "xc4000.h" 41 #include "xc5000.h" 42 #include "max2165.h" 43 #include "tda10048.h" 44 #include "tuner-xc2028.h" 45 #include "tuner-simple.h" 46 #include "dib7000p.h" 47 #include "dib0070.h" 48 #include "dibx000_common.h" 49 #include "zl10353.h" 50 #include "stv0900.h" 51 #include "stv0900_reg.h" 52 #include "stv6110.h" 53 #include "lnbh24.h" 54 #include "cx24116.h" 55 #include "cx24117.h" 56 #include "cimax2.h" 57 #include "lgs8gxx.h" 58 #include "netup-eeprom.h" 59 #include "netup-init.h" 60 #include "lgdt3305.h" 61 #include "atbm8830.h" 62 #include "ts2020.h" 63 #include "ds3000.h" 64 #include "cx23885-f300.h" 65 #include "altera-ci.h" 66 #include "stv0367.h" 67 #include "drxk.h" 68 #include "mt2063.h" 69 #include "stv090x.h" 70 #include "stb6100.h" 71 #include "stb6100_cfg.h" 72 #include "tda10071.h" 73 #include "a8293.h" 74 #include "mb86a20s.h" 75 #include "si2165.h" 76 77 static unsigned int debug; 78 79 #define dprintk(level, fmt, arg...)\ 80 do { if (debug >= level)\ 81 printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\ 82 } while (0) 83 84 /* ------------------------------------------------------------------ */ 85 86 static unsigned int alt_tuner; 87 module_param(alt_tuner, int, 0644); 88 MODULE_PARM_DESC(alt_tuner, "Enable alternate tuner configuration"); 89 90 DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); 91 92 /* ------------------------------------------------------------------ */ 93 94 static int dvb_buf_setup(struct videobuf_queue *q, 95 unsigned int *count, unsigned int *size) 96 { 97 struct cx23885_tsport *port = q->priv_data; 98 99 port->ts_packet_size = 188 * 4; 100 port->ts_packet_count = 32; 101 102 *size = port->ts_packet_size * port->ts_packet_count; 103 *count = 32; 104 return 0; 105 } 106 107 static int dvb_buf_prepare(struct videobuf_queue *q, 108 struct videobuf_buffer *vb, enum v4l2_field field) 109 { 110 struct cx23885_tsport *port = q->priv_data; 111 return cx23885_buf_prepare(q, port, (struct cx23885_buffer *)vb, field); 112 } 113 114 static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb) 115 { 116 struct cx23885_tsport *port = q->priv_data; 117 cx23885_buf_queue(port, (struct cx23885_buffer *)vb); 118 } 119 120 static void dvb_buf_release(struct videobuf_queue *q, 121 struct videobuf_buffer *vb) 122 { 123 cx23885_free_buffer(q, (struct cx23885_buffer *)vb); 124 } 125 126 static void cx23885_dvb_gate_ctrl(struct cx23885_tsport *port, int open) 127 { 128 struct videobuf_dvb_frontends *f; 129 struct videobuf_dvb_frontend *fe; 130 131 f = &port->frontends; 132 133 if (f->gate <= 1) /* undefined or fe0 */ 134 fe = videobuf_dvb_get_frontend(f, 1); 135 else 136 fe = videobuf_dvb_get_frontend(f, f->gate); 137 138 if (fe && fe->dvb.frontend && fe->dvb.frontend->ops.i2c_gate_ctrl) 139 fe->dvb.frontend->ops.i2c_gate_ctrl(fe->dvb.frontend, open); 140 } 141 142 static struct videobuf_queue_ops dvb_qops = { 143 .buf_setup = dvb_buf_setup, 144 .buf_prepare = dvb_buf_prepare, 145 .buf_queue = dvb_buf_queue, 146 .buf_release = dvb_buf_release, 147 }; 148 149 static struct s5h1409_config hauppauge_generic_config = { 150 .demod_address = 0x32 >> 1, 151 .output_mode = S5H1409_SERIAL_OUTPUT, 152 .gpio = S5H1409_GPIO_ON, 153 .qam_if = 44000, 154 .inversion = S5H1409_INVERSION_OFF, 155 .status_mode = S5H1409_DEMODLOCKING, 156 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, 157 }; 158 159 static struct tda10048_config hauppauge_hvr1200_config = { 160 .demod_address = 0x10 >> 1, 161 .output_mode = TDA10048_SERIAL_OUTPUT, 162 .fwbulkwritelen = TDA10048_BULKWRITE_200, 163 .inversion = TDA10048_INVERSION_ON, 164 .dtv6_if_freq_khz = TDA10048_IF_3300, 165 .dtv7_if_freq_khz = TDA10048_IF_3800, 166 .dtv8_if_freq_khz = TDA10048_IF_4300, 167 .clk_freq_khz = TDA10048_CLK_16000, 168 }; 169 170 static struct tda10048_config hauppauge_hvr1210_config = { 171 .demod_address = 0x10 >> 1, 172 .output_mode = TDA10048_SERIAL_OUTPUT, 173 .fwbulkwritelen = TDA10048_BULKWRITE_200, 174 .inversion = TDA10048_INVERSION_ON, 175 .dtv6_if_freq_khz = TDA10048_IF_3300, 176 .dtv7_if_freq_khz = TDA10048_IF_3500, 177 .dtv8_if_freq_khz = TDA10048_IF_4000, 178 .clk_freq_khz = TDA10048_CLK_16000, 179 }; 180 181 static struct s5h1409_config hauppauge_ezqam_config = { 182 .demod_address = 0x32 >> 1, 183 .output_mode = S5H1409_SERIAL_OUTPUT, 184 .gpio = S5H1409_GPIO_OFF, 185 .qam_if = 4000, 186 .inversion = S5H1409_INVERSION_ON, 187 .status_mode = S5H1409_DEMODLOCKING, 188 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, 189 }; 190 191 static struct s5h1409_config hauppauge_hvr1800lp_config = { 192 .demod_address = 0x32 >> 1, 193 .output_mode = S5H1409_SERIAL_OUTPUT, 194 .gpio = S5H1409_GPIO_OFF, 195 .qam_if = 44000, 196 .inversion = S5H1409_INVERSION_OFF, 197 .status_mode = S5H1409_DEMODLOCKING, 198 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, 199 }; 200 201 static struct s5h1409_config hauppauge_hvr1500_config = { 202 .demod_address = 0x32 >> 1, 203 .output_mode = S5H1409_SERIAL_OUTPUT, 204 .gpio = S5H1409_GPIO_OFF, 205 .inversion = S5H1409_INVERSION_OFF, 206 .status_mode = S5H1409_DEMODLOCKING, 207 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, 208 }; 209 210 static struct mt2131_config hauppauge_generic_tunerconfig = { 211 0x61 212 }; 213 214 static struct lgdt330x_config fusionhdtv_5_express = { 215 .demod_address = 0x0e, 216 .demod_chip = LGDT3303, 217 .serial_mpeg = 0x40, 218 }; 219 220 static struct s5h1409_config hauppauge_hvr1500q_config = { 221 .demod_address = 0x32 >> 1, 222 .output_mode = S5H1409_SERIAL_OUTPUT, 223 .gpio = S5H1409_GPIO_ON, 224 .qam_if = 44000, 225 .inversion = S5H1409_INVERSION_OFF, 226 .status_mode = S5H1409_DEMODLOCKING, 227 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, 228 }; 229 230 static struct s5h1409_config dvico_s5h1409_config = { 231 .demod_address = 0x32 >> 1, 232 .output_mode = S5H1409_SERIAL_OUTPUT, 233 .gpio = S5H1409_GPIO_ON, 234 .qam_if = 44000, 235 .inversion = S5H1409_INVERSION_OFF, 236 .status_mode = S5H1409_DEMODLOCKING, 237 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, 238 }; 239 240 static struct s5h1411_config dvico_s5h1411_config = { 241 .output_mode = S5H1411_SERIAL_OUTPUT, 242 .gpio = S5H1411_GPIO_ON, 243 .qam_if = S5H1411_IF_44000, 244 .vsb_if = S5H1411_IF_44000, 245 .inversion = S5H1411_INVERSION_OFF, 246 .status_mode = S5H1411_DEMODLOCKING, 247 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, 248 }; 249 250 static struct s5h1411_config hcw_s5h1411_config = { 251 .output_mode = S5H1411_SERIAL_OUTPUT, 252 .gpio = S5H1411_GPIO_OFF, 253 .vsb_if = S5H1411_IF_44000, 254 .qam_if = S5H1411_IF_4000, 255 .inversion = S5H1411_INVERSION_ON, 256 .status_mode = S5H1411_DEMODLOCKING, 257 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, 258 }; 259 260 static struct xc5000_config hauppauge_hvr1500q_tunerconfig = { 261 .i2c_address = 0x61, 262 .if_khz = 5380, 263 }; 264 265 static struct xc5000_config dvico_xc5000_tunerconfig = { 266 .i2c_address = 0x64, 267 .if_khz = 5380, 268 }; 269 270 static struct tda829x_config tda829x_no_probe = { 271 .probe_tuner = TDA829X_DONT_PROBE, 272 }; 273 274 static struct tda18271_std_map hauppauge_tda18271_std_map = { 275 .atsc_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3, 276 .if_lvl = 6, .rfagc_top = 0x37 }, 277 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 0, 278 .if_lvl = 6, .rfagc_top = 0x37 }, 279 }; 280 281 static struct tda18271_std_map hauppauge_hvr1200_tda18271_std_map = { 282 .dvbt_6 = { .if_freq = 3300, .agc_mode = 3, .std = 4, 283 .if_lvl = 1, .rfagc_top = 0x37, }, 284 .dvbt_7 = { .if_freq = 3800, .agc_mode = 3, .std = 5, 285 .if_lvl = 1, .rfagc_top = 0x37, }, 286 .dvbt_8 = { .if_freq = 4300, .agc_mode = 3, .std = 6, 287 .if_lvl = 1, .rfagc_top = 0x37, }, 288 }; 289 290 static struct tda18271_config hauppauge_tda18271_config = { 291 .std_map = &hauppauge_tda18271_std_map, 292 .gate = TDA18271_GATE_ANALOG, 293 .output_opt = TDA18271_OUTPUT_LT_OFF, 294 }; 295 296 static struct tda18271_config hauppauge_hvr1200_tuner_config = { 297 .std_map = &hauppauge_hvr1200_tda18271_std_map, 298 .gate = TDA18271_GATE_ANALOG, 299 .output_opt = TDA18271_OUTPUT_LT_OFF, 300 }; 301 302 static struct tda18271_config hauppauge_hvr1210_tuner_config = { 303 .gate = TDA18271_GATE_DIGITAL, 304 .output_opt = TDA18271_OUTPUT_LT_OFF, 305 }; 306 307 static struct tda18271_config hauppauge_hvr4400_tuner_config = { 308 .gate = TDA18271_GATE_DIGITAL, 309 .output_opt = TDA18271_OUTPUT_LT_OFF, 310 }; 311 312 static struct tda18271_std_map hauppauge_hvr127x_std_map = { 313 .atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 4, 314 .if_lvl = 1, .rfagc_top = 0x58 }, 315 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 5, 316 .if_lvl = 1, .rfagc_top = 0x58 }, 317 }; 318 319 static struct tda18271_config hauppauge_hvr127x_config = { 320 .std_map = &hauppauge_hvr127x_std_map, 321 .output_opt = TDA18271_OUTPUT_LT_OFF, 322 }; 323 324 static struct lgdt3305_config hauppauge_lgdt3305_config = { 325 .i2c_addr = 0x0e, 326 .mpeg_mode = LGDT3305_MPEG_SERIAL, 327 .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE, 328 .tpvalid_polarity = LGDT3305_TP_VALID_HIGH, 329 .deny_i2c_rptr = 1, 330 .spectral_inversion = 1, 331 .qam_if_khz = 4000, 332 .vsb_if_khz = 3250, 333 }; 334 335 static struct dibx000_agc_config xc3028_agc_config = { 336 BAND_VHF | BAND_UHF, /* band_caps */ 337 338 /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0, 339 * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0, 340 * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, 341 * P_agc_nb_est=2, P_agc_write=0 342 */ 343 (0 << 15) | (0 << 14) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) | 344 (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), /* setup */ 345 346 712, /* inv_gain */ 347 21, /* time_stabiliz */ 348 349 0, /* alpha_level */ 350 118, /* thlock */ 351 352 0, /* wbd_inv */ 353 2867, /* wbd_ref */ 354 0, /* wbd_sel */ 355 2, /* wbd_alpha */ 356 357 0, /* agc1_max */ 358 0, /* agc1_min */ 359 39718, /* agc2_max */ 360 9930, /* agc2_min */ 361 0, /* agc1_pt1 */ 362 0, /* agc1_pt2 */ 363 0, /* agc1_pt3 */ 364 0, /* agc1_slope1 */ 365 0, /* agc1_slope2 */ 366 0, /* agc2_pt1 */ 367 128, /* agc2_pt2 */ 368 29, /* agc2_slope1 */ 369 29, /* agc2_slope2 */ 370 371 17, /* alpha_mant */ 372 27, /* alpha_exp */ 373 23, /* beta_mant */ 374 51, /* beta_exp */ 375 376 1, /* perform_agc_softsplit */ 377 }; 378 379 /* PLL Configuration for COFDM BW_MHz = 8.000000 380 * With external clock = 30.000000 */ 381 static struct dibx000_bandwidth_config xc3028_bw_config = { 382 60000, /* internal */ 383 30000, /* sampling */ 384 1, /* pll_cfg: prediv */ 385 8, /* pll_cfg: ratio */ 386 3, /* pll_cfg: range */ 387 1, /* pll_cfg: reset */ 388 0, /* pll_cfg: bypass */ 389 0, /* misc: refdiv */ 390 0, /* misc: bypclk_div */ 391 1, /* misc: IO_CLK_en_core */ 392 1, /* misc: ADClkSrc */ 393 0, /* misc: modulo */ 394 (3 << 14) | (1 << 12) | (524 << 0), /* sad_cfg: refsel, sel, freq_15k */ 395 (1 << 25) | 5816102, /* ifreq = 5.200000 MHz */ 396 20452225, /* timf */ 397 30000000 /* xtal_hz */ 398 }; 399 400 static struct dib7000p_config hauppauge_hvr1400_dib7000_config = { 401 .output_mpeg2_in_188_bytes = 1, 402 .hostbus_diversity = 1, 403 .tuner_is_baseband = 0, 404 .update_lna = NULL, 405 406 .agc_config_count = 1, 407 .agc = &xc3028_agc_config, 408 .bw = &xc3028_bw_config, 409 410 .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS, 411 .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES, 412 .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS, 413 414 .pwm_freq_div = 0, 415 .agc_control = NULL, 416 .spur_protect = 0, 417 418 .output_mode = OUTMODE_MPEG2_SERIAL, 419 }; 420 421 static struct zl10353_config dvico_fusionhdtv_xc3028 = { 422 .demod_address = 0x0f, 423 .if2 = 45600, 424 .no_tuner = 1, 425 .disable_i2c_gate_ctrl = 1, 426 }; 427 428 static struct stv0900_reg stv0900_ts_regs[] = { 429 { R0900_TSGENERAL, 0x00 }, 430 { R0900_P1_TSSPEED, 0x40 }, 431 { R0900_P2_TSSPEED, 0x40 }, 432 { R0900_P1_TSCFGM, 0xc0 }, 433 { R0900_P2_TSCFGM, 0xc0 }, 434 { R0900_P1_TSCFGH, 0xe0 }, 435 { R0900_P2_TSCFGH, 0xe0 }, 436 { R0900_P1_TSCFGL, 0x20 }, 437 { R0900_P2_TSCFGL, 0x20 }, 438 { 0xffff, 0xff }, /* terminate */ 439 }; 440 441 static struct stv0900_config netup_stv0900_config = { 442 .demod_address = 0x68, 443 .demod_mode = 1, /* dual */ 444 .xtal = 8000000, 445 .clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */ 446 .diseqc_mode = 2,/* 2/3 PWM */ 447 .ts_config_regs = stv0900_ts_regs, 448 .tun1_maddress = 0,/* 0x60 */ 449 .tun2_maddress = 3,/* 0x63 */ 450 .tun1_adc = 1,/* 1 Vpp */ 451 .tun2_adc = 1,/* 1 Vpp */ 452 }; 453 454 static struct stv6110_config netup_stv6110_tunerconfig_a = { 455 .i2c_address = 0x60, 456 .mclk = 16000000, 457 .clk_div = 1, 458 .gain = 8, /* +16 dB - maximum gain */ 459 }; 460 461 static struct stv6110_config netup_stv6110_tunerconfig_b = { 462 .i2c_address = 0x63, 463 .mclk = 16000000, 464 .clk_div = 1, 465 .gain = 8, /* +16 dB - maximum gain */ 466 }; 467 468 static struct cx24116_config tbs_cx24116_config = { 469 .demod_address = 0x55, 470 }; 471 472 static struct cx24117_config tbs_cx24117_config = { 473 .demod_address = 0x55, 474 }; 475 476 static struct ds3000_config tevii_ds3000_config = { 477 .demod_address = 0x68, 478 }; 479 480 static struct ts2020_config tevii_ts2020_config = { 481 .tuner_address = 0x60, 482 .clk_out_div = 1, 483 .frequency_div = 1146000, 484 }; 485 486 static struct cx24116_config dvbworld_cx24116_config = { 487 .demod_address = 0x05, 488 }; 489 490 static struct lgs8gxx_config mygica_x8506_lgs8gl5_config = { 491 .prod = LGS8GXX_PROD_LGS8GL5, 492 .demod_address = 0x19, 493 .serial_ts = 0, 494 .ts_clk_pol = 1, 495 .ts_clk_gated = 1, 496 .if_clk_freq = 30400, /* 30.4 MHz */ 497 .if_freq = 5380, /* 5.38 MHz */ 498 .if_neg_center = 1, 499 .ext_adc = 0, 500 .adc_signed = 0, 501 .if_neg_edge = 0, 502 }; 503 504 static struct xc5000_config mygica_x8506_xc5000_config = { 505 .i2c_address = 0x61, 506 .if_khz = 5380, 507 }; 508 509 static struct mb86a20s_config mygica_x8507_mb86a20s_config = { 510 .demod_address = 0x10, 511 }; 512 513 static struct xc5000_config mygica_x8507_xc5000_config = { 514 .i2c_address = 0x61, 515 .if_khz = 4000, 516 }; 517 518 static struct stv090x_config prof_8000_stv090x_config = { 519 .device = STV0903, 520 .demod_mode = STV090x_SINGLE, 521 .clk_mode = STV090x_CLK_EXT, 522 .xtal = 27000000, 523 .address = 0x6A, 524 .ts1_mode = STV090x_TSMODE_PARALLEL_PUNCTURED, 525 .repeater_level = STV090x_RPTLEVEL_64, 526 .adc1_range = STV090x_ADC_2Vpp, 527 .diseqc_envelope_mode = false, 528 529 .tuner_get_frequency = stb6100_get_frequency, 530 .tuner_set_frequency = stb6100_set_frequency, 531 .tuner_set_bandwidth = stb6100_set_bandwidth, 532 .tuner_get_bandwidth = stb6100_get_bandwidth, 533 }; 534 535 static struct stb6100_config prof_8000_stb6100_config = { 536 .tuner_address = 0x60, 537 .refclock = 27000000, 538 }; 539 540 static int p8000_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage) 541 { 542 struct cx23885_tsport *port = fe->dvb->priv; 543 struct cx23885_dev *dev = port->dev; 544 545 if (voltage == SEC_VOLTAGE_18) 546 cx_write(MC417_RWD, 0x00001e00); 547 else if (voltage == SEC_VOLTAGE_13) 548 cx_write(MC417_RWD, 0x00001a00); 549 else 550 cx_write(MC417_RWD, 0x00001800); 551 return 0; 552 } 553 554 static int cx23885_dvb_set_frontend(struct dvb_frontend *fe) 555 { 556 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 557 struct cx23885_tsport *port = fe->dvb->priv; 558 struct cx23885_dev *dev = port->dev; 559 560 switch (dev->board) { 561 case CX23885_BOARD_HAUPPAUGE_HVR1275: 562 switch (p->modulation) { 563 case VSB_8: 564 cx23885_gpio_clear(dev, GPIO_5); 565 break; 566 case QAM_64: 567 case QAM_256: 568 default: 569 cx23885_gpio_set(dev, GPIO_5); 570 break; 571 } 572 break; 573 case CX23885_BOARD_MYGICA_X8506: 574 case CX23885_BOARD_MYGICA_X8507: 575 case CX23885_BOARD_MAGICPRO_PROHDTVE2: 576 /* Select Digital TV */ 577 cx23885_gpio_set(dev, GPIO_0); 578 break; 579 } 580 581 /* Call the real set_frontend */ 582 if (port->set_frontend) 583 return port->set_frontend(fe); 584 585 return 0; 586 } 587 588 static void cx23885_set_frontend_hook(struct cx23885_tsport *port, 589 struct dvb_frontend *fe) 590 { 591 port->set_frontend = fe->ops.set_frontend; 592 fe->ops.set_frontend = cx23885_dvb_set_frontend; 593 } 594 595 static struct lgs8gxx_config magicpro_prohdtve2_lgs8g75_config = { 596 .prod = LGS8GXX_PROD_LGS8G75, 597 .demod_address = 0x19, 598 .serial_ts = 0, 599 .ts_clk_pol = 1, 600 .ts_clk_gated = 1, 601 .if_clk_freq = 30400, /* 30.4 MHz */ 602 .if_freq = 6500, /* 6.50 MHz */ 603 .if_neg_center = 1, 604 .ext_adc = 0, 605 .adc_signed = 1, 606 .adc_vpp = 2, /* 1.6 Vpp */ 607 .if_neg_edge = 1, 608 }; 609 610 static struct xc5000_config magicpro_prohdtve2_xc5000_config = { 611 .i2c_address = 0x61, 612 .if_khz = 6500, 613 }; 614 615 static struct atbm8830_config mygica_x8558pro_atbm8830_cfg1 = { 616 .prod = ATBM8830_PROD_8830, 617 .demod_address = 0x44, 618 .serial_ts = 0, 619 .ts_sampling_edge = 1, 620 .ts_clk_gated = 0, 621 .osc_clk_freq = 30400, /* in kHz */ 622 .if_freq = 0, /* zero IF */ 623 .zif_swap_iq = 1, 624 .agc_min = 0x2E, 625 .agc_max = 0xFF, 626 .agc_hold_loop = 0, 627 }; 628 629 static struct max2165_config mygic_x8558pro_max2165_cfg1 = { 630 .i2c_address = 0x60, 631 .osc_clk = 20 632 }; 633 634 static struct atbm8830_config mygica_x8558pro_atbm8830_cfg2 = { 635 .prod = ATBM8830_PROD_8830, 636 .demod_address = 0x44, 637 .serial_ts = 1, 638 .ts_sampling_edge = 1, 639 .ts_clk_gated = 0, 640 .osc_clk_freq = 30400, /* in kHz */ 641 .if_freq = 0, /* zero IF */ 642 .zif_swap_iq = 1, 643 .agc_min = 0x2E, 644 .agc_max = 0xFF, 645 .agc_hold_loop = 0, 646 }; 647 648 static struct max2165_config mygic_x8558pro_max2165_cfg2 = { 649 .i2c_address = 0x60, 650 .osc_clk = 20 651 }; 652 static struct stv0367_config netup_stv0367_config[] = { 653 { 654 .demod_address = 0x1c, 655 .xtal = 27000000, 656 .if_khz = 4500, 657 .if_iq_mode = 0, 658 .ts_mode = 1, 659 .clk_pol = 0, 660 }, { 661 .demod_address = 0x1d, 662 .xtal = 27000000, 663 .if_khz = 4500, 664 .if_iq_mode = 0, 665 .ts_mode = 1, 666 .clk_pol = 0, 667 }, 668 }; 669 670 static struct xc5000_config netup_xc5000_config[] = { 671 { 672 .i2c_address = 0x61, 673 .if_khz = 4500, 674 }, { 675 .i2c_address = 0x64, 676 .if_khz = 4500, 677 }, 678 }; 679 680 static struct drxk_config terratec_drxk_config[] = { 681 { 682 .adr = 0x29, 683 .no_i2c_bridge = 1, 684 }, { 685 .adr = 0x2a, 686 .no_i2c_bridge = 1, 687 }, 688 }; 689 690 static struct mt2063_config terratec_mt2063_config[] = { 691 { 692 .tuner_address = 0x60, 693 }, { 694 .tuner_address = 0x67, 695 }, 696 }; 697 698 static const struct tda10071_config hauppauge_tda10071_config = { 699 .demod_i2c_addr = 0x05, 700 .tuner_i2c_addr = 0x54, 701 .i2c_wr_max = 64, 702 .ts_mode = TDA10071_TS_SERIAL, 703 .spec_inv = 0, 704 .xtal = 40444000, /* 40.444 MHz */ 705 .pll_multiplier = 20, 706 }; 707 708 static const struct a8293_config hauppauge_a8293_config = { 709 .i2c_addr = 0x0b, 710 }; 711 712 static const struct si2165_config hauppauge_hvr4400_si2165_config = { 713 .i2c_addr = 0x64, 714 .chip_mode = SI2165_MODE_PLL_XTAL, 715 .ref_freq_Hz = 16000000, 716 }; 717 718 static int netup_altera_fpga_rw(void *device, int flag, int data, int read) 719 { 720 struct cx23885_dev *dev = (struct cx23885_dev *)device; 721 unsigned long timeout = jiffies + msecs_to_jiffies(1); 722 uint32_t mem = 0; 723 724 mem = cx_read(MC417_RWD); 725 if (read) 726 cx_set(MC417_OEN, ALT_DATA); 727 else { 728 cx_clear(MC417_OEN, ALT_DATA);/* D0-D7 out */ 729 mem &= ~ALT_DATA; 730 mem |= (data & ALT_DATA); 731 } 732 733 if (flag) 734 mem |= ALT_AD_RG; 735 else 736 mem &= ~ALT_AD_RG; 737 738 mem &= ~ALT_CS; 739 if (read) 740 mem = (mem & ~ALT_RD) | ALT_WR; 741 else 742 mem = (mem & ~ALT_WR) | ALT_RD; 743 744 cx_write(MC417_RWD, mem); /* start RW cycle */ 745 746 for (;;) { 747 mem = cx_read(MC417_RWD); 748 if ((mem & ALT_RDY) == 0) 749 break; 750 if (time_after(jiffies, timeout)) 751 break; 752 udelay(1); 753 } 754 755 cx_set(MC417_RWD, ALT_RD | ALT_WR | ALT_CS); 756 if (read) 757 return mem & ALT_DATA; 758 759 return 0; 760 }; 761 762 static int dib7070_tuner_reset(struct dvb_frontend *fe, int onoff) 763 { 764 struct dib7000p_ops *dib7000p_ops = fe->sec_priv; 765 766 return dib7000p_ops->set_gpio(fe, 8, 0, !onoff); 767 } 768 769 static int dib7070_tuner_sleep(struct dvb_frontend *fe, int onoff) 770 { 771 return 0; 772 } 773 774 static struct dib0070_config dib7070p_dib0070_config = { 775 .i2c_address = DEFAULT_DIB0070_I2C_ADDRESS, 776 .reset = dib7070_tuner_reset, 777 .sleep = dib7070_tuner_sleep, 778 .clock_khz = 12000, 779 .freq_offset_khz_vhf = 550, 780 /* .flip_chip = 1, */ 781 }; 782 783 /* DIB7070 generic */ 784 static struct dibx000_agc_config dib7070_agc_config = { 785 .band_caps = BAND_UHF | BAND_VHF | BAND_LBAND | BAND_SBAND, 786 787 /* 788 * P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=5, 789 * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0, P_agc_inh_dc_rv_est=0, 790 * P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5, P_agc_write=0 791 */ 792 .setup = (0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | 793 (0 << 8) | (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0), 794 .inv_gain = 600, 795 .time_stabiliz = 10, 796 .alpha_level = 0, 797 .thlock = 118, 798 .wbd_inv = 0, 799 .wbd_ref = 3530, 800 .wbd_sel = 1, 801 .wbd_alpha = 5, 802 .agc1_max = 65535, 803 .agc1_min = 0, 804 .agc2_max = 65535, 805 .agc2_min = 0, 806 .agc1_pt1 = 0, 807 .agc1_pt2 = 40, 808 .agc1_pt3 = 183, 809 .agc1_slope1 = 206, 810 .agc1_slope2 = 255, 811 .agc2_pt1 = 72, 812 .agc2_pt2 = 152, 813 .agc2_slope1 = 88, 814 .agc2_slope2 = 90, 815 .alpha_mant = 17, 816 .alpha_exp = 27, 817 .beta_mant = 23, 818 .beta_exp = 51, 819 .perform_agc_softsplit = 0, 820 }; 821 822 static struct dibx000_bandwidth_config dib7070_bw_config_12_mhz = { 823 .internal = 60000, 824 .sampling = 15000, 825 .pll_prediv = 1, 826 .pll_ratio = 20, 827 .pll_range = 3, 828 .pll_reset = 1, 829 .pll_bypass = 0, 830 .enable_refdiv = 0, 831 .bypclk_div = 0, 832 .IO_CLK_en_core = 1, 833 .ADClkSrc = 1, 834 .modulo = 2, 835 /* refsel, sel, freq_15k */ 836 .sad_cfg = (3 << 14) | (1 << 12) | (524 << 0), 837 .ifreq = (0 << 25) | 0, 838 .timf = 20452225, 839 .xtal_hz = 12000000, 840 }; 841 842 static struct dib7000p_config dib7070p_dib7000p_config = { 843 /* .output_mode = OUTMODE_MPEG2_FIFO, */ 844 .output_mode = OUTMODE_MPEG2_SERIAL, 845 /* .output_mode = OUTMODE_MPEG2_PAR_GATED_CLK, */ 846 .output_mpeg2_in_188_bytes = 1, 847 848 .agc_config_count = 1, 849 .agc = &dib7070_agc_config, 850 .bw = &dib7070_bw_config_12_mhz, 851 .tuner_is_baseband = 1, 852 .spur_protect = 1, 853 854 .gpio_dir = 0xfcef, /* DIB7000P_GPIO_DEFAULT_DIRECTIONS, */ 855 .gpio_val = 0x0110, /* DIB7000P_GPIO_DEFAULT_VALUES, */ 856 .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS, 857 858 .hostbus_diversity = 1, 859 }; 860 861 static int dvb_register(struct cx23885_tsport *port) 862 { 863 struct dib7000p_ops dib7000p_ops; 864 struct cx23885_dev *dev = port->dev; 865 struct cx23885_i2c *i2c_bus = NULL, *i2c_bus2 = NULL; 866 struct videobuf_dvb_frontend *fe0, *fe1 = NULL; 867 int mfe_shared = 0; /* bus not shared by default */ 868 int ret; 869 870 /* Get the first frontend */ 871 fe0 = videobuf_dvb_get_frontend(&port->frontends, 1); 872 if (!fe0) 873 return -EINVAL; 874 875 /* init struct videobuf_dvb */ 876 fe0->dvb.name = dev->name; 877 878 /* multi-frontend gate control is undefined or defaults to fe0 */ 879 port->frontends.gate = 0; 880 881 /* Sets the gate control callback to be used by i2c command calls */ 882 port->gate_ctrl = cx23885_dvb_gate_ctrl; 883 884 /* init frontend */ 885 switch (dev->board) { 886 case CX23885_BOARD_HAUPPAUGE_HVR1250: 887 i2c_bus = &dev->i2c_bus[0]; 888 fe0->dvb.frontend = dvb_attach(s5h1409_attach, 889 &hauppauge_generic_config, 890 &i2c_bus->i2c_adap); 891 if (fe0->dvb.frontend != NULL) { 892 dvb_attach(mt2131_attach, fe0->dvb.frontend, 893 &i2c_bus->i2c_adap, 894 &hauppauge_generic_tunerconfig, 0); 895 } 896 break; 897 case CX23885_BOARD_HAUPPAUGE_HVR1270: 898 case CX23885_BOARD_HAUPPAUGE_HVR1275: 899 i2c_bus = &dev->i2c_bus[0]; 900 fe0->dvb.frontend = dvb_attach(lgdt3305_attach, 901 &hauppauge_lgdt3305_config, 902 &i2c_bus->i2c_adap); 903 if (fe0->dvb.frontend != NULL) { 904 dvb_attach(tda18271_attach, fe0->dvb.frontend, 905 0x60, &dev->i2c_bus[1].i2c_adap, 906 &hauppauge_hvr127x_config); 907 } 908 if (dev->board == CX23885_BOARD_HAUPPAUGE_HVR1275) 909 cx23885_set_frontend_hook(port, fe0->dvb.frontend); 910 break; 911 case CX23885_BOARD_HAUPPAUGE_HVR1255: 912 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111: 913 i2c_bus = &dev->i2c_bus[0]; 914 fe0->dvb.frontend = dvb_attach(s5h1411_attach, 915 &hcw_s5h1411_config, 916 &i2c_bus->i2c_adap); 917 if (fe0->dvb.frontend != NULL) { 918 dvb_attach(tda18271_attach, fe0->dvb.frontend, 919 0x60, &dev->i2c_bus[1].i2c_adap, 920 &hauppauge_tda18271_config); 921 } 922 923 tda18271_attach(&dev->ts1.analog_fe, 924 0x60, &dev->i2c_bus[1].i2c_adap, 925 &hauppauge_tda18271_config); 926 927 break; 928 case CX23885_BOARD_HAUPPAUGE_HVR1800: 929 i2c_bus = &dev->i2c_bus[0]; 930 switch (alt_tuner) { 931 case 1: 932 fe0->dvb.frontend = 933 dvb_attach(s5h1409_attach, 934 &hauppauge_ezqam_config, 935 &i2c_bus->i2c_adap); 936 if (fe0->dvb.frontend != NULL) { 937 dvb_attach(tda829x_attach, fe0->dvb.frontend, 938 &dev->i2c_bus[1].i2c_adap, 0x42, 939 &tda829x_no_probe); 940 dvb_attach(tda18271_attach, fe0->dvb.frontend, 941 0x60, &dev->i2c_bus[1].i2c_adap, 942 &hauppauge_tda18271_config); 943 } 944 break; 945 case 0: 946 default: 947 fe0->dvb.frontend = 948 dvb_attach(s5h1409_attach, 949 &hauppauge_generic_config, 950 &i2c_bus->i2c_adap); 951 if (fe0->dvb.frontend != NULL) 952 dvb_attach(mt2131_attach, fe0->dvb.frontend, 953 &i2c_bus->i2c_adap, 954 &hauppauge_generic_tunerconfig, 0); 955 break; 956 } 957 break; 958 case CX23885_BOARD_HAUPPAUGE_HVR1800lp: 959 i2c_bus = &dev->i2c_bus[0]; 960 fe0->dvb.frontend = dvb_attach(s5h1409_attach, 961 &hauppauge_hvr1800lp_config, 962 &i2c_bus->i2c_adap); 963 if (fe0->dvb.frontend != NULL) { 964 dvb_attach(mt2131_attach, fe0->dvb.frontend, 965 &i2c_bus->i2c_adap, 966 &hauppauge_generic_tunerconfig, 0); 967 } 968 break; 969 case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP: 970 i2c_bus = &dev->i2c_bus[0]; 971 fe0->dvb.frontend = dvb_attach(lgdt330x_attach, 972 &fusionhdtv_5_express, 973 &i2c_bus->i2c_adap); 974 if (fe0->dvb.frontend != NULL) { 975 dvb_attach(simple_tuner_attach, fe0->dvb.frontend, 976 &i2c_bus->i2c_adap, 0x61, 977 TUNER_LG_TDVS_H06XF); 978 } 979 break; 980 case CX23885_BOARD_HAUPPAUGE_HVR1500Q: 981 i2c_bus = &dev->i2c_bus[1]; 982 fe0->dvb.frontend = dvb_attach(s5h1409_attach, 983 &hauppauge_hvr1500q_config, 984 &dev->i2c_bus[0].i2c_adap); 985 if (fe0->dvb.frontend != NULL) 986 dvb_attach(xc5000_attach, fe0->dvb.frontend, 987 &i2c_bus->i2c_adap, 988 &hauppauge_hvr1500q_tunerconfig); 989 break; 990 case CX23885_BOARD_HAUPPAUGE_HVR1500: 991 i2c_bus = &dev->i2c_bus[1]; 992 fe0->dvb.frontend = dvb_attach(s5h1409_attach, 993 &hauppauge_hvr1500_config, 994 &dev->i2c_bus[0].i2c_adap); 995 if (fe0->dvb.frontend != NULL) { 996 struct dvb_frontend *fe; 997 struct xc2028_config cfg = { 998 .i2c_adap = &i2c_bus->i2c_adap, 999 .i2c_addr = 0x61, 1000 }; 1001 static struct xc2028_ctrl ctl = { 1002 .fname = XC2028_DEFAULT_FIRMWARE, 1003 .max_len = 64, 1004 .demod = XC3028_FE_OREN538, 1005 }; 1006 1007 fe = dvb_attach(xc2028_attach, 1008 fe0->dvb.frontend, &cfg); 1009 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL) 1010 fe->ops.tuner_ops.set_config(fe, &ctl); 1011 } 1012 break; 1013 case CX23885_BOARD_HAUPPAUGE_HVR1200: 1014 case CX23885_BOARD_HAUPPAUGE_HVR1700: 1015 i2c_bus = &dev->i2c_bus[0]; 1016 fe0->dvb.frontend = dvb_attach(tda10048_attach, 1017 &hauppauge_hvr1200_config, 1018 &i2c_bus->i2c_adap); 1019 if (fe0->dvb.frontend != NULL) { 1020 dvb_attach(tda829x_attach, fe0->dvb.frontend, 1021 &dev->i2c_bus[1].i2c_adap, 0x42, 1022 &tda829x_no_probe); 1023 dvb_attach(tda18271_attach, fe0->dvb.frontend, 1024 0x60, &dev->i2c_bus[1].i2c_adap, 1025 &hauppauge_hvr1200_tuner_config); 1026 } 1027 break; 1028 case CX23885_BOARD_HAUPPAUGE_HVR1210: 1029 i2c_bus = &dev->i2c_bus[0]; 1030 fe0->dvb.frontend = dvb_attach(tda10048_attach, 1031 &hauppauge_hvr1210_config, 1032 &i2c_bus->i2c_adap); 1033 if (fe0->dvb.frontend != NULL) { 1034 dvb_attach(tda18271_attach, fe0->dvb.frontend, 1035 0x60, &dev->i2c_bus[1].i2c_adap, 1036 &hauppauge_hvr1210_tuner_config); 1037 } 1038 break; 1039 case CX23885_BOARD_HAUPPAUGE_HVR1400: 1040 i2c_bus = &dev->i2c_bus[0]; 1041 1042 if (!dvb_attach(dib7000p_attach, &dib7000p_ops)) 1043 return -ENODEV; 1044 1045 fe0->dvb.frontend = dib7000p_ops.init(&i2c_bus->i2c_adap, 1046 0x12, &hauppauge_hvr1400_dib7000_config); 1047 if (fe0->dvb.frontend != NULL) { 1048 struct dvb_frontend *fe; 1049 struct xc2028_config cfg = { 1050 .i2c_adap = &dev->i2c_bus[1].i2c_adap, 1051 .i2c_addr = 0x64, 1052 }; 1053 static struct xc2028_ctrl ctl = { 1054 .fname = XC3028L_DEFAULT_FIRMWARE, 1055 .max_len = 64, 1056 .demod = XC3028_FE_DIBCOM52, 1057 /* This is true for all demods with 1058 v36 firmware? */ 1059 .type = XC2028_D2633, 1060 }; 1061 1062 fe = dvb_attach(xc2028_attach, 1063 fe0->dvb.frontend, &cfg); 1064 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL) 1065 fe->ops.tuner_ops.set_config(fe, &ctl); 1066 } 1067 break; 1068 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP: 1069 i2c_bus = &dev->i2c_bus[port->nr - 1]; 1070 1071 fe0->dvb.frontend = dvb_attach(s5h1409_attach, 1072 &dvico_s5h1409_config, 1073 &i2c_bus->i2c_adap); 1074 if (fe0->dvb.frontend == NULL) 1075 fe0->dvb.frontend = dvb_attach(s5h1411_attach, 1076 &dvico_s5h1411_config, 1077 &i2c_bus->i2c_adap); 1078 if (fe0->dvb.frontend != NULL) 1079 dvb_attach(xc5000_attach, fe0->dvb.frontend, 1080 &i2c_bus->i2c_adap, 1081 &dvico_xc5000_tunerconfig); 1082 break; 1083 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: { 1084 i2c_bus = &dev->i2c_bus[port->nr - 1]; 1085 1086 fe0->dvb.frontend = dvb_attach(zl10353_attach, 1087 &dvico_fusionhdtv_xc3028, 1088 &i2c_bus->i2c_adap); 1089 if (fe0->dvb.frontend != NULL) { 1090 struct dvb_frontend *fe; 1091 struct xc2028_config cfg = { 1092 .i2c_adap = &i2c_bus->i2c_adap, 1093 .i2c_addr = 0x61, 1094 }; 1095 static struct xc2028_ctrl ctl = { 1096 .fname = XC2028_DEFAULT_FIRMWARE, 1097 .max_len = 64, 1098 .demod = XC3028_FE_ZARLINK456, 1099 }; 1100 1101 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend, 1102 &cfg); 1103 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL) 1104 fe->ops.tuner_ops.set_config(fe, &ctl); 1105 } 1106 break; 1107 } 1108 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2: { 1109 i2c_bus = &dev->i2c_bus[port->nr - 1]; 1110 /* cxusb_ctrl_msg(adap->dev, CMD_DIGITAL, NULL, 0, NULL, 0); */ 1111 /* cxusb_bluebird_gpio_pulse(adap->dev, 0x02, 1); */ 1112 1113 if (!dvb_attach(dib7000p_attach, &dib7000p_ops)) 1114 return -ENODEV; 1115 1116 if (dib7000p_ops.i2c_enumeration(&i2c_bus->i2c_adap, 1, 0x12, &dib7070p_dib7000p_config) < 0) { 1117 printk(KERN_WARNING "Unable to enumerate dib7000p\n"); 1118 return -ENODEV; 1119 } 1120 fe0->dvb.frontend = dib7000p_ops.init(&i2c_bus->i2c_adap, 0x80, &dib7070p_dib7000p_config); 1121 if (fe0->dvb.frontend != NULL) { 1122 struct i2c_adapter *tun_i2c; 1123 1124 fe0->dvb.frontend->sec_priv = kmalloc(sizeof(dib7000p_ops), GFP_KERNEL); 1125 memcpy(fe0->dvb.frontend->sec_priv, &dib7000p_ops, sizeof(dib7000p_ops)); 1126 tun_i2c = dib7000p_ops.get_i2c_master(fe0->dvb.frontend, DIBX000_I2C_INTERFACE_TUNER, 1); 1127 if (!dvb_attach(dib0070_attach, fe0->dvb.frontend, tun_i2c, &dib7070p_dib0070_config)) 1128 return -ENODEV; 1129 } 1130 break; 1131 } 1132 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H: 1133 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F: 1134 case CX23885_BOARD_COMPRO_VIDEOMATE_E800: 1135 i2c_bus = &dev->i2c_bus[0]; 1136 1137 fe0->dvb.frontend = dvb_attach(zl10353_attach, 1138 &dvico_fusionhdtv_xc3028, 1139 &i2c_bus->i2c_adap); 1140 if (fe0->dvb.frontend != NULL) { 1141 struct dvb_frontend *fe; 1142 struct xc2028_config cfg = { 1143 .i2c_adap = &dev->i2c_bus[1].i2c_adap, 1144 .i2c_addr = 0x61, 1145 }; 1146 static struct xc2028_ctrl ctl = { 1147 .fname = XC2028_DEFAULT_FIRMWARE, 1148 .max_len = 64, 1149 .demod = XC3028_FE_ZARLINK456, 1150 }; 1151 1152 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend, 1153 &cfg); 1154 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL) 1155 fe->ops.tuner_ops.set_config(fe, &ctl); 1156 } 1157 break; 1158 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000: 1159 i2c_bus = &dev->i2c_bus[0]; 1160 1161 fe0->dvb.frontend = dvb_attach(zl10353_attach, 1162 &dvico_fusionhdtv_xc3028, 1163 &i2c_bus->i2c_adap); 1164 if (fe0->dvb.frontend != NULL) { 1165 struct dvb_frontend *fe; 1166 struct xc4000_config cfg = { 1167 .i2c_address = 0x61, 1168 .default_pm = 0, 1169 .dvb_amplitude = 134, 1170 .set_smoothedcvbs = 1, 1171 .if_khz = 4560 1172 }; 1173 1174 fe = dvb_attach(xc4000_attach, fe0->dvb.frontend, 1175 &dev->i2c_bus[1].i2c_adap, &cfg); 1176 if (!fe) { 1177 printk(KERN_ERR "%s/2: xc4000 attach failed\n", 1178 dev->name); 1179 goto frontend_detach; 1180 } 1181 } 1182 break; 1183 case CX23885_BOARD_TBS_6920: 1184 i2c_bus = &dev->i2c_bus[1]; 1185 1186 fe0->dvb.frontend = dvb_attach(cx24116_attach, 1187 &tbs_cx24116_config, 1188 &i2c_bus->i2c_adap); 1189 if (fe0->dvb.frontend != NULL) 1190 fe0->dvb.frontend->ops.set_voltage = f300_set_voltage; 1191 1192 break; 1193 case CX23885_BOARD_TBS_6980: 1194 case CX23885_BOARD_TBS_6981: 1195 i2c_bus = &dev->i2c_bus[1]; 1196 1197 switch (port->nr) { 1198 /* PORT B */ 1199 case 1: 1200 fe0->dvb.frontend = dvb_attach(cx24117_attach, 1201 &tbs_cx24117_config, 1202 &i2c_bus->i2c_adap); 1203 break; 1204 /* PORT C */ 1205 case 2: 1206 fe0->dvb.frontend = dvb_attach(cx24117_attach, 1207 &tbs_cx24117_config, 1208 &i2c_bus->i2c_adap); 1209 break; 1210 } 1211 break; 1212 case CX23885_BOARD_TEVII_S470: 1213 i2c_bus = &dev->i2c_bus[1]; 1214 1215 fe0->dvb.frontend = dvb_attach(ds3000_attach, 1216 &tevii_ds3000_config, 1217 &i2c_bus->i2c_adap); 1218 if (fe0->dvb.frontend != NULL) { 1219 dvb_attach(ts2020_attach, fe0->dvb.frontend, 1220 &tevii_ts2020_config, &i2c_bus->i2c_adap); 1221 fe0->dvb.frontend->ops.set_voltage = f300_set_voltage; 1222 } 1223 1224 break; 1225 case CX23885_BOARD_DVBWORLD_2005: 1226 i2c_bus = &dev->i2c_bus[1]; 1227 1228 fe0->dvb.frontend = dvb_attach(cx24116_attach, 1229 &dvbworld_cx24116_config, 1230 &i2c_bus->i2c_adap); 1231 break; 1232 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: 1233 i2c_bus = &dev->i2c_bus[0]; 1234 switch (port->nr) { 1235 /* port B */ 1236 case 1: 1237 fe0->dvb.frontend = dvb_attach(stv0900_attach, 1238 &netup_stv0900_config, 1239 &i2c_bus->i2c_adap, 0); 1240 if (fe0->dvb.frontend != NULL) { 1241 if (dvb_attach(stv6110_attach, 1242 fe0->dvb.frontend, 1243 &netup_stv6110_tunerconfig_a, 1244 &i2c_bus->i2c_adap)) { 1245 if (!dvb_attach(lnbh24_attach, 1246 fe0->dvb.frontend, 1247 &i2c_bus->i2c_adap, 1248 LNBH24_PCL | LNBH24_TTX, 1249 LNBH24_TEN, 0x09)) 1250 printk(KERN_ERR 1251 "No LNBH24 found!\n"); 1252 1253 } 1254 } 1255 break; 1256 /* port C */ 1257 case 2: 1258 fe0->dvb.frontend = dvb_attach(stv0900_attach, 1259 &netup_stv0900_config, 1260 &i2c_bus->i2c_adap, 1); 1261 if (fe0->dvb.frontend != NULL) { 1262 if (dvb_attach(stv6110_attach, 1263 fe0->dvb.frontend, 1264 &netup_stv6110_tunerconfig_b, 1265 &i2c_bus->i2c_adap)) { 1266 if (!dvb_attach(lnbh24_attach, 1267 fe0->dvb.frontend, 1268 &i2c_bus->i2c_adap, 1269 LNBH24_PCL | LNBH24_TTX, 1270 LNBH24_TEN, 0x0a)) 1271 printk(KERN_ERR 1272 "No LNBH24 found!\n"); 1273 1274 } 1275 } 1276 break; 1277 } 1278 break; 1279 case CX23885_BOARD_MYGICA_X8506: 1280 i2c_bus = &dev->i2c_bus[0]; 1281 i2c_bus2 = &dev->i2c_bus[1]; 1282 fe0->dvb.frontend = dvb_attach(lgs8gxx_attach, 1283 &mygica_x8506_lgs8gl5_config, 1284 &i2c_bus->i2c_adap); 1285 if (fe0->dvb.frontend != NULL) { 1286 dvb_attach(xc5000_attach, 1287 fe0->dvb.frontend, 1288 &i2c_bus2->i2c_adap, 1289 &mygica_x8506_xc5000_config); 1290 } 1291 cx23885_set_frontend_hook(port, fe0->dvb.frontend); 1292 break; 1293 case CX23885_BOARD_MYGICA_X8507: 1294 i2c_bus = &dev->i2c_bus[0]; 1295 i2c_bus2 = &dev->i2c_bus[1]; 1296 fe0->dvb.frontend = dvb_attach(mb86a20s_attach, 1297 &mygica_x8507_mb86a20s_config, 1298 &i2c_bus->i2c_adap); 1299 if (fe0->dvb.frontend != NULL) { 1300 dvb_attach(xc5000_attach, 1301 fe0->dvb.frontend, 1302 &i2c_bus2->i2c_adap, 1303 &mygica_x8507_xc5000_config); 1304 } 1305 cx23885_set_frontend_hook(port, fe0->dvb.frontend); 1306 break; 1307 case CX23885_BOARD_MAGICPRO_PROHDTVE2: 1308 i2c_bus = &dev->i2c_bus[0]; 1309 i2c_bus2 = &dev->i2c_bus[1]; 1310 fe0->dvb.frontend = dvb_attach(lgs8gxx_attach, 1311 &magicpro_prohdtve2_lgs8g75_config, 1312 &i2c_bus->i2c_adap); 1313 if (fe0->dvb.frontend != NULL) { 1314 dvb_attach(xc5000_attach, 1315 fe0->dvb.frontend, 1316 &i2c_bus2->i2c_adap, 1317 &magicpro_prohdtve2_xc5000_config); 1318 } 1319 cx23885_set_frontend_hook(port, fe0->dvb.frontend); 1320 break; 1321 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1322 i2c_bus = &dev->i2c_bus[0]; 1323 fe0->dvb.frontend = dvb_attach(s5h1411_attach, 1324 &hcw_s5h1411_config, 1325 &i2c_bus->i2c_adap); 1326 if (fe0->dvb.frontend != NULL) 1327 dvb_attach(tda18271_attach, fe0->dvb.frontend, 1328 0x60, &dev->i2c_bus[0].i2c_adap, 1329 &hauppauge_tda18271_config); 1330 1331 tda18271_attach(&dev->ts1.analog_fe, 1332 0x60, &dev->i2c_bus[1].i2c_adap, 1333 &hauppauge_tda18271_config); 1334 1335 break; 1336 case CX23885_BOARD_HAUPPAUGE_HVR1290: 1337 i2c_bus = &dev->i2c_bus[0]; 1338 fe0->dvb.frontend = dvb_attach(s5h1411_attach, 1339 &hcw_s5h1411_config, 1340 &i2c_bus->i2c_adap); 1341 if (fe0->dvb.frontend != NULL) 1342 dvb_attach(tda18271_attach, fe0->dvb.frontend, 1343 0x60, &dev->i2c_bus[0].i2c_adap, 1344 &hauppauge_tda18271_config); 1345 break; 1346 case CX23885_BOARD_MYGICA_X8558PRO: 1347 switch (port->nr) { 1348 /* port B */ 1349 case 1: 1350 i2c_bus = &dev->i2c_bus[0]; 1351 fe0->dvb.frontend = dvb_attach(atbm8830_attach, 1352 &mygica_x8558pro_atbm8830_cfg1, 1353 &i2c_bus->i2c_adap); 1354 if (fe0->dvb.frontend != NULL) { 1355 dvb_attach(max2165_attach, 1356 fe0->dvb.frontend, 1357 &i2c_bus->i2c_adap, 1358 &mygic_x8558pro_max2165_cfg1); 1359 } 1360 break; 1361 /* port C */ 1362 case 2: 1363 i2c_bus = &dev->i2c_bus[1]; 1364 fe0->dvb.frontend = dvb_attach(atbm8830_attach, 1365 &mygica_x8558pro_atbm8830_cfg2, 1366 &i2c_bus->i2c_adap); 1367 if (fe0->dvb.frontend != NULL) { 1368 dvb_attach(max2165_attach, 1369 fe0->dvb.frontend, 1370 &i2c_bus->i2c_adap, 1371 &mygic_x8558pro_max2165_cfg2); 1372 } 1373 break; 1374 } 1375 break; 1376 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: 1377 i2c_bus = &dev->i2c_bus[0]; 1378 mfe_shared = 1;/* MFE */ 1379 port->frontends.gate = 0;/* not clear for me yet */ 1380 /* ports B, C */ 1381 /* MFE frontend 1 DVB-T */ 1382 fe0->dvb.frontend = dvb_attach(stv0367ter_attach, 1383 &netup_stv0367_config[port->nr - 1], 1384 &i2c_bus->i2c_adap); 1385 if (fe0->dvb.frontend != NULL) { 1386 if (NULL == dvb_attach(xc5000_attach, 1387 fe0->dvb.frontend, 1388 &i2c_bus->i2c_adap, 1389 &netup_xc5000_config[port->nr - 1])) 1390 goto frontend_detach; 1391 /* load xc5000 firmware */ 1392 fe0->dvb.frontend->ops.tuner_ops.init(fe0->dvb.frontend); 1393 } 1394 /* MFE frontend 2 */ 1395 fe1 = videobuf_dvb_get_frontend(&port->frontends, 2); 1396 if (fe1 == NULL) 1397 goto frontend_detach; 1398 /* DVB-C init */ 1399 fe1->dvb.frontend = dvb_attach(stv0367cab_attach, 1400 &netup_stv0367_config[port->nr - 1], 1401 &i2c_bus->i2c_adap); 1402 if (fe1->dvb.frontend != NULL) { 1403 fe1->dvb.frontend->id = 1; 1404 if (NULL == dvb_attach(xc5000_attach, 1405 fe1->dvb.frontend, 1406 &i2c_bus->i2c_adap, 1407 &netup_xc5000_config[port->nr - 1])) 1408 goto frontend_detach; 1409 } 1410 break; 1411 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL: 1412 i2c_bus = &dev->i2c_bus[0]; 1413 i2c_bus2 = &dev->i2c_bus[1]; 1414 1415 switch (port->nr) { 1416 /* port b */ 1417 case 1: 1418 fe0->dvb.frontend = dvb_attach(drxk_attach, 1419 &terratec_drxk_config[0], 1420 &i2c_bus->i2c_adap); 1421 if (fe0->dvb.frontend != NULL) { 1422 if (!dvb_attach(mt2063_attach, 1423 fe0->dvb.frontend, 1424 &terratec_mt2063_config[0], 1425 &i2c_bus2->i2c_adap)) 1426 goto frontend_detach; 1427 } 1428 break; 1429 /* port c */ 1430 case 2: 1431 fe0->dvb.frontend = dvb_attach(drxk_attach, 1432 &terratec_drxk_config[1], 1433 &i2c_bus->i2c_adap); 1434 if (fe0->dvb.frontend != NULL) { 1435 if (!dvb_attach(mt2063_attach, 1436 fe0->dvb.frontend, 1437 &terratec_mt2063_config[1], 1438 &i2c_bus2->i2c_adap)) 1439 goto frontend_detach; 1440 } 1441 break; 1442 } 1443 break; 1444 case CX23885_BOARD_TEVII_S471: 1445 i2c_bus = &dev->i2c_bus[1]; 1446 1447 fe0->dvb.frontend = dvb_attach(ds3000_attach, 1448 &tevii_ds3000_config, 1449 &i2c_bus->i2c_adap); 1450 if (fe0->dvb.frontend != NULL) { 1451 dvb_attach(ts2020_attach, fe0->dvb.frontend, 1452 &tevii_ts2020_config, &i2c_bus->i2c_adap); 1453 } 1454 break; 1455 case CX23885_BOARD_PROF_8000: 1456 i2c_bus = &dev->i2c_bus[0]; 1457 1458 fe0->dvb.frontend = dvb_attach(stv090x_attach, 1459 &prof_8000_stv090x_config, 1460 &i2c_bus->i2c_adap, 1461 STV090x_DEMODULATOR_0); 1462 if (fe0->dvb.frontend != NULL) { 1463 if (!dvb_attach(stb6100_attach, 1464 fe0->dvb.frontend, 1465 &prof_8000_stb6100_config, 1466 &i2c_bus->i2c_adap)) 1467 goto frontend_detach; 1468 1469 fe0->dvb.frontend->ops.set_voltage = p8000_set_voltage; 1470 } 1471 break; 1472 case CX23885_BOARD_HAUPPAUGE_HVR4400: 1473 i2c_bus = &dev->i2c_bus[0]; 1474 i2c_bus2 = &dev->i2c_bus[1]; 1475 switch (port->nr) { 1476 /* port b */ 1477 case 1: 1478 fe0->dvb.frontend = dvb_attach(tda10071_attach, 1479 &hauppauge_tda10071_config, 1480 &i2c_bus->i2c_adap); 1481 if (fe0->dvb.frontend != NULL) { 1482 if (!dvb_attach(a8293_attach, fe0->dvb.frontend, 1483 &i2c_bus->i2c_adap, 1484 &hauppauge_a8293_config)) 1485 goto frontend_detach; 1486 } 1487 break; 1488 /* port c */ 1489 case 2: 1490 fe0->dvb.frontend = dvb_attach(si2165_attach, 1491 &hauppauge_hvr4400_si2165_config, 1492 &i2c_bus->i2c_adap); 1493 if (fe0->dvb.frontend != NULL) { 1494 fe0->dvb.frontend->ops.i2c_gate_ctrl = 0; 1495 if (!dvb_attach(tda18271_attach, 1496 fe0->dvb.frontend, 1497 0x60, &i2c_bus2->i2c_adap, 1498 &hauppauge_hvr4400_tuner_config)) 1499 goto frontend_detach; 1500 } 1501 break; 1502 } 1503 break; 1504 default: 1505 printk(KERN_INFO "%s: The frontend of your DVB/ATSC card " 1506 " isn't supported yet\n", 1507 dev->name); 1508 break; 1509 } 1510 1511 if ((NULL == fe0->dvb.frontend) || (fe1 && NULL == fe1->dvb.frontend)) { 1512 printk(KERN_ERR "%s: frontend initialization failed\n", 1513 dev->name); 1514 goto frontend_detach; 1515 } 1516 1517 /* define general-purpose callback pointer */ 1518 fe0->dvb.frontend->callback = cx23885_tuner_callback; 1519 if (fe1) 1520 fe1->dvb.frontend->callback = cx23885_tuner_callback; 1521 #if 0 1522 /* Ensure all frontends negotiate bus access */ 1523 fe0->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl; 1524 if (fe1) 1525 fe1->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl; 1526 #endif 1527 1528 /* Put the analog decoder in standby to keep it quiet */ 1529 call_all(dev, core, s_power, 0); 1530 1531 if (fe0->dvb.frontend->ops.analog_ops.standby) 1532 fe0->dvb.frontend->ops.analog_ops.standby(fe0->dvb.frontend); 1533 1534 /* register everything */ 1535 ret = videobuf_dvb_register_bus(&port->frontends, THIS_MODULE, port, 1536 &dev->pci->dev, adapter_nr, mfe_shared); 1537 if (ret) 1538 goto frontend_detach; 1539 1540 /* init CI & MAC */ 1541 switch (dev->board) { 1542 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: { 1543 static struct netup_card_info cinfo; 1544 1545 netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo); 1546 memcpy(port->frontends.adapter.proposed_mac, 1547 cinfo.port[port->nr - 1].mac, 6); 1548 printk(KERN_INFO "NetUP Dual DVB-S2 CI card port%d MAC=%pM\n", 1549 port->nr, port->frontends.adapter.proposed_mac); 1550 1551 netup_ci_init(port); 1552 break; 1553 } 1554 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: { 1555 struct altera_ci_config netup_ci_cfg = { 1556 .dev = dev,/* magic number to identify*/ 1557 .adapter = &port->frontends.adapter,/* for CI */ 1558 .demux = &fe0->dvb.demux,/* for hw pid filter */ 1559 .fpga_rw = netup_altera_fpga_rw, 1560 }; 1561 1562 altera_ci_init(&netup_ci_cfg, port->nr); 1563 break; 1564 } 1565 case CX23885_BOARD_TEVII_S470: { 1566 u8 eeprom[256]; /* 24C02 i2c eeprom */ 1567 1568 if (port->nr != 1) 1569 break; 1570 1571 /* Read entire EEPROM */ 1572 dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1; 1573 tveeprom_read(&dev->i2c_bus[0].i2c_client, eeprom, sizeof(eeprom)); 1574 printk(KERN_INFO "TeVii S470 MAC= %pM\n", eeprom + 0xa0); 1575 memcpy(port->frontends.adapter.proposed_mac, eeprom + 0xa0, 6); 1576 break; 1577 } 1578 } 1579 1580 return ret; 1581 1582 frontend_detach: 1583 port->gate_ctrl = NULL; 1584 videobuf_dvb_dealloc_frontends(&port->frontends); 1585 return -EINVAL; 1586 } 1587 1588 int cx23885_dvb_register(struct cx23885_tsport *port) 1589 { 1590 1591 struct videobuf_dvb_frontend *fe0; 1592 struct cx23885_dev *dev = port->dev; 1593 int err, i; 1594 1595 /* Here we need to allocate the correct number of frontends, 1596 * as reflected in the cards struct. The reality is that currently 1597 * no cx23885 boards support this - yet. But, if we don't modify this 1598 * code then the second frontend would never be allocated (later) 1599 * and fail with error before the attach in dvb_register(). 1600 * Without these changes we risk an OOPS later. The changes here 1601 * are for safety, and should provide a good foundation for the 1602 * future addition of any multi-frontend cx23885 based boards. 1603 */ 1604 printk(KERN_INFO "%s() allocating %d frontend(s)\n", __func__, 1605 port->num_frontends); 1606 1607 for (i = 1; i <= port->num_frontends; i++) { 1608 if (videobuf_dvb_alloc_frontend( 1609 &port->frontends, i) == NULL) { 1610 printk(KERN_ERR "%s() failed to alloc\n", __func__); 1611 return -ENOMEM; 1612 } 1613 1614 fe0 = videobuf_dvb_get_frontend(&port->frontends, i); 1615 if (!fe0) 1616 err = -EINVAL; 1617 1618 dprintk(1, "%s\n", __func__); 1619 dprintk(1, " ->probed by Card=%d Name=%s, PCI %02x:%02x\n", 1620 dev->board, 1621 dev->name, 1622 dev->pci_bus, 1623 dev->pci_slot); 1624 1625 err = -ENODEV; 1626 1627 /* dvb stuff */ 1628 /* We have to init the queue for each frontend on a port. */ 1629 printk(KERN_INFO "%s: cx23885 based dvb card\n", dev->name); 1630 videobuf_queue_sg_init(&fe0->dvb.dvbq, &dvb_qops, 1631 &dev->pci->dev, &port->slock, 1632 V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_TOP, 1633 sizeof(struct cx23885_buffer), port, NULL); 1634 } 1635 err = dvb_register(port); 1636 if (err != 0) 1637 printk(KERN_ERR "%s() dvb_register failed err = %d\n", 1638 __func__, err); 1639 1640 return err; 1641 } 1642 1643 int cx23885_dvb_unregister(struct cx23885_tsport *port) 1644 { 1645 struct videobuf_dvb_frontend *fe0; 1646 1647 /* FIXME: in an error condition where the we have 1648 * an expected number of frontends (attach problem) 1649 * then this might not clean up correctly, if 1 1650 * is invalid. 1651 * This comment only applies to future boards IF they 1652 * implement MFE support. 1653 */ 1654 fe0 = videobuf_dvb_get_frontend(&port->frontends, 1); 1655 if (fe0 && fe0->dvb.frontend) 1656 videobuf_dvb_unregister_bus(&port->frontends); 1657 1658 switch (port->dev->board) { 1659 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: 1660 netup_ci_exit(port); 1661 break; 1662 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: 1663 altera_ci_release(port->dev, port->nr); 1664 break; 1665 } 1666 1667 port->gate_ctrl = NULL; 1668 1669 return 0; 1670 } 1671 1672