1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * cx18 init/start/stop/exit stream functions 4 * 5 * Derived from ivtv-streams.c 6 * 7 * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl> 8 * Copyright (C) 2008 Andy Walls <awalls@md.metrocast.net> 9 */ 10 11 #include "cx18-driver.h" 12 #include "cx18-io.h" 13 #include "cx18-fileops.h" 14 #include "cx18-mailbox.h" 15 #include "cx18-i2c.h" 16 #include "cx18-queue.h" 17 #include "cx18-ioctl.h" 18 #include "cx18-streams.h" 19 #include "cx18-cards.h" 20 #include "cx18-scb.h" 21 #include "cx18-dvb.h" 22 23 #define CX18_DSP0_INTERRUPT_MASK 0xd0004C 24 25 static const struct v4l2_file_operations cx18_v4l2_enc_fops = { 26 .owner = THIS_MODULE, 27 .read = cx18_v4l2_read, 28 .open = cx18_v4l2_open, 29 .unlocked_ioctl = video_ioctl2, 30 .release = cx18_v4l2_close, 31 .poll = cx18_v4l2_enc_poll, 32 }; 33 34 static const struct v4l2_file_operations cx18_v4l2_enc_yuv_fops = { 35 .owner = THIS_MODULE, 36 .open = cx18_v4l2_open, 37 .unlocked_ioctl = video_ioctl2, 38 .release = cx18_v4l2_close, 39 .poll = vb2_fop_poll, 40 .read = vb2_fop_read, 41 .mmap = vb2_fop_mmap, 42 }; 43 44 /* offset from 0 to register ts v4l2 minors on */ 45 #define CX18_V4L2_ENC_TS_OFFSET 16 46 /* offset from 0 to register pcm v4l2 minors on */ 47 #define CX18_V4L2_ENC_PCM_OFFSET 24 48 /* offset from 0 to register yuv v4l2 minors on */ 49 #define CX18_V4L2_ENC_YUV_OFFSET 32 50 51 static struct { 52 const char *name; 53 int vfl_type; 54 int num_offset; 55 int dma; 56 u32 caps; 57 } cx18_stream_info[] = { 58 { /* CX18_ENC_STREAM_TYPE_MPG */ 59 "encoder MPEG", 60 VFL_TYPE_VIDEO, 0, 61 DMA_FROM_DEVICE, 62 V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_READWRITE | 63 V4L2_CAP_AUDIO | V4L2_CAP_TUNER 64 }, 65 { /* CX18_ENC_STREAM_TYPE_TS */ 66 "TS", 67 VFL_TYPE_VIDEO, -1, 68 DMA_FROM_DEVICE, 69 }, 70 { /* CX18_ENC_STREAM_TYPE_YUV */ 71 "encoder YUV", 72 VFL_TYPE_VIDEO, CX18_V4L2_ENC_YUV_OFFSET, 73 DMA_FROM_DEVICE, 74 V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_READWRITE | 75 V4L2_CAP_STREAMING | V4L2_CAP_AUDIO | V4L2_CAP_TUNER 76 }, 77 { /* CX18_ENC_STREAM_TYPE_VBI */ 78 "encoder VBI", 79 VFL_TYPE_VBI, 0, 80 DMA_FROM_DEVICE, 81 V4L2_CAP_VBI_CAPTURE | V4L2_CAP_SLICED_VBI_CAPTURE | 82 V4L2_CAP_READWRITE | V4L2_CAP_AUDIO | V4L2_CAP_TUNER 83 }, 84 { /* CX18_ENC_STREAM_TYPE_PCM */ 85 "encoder PCM audio", 86 VFL_TYPE_VIDEO, CX18_V4L2_ENC_PCM_OFFSET, 87 DMA_FROM_DEVICE, 88 V4L2_CAP_TUNER | V4L2_CAP_AUDIO | V4L2_CAP_READWRITE, 89 }, 90 { /* CX18_ENC_STREAM_TYPE_IDX */ 91 "encoder IDX", 92 VFL_TYPE_VIDEO, -1, 93 DMA_FROM_DEVICE, 94 }, 95 { /* CX18_ENC_STREAM_TYPE_RAD */ 96 "encoder radio", 97 VFL_TYPE_RADIO, 0, 98 DMA_NONE, 99 V4L2_CAP_RADIO | V4L2_CAP_TUNER 100 }, 101 }; 102 103 static int cx18_queue_setup(struct vb2_queue *vq, 104 unsigned int *nbuffers, unsigned int *nplanes, 105 unsigned int sizes[], struct device *alloc_devs[]) 106 { 107 unsigned int q_num_bufs = vb2_get_num_buffers(vq); 108 struct cx18_stream *s = vb2_get_drv_priv(vq); 109 struct cx18 *cx = s->cx; 110 unsigned int szimage; 111 112 /* 113 * HM12 YUV size is (Y=(h*720) + UV=(h*(720/2))) 114 * UYUV YUV size is (Y=(h*720) + UV=(h*(720))) 115 */ 116 if (s->pixelformat == V4L2_PIX_FMT_NV12_16L16) 117 szimage = cx->cxhdl.height * 720 * 3 / 2; 118 else 119 szimage = cx->cxhdl.height * 720 * 2; 120 121 /* 122 * Let's request at least three buffers: two for the 123 * DMA engine and one for userspace. 124 */ 125 if (q_num_bufs + *nbuffers < 3) 126 *nbuffers = 3 - q_num_bufs; 127 128 if (*nplanes) { 129 if (*nplanes != 1 || sizes[0] < szimage) 130 return -EINVAL; 131 return 0; 132 } 133 134 sizes[0] = szimage; 135 *nplanes = 1; 136 return 0; 137 } 138 139 static void cx18_buf_queue(struct vb2_buffer *vb) 140 { 141 struct cx18_stream *s = vb2_get_drv_priv(vb->vb2_queue); 142 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 143 struct cx18_vb2_buffer *buf = 144 container_of(vbuf, struct cx18_vb2_buffer, vb); 145 unsigned long flags; 146 147 spin_lock_irqsave(&s->vb_lock, flags); 148 list_add_tail(&buf->list, &s->vb_capture); 149 spin_unlock_irqrestore(&s->vb_lock, flags); 150 } 151 152 static int cx18_buf_prepare(struct vb2_buffer *vb) 153 { 154 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 155 struct cx18_stream *s = vb2_get_drv_priv(vb->vb2_queue); 156 struct cx18 *cx = s->cx; 157 unsigned int size; 158 159 /* 160 * HM12 YUV size is (Y=(h*720) + UV=(h*(720/2))) 161 * UYUV YUV size is (Y=(h*720) + UV=(h*(720))) 162 */ 163 if (s->pixelformat == V4L2_PIX_FMT_NV12_16L16) 164 size = cx->cxhdl.height * 720 * 3 / 2; 165 else 166 size = cx->cxhdl.height * 720 * 2; 167 168 if (vb2_plane_size(vb, 0) < size) 169 return -EINVAL; 170 vb2_set_plane_payload(vb, 0, size); 171 vbuf->field = V4L2_FIELD_INTERLACED; 172 return 0; 173 } 174 175 void cx18_clear_queue(struct cx18_stream *s, enum vb2_buffer_state state) 176 { 177 while (!list_empty(&s->vb_capture)) { 178 struct cx18_vb2_buffer *buf; 179 180 buf = list_first_entry(&s->vb_capture, 181 struct cx18_vb2_buffer, list); 182 list_del(&buf->list); 183 vb2_buffer_done(&buf->vb.vb2_buf, state); 184 } 185 } 186 187 static int cx18_start_streaming(struct vb2_queue *vq, unsigned int count) 188 { 189 struct v4l2_fh *owner = vq->owner; 190 struct cx18_stream *s = vb2_get_drv_priv(vq); 191 unsigned long flags; 192 int rc; 193 194 if (WARN_ON(!owner)) { 195 rc = -EIO; 196 goto clear_queue; 197 } 198 199 s->sequence = 0; 200 rc = cx18_start_capture(fh2id(owner)); 201 if (!rc) { 202 /* Establish a buffer timeout */ 203 mod_timer(&s->vb_timeout, msecs_to_jiffies(2000) + jiffies); 204 return 0; 205 } 206 207 clear_queue: 208 spin_lock_irqsave(&s->vb_lock, flags); 209 cx18_clear_queue(s, VB2_BUF_STATE_QUEUED); 210 spin_unlock_irqrestore(&s->vb_lock, flags); 211 return rc; 212 } 213 214 static void cx18_stop_streaming(struct vb2_queue *vq) 215 { 216 struct cx18_stream *s = vb2_get_drv_priv(vq); 217 unsigned long flags; 218 219 cx18_stop_capture(s, 0); 220 timer_delete_sync(&s->vb_timeout); 221 spin_lock_irqsave(&s->vb_lock, flags); 222 cx18_clear_queue(s, VB2_BUF_STATE_ERROR); 223 spin_unlock_irqrestore(&s->vb_lock, flags); 224 } 225 226 static const struct vb2_ops cx18_vb2_qops = { 227 .queue_setup = cx18_queue_setup, 228 .buf_queue = cx18_buf_queue, 229 .buf_prepare = cx18_buf_prepare, 230 .start_streaming = cx18_start_streaming, 231 .stop_streaming = cx18_stop_streaming, 232 }; 233 234 static int cx18_stream_init(struct cx18 *cx, int type) 235 { 236 struct cx18_stream *s = &cx->streams[type]; 237 int err = 0; 238 239 memset(s, 0, sizeof(*s)); 240 241 /* initialize cx18_stream fields */ 242 s->dvb = NULL; 243 s->cx = cx; 244 s->type = type; 245 s->name = cx18_stream_info[type].name; 246 s->handle = CX18_INVALID_TASK_HANDLE; 247 248 s->dma = cx18_stream_info[type].dma; 249 s->v4l2_dev_caps = cx18_stream_info[type].caps; 250 s->buffers = cx->stream_buffers[type]; 251 s->buf_size = cx->stream_buf_size[type]; 252 INIT_LIST_HEAD(&s->buf_pool); 253 s->bufs_per_mdl = 1; 254 s->mdl_size = s->buf_size * s->bufs_per_mdl; 255 256 init_waitqueue_head(&s->waitq); 257 s->id = -1; 258 spin_lock_init(&s->q_free.lock); 259 cx18_queue_init(&s->q_free); 260 spin_lock_init(&s->q_busy.lock); 261 cx18_queue_init(&s->q_busy); 262 spin_lock_init(&s->q_full.lock); 263 cx18_queue_init(&s->q_full); 264 spin_lock_init(&s->q_idle.lock); 265 cx18_queue_init(&s->q_idle); 266 267 INIT_WORK(&s->out_work_order, cx18_out_work_handler); 268 269 INIT_LIST_HEAD(&s->vb_capture); 270 timer_setup(&s->vb_timeout, cx18_vb_timeout, 0); 271 spin_lock_init(&s->vb_lock); 272 273 if (type == CX18_ENC_STREAM_TYPE_YUV) { 274 s->vb_type = V4L2_BUF_TYPE_VIDEO_CAPTURE; 275 276 /* Assume the previous pixel default */ 277 s->pixelformat = V4L2_PIX_FMT_NV12_16L16; 278 s->vb_bytes_per_frame = cx->cxhdl.height * 720 * 3 / 2; 279 s->vb_bytes_per_line = 720; 280 281 s->vidq.io_modes = VB2_READ | VB2_MMAP | VB2_DMABUF; 282 s->vidq.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; 283 s->vidq.drv_priv = s; 284 s->vidq.buf_struct_size = sizeof(struct cx18_vb2_buffer); 285 s->vidq.ops = &cx18_vb2_qops; 286 s->vidq.mem_ops = &vb2_vmalloc_memops; 287 s->vidq.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; 288 s->vidq.min_queued_buffers = 2; 289 s->vidq.gfp_flags = GFP_DMA32; 290 s->vidq.dev = &cx->pci_dev->dev; 291 s->vidq.lock = &cx->serialize_lock; 292 293 err = vb2_queue_init(&s->vidq); 294 if (err) 295 v4l2_err(&cx->v4l2_dev, "cannot init vb2 queue\n"); 296 s->video_dev.queue = &s->vidq; 297 } 298 return err; 299 } 300 301 static int cx18_prep_dev(struct cx18 *cx, int type) 302 { 303 struct cx18_stream *s = &cx->streams[type]; 304 u32 cap = cx->v4l2_cap; 305 int num_offset = cx18_stream_info[type].num_offset; 306 int num = cx->instance + cx18_first_minor + num_offset; 307 int err; 308 309 /* 310 * These five fields are always initialized. 311 * For analog capture related streams, if video_dev.v4l2_dev == NULL then the 312 * stream is not in use. 313 * For the TS stream, if dvb == NULL then the stream is not in use. 314 * In those cases no other fields but these four can be used. 315 */ 316 s->video_dev.v4l2_dev = NULL; 317 s->dvb = NULL; 318 s->cx = cx; 319 s->type = type; 320 s->name = cx18_stream_info[type].name; 321 322 /* Check whether the radio is supported */ 323 if (type == CX18_ENC_STREAM_TYPE_RAD && !(cap & V4L2_CAP_RADIO)) 324 return 0; 325 326 /* Check whether VBI is supported */ 327 if (type == CX18_ENC_STREAM_TYPE_VBI && 328 !(cap & (V4L2_CAP_VBI_CAPTURE | V4L2_CAP_SLICED_VBI_CAPTURE))) 329 return 0; 330 331 /* User explicitly selected 0 buffers for these streams, so don't 332 create them. */ 333 if (cx18_stream_info[type].dma != DMA_NONE && 334 cx->stream_buffers[type] == 0) { 335 CX18_INFO("Disabled %s device\n", cx18_stream_info[type].name); 336 return 0; 337 } 338 339 err = cx18_stream_init(cx, type); 340 if (err) 341 return err; 342 343 /* Allocate the cx18_dvb struct only for the TS on cards with DTV */ 344 if (type == CX18_ENC_STREAM_TYPE_TS) { 345 if (cx->card->hw_all & CX18_HW_DVB) { 346 s->dvb = kzalloc(sizeof(struct cx18_dvb), GFP_KERNEL); 347 if (s->dvb == NULL) { 348 CX18_ERR("Couldn't allocate cx18_dvb structure for %s\n", 349 s->name); 350 return -ENOMEM; 351 } 352 } else { 353 /* Don't need buffers for the TS, if there is no DVB */ 354 s->buffers = 0; 355 } 356 } 357 358 if (num_offset == -1) 359 return 0; 360 361 /* initialize the v4l2 video device structure */ 362 snprintf(s->video_dev.name, sizeof(s->video_dev.name), "%s %s", 363 cx->v4l2_dev.name, s->name); 364 365 s->video_dev.num = num; 366 s->video_dev.v4l2_dev = &cx->v4l2_dev; 367 if (type == CX18_ENC_STREAM_TYPE_YUV) 368 s->video_dev.fops = &cx18_v4l2_enc_yuv_fops; 369 else 370 s->video_dev.fops = &cx18_v4l2_enc_fops; 371 s->video_dev.release = video_device_release_empty; 372 if (cx->card->video_inputs->video_type == CX18_CARD_INPUT_VID_TUNER) 373 s->video_dev.tvnorms = cx->tuner_std; 374 else 375 s->video_dev.tvnorms = V4L2_STD_ALL; 376 s->video_dev.lock = &cx->serialize_lock; 377 cx18_set_funcs(&s->video_dev); 378 return 0; 379 } 380 381 /* Initialize v4l2 variables and register v4l2 devices */ 382 int cx18_streams_setup(struct cx18 *cx) 383 { 384 int type, ret; 385 386 /* Setup V4L2 Devices */ 387 for (type = 0; type < CX18_MAX_STREAMS; type++) { 388 /* Prepare device */ 389 ret = cx18_prep_dev(cx, type); 390 if (ret < 0) 391 break; 392 393 /* Allocate Stream */ 394 ret = cx18_stream_alloc(&cx->streams[type]); 395 if (ret < 0) 396 break; 397 } 398 if (type == CX18_MAX_STREAMS) 399 return 0; 400 401 /* One or more streams could not be initialized. Clean 'em all up. */ 402 cx18_streams_cleanup(cx, 0); 403 return ret; 404 } 405 406 static int cx18_reg_dev(struct cx18 *cx, int type) 407 { 408 struct cx18_stream *s = &cx->streams[type]; 409 int vfl_type = cx18_stream_info[type].vfl_type; 410 const char *name; 411 int num, ret; 412 413 if (type == CX18_ENC_STREAM_TYPE_TS && s->dvb != NULL) { 414 ret = cx18_dvb_register(s); 415 if (ret < 0) { 416 CX18_ERR("DVB failed to register\n"); 417 return ret; 418 } 419 } 420 421 if (s->video_dev.v4l2_dev == NULL) 422 return 0; 423 424 num = s->video_dev.num; 425 s->video_dev.device_caps = s->v4l2_dev_caps; /* device capabilities */ 426 /* card number + user defined offset + device offset */ 427 if (type != CX18_ENC_STREAM_TYPE_MPG) { 428 struct cx18_stream *s_mpg = &cx->streams[CX18_ENC_STREAM_TYPE_MPG]; 429 430 if (s_mpg->video_dev.v4l2_dev) 431 num = s_mpg->video_dev.num 432 + cx18_stream_info[type].num_offset; 433 } 434 video_set_drvdata(&s->video_dev, s); 435 436 /* Register device. First try the desired minor, then any free one. */ 437 ret = video_register_device_no_warn(&s->video_dev, vfl_type, num); 438 if (ret < 0) { 439 CX18_ERR("Couldn't register v4l2 device for %s (device node number %d)\n", 440 s->name, num); 441 s->video_dev.v4l2_dev = NULL; 442 return ret; 443 } 444 445 name = video_device_node_name(&s->video_dev); 446 447 switch (vfl_type) { 448 case VFL_TYPE_VIDEO: 449 CX18_INFO("Registered device %s for %s (%d x %d.%02d kB)\n", 450 name, s->name, cx->stream_buffers[type], 451 cx->stream_buf_size[type] / 1024, 452 (cx->stream_buf_size[type] * 100 / 1024) % 100); 453 break; 454 455 case VFL_TYPE_RADIO: 456 CX18_INFO("Registered device %s for %s\n", name, s->name); 457 break; 458 459 case VFL_TYPE_VBI: 460 if (cx->stream_buffers[type]) 461 CX18_INFO("Registered device %s for %s (%d x %d bytes)\n", 462 name, s->name, cx->stream_buffers[type], 463 cx->stream_buf_size[type]); 464 else 465 CX18_INFO("Registered device %s for %s\n", 466 name, s->name); 467 break; 468 } 469 470 return 0; 471 } 472 473 /* Register v4l2 devices */ 474 int cx18_streams_register(struct cx18 *cx) 475 { 476 int type; 477 int err; 478 int ret = 0; 479 480 /* Register V4L2 devices */ 481 for (type = 0; type < CX18_MAX_STREAMS; type++) { 482 err = cx18_reg_dev(cx, type); 483 if (err && ret == 0) 484 ret = err; 485 } 486 487 if (ret == 0) 488 return 0; 489 490 /* One or more streams could not be initialized. Clean 'em all up. */ 491 cx18_streams_cleanup(cx, 1); 492 return ret; 493 } 494 495 /* Unregister v4l2 devices */ 496 void cx18_streams_cleanup(struct cx18 *cx, int unregister) 497 { 498 struct video_device *vdev; 499 int type; 500 501 /* Teardown all streams */ 502 for (type = 0; type < CX18_MAX_STREAMS; type++) { 503 504 /* The TS has a cx18_dvb structure, not a video_device */ 505 if (type == CX18_ENC_STREAM_TYPE_TS) { 506 if (cx->streams[type].dvb != NULL) { 507 if (unregister) 508 cx18_dvb_unregister(&cx->streams[type]); 509 kfree(cx->streams[type].dvb); 510 cx->streams[type].dvb = NULL; 511 cx18_stream_free(&cx->streams[type]); 512 } 513 continue; 514 } 515 516 /* No struct video_device, but can have buffers allocated */ 517 if (type == CX18_ENC_STREAM_TYPE_IDX) { 518 /* If the module params didn't inhibit IDX ... */ 519 if (cx->stream_buffers[type] != 0) { 520 cx->stream_buffers[type] = 0; 521 /* 522 * Before calling cx18_stream_free(), 523 * check if the IDX stream was actually set up. 524 * Needed, since the cx18_probe() error path 525 * exits through here as well as normal clean up 526 */ 527 if (cx->streams[type].buffers != 0) 528 cx18_stream_free(&cx->streams[type]); 529 } 530 continue; 531 } 532 533 /* If struct video_device exists, can have buffers allocated */ 534 vdev = &cx->streams[type].video_dev; 535 536 if (vdev->v4l2_dev == NULL) 537 continue; 538 539 cx18_stream_free(&cx->streams[type]); 540 541 if (type == CX18_ENC_STREAM_TYPE_YUV) 542 vb2_video_unregister_device(vdev); 543 else 544 video_unregister_device(vdev); 545 } 546 } 547 548 static void cx18_vbi_setup(struct cx18_stream *s) 549 { 550 struct cx18 *cx = s->cx; 551 int raw = cx18_raw_vbi(cx); 552 u32 data[CX2341X_MBOX_MAX_DATA]; 553 int lines; 554 555 if (cx->is_60hz) { 556 cx->vbi.count = 12; 557 cx->vbi.start[0] = 10; 558 cx->vbi.start[1] = 273; 559 } else { /* PAL/SECAM */ 560 cx->vbi.count = 18; 561 cx->vbi.start[0] = 6; 562 cx->vbi.start[1] = 318; 563 } 564 565 /* setup VBI registers */ 566 if (raw) 567 v4l2_subdev_call(cx->sd_av, vbi, s_raw_fmt, &cx->vbi.in.fmt.vbi); 568 else 569 v4l2_subdev_call(cx->sd_av, vbi, s_sliced_fmt, &cx->vbi.in.fmt.sliced); 570 571 /* 572 * Send the CX18_CPU_SET_RAW_VBI_PARAM API command to setup Encoder Raw 573 * VBI when the first analog capture channel starts, as once it starts 574 * (e.g. MPEG), we can't effect any change in the Encoder Raw VBI setup 575 * (i.e. for the VBI capture channels). We also send it for each 576 * analog capture channel anyway just to make sure we get the proper 577 * behavior 578 */ 579 if (raw) { 580 lines = cx->vbi.count * 2; 581 } else { 582 /* 583 * For 525/60 systems, according to the VIP 2 & BT.656 std: 584 * The EAV RP code's Field bit toggles on line 4, a few lines 585 * after the Vertcal Blank bit has already toggled. 586 * Tell the encoder to capture 21-4+1=18 lines per field, 587 * since we want lines 10 through 21. 588 * 589 * For 625/50 systems, according to the VIP 2 & BT.656 std: 590 * The EAV RP code's Field bit toggles on line 1, a few lines 591 * after the Vertcal Blank bit has already toggled. 592 * (We've actually set the digitizer so that the Field bit 593 * toggles on line 2.) Tell the encoder to capture 23-2+1=22 594 * lines per field, since we want lines 6 through 23. 595 */ 596 lines = cx->is_60hz ? (21 - 4 + 1) * 2 : (23 - 2 + 1) * 2; 597 } 598 599 data[0] = s->handle; 600 /* Lines per field */ 601 data[1] = (lines / 2) | ((lines / 2) << 16); 602 /* bytes per line */ 603 data[2] = (raw ? VBI_ACTIVE_SAMPLES 604 : (cx->is_60hz ? VBI_HBLANK_SAMPLES_60HZ 605 : VBI_HBLANK_SAMPLES_50HZ)); 606 /* Every X number of frames a VBI interrupt arrives 607 (frames as in 25 or 30 fps) */ 608 data[3] = 1; 609 /* 610 * Set the SAV/EAV RP codes to look for as start/stop points 611 * when in VIP-1.1 mode 612 */ 613 if (raw) { 614 /* 615 * Start codes for beginning of "active" line in vertical blank 616 * 0x20 ( VerticalBlank ) 617 * 0x60 ( EvenField VerticalBlank ) 618 */ 619 data[4] = 0x20602060; 620 /* 621 * End codes for end of "active" raw lines and regular lines 622 * 0x30 ( VerticalBlank HorizontalBlank) 623 * 0x70 ( EvenField VerticalBlank HorizontalBlank) 624 * 0x90 (Task HorizontalBlank) 625 * 0xd0 (Task EvenField HorizontalBlank) 626 */ 627 data[5] = 0x307090d0; 628 } else { 629 /* 630 * End codes for active video, we want data in the hblank region 631 * 0xb0 (Task 0 VerticalBlank HorizontalBlank) 632 * 0xf0 (Task EvenField VerticalBlank HorizontalBlank) 633 * 634 * Since the V bit is only allowed to toggle in the EAV RP code, 635 * just before the first active region line, these two 636 * are problematic: 637 * 0x90 (Task HorizontalBlank) 638 * 0xd0 (Task EvenField HorizontalBlank) 639 * 640 * We have set the digitzer such that we don't have to worry 641 * about these problem codes. 642 */ 643 data[4] = 0xB0F0B0F0; 644 /* 645 * Start codes for beginning of active line in vertical blank 646 * 0xa0 (Task VerticalBlank ) 647 * 0xe0 (Task EvenField VerticalBlank ) 648 */ 649 data[5] = 0xA0E0A0E0; 650 } 651 652 CX18_DEBUG_INFO("Setup VBI h: %d lines %x bpl %d fr %d %x %x\n", 653 data[0], data[1], data[2], data[3], data[4], data[5]); 654 655 cx18_api(cx, CX18_CPU_SET_RAW_VBI_PARAM, 6, data); 656 } 657 658 void cx18_stream_rotate_idx_mdls(struct cx18 *cx) 659 { 660 struct cx18_stream *s = &cx->streams[CX18_ENC_STREAM_TYPE_IDX]; 661 struct cx18_mdl *mdl; 662 663 if (!cx18_stream_enabled(s)) 664 return; 665 666 /* Return if the firmware is not running low on MDLs */ 667 if ((atomic_read(&s->q_free.depth) + atomic_read(&s->q_busy.depth)) >= 668 CX18_ENC_STREAM_TYPE_IDX_FW_MDL_MIN) 669 return; 670 671 /* Return if there are no MDLs to rotate back to the firmware */ 672 if (atomic_read(&s->q_full.depth) < 2) 673 return; 674 675 /* 676 * Take the oldest IDX MDL still holding data, and discard its index 677 * entries by scheduling the MDL to go back to the firmware 678 */ 679 mdl = cx18_dequeue(s, &s->q_full); 680 if (mdl != NULL) 681 cx18_enqueue(s, mdl, &s->q_free); 682 } 683 684 static 685 struct cx18_queue *_cx18_stream_put_mdl_fw(struct cx18_stream *s, 686 struct cx18_mdl *mdl) 687 { 688 struct cx18 *cx = s->cx; 689 struct cx18_queue *q; 690 691 /* Don't give it to the firmware, if we're not running a capture */ 692 if (s->handle == CX18_INVALID_TASK_HANDLE || 693 test_bit(CX18_F_S_STOPPING, &s->s_flags) || 694 !test_bit(CX18_F_S_STREAMING, &s->s_flags)) 695 return cx18_enqueue(s, mdl, &s->q_free); 696 697 q = cx18_enqueue(s, mdl, &s->q_busy); 698 if (q != &s->q_busy) 699 return q; /* The firmware has the max MDLs it can handle */ 700 701 cx18_mdl_sync_for_device(s, mdl); 702 cx18_vapi(cx, CX18_CPU_DE_SET_MDL, 5, s->handle, 703 (void __iomem *) &cx->scb->cpu_mdl[mdl->id] - cx->enc_mem, 704 s->bufs_per_mdl, mdl->id, s->mdl_size); 705 return q; 706 } 707 708 static 709 void _cx18_stream_load_fw_queue(struct cx18_stream *s) 710 { 711 struct cx18_queue *q; 712 struct cx18_mdl *mdl; 713 714 if (atomic_read(&s->q_free.depth) == 0 || 715 atomic_read(&s->q_busy.depth) >= CX18_MAX_FW_MDLS_PER_STREAM) 716 return; 717 718 /* Move from q_free to q_busy notifying the firmware, until the limit */ 719 do { 720 mdl = cx18_dequeue(s, &s->q_free); 721 if (mdl == NULL) 722 break; 723 q = _cx18_stream_put_mdl_fw(s, mdl); 724 } while (atomic_read(&s->q_busy.depth) < CX18_MAX_FW_MDLS_PER_STREAM 725 && q == &s->q_busy); 726 } 727 728 void cx18_out_work_handler(struct work_struct *work) 729 { 730 struct cx18_stream *s = 731 container_of(work, struct cx18_stream, out_work_order); 732 733 _cx18_stream_load_fw_queue(s); 734 } 735 736 static void cx18_stream_configure_mdls(struct cx18_stream *s) 737 { 738 cx18_unload_queues(s); 739 740 switch (s->type) { 741 case CX18_ENC_STREAM_TYPE_YUV: 742 /* 743 * Height should be a multiple of 32 lines. 744 * Set the MDL size to the exact size needed for one frame. 745 * Use enough buffers per MDL to cover the MDL size 746 */ 747 if (s->pixelformat == V4L2_PIX_FMT_NV12_16L16) 748 s->mdl_size = 720 * s->cx->cxhdl.height * 3 / 2; 749 else 750 s->mdl_size = 720 * s->cx->cxhdl.height * 2; 751 s->bufs_per_mdl = s->mdl_size / s->buf_size; 752 if (s->mdl_size % s->buf_size) 753 s->bufs_per_mdl++; 754 break; 755 case CX18_ENC_STREAM_TYPE_VBI: 756 s->bufs_per_mdl = 1; 757 if (cx18_raw_vbi(s->cx)) { 758 s->mdl_size = (s->cx->is_60hz ? 12 : 18) 759 * 2 * VBI_ACTIVE_SAMPLES; 760 } else { 761 /* 762 * See comment in cx18_vbi_setup() below about the 763 * extra lines we capture in sliced VBI mode due to 764 * the lines on which EAV RP codes toggle. 765 */ 766 s->mdl_size = s->cx->is_60hz 767 ? (21 - 4 + 1) * 2 * VBI_HBLANK_SAMPLES_60HZ 768 : (23 - 2 + 1) * 2 * VBI_HBLANK_SAMPLES_50HZ; 769 } 770 break; 771 default: 772 s->bufs_per_mdl = 1; 773 s->mdl_size = s->buf_size * s->bufs_per_mdl; 774 break; 775 } 776 777 cx18_load_queues(s); 778 } 779 780 int cx18_start_v4l2_encode_stream(struct cx18_stream *s) 781 { 782 u32 data[MAX_MB_ARGUMENTS]; 783 struct cx18 *cx = s->cx; 784 int captype = 0; 785 struct cx18_stream *s_idx; 786 787 if (!cx18_stream_enabled(s)) 788 return -EINVAL; 789 790 CX18_DEBUG_INFO("Start encoder stream %s\n", s->name); 791 792 switch (s->type) { 793 case CX18_ENC_STREAM_TYPE_MPG: 794 captype = CAPTURE_CHANNEL_TYPE_MPEG; 795 cx->mpg_data_received = cx->vbi_data_inserted = 0; 796 cx->dualwatch_jiffies = jiffies; 797 cx->dualwatch_stereo_mode = v4l2_ctrl_g_ctrl(cx->cxhdl.audio_mode); 798 cx->search_pack_header = 0; 799 break; 800 801 case CX18_ENC_STREAM_TYPE_IDX: 802 captype = CAPTURE_CHANNEL_TYPE_INDEX; 803 break; 804 case CX18_ENC_STREAM_TYPE_TS: 805 captype = CAPTURE_CHANNEL_TYPE_TS; 806 break; 807 case CX18_ENC_STREAM_TYPE_YUV: 808 captype = CAPTURE_CHANNEL_TYPE_YUV; 809 break; 810 case CX18_ENC_STREAM_TYPE_PCM: 811 captype = CAPTURE_CHANNEL_TYPE_PCM; 812 break; 813 case CX18_ENC_STREAM_TYPE_VBI: 814 #ifdef CX18_ENCODER_PARSES_SLICED 815 captype = cx18_raw_vbi(cx) ? 816 CAPTURE_CHANNEL_TYPE_VBI : CAPTURE_CHANNEL_TYPE_SLICED_VBI; 817 #else 818 /* 819 * Currently we set things up so that Sliced VBI from the 820 * digitizer is handled as Raw VBI by the encoder 821 */ 822 captype = CAPTURE_CHANNEL_TYPE_VBI; 823 #endif 824 cx->vbi.frame = 0; 825 cx->vbi.inserted_frame = 0; 826 memset(cx->vbi.sliced_mpeg_size, 827 0, sizeof(cx->vbi.sliced_mpeg_size)); 828 break; 829 default: 830 return -EINVAL; 831 } 832 833 /* Clear Streamoff flags in case left from last capture */ 834 clear_bit(CX18_F_S_STREAMOFF, &s->s_flags); 835 836 cx18_vapi_result(cx, data, CX18_CREATE_TASK, 1, CPU_CMD_MASK_CAPTURE); 837 s->handle = data[0]; 838 cx18_vapi(cx, CX18_CPU_SET_CHANNEL_TYPE, 2, s->handle, captype); 839 840 /* 841 * For everything but CAPTURE_CHANNEL_TYPE_TS, play it safe and 842 * set up all the parameters, as it is not obvious which parameters the 843 * firmware shares across capture channel types and which it does not. 844 * 845 * Some of the cx18_vapi() calls below apply to only certain capture 846 * channel types. We're hoping there's no harm in calling most of them 847 * anyway, as long as the values are all consistent. Setting some 848 * shared parameters will have no effect once an analog capture channel 849 * has started streaming. 850 */ 851 if (captype != CAPTURE_CHANNEL_TYPE_TS) { 852 cx18_vapi(cx, CX18_CPU_SET_VER_CROP_LINE, 2, s->handle, 0); 853 cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 3, s->handle, 3, 1); 854 cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 3, s->handle, 8, 0); 855 cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 3, s->handle, 4, 1); 856 857 /* 858 * Audio related reset according to 859 * Documentation/driver-api/media/drivers/cx2341x-devel.rst 860 */ 861 if (atomic_read(&cx->ana_capturing) == 0) 862 cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 2, 863 s->handle, 12); 864 865 /* 866 * Number of lines for Field 1 & Field 2 according to 867 * Documentation/driver-api/media/drivers/cx2341x-devel.rst 868 * Field 1 is 312 for 625 line systems in BT.656 869 * Field 2 is 313 for 625 line systems in BT.656 870 */ 871 cx18_vapi(cx, CX18_CPU_SET_CAPTURE_LINE_NO, 3, 872 s->handle, 312, 313); 873 874 if (cx->v4l2_cap & V4L2_CAP_VBI_CAPTURE) 875 cx18_vbi_setup(s); 876 877 /* 878 * Select to receive I, P, and B frame index entries, if the 879 * index stream is enabled. Otherwise disable index entry 880 * generation. 881 */ 882 s_idx = &cx->streams[CX18_ENC_STREAM_TYPE_IDX]; 883 cx18_vapi_result(cx, data, CX18_CPU_SET_INDEXTABLE, 2, 884 s->handle, cx18_stream_enabled(s_idx) ? 7 : 0); 885 886 /* Call out to the common CX2341x API setup for user controls */ 887 cx->cxhdl.priv = s; 888 cx2341x_handler_setup(&cx->cxhdl); 889 890 /* 891 * When starting a capture and we're set for radio, 892 * ensure the video is muted, despite the user control. 893 */ 894 if (!cx->cxhdl.video_mute && 895 test_bit(CX18_F_I_RADIO_USER, &cx->i_flags)) 896 cx18_vapi(cx, CX18_CPU_SET_VIDEO_MUTE, 2, s->handle, 897 (v4l2_ctrl_g_ctrl(cx->cxhdl.video_mute_yuv) << 8) | 1); 898 899 /* Enable the Video Format Converter for UYVY 4:2:2 support, 900 * rather than the default HM12 Macroblovk 4:2:0 support. 901 */ 902 if (captype == CAPTURE_CHANNEL_TYPE_YUV) { 903 if (s->pixelformat == V4L2_PIX_FMT_UYVY) 904 cx18_vapi(cx, CX18_CPU_SET_VFC_PARAM, 2, 905 s->handle, 1); 906 else 907 /* If in doubt, default to HM12 */ 908 cx18_vapi(cx, CX18_CPU_SET_VFC_PARAM, 2, 909 s->handle, 0); 910 } 911 } 912 913 if (atomic_read(&cx->tot_capturing) == 0) { 914 cx2341x_handler_set_busy(&cx->cxhdl, 1); 915 clear_bit(CX18_F_I_EOS, &cx->i_flags); 916 cx18_write_reg(cx, 7, CX18_DSP0_INTERRUPT_MASK); 917 } 918 919 cx18_vapi(cx, CX18_CPU_DE_SET_MDL_ACK, 3, s->handle, 920 (void __iomem *)&cx->scb->cpu_mdl_ack[s->type][0] - cx->enc_mem, 921 (void __iomem *)&cx->scb->cpu_mdl_ack[s->type][1] - cx->enc_mem); 922 923 /* Init all the cpu_mdls for this stream */ 924 cx18_stream_configure_mdls(s); 925 _cx18_stream_load_fw_queue(s); 926 927 /* begin_capture */ 928 if (cx18_vapi(cx, CX18_CPU_CAPTURE_START, 1, s->handle)) { 929 CX18_DEBUG_WARN("Error starting capture!\n"); 930 /* Ensure we're really not capturing before releasing MDLs */ 931 set_bit(CX18_F_S_STOPPING, &s->s_flags); 932 if (s->type == CX18_ENC_STREAM_TYPE_MPG) 933 cx18_vapi(cx, CX18_CPU_CAPTURE_STOP, 2, s->handle, 1); 934 else 935 cx18_vapi(cx, CX18_CPU_CAPTURE_STOP, 1, s->handle); 936 clear_bit(CX18_F_S_STREAMING, &s->s_flags); 937 /* FIXME - CX18_F_S_STREAMOFF as well? */ 938 cx18_vapi(cx, CX18_CPU_DE_RELEASE_MDL, 1, s->handle); 939 cx18_vapi(cx, CX18_DESTROY_TASK, 1, s->handle); 940 s->handle = CX18_INVALID_TASK_HANDLE; 941 clear_bit(CX18_F_S_STOPPING, &s->s_flags); 942 if (atomic_read(&cx->tot_capturing) == 0) { 943 set_bit(CX18_F_I_EOS, &cx->i_flags); 944 cx18_write_reg(cx, 5, CX18_DSP0_INTERRUPT_MASK); 945 } 946 return -EINVAL; 947 } 948 949 /* you're live! sit back and await interrupts :) */ 950 if (captype != CAPTURE_CHANNEL_TYPE_TS) 951 atomic_inc(&cx->ana_capturing); 952 atomic_inc(&cx->tot_capturing); 953 return 0; 954 } 955 EXPORT_SYMBOL(cx18_start_v4l2_encode_stream); 956 957 void cx18_stop_all_captures(struct cx18 *cx) 958 { 959 int i; 960 961 for (i = CX18_MAX_STREAMS - 1; i >= 0; i--) { 962 struct cx18_stream *s = &cx->streams[i]; 963 964 if (!cx18_stream_enabled(s)) 965 continue; 966 if (test_bit(CX18_F_S_STREAMING, &s->s_flags)) 967 cx18_stop_v4l2_encode_stream(s, 0); 968 } 969 } 970 971 int cx18_stop_v4l2_encode_stream(struct cx18_stream *s, int gop_end) 972 { 973 struct cx18 *cx = s->cx; 974 975 if (!cx18_stream_enabled(s)) 976 return -EINVAL; 977 978 /* This function assumes that you are allowed to stop the capture 979 and that we are actually capturing */ 980 981 CX18_DEBUG_INFO("Stop Capture\n"); 982 983 if (atomic_read(&cx->tot_capturing) == 0) 984 return 0; 985 986 set_bit(CX18_F_S_STOPPING, &s->s_flags); 987 if (s->type == CX18_ENC_STREAM_TYPE_MPG) 988 cx18_vapi(cx, CX18_CPU_CAPTURE_STOP, 2, s->handle, !gop_end); 989 else 990 cx18_vapi(cx, CX18_CPU_CAPTURE_STOP, 1, s->handle); 991 992 if (s->type == CX18_ENC_STREAM_TYPE_MPG && gop_end) { 993 CX18_INFO("ignoring gop_end: not (yet?) supported by the firmware\n"); 994 } 995 996 if (s->type != CX18_ENC_STREAM_TYPE_TS) 997 atomic_dec(&cx->ana_capturing); 998 atomic_dec(&cx->tot_capturing); 999 1000 /* Clear capture and no-read bits */ 1001 clear_bit(CX18_F_S_STREAMING, &s->s_flags); 1002 1003 /* Tell the CX23418 it can't use our buffers anymore */ 1004 cx18_vapi(cx, CX18_CPU_DE_RELEASE_MDL, 1, s->handle); 1005 1006 cx18_vapi(cx, CX18_DESTROY_TASK, 1, s->handle); 1007 s->handle = CX18_INVALID_TASK_HANDLE; 1008 clear_bit(CX18_F_S_STOPPING, &s->s_flags); 1009 1010 if (atomic_read(&cx->tot_capturing) > 0) 1011 return 0; 1012 1013 cx2341x_handler_set_busy(&cx->cxhdl, 0); 1014 cx18_write_reg(cx, 5, CX18_DSP0_INTERRUPT_MASK); 1015 wake_up(&s->waitq); 1016 1017 return 0; 1018 } 1019 EXPORT_SYMBOL(cx18_stop_v4l2_encode_stream); 1020 1021 u32 cx18_find_handle(struct cx18 *cx) 1022 { 1023 int i; 1024 1025 /* find first available handle to be used for global settings */ 1026 for (i = 0; i < CX18_MAX_STREAMS; i++) { 1027 struct cx18_stream *s = &cx->streams[i]; 1028 1029 if (s->video_dev.v4l2_dev && (s->handle != CX18_INVALID_TASK_HANDLE)) 1030 return s->handle; 1031 } 1032 return CX18_INVALID_TASK_HANDLE; 1033 } 1034 1035 struct cx18_stream *cx18_handle_to_stream(struct cx18 *cx, u32 handle) 1036 { 1037 int i; 1038 struct cx18_stream *s; 1039 1040 if (handle == CX18_INVALID_TASK_HANDLE) 1041 return NULL; 1042 1043 for (i = 0; i < CX18_MAX_STREAMS; i++) { 1044 s = &cx->streams[i]; 1045 if (s->handle != handle) 1046 continue; 1047 if (cx18_stream_enabled(s)) 1048 return s; 1049 } 1050 return NULL; 1051 } 1052