xref: /linux/drivers/media/pci/cx18/cx18-scb.h (revision e5c86679d5e864947a52fb31e45a425dea3e7fa9)
1 /*
2  *  cx18 System Control Block initialization
3  *
4  *  Copyright (C) 2007  Hans Verkuil <hverkuil@xs4all.nl>
5  *  Copyright (C) 2008  Andy Walls <awalls@md.metrocast.net>
6  *
7  *  This program is free software; you can redistribute it and/or modify
8  *  it under the terms of the GNU General Public License as published by
9  *  the Free Software Foundation; either version 2 of the License, or
10  *  (at your option) any later version.
11  *
12  *  This program is distributed in the hope that it will be useful,
13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  *  GNU General Public License for more details.
16  */
17 
18 #ifndef CX18_SCB_H
19 #define CX18_SCB_H
20 
21 #include "cx18-mailbox.h"
22 
23 /* NOTE: All ACK interrupts are in the SW2 register.  All non-ACK interrupts
24    are in the SW1 register. */
25 
26 #define IRQ_APU_TO_CPU         0x00000001
27 #define IRQ_CPU_TO_APU_ACK     0x00000001
28 #define IRQ_HPU_TO_CPU         0x00000002
29 #define IRQ_CPU_TO_HPU_ACK     0x00000002
30 #define IRQ_PPU_TO_CPU         0x00000004
31 #define IRQ_CPU_TO_PPU_ACK     0x00000004
32 #define IRQ_EPU_TO_CPU         0x00000008
33 #define IRQ_CPU_TO_EPU_ACK     0x00000008
34 
35 #define IRQ_CPU_TO_APU         0x00000010
36 #define IRQ_APU_TO_CPU_ACK     0x00000010
37 #define IRQ_HPU_TO_APU         0x00000020
38 #define IRQ_APU_TO_HPU_ACK     0x00000020
39 #define IRQ_PPU_TO_APU         0x00000040
40 #define IRQ_APU_TO_PPU_ACK     0x00000040
41 #define IRQ_EPU_TO_APU         0x00000080
42 #define IRQ_APU_TO_EPU_ACK     0x00000080
43 
44 #define IRQ_CPU_TO_HPU         0x00000100
45 #define IRQ_HPU_TO_CPU_ACK     0x00000100
46 #define IRQ_APU_TO_HPU         0x00000200
47 #define IRQ_HPU_TO_APU_ACK     0x00000200
48 #define IRQ_PPU_TO_HPU         0x00000400
49 #define IRQ_HPU_TO_PPU_ACK     0x00000400
50 #define IRQ_EPU_TO_HPU         0x00000800
51 #define IRQ_HPU_TO_EPU_ACK     0x00000800
52 
53 #define IRQ_CPU_TO_PPU         0x00001000
54 #define IRQ_PPU_TO_CPU_ACK     0x00001000
55 #define IRQ_APU_TO_PPU         0x00002000
56 #define IRQ_PPU_TO_APU_ACK     0x00002000
57 #define IRQ_HPU_TO_PPU         0x00004000
58 #define IRQ_PPU_TO_HPU_ACK     0x00004000
59 #define IRQ_EPU_TO_PPU         0x00008000
60 #define IRQ_PPU_TO_EPU_ACK     0x00008000
61 
62 #define IRQ_CPU_TO_EPU         0x00010000
63 #define IRQ_EPU_TO_CPU_ACK     0x00010000
64 #define IRQ_APU_TO_EPU         0x00020000
65 #define IRQ_EPU_TO_APU_ACK     0x00020000
66 #define IRQ_HPU_TO_EPU         0x00040000
67 #define IRQ_EPU_TO_HPU_ACK     0x00040000
68 #define IRQ_PPU_TO_EPU         0x00080000
69 #define IRQ_EPU_TO_PPU_ACK     0x00080000
70 
71 #define SCB_OFFSET  0xDC0000
72 
73 /* If Firmware uses fixed memory map, it shall not allocate the area
74    between SCB_OFFSET and SCB_OFFSET+SCB_RESERVED_SIZE-1 inclusive */
75 #define SCB_RESERVED_SIZE 0x10000
76 
77 
78 /* This structure is used by EPU to provide memory descriptors in its memory */
79 struct cx18_mdl_ent {
80     u32 paddr;  /* Physical address of a buffer segment */
81     u32 length; /* Length of the buffer segment */
82 };
83 
84 struct cx18_scb {
85 	/* These fields form the System Control Block which is used at boot time
86 	   for localizing the IPC data as well as the code positions for all
87 	   processors. The offsets are from the start of this struct. */
88 
89 	/* Offset where to find the Inter-Processor Communication data */
90 	u32 ipc_offset;
91 	u32 reserved01[7];
92 	/* Offset where to find the start of the CPU code */
93 	u32 cpu_code_offset;
94 	u32 reserved02[3];
95 	/* Offset where to find the start of the APU code */
96 	u32 apu_code_offset;
97 	u32 reserved03[3];
98 	/* Offset where to find the start of the HPU code */
99 	u32 hpu_code_offset;
100 	u32 reserved04[3];
101 	/* Offset where to find the start of the PPU code */
102 	u32 ppu_code_offset;
103 	u32 reserved05[3];
104 
105 	/* These fields form Inter-Processor Communication data which is used
106 	   by all processors to locate the information needed for communicating
107 	   with other processors */
108 
109 	/* Fields for CPU: */
110 
111 	/* bit 0: 1/0 processor ready/not ready. Set other bits to 0. */
112 	u32 cpu_state;
113 	u32 reserved1[7];
114 	/* Offset to the mailbox used for sending commands from APU to CPU */
115 	u32 apu2cpu_mb_offset;
116 	/* Value to write to register SW1 register set (0xC7003100) after the
117 	   command is ready */
118 	u32 apu2cpu_irq;
119 	/* Value to write to register SW2 register set (0xC7003140) after the
120 	   command is cleared */
121 	u32 cpu2apu_irq_ack;
122 	u32 reserved2[13];
123 
124 	u32 hpu2cpu_mb_offset;
125 	u32 hpu2cpu_irq;
126 	u32 cpu2hpu_irq_ack;
127 	u32 reserved3[13];
128 
129 	u32 ppu2cpu_mb_offset;
130 	u32 ppu2cpu_irq;
131 	u32 cpu2ppu_irq_ack;
132 	u32 reserved4[13];
133 
134 	u32 epu2cpu_mb_offset;
135 	u32 epu2cpu_irq;
136 	u32 cpu2epu_irq_ack;
137 	u32 reserved5[13];
138 	u32 reserved6[8];
139 
140 	/* Fields for APU: */
141 
142 	u32 apu_state;
143 	u32 reserved11[7];
144 	u32 cpu2apu_mb_offset;
145 	u32 cpu2apu_irq;
146 	u32 apu2cpu_irq_ack;
147 	u32 reserved12[13];
148 
149 	u32 hpu2apu_mb_offset;
150 	u32 hpu2apu_irq;
151 	u32 apu2hpu_irq_ack;
152 	u32 reserved13[13];
153 
154 	u32 ppu2apu_mb_offset;
155 	u32 ppu2apu_irq;
156 	u32 apu2ppu_irq_ack;
157 	u32 reserved14[13];
158 
159 	u32 epu2apu_mb_offset;
160 	u32 epu2apu_irq;
161 	u32 apu2epu_irq_ack;
162 	u32 reserved15[13];
163 	u32 reserved16[8];
164 
165 	/* Fields for HPU: */
166 
167 	u32 hpu_state;
168 	u32 reserved21[7];
169 	u32 cpu2hpu_mb_offset;
170 	u32 cpu2hpu_irq;
171 	u32 hpu2cpu_irq_ack;
172 	u32 reserved22[13];
173 
174 	u32 apu2hpu_mb_offset;
175 	u32 apu2hpu_irq;
176 	u32 hpu2apu_irq_ack;
177 	u32 reserved23[13];
178 
179 	u32 ppu2hpu_mb_offset;
180 	u32 ppu2hpu_irq;
181 	u32 hpu2ppu_irq_ack;
182 	u32 reserved24[13];
183 
184 	u32 epu2hpu_mb_offset;
185 	u32 epu2hpu_irq;
186 	u32 hpu2epu_irq_ack;
187 	u32 reserved25[13];
188 	u32 reserved26[8];
189 
190 	/* Fields for PPU: */
191 
192 	u32 ppu_state;
193 	u32 reserved31[7];
194 	u32 cpu2ppu_mb_offset;
195 	u32 cpu2ppu_irq;
196 	u32 ppu2cpu_irq_ack;
197 	u32 reserved32[13];
198 
199 	u32 apu2ppu_mb_offset;
200 	u32 apu2ppu_irq;
201 	u32 ppu2apu_irq_ack;
202 	u32 reserved33[13];
203 
204 	u32 hpu2ppu_mb_offset;
205 	u32 hpu2ppu_irq;
206 	u32 ppu2hpu_irq_ack;
207 	u32 reserved34[13];
208 
209 	u32 epu2ppu_mb_offset;
210 	u32 epu2ppu_irq;
211 	u32 ppu2epu_irq_ack;
212 	u32 reserved35[13];
213 	u32 reserved36[8];
214 
215 	/* Fields for EPU: */
216 
217 	u32 epu_state;
218 	u32 reserved41[7];
219 	u32 cpu2epu_mb_offset;
220 	u32 cpu2epu_irq;
221 	u32 epu2cpu_irq_ack;
222 	u32 reserved42[13];
223 
224 	u32 apu2epu_mb_offset;
225 	u32 apu2epu_irq;
226 	u32 epu2apu_irq_ack;
227 	u32 reserved43[13];
228 
229 	u32 hpu2epu_mb_offset;
230 	u32 hpu2epu_irq;
231 	u32 epu2hpu_irq_ack;
232 	u32 reserved44[13];
233 
234 	u32 ppu2epu_mb_offset;
235 	u32 ppu2epu_irq;
236 	u32 epu2ppu_irq_ack;
237 	u32 reserved45[13];
238 	u32 reserved46[8];
239 
240 	u32 semaphores[8];  /* Semaphores */
241 
242 	u32 reserved50[32]; /* Reserved for future use */
243 
244 	struct cx18_mailbox  apu2cpu_mb;
245 	struct cx18_mailbox  hpu2cpu_mb;
246 	struct cx18_mailbox  ppu2cpu_mb;
247 	struct cx18_mailbox  epu2cpu_mb;
248 
249 	struct cx18_mailbox  cpu2apu_mb;
250 	struct cx18_mailbox  hpu2apu_mb;
251 	struct cx18_mailbox  ppu2apu_mb;
252 	struct cx18_mailbox  epu2apu_mb;
253 
254 	struct cx18_mailbox  cpu2hpu_mb;
255 	struct cx18_mailbox  apu2hpu_mb;
256 	struct cx18_mailbox  ppu2hpu_mb;
257 	struct cx18_mailbox  epu2hpu_mb;
258 
259 	struct cx18_mailbox  cpu2ppu_mb;
260 	struct cx18_mailbox  apu2ppu_mb;
261 	struct cx18_mailbox  hpu2ppu_mb;
262 	struct cx18_mailbox  epu2ppu_mb;
263 
264 	struct cx18_mailbox  cpu2epu_mb;
265 	struct cx18_mailbox  apu2epu_mb;
266 	struct cx18_mailbox  hpu2epu_mb;
267 	struct cx18_mailbox  ppu2epu_mb;
268 
269 	struct cx18_mdl_ack  cpu_mdl_ack[CX18_MAX_STREAMS][CX18_MAX_MDL_ACKS];
270 	struct cx18_mdl_ent  cpu_mdl[1];
271 };
272 
273 void cx18_init_scb(struct cx18 *cx);
274 
275 #endif
276