1 /* 2 * cx18 ADEC audio functions 3 * 4 * Derived from cx25840-audio.c 5 * 6 * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl> 7 * Copyright (C) 2008 Andy Walls <awalls@md.metrocast.net> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 2 12 * of the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 */ 19 20 #include "cx18-driver.h" 21 22 static int set_audclk_freq(struct cx18 *cx, u32 freq) 23 { 24 struct cx18_av_state *state = &cx->av_state; 25 26 if (freq != 32000 && freq != 44100 && freq != 48000) 27 return -EINVAL; 28 29 /* 30 * The PLL parameters are based on the external crystal frequency that 31 * would ideally be: 32 * 33 * NTSC Color subcarrier freq * 8 = 34 * 4.5 MHz/286 * 455/2 * 8 = 28.63636363... MHz 35 * 36 * The accidents of history and rationale that explain from where this 37 * combination of magic numbers originate can be found in: 38 * 39 * [1] Abrahams, I. C., "Choice of Chrominance Subcarrier Frequency in 40 * the NTSC Standards", Proceedings of the I-R-E, January 1954, pp 79-80 41 * 42 * [2] Abrahams, I. C., "The 'Frequency Interleaving' Principle in the 43 * NTSC Standards", Proceedings of the I-R-E, January 1954, pp 81-83 44 * 45 * As Mike Bradley has rightly pointed out, it's not the exact crystal 46 * frequency that matters, only that all parts of the driver and 47 * firmware are using the same value (close to the ideal value). 48 * 49 * Since I have a strong suspicion that, if the firmware ever assumes a 50 * crystal value at all, it will assume 28.636360 MHz, the crystal 51 * freq used in calculations in this driver will be: 52 * 53 * xtal_freq = 28.636360 MHz 54 * 55 * an error of less than 0.13 ppm which is way, way better than any off 56 * the shelf crystal will have for accuracy anyway. 57 * 58 * Below I aim to run the PLLs' VCOs near 400 MHz to minimze error. 59 * 60 * Many thanks to Jeff Campbell and Mike Bradley for their extensive 61 * investigation, experimentation, testing, and suggested solutions of 62 * of audio/video sync problems with SVideo and CVBS captures. 63 */ 64 65 if (state->aud_input > CX18_AV_AUDIO_SERIAL2) { 66 switch (freq) { 67 case 32000: 68 /* 69 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 70 * AUX_PLL Integer = 0x0d, AUX PLL Post Divider = 0x20 71 */ 72 cx18_av_write4(cx, 0x108, 0x200d040f); 73 74 /* VID_PLL Fraction = 0x2be2fe */ 75 /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/ 76 cx18_av_write4(cx, 0x10c, 0x002be2fe); 77 78 /* AUX_PLL Fraction = 0x176740c */ 79 /* xtal * 0xd.bb3a060/0x20 = 32000 * 384: 393 MHz p-pd*/ 80 cx18_av_write4(cx, 0x110, 0x0176740c); 81 82 /* src3/4/6_ctl */ 83 /* 0x1.f77f = (4 * xtal/8*2/455) / 32000 */ 84 cx18_av_write4(cx, 0x900, 0x0801f77f); 85 cx18_av_write4(cx, 0x904, 0x0801f77f); 86 cx18_av_write4(cx, 0x90c, 0x0801f77f); 87 88 /* SA_MCLK_SEL=1, SA_MCLK_DIV=0x20 */ 89 cx18_av_write(cx, 0x127, 0x60); 90 91 /* AUD_COUNT = 0x2fff = 8 samples * 4 * 384 - 1 */ 92 cx18_av_write4(cx, 0x12c, 0x11202fff); 93 94 /* 95 * EN_AV_LOCK = 0 96 * VID_COUNT = 0x0d2ef8 = 107999.000 * 8 = 97 * ((8 samples/32,000) * (13,500,000 * 8) * 4 - 1) * 8 98 */ 99 cx18_av_write4(cx, 0x128, 0xa00d2ef8); 100 break; 101 102 case 44100: 103 /* 104 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 105 * AUX_PLL Integer = 0x0e, AUX PLL Post Divider = 0x18 106 */ 107 cx18_av_write4(cx, 0x108, 0x180e040f); 108 109 /* VID_PLL Fraction = 0x2be2fe */ 110 /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/ 111 cx18_av_write4(cx, 0x10c, 0x002be2fe); 112 113 /* AUX_PLL Fraction = 0x062a1f2 */ 114 /* xtal * 0xe.3150f90/0x18 = 44100 * 384: 406 MHz p-pd*/ 115 cx18_av_write4(cx, 0x110, 0x0062a1f2); 116 117 /* src3/4/6_ctl */ 118 /* 0x1.6d59 = (4 * xtal/8*2/455) / 44100 */ 119 cx18_av_write4(cx, 0x900, 0x08016d59); 120 cx18_av_write4(cx, 0x904, 0x08016d59); 121 cx18_av_write4(cx, 0x90c, 0x08016d59); 122 123 /* SA_MCLK_SEL=1, SA_MCLK_DIV=0x18 */ 124 cx18_av_write(cx, 0x127, 0x58); 125 126 /* AUD_COUNT = 0x92ff = 49 samples * 2 * 384 - 1 */ 127 cx18_av_write4(cx, 0x12c, 0x112092ff); 128 129 /* 130 * EN_AV_LOCK = 0 131 * VID_COUNT = 0x1d4bf8 = 239999.000 * 8 = 132 * ((49 samples/44,100) * (13,500,000 * 8) * 2 - 1) * 8 133 */ 134 cx18_av_write4(cx, 0x128, 0xa01d4bf8); 135 break; 136 137 case 48000: 138 /* 139 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 140 * AUX_PLL Integer = 0x0e, AUX PLL Post Divider = 0x16 141 */ 142 cx18_av_write4(cx, 0x108, 0x160e040f); 143 144 /* VID_PLL Fraction = 0x2be2fe */ 145 /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/ 146 cx18_av_write4(cx, 0x10c, 0x002be2fe); 147 148 /* AUX_PLL Fraction = 0x05227ad */ 149 /* xtal * 0xe.2913d68/0x16 = 48000 * 384: 406 MHz p-pd*/ 150 cx18_av_write4(cx, 0x110, 0x005227ad); 151 152 /* src3/4/6_ctl */ 153 /* 0x1.4faa = (4 * xtal/8*2/455) / 48000 */ 154 cx18_av_write4(cx, 0x900, 0x08014faa); 155 cx18_av_write4(cx, 0x904, 0x08014faa); 156 cx18_av_write4(cx, 0x90c, 0x08014faa); 157 158 /* SA_MCLK_SEL=1, SA_MCLK_DIV=0x16 */ 159 cx18_av_write(cx, 0x127, 0x56); 160 161 /* AUD_COUNT = 0x5fff = 4 samples * 16 * 384 - 1 */ 162 cx18_av_write4(cx, 0x12c, 0x11205fff); 163 164 /* 165 * EN_AV_LOCK = 0 166 * VID_COUNT = 0x1193f8 = 143999.000 * 8 = 167 * ((4 samples/48,000) * (13,500,000 * 8) * 16 - 1) * 8 168 */ 169 cx18_av_write4(cx, 0x128, 0xa01193f8); 170 break; 171 } 172 } else { 173 switch (freq) { 174 case 32000: 175 /* 176 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 177 * AUX_PLL Integer = 0x0d, AUX PLL Post Divider = 0x30 178 */ 179 cx18_av_write4(cx, 0x108, 0x300d040f); 180 181 /* VID_PLL Fraction = 0x2be2fe */ 182 /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/ 183 cx18_av_write4(cx, 0x10c, 0x002be2fe); 184 185 /* AUX_PLL Fraction = 0x176740c */ 186 /* xtal * 0xd.bb3a060/0x30 = 32000 * 256: 393 MHz p-pd*/ 187 cx18_av_write4(cx, 0x110, 0x0176740c); 188 189 /* src1_ctl */ 190 /* 0x1.0000 = 32000/32000 */ 191 cx18_av_write4(cx, 0x8f8, 0x08010000); 192 193 /* src3/4/6_ctl */ 194 /* 0x2.0000 = 2 * (32000/32000) */ 195 cx18_av_write4(cx, 0x900, 0x08020000); 196 cx18_av_write4(cx, 0x904, 0x08020000); 197 cx18_av_write4(cx, 0x90c, 0x08020000); 198 199 /* SA_MCLK_SEL=1, SA_MCLK_DIV=0x30 */ 200 cx18_av_write(cx, 0x127, 0x70); 201 202 /* AUD_COUNT = 0x1fff = 8 samples * 4 * 256 - 1 */ 203 cx18_av_write4(cx, 0x12c, 0x11201fff); 204 205 /* 206 * EN_AV_LOCK = 0 207 * VID_COUNT = 0x0d2ef8 = 107999.000 * 8 = 208 * ((8 samples/32,000) * (13,500,000 * 8) * 4 - 1) * 8 209 */ 210 cx18_av_write4(cx, 0x128, 0xa00d2ef8); 211 break; 212 213 case 44100: 214 /* 215 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 216 * AUX_PLL Integer = 0x0e, AUX PLL Post Divider = 0x24 217 */ 218 cx18_av_write4(cx, 0x108, 0x240e040f); 219 220 /* VID_PLL Fraction = 0x2be2fe */ 221 /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/ 222 cx18_av_write4(cx, 0x10c, 0x002be2fe); 223 224 /* AUX_PLL Fraction = 0x062a1f2 */ 225 /* xtal * 0xe.3150f90/0x24 = 44100 * 256: 406 MHz p-pd*/ 226 cx18_av_write4(cx, 0x110, 0x0062a1f2); 227 228 /* src1_ctl */ 229 /* 0x1.60cd = 44100/32000 */ 230 cx18_av_write4(cx, 0x8f8, 0x080160cd); 231 232 /* src3/4/6_ctl */ 233 /* 0x1.7385 = 2 * (32000/44100) */ 234 cx18_av_write4(cx, 0x900, 0x08017385); 235 cx18_av_write4(cx, 0x904, 0x08017385); 236 cx18_av_write4(cx, 0x90c, 0x08017385); 237 238 /* SA_MCLK_SEL=1, SA_MCLK_DIV=0x24 */ 239 cx18_av_write(cx, 0x127, 0x64); 240 241 /* AUD_COUNT = 0x61ff = 49 samples * 2 * 256 - 1 */ 242 cx18_av_write4(cx, 0x12c, 0x112061ff); 243 244 /* 245 * EN_AV_LOCK = 0 246 * VID_COUNT = 0x1d4bf8 = 239999.000 * 8 = 247 * ((49 samples/44,100) * (13,500,000 * 8) * 2 - 1) * 8 248 */ 249 cx18_av_write4(cx, 0x128, 0xa01d4bf8); 250 break; 251 252 case 48000: 253 /* 254 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 255 * AUX_PLL Integer = 0x0d, AUX PLL Post Divider = 0x20 256 */ 257 cx18_av_write4(cx, 0x108, 0x200d040f); 258 259 /* VID_PLL Fraction = 0x2be2fe */ 260 /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/ 261 cx18_av_write4(cx, 0x10c, 0x002be2fe); 262 263 /* AUX_PLL Fraction = 0x176740c */ 264 /* xtal * 0xd.bb3a060/0x20 = 48000 * 256: 393 MHz p-pd*/ 265 cx18_av_write4(cx, 0x110, 0x0176740c); 266 267 /* src1_ctl */ 268 /* 0x1.8000 = 48000/32000 */ 269 cx18_av_write4(cx, 0x8f8, 0x08018000); 270 271 /* src3/4/6_ctl */ 272 /* 0x1.5555 = 2 * (32000/48000) */ 273 cx18_av_write4(cx, 0x900, 0x08015555); 274 cx18_av_write4(cx, 0x904, 0x08015555); 275 cx18_av_write4(cx, 0x90c, 0x08015555); 276 277 /* SA_MCLK_SEL=1, SA_MCLK_DIV=0x20 */ 278 cx18_av_write(cx, 0x127, 0x60); 279 280 /* AUD_COUNT = 0x3fff = 4 samples * 16 * 256 - 1 */ 281 cx18_av_write4(cx, 0x12c, 0x11203fff); 282 283 /* 284 * EN_AV_LOCK = 0 285 * VID_COUNT = 0x1193f8 = 143999.000 * 8 = 286 * ((4 samples/48,000) * (13,500,000 * 8) * 16 - 1) * 8 287 */ 288 cx18_av_write4(cx, 0x128, 0xa01193f8); 289 break; 290 } 291 } 292 293 state->audclk_freq = freq; 294 295 return 0; 296 } 297 298 void cx18_av_audio_set_path(struct cx18 *cx) 299 { 300 struct cx18_av_state *state = &cx->av_state; 301 u8 v; 302 303 /* stop microcontroller */ 304 v = cx18_av_read(cx, 0x803) & ~0x10; 305 cx18_av_write_expect(cx, 0x803, v, v, 0x1f); 306 307 /* assert soft reset */ 308 v = cx18_av_read(cx, 0x810) | 0x01; 309 cx18_av_write_expect(cx, 0x810, v, v, 0x0f); 310 311 /* Mute everything to prevent the PFFT! */ 312 cx18_av_write(cx, 0x8d3, 0x1f); 313 314 if (state->aud_input <= CX18_AV_AUDIO_SERIAL2) { 315 /* Set Path1 to Serial Audio Input */ 316 cx18_av_write4(cx, 0x8d0, 0x01011012); 317 318 /* The microcontroller should not be started for the 319 * non-tuner inputs: autodetection is specific for 320 * TV audio. */ 321 } else { 322 /* Set Path1 to Analog Demod Main Channel */ 323 cx18_av_write4(cx, 0x8d0, 0x1f063870); 324 } 325 326 set_audclk_freq(cx, state->audclk_freq); 327 328 /* deassert soft reset */ 329 v = cx18_av_read(cx, 0x810) & ~0x01; 330 cx18_av_write_expect(cx, 0x810, v, v, 0x0f); 331 332 if (state->aud_input > CX18_AV_AUDIO_SERIAL2) { 333 /* When the microcontroller detects the 334 * audio format, it will unmute the lines */ 335 v = cx18_av_read(cx, 0x803) | 0x10; 336 cx18_av_write_expect(cx, 0x803, v, v, 0x1f); 337 } 338 } 339 340 static void set_volume(struct cx18 *cx, int volume) 341 { 342 /* First convert the volume to msp3400 values (0-127) */ 343 int vol = volume >> 9; 344 /* now scale it up to cx18_av values 345 * -114dB to -96dB maps to 0 346 * this should be 19, but in my testing that was 4dB too loud */ 347 if (vol <= 23) 348 vol = 0; 349 else 350 vol -= 23; 351 352 /* PATH1_VOLUME */ 353 cx18_av_write(cx, 0x8d4, 228 - (vol * 2)); 354 } 355 356 static void set_bass(struct cx18 *cx, int bass) 357 { 358 /* PATH1_EQ_BASS_VOL */ 359 cx18_av_and_or(cx, 0x8d9, ~0x3f, 48 - (bass * 48 / 0xffff)); 360 } 361 362 static void set_treble(struct cx18 *cx, int treble) 363 { 364 /* PATH1_EQ_TREBLE_VOL */ 365 cx18_av_and_or(cx, 0x8db, ~0x3f, 48 - (treble * 48 / 0xffff)); 366 } 367 368 static void set_balance(struct cx18 *cx, int balance) 369 { 370 int bal = balance >> 8; 371 if (bal > 0x80) { 372 /* PATH1_BAL_LEFT */ 373 cx18_av_and_or(cx, 0x8d5, 0x7f, 0x80); 374 /* PATH1_BAL_LEVEL */ 375 cx18_av_and_or(cx, 0x8d5, ~0x7f, bal & 0x7f); 376 } else { 377 /* PATH1_BAL_LEFT */ 378 cx18_av_and_or(cx, 0x8d5, 0x7f, 0x00); 379 /* PATH1_BAL_LEVEL */ 380 cx18_av_and_or(cx, 0x8d5, ~0x7f, 0x80 - bal); 381 } 382 } 383 384 static void set_mute(struct cx18 *cx, int mute) 385 { 386 struct cx18_av_state *state = &cx->av_state; 387 u8 v; 388 389 if (state->aud_input > CX18_AV_AUDIO_SERIAL2) { 390 /* Must turn off microcontroller in order to mute sound. 391 * Not sure if this is the best method, but it does work. 392 * If the microcontroller is running, then it will undo any 393 * changes to the mute register. */ 394 v = cx18_av_read(cx, 0x803); 395 if (mute) { 396 /* disable microcontroller */ 397 v &= ~0x10; 398 cx18_av_write_expect(cx, 0x803, v, v, 0x1f); 399 cx18_av_write(cx, 0x8d3, 0x1f); 400 } else { 401 /* enable microcontroller */ 402 v |= 0x10; 403 cx18_av_write_expect(cx, 0x803, v, v, 0x1f); 404 } 405 } else { 406 /* SRC1_MUTE_EN */ 407 cx18_av_and_or(cx, 0x8d3, ~0x2, mute ? 0x02 : 0x00); 408 } 409 } 410 411 int cx18_av_s_clock_freq(struct v4l2_subdev *sd, u32 freq) 412 { 413 struct cx18 *cx = v4l2_get_subdevdata(sd); 414 struct cx18_av_state *state = &cx->av_state; 415 int retval; 416 u8 v; 417 418 if (state->aud_input > CX18_AV_AUDIO_SERIAL2) { 419 v = cx18_av_read(cx, 0x803) & ~0x10; 420 cx18_av_write_expect(cx, 0x803, v, v, 0x1f); 421 cx18_av_write(cx, 0x8d3, 0x1f); 422 } 423 v = cx18_av_read(cx, 0x810) | 0x1; 424 cx18_av_write_expect(cx, 0x810, v, v, 0x0f); 425 426 retval = set_audclk_freq(cx, freq); 427 428 v = cx18_av_read(cx, 0x810) & ~0x1; 429 cx18_av_write_expect(cx, 0x810, v, v, 0x0f); 430 if (state->aud_input > CX18_AV_AUDIO_SERIAL2) { 431 v = cx18_av_read(cx, 0x803) | 0x10; 432 cx18_av_write_expect(cx, 0x803, v, v, 0x1f); 433 } 434 return retval; 435 } 436 437 static int cx18_av_audio_s_ctrl(struct v4l2_ctrl *ctrl) 438 { 439 struct v4l2_subdev *sd = to_sd(ctrl); 440 struct cx18 *cx = v4l2_get_subdevdata(sd); 441 442 switch (ctrl->id) { 443 case V4L2_CID_AUDIO_VOLUME: 444 set_volume(cx, ctrl->val); 445 break; 446 case V4L2_CID_AUDIO_BASS: 447 set_bass(cx, ctrl->val); 448 break; 449 case V4L2_CID_AUDIO_TREBLE: 450 set_treble(cx, ctrl->val); 451 break; 452 case V4L2_CID_AUDIO_BALANCE: 453 set_balance(cx, ctrl->val); 454 break; 455 case V4L2_CID_AUDIO_MUTE: 456 set_mute(cx, ctrl->val); 457 break; 458 default: 459 return -EINVAL; 460 } 461 return 0; 462 } 463 464 const struct v4l2_ctrl_ops cx18_av_audio_ctrl_ops = { 465 .s_ctrl = cx18_av_audio_s_ctrl, 466 }; 467