1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2021 THine Electronics, Inc. 4 * Copyright (C) 2023 Ideas on Board Oy 5 */ 6 7 #include <linux/unaligned.h> 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/device.h> 12 #include <linux/firmware.h> 13 #include <linux/gpio/consumer.h> 14 #include <linux/i2c.h> 15 #include <linux/init.h> 16 #include <linux/iopoll.h> 17 #include <linux/kernel.h> 18 #include <linux/module.h> 19 #include <linux/mtd/spi-nor.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/property.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/slab.h> 24 #include <linux/types.h> 25 26 #include <media/v4l2-async.h> 27 #include <media/v4l2-cci.h> 28 #include <media/v4l2-ctrls.h> 29 #include <media/v4l2-device.h> 30 #include <media/v4l2-fwnode.h> 31 #include <media/v4l2-subdev.h> 32 33 #include <uapi/linux/thp7312.h> 34 35 /* ISP registers */ 36 37 #define THP7312_REG_FIRMWARE_VERSION_1 CCI_REG8(0xf000) 38 #define THP7312_REG_CAMERA_STATUS CCI_REG8(0xf001) 39 #define THP7312_REG_FIRMWARE_VERSION_2 CCI_REG8(0xf005) 40 #define THP7312_REG_SET_OUTPUT_ENABLE CCI_REG8(0xf008) 41 #define THP7312_OUTPUT_ENABLE 0x01 42 #define THP7312_OUTPUT_DISABLE 0x00 43 #define THP7312_REG_SET_OUTPUT_COLOR_COMPRESSION CCI_REG8(0xf009) 44 #define THP7312_REG_SET_OUTPUT_COLOR_UYVY 0x00 45 #define THP7312_REG_SET_OUTPUT_COLOR_YUY2 0x04 46 #define THP7312_REG_FLIP_MIRROR CCI_REG8(0xf00c) 47 #define THP7312_REG_FLIP_MIRROR_FLIP BIT(0) 48 #define THP7312_REG_FLIP_MIRROR_MIRROR BIT(1) 49 #define THP7312_REG_VIDEO_IMAGE_SIZE CCI_REG8(0xf00d) 50 #define THP7312_VIDEO_IMAGE_SIZE_640x360 0x52 51 #define THP7312_VIDEO_IMAGE_SIZE_640x460 0x03 52 #define THP7312_VIDEO_IMAGE_SIZE_1280x720 0x0a 53 #define THP7312_VIDEO_IMAGE_SIZE_1920x1080 0x0b 54 #define THP7312_VIDEO_IMAGE_SIZE_3840x2160 0x0d 55 #define THP7312_VIDEO_IMAGE_SIZE_4160x3120 0x14 56 #define THP7312_VIDEO_IMAGE_SIZE_2016x1512 0x20 57 #define THP7312_VIDEO_IMAGE_SIZE_2048x1536 0x21 58 #define THP7312_REG_VIDEO_FRAME_RATE_MODE CCI_REG8(0xf00f) 59 #define THP7312_VIDEO_FRAME_RATE_MODE1 0x80 60 #define THP7312_VIDEO_FRAME_RATE_MODE2 0x81 61 #define THP7312_VIDEO_FRAME_RATE_MODE3 0x82 62 #define THP7312_REG_SET_DRIVING_MODE CCI_REG8(0xf010) 63 #define THP7312_REG_DRIVING_MODE_STATUS CCI_REG8(0xf011) 64 #define THP7312_REG_JPEG_COMPRESSION_FACTOR CCI_REG8(0xf01b) 65 #define THP7312_REG_AE_EXPOSURE_COMPENSATION CCI_REG8(0xf022) 66 #define THP7312_REG_AE_FLICKER_MODE CCI_REG8(0xf023) 67 #define THP7312_AE_FLICKER_MODE_50 0x00 68 #define THP7312_AE_FLICKER_MODE_60 0x01 69 #define THP7312_AE_FLICKER_MODE_DISABLE 0x80 70 #define THP7312_REG_AE_FIX_FRAME_RATE CCI_REG8(0xf02e) 71 #define THP7312_REG_MANUAL_WB_RED_GAIN CCI_REG8(0xf036) 72 #define THP7312_REG_MANUAL_WB_BLUE_GAIN CCI_REG8(0xf037) 73 #define THP7312_REG_WB_MODE CCI_REG8(0xf039) 74 #define THP7312_WB_MODE_AUTO 0x00 75 #define THP7312_WB_MODE_MANUAL 0x11 76 #define THP7312_REG_MANUAL_FOCUS_POSITION CCI_REG16(0xf03c) 77 #define THP7312_REG_AF_CONTROL CCI_REG8(0xf040) 78 #define THP7312_REG_AF_CONTROL_AF 0x01 79 #define THP7312_REG_AF_CONTROL_MANUAL 0x10 80 #define THP7312_REG_AF_CONTROL_LOCK 0x80 81 #define THP7312_REG_AF_SETTING CCI_REG8(0xf041) 82 #define THP7312_REG_AF_SETTING_ONESHOT_CONTRAST 0x00 83 #define THP7312_REG_AF_SETTING_ONESHOT_PDAF 0x40 84 #define THP7312_REG_AF_SETTING_ONESHOT_HYBRID 0x80 85 #define THP7312_REG_AF_SETTING_CONTINUOUS_CONTRAST 0x30 86 #define THP7312_REG_AF_SETTING_CONTINUOUS_PDAF 0x70 87 #define THP7312_REG_AF_SETTING_CONTINUOUS_HYBRID 0xf0 88 #define THP7312_REG_AF_SUPPORT CCI_REG8(0xf043) 89 #define THP7312_AF_SUPPORT_PDAF BIT(1) 90 #define THP7312_AF_SUPPORT_CONTRAST BIT(0) 91 #define THP7312_REG_SATURATION CCI_REG8(0xf052) 92 #define THP7312_REG_SHARPNESS CCI_REG8(0xf053) 93 #define THP7312_REG_BRIGHTNESS CCI_REG8(0xf056) 94 #define THP7312_REG_CONTRAST CCI_REG8(0xf057) 95 #define THP7312_REG_NOISE_REDUCTION CCI_REG8(0xf059) 96 #define THP7312_REG_NOISE_REDUCTION_FIXED BIT(7) 97 98 #define TH7312_REG_CUSTOM_MIPI_SET CCI_REG8(0xf0f6) 99 #define TH7312_REG_CUSTOM_MIPI_STATUS CCI_REG8(0xf0f7) 100 #define TH7312_REG_CUSTOM_MIPI_RD CCI_REG8(0xf0f8) 101 #define TH7312_REG_CUSTOM_MIPI_TD CCI_REG8(0xf0f9) 102 103 /* 104 * Firmware update registers. Those use a different address space than the 105 * normal operation ISP registers. 106 */ 107 108 #define THP7312_REG_FW_DRIVABILITY CCI_REG32(0xd65c) 109 #define THP7312_REG_FW_DEST_BANK_ADDR CCI_REG32(0xff08) 110 #define THP7312_REG_FW_VERIFY_RESULT CCI_REG8(0xff60) 111 #define THP7312_REG_FW_RESET_FLASH CCI_REG8(0xff61) 112 #define THP7312_REG_FW_MEMORY_IO_SETTING CCI_REG8(0xff62) 113 #define THP7312_FW_MEMORY_IO_GPIO0 1 114 #define THP7312_FW_MEMORY_IO_GPIO1 0 115 #define THP7312_REG_FW_CRC_RESULT CCI_REG32(0xff64) 116 #define THP7312_REG_FW_STATUS CCI_REG8(0xfffc) 117 118 #define THP7312_FW_VERSION(major, minor) (((major) << 8) | (minor)) 119 #define THP7312_FW_VERSION_MAJOR(v) ((v) >> 8) 120 #define THP7312_FW_VERSION_MINOR(v) ((v) & 0xff) 121 122 enum thp7312_focus_method { 123 THP7312_FOCUS_METHOD_CONTRAST, 124 THP7312_FOCUS_METHOD_PDAF, 125 THP7312_FOCUS_METHOD_HYBRID, 126 }; 127 128 /* 129 * enum thp7312_focus_state - State of the focus handler 130 * 131 * @THP7312_FOCUS_STATE_MANUAL: Manual focus, controlled through the 132 * V4L2_CID_FOCUS_ABSOLUTE control 133 * @THP7312_FOCUS_STATE_AUTO: Continuous auto-focus 134 * @THP7312_FOCUS_STATE_LOCKED: Lock the focus to a fixed position. This state 135 * is entered when switching from auto to manual mode. 136 * @THP7312_FOCUS_STATE_ONESHOT: One-shot auto-focus 137 * 138 * Valid transitions are as follow: 139 * 140 * digraph fsm { 141 * node [shape=circle]; 142 * 143 * manual [label="MANUAL"]; 144 * auto [label="AUTO"]; 145 * locked [label="LOCKED"]; 146 * oneshot [label="ONESHOT"]; 147 * 148 * manual -> auto [label="FOCUS_AUTO <- true"] 149 * locked -> auto [label="FOCUS_AUTO <- true"] 150 * oneshot -> auto [label="FOCUS_AUTO <- true"] 151 * auto -> locked [label="FOCUS_AUTO <- false"] 152 * 153 * locked -> manual [label="FOCUS_ABSOLUTE <- *"] 154 * oneshot -> manual [label="FOCUS_ABSOLUTE <- *"] 155 * 156 * manual -> oneshot [label="FOCUS_START <- *"] 157 * locked -> oneshot [label="FOCUS_START <- *"] 158 * } 159 */ 160 enum thp7312_focus_state { 161 THP7312_FOCUS_STATE_MANUAL, 162 THP7312_FOCUS_STATE_AUTO, 163 THP7312_FOCUS_STATE_LOCKED, 164 THP7312_FOCUS_STATE_ONESHOT, 165 }; 166 167 enum thp7312_boot_mode { 168 THP7312_BOOT_MODE_2WIRE_SLAVE = 0, 169 THP7312_BOOT_MODE_SPI_MASTER = 1, 170 }; 171 172 struct thp7312_frame_rate { 173 u32 fps; 174 u32 link_freq; 175 u8 reg_frame_rate_mode; 176 }; 177 178 struct thp7312_mode_info { 179 u32 width; 180 u32 height; 181 u8 reg_image_size; 182 const struct thp7312_frame_rate *rates; 183 }; 184 185 static const u32 thp7312_colour_fmts[] = { 186 MEDIA_BUS_FMT_YUYV8_1X16, 187 }; 188 189 /* regulator supplies */ 190 static const char * const thp7312_supply_name[] = { 191 "vddcore", 192 "vhtermrx", 193 "vddtx", 194 "vddhost", 195 "vddcmos", 196 "vddgpio-0", 197 "vddgpio-1", 198 }; 199 200 static const struct thp7312_mode_info thp7312_mode_info_data[] = { 201 { 202 .width = 1920, 203 .height = 1080, 204 .reg_image_size = THP7312_VIDEO_IMAGE_SIZE_1920x1080, 205 .rates = (const struct thp7312_frame_rate[]) { 206 { 30, 300000000, 0x81 }, 207 { 60, 387500000, 0x82 }, 208 { 0 } 209 }, 210 }, { 211 .width = 2048, 212 .height = 1536, 213 .reg_image_size = THP7312_VIDEO_IMAGE_SIZE_2048x1536, 214 .rates = (const struct thp7312_frame_rate[]) { 215 { 30, 300000000, 0x81 }, 216 { 0 } 217 } 218 }, { 219 .width = 3840, 220 .height = 2160, 221 .reg_image_size = THP7312_VIDEO_IMAGE_SIZE_3840x2160, 222 .rates = (const struct thp7312_frame_rate[]) { 223 { 30, 600000000, 0x81 }, 224 { 0 } 225 }, 226 }, { 227 .width = 4160, 228 .height = 3120, 229 .reg_image_size = THP7312_VIDEO_IMAGE_SIZE_4160x3120, 230 .rates = (const struct thp7312_frame_rate[]) { 231 { 20, 600000000, 0x81 }, 232 { 0 } 233 }, 234 }, 235 }; 236 237 struct thp7312_device; 238 239 struct thp7312_sensor_info { 240 const char *model; 241 }; 242 243 struct thp7312_sensor { 244 const struct thp7312_sensor_info *info; 245 u8 lane_remap; 246 }; 247 248 struct thp7312_device { 249 struct device *dev; 250 struct regmap *regmap; 251 252 struct v4l2_subdev sd; 253 struct media_pad pad; 254 255 struct gpio_desc *reset_gpio; 256 struct regulator_bulk_data supplies[ARRAY_SIZE(thp7312_supply_name)]; 257 struct clk *iclk; 258 259 u8 lane_remap; 260 261 struct thp7312_sensor sensors[1]; 262 263 enum thp7312_boot_mode boot_mode; 264 265 struct v4l2_ctrl_handler ctrl_handler; 266 bool ctrls_applied; 267 268 s64 link_freq; 269 270 struct { 271 struct v4l2_ctrl *hflip; 272 struct v4l2_ctrl *vflip; 273 }; 274 275 struct { 276 struct v4l2_ctrl *focus_auto; 277 struct v4l2_ctrl *focus_absolute; 278 struct v4l2_ctrl *focus_start; 279 struct v4l2_ctrl *focus_method; 280 }; 281 282 enum thp7312_focus_state focus_state; 283 284 struct { 285 struct v4l2_ctrl *noise_reduction_auto; 286 struct v4l2_ctrl *noise_reduction_absolute; 287 }; 288 289 /* Lock to protect fw_cancel */ 290 struct mutex fw_lock; 291 struct fw_upload *fwl; 292 u8 *fw_write_buf; 293 bool fw_cancel; 294 295 u16 fw_version; 296 }; 297 298 static const struct thp7312_sensor_info thp7312_sensor_info[] = { 299 { 300 .model = "sony,imx258", 301 }, 302 }; 303 304 static inline struct thp7312_device *to_thp7312_dev(struct v4l2_subdev *sd) 305 { 306 return container_of(sd, struct thp7312_device, sd); 307 } 308 309 static const struct thp7312_mode_info * 310 thp7312_find_mode(unsigned int width, unsigned int height, bool nearest) 311 { 312 const struct thp7312_mode_info *mode; 313 314 mode = v4l2_find_nearest_size(thp7312_mode_info_data, 315 ARRAY_SIZE(thp7312_mode_info_data), 316 width, height, width, height); 317 318 if (!nearest && (mode->width != width || mode->height != height)) 319 return NULL; 320 321 return mode; 322 } 323 324 static const struct thp7312_frame_rate * 325 thp7312_find_rate(const struct thp7312_mode_info *mode, unsigned int fps, 326 bool nearest) 327 { 328 const struct thp7312_frame_rate *best_rate = NULL; 329 const struct thp7312_frame_rate *rate; 330 unsigned int best_delta = UINT_MAX; 331 332 if (!mode) 333 return NULL; 334 335 for (rate = mode->rates; rate->fps && best_delta; ++rate) { 336 unsigned int delta = abs(rate->fps - fps); 337 338 if (delta <= best_delta) { 339 best_delta = delta; 340 best_rate = rate; 341 } 342 } 343 344 if (!nearest && best_delta) 345 return NULL; 346 347 return best_rate; 348 } 349 350 /* ----------------------------------------------------------------------------- 351 * Device Access & Configuration 352 */ 353 354 #define thp7312_read_poll_timeout(dev, addr, val, cond, sleep_us, timeout_us) \ 355 ({ \ 356 int __ret, __err; \ 357 __ret = read_poll_timeout(cci_read, __err, __err || (cond), sleep_us, \ 358 timeout_us, false, (dev)->regmap, addr, \ 359 &(val), NULL); \ 360 __ret ? : __err; \ 361 }) 362 363 static int thp7312_map_data_lanes(u8 *lane_remap, const u8 *lanes, u8 num_lanes) 364 { 365 u8 used_lanes = 0; 366 u8 val = 0; 367 unsigned int i; 368 369 /* 370 * The value that we write to the register is the index in the 371 * data-lanes array, so we need to do a conversion. Do this in the same 372 * pass as validating data-lanes. 373 */ 374 for (i = 0; i < num_lanes; i++) { 375 if (lanes[i] < 1 || lanes[i] > 4) 376 return -EINVAL; 377 378 if (used_lanes & (BIT(lanes[i]))) 379 return -EINVAL; 380 381 used_lanes |= BIT(lanes[i]); 382 383 /* 384 * data-lanes is 1-indexed while the field position in the 385 * register is 0-indexed. 386 */ 387 val |= i << ((lanes[i] - 1) * 2); 388 } 389 390 *lane_remap = val; 391 392 return 0; 393 } 394 395 static int thp7312_set_mipi_lanes(struct thp7312_device *thp7312) 396 { 397 struct device *dev = thp7312->dev; 398 int ret = 0; 399 u64 val; 400 401 cci_write(thp7312->regmap, TH7312_REG_CUSTOM_MIPI_RD, 402 thp7312->sensors[0].lane_remap, &ret); 403 cci_write(thp7312->regmap, TH7312_REG_CUSTOM_MIPI_TD, 404 thp7312->lane_remap, &ret); 405 cci_write(thp7312->regmap, TH7312_REG_CUSTOM_MIPI_SET, 1, &ret); 406 407 if (ret) 408 return ret; 409 410 ret = thp7312_read_poll_timeout(thp7312, TH7312_REG_CUSTOM_MIPI_STATUS, 411 val, val == 0x00, 100000, 2000000); 412 if (ret) { 413 dev_err(dev, "Failed to poll MIPI lane status: %d\n", ret); 414 return ret; 415 } 416 417 return 0; 418 } 419 420 static int thp7312_change_mode(struct thp7312_device *thp7312, 421 const struct thp7312_mode_info *mode, 422 const struct thp7312_frame_rate *rate) 423 { 424 struct device *dev = thp7312->dev; 425 u64 val = 0; 426 int ret; 427 428 ret = thp7312_read_poll_timeout(thp7312, THP7312_REG_CAMERA_STATUS, val, 429 val == 0x80, 20000, 200000); 430 if (ret < 0) { 431 dev_err(dev, "%s(): failed to poll ISP: %d\n", __func__, ret); 432 return ret; 433 } 434 435 cci_write(thp7312->regmap, THP7312_REG_VIDEO_IMAGE_SIZE, 436 mode->reg_image_size, &ret); 437 cci_write(thp7312->regmap, THP7312_REG_VIDEO_FRAME_RATE_MODE, 438 rate->reg_frame_rate_mode, &ret); 439 cci_write(thp7312->regmap, THP7312_REG_JPEG_COMPRESSION_FACTOR, 0x5e, 440 &ret); 441 cci_write(thp7312->regmap, THP7312_REG_SET_DRIVING_MODE, 0x01, &ret); 442 443 if (ret) 444 return ret; 445 446 ret = thp7312_read_poll_timeout(thp7312, THP7312_REG_DRIVING_MODE_STATUS, 447 val, val == 0x01, 20000, 100000); 448 if (ret < 0) { 449 dev_err(dev, "%s(): failed\n", __func__); 450 return ret; 451 } 452 453 return 0; 454 } 455 456 static int thp7312_set_framefmt(struct thp7312_device *thp7312, 457 struct v4l2_mbus_framefmt *format) 458 { 459 u8 val; 460 461 switch (format->code) { 462 case MEDIA_BUS_FMT_UYVY8_1X16: 463 /* YUV422, UYVY */ 464 val = THP7312_REG_SET_OUTPUT_COLOR_UYVY; 465 break; 466 case MEDIA_BUS_FMT_YUYV8_1X16: 467 /* YUV422, YUYV */ 468 val = THP7312_REG_SET_OUTPUT_COLOR_YUY2; 469 break; 470 default: 471 /* Should never happen */ 472 return -EINVAL; 473 } 474 475 return cci_write(thp7312->regmap, 476 THP7312_REG_SET_OUTPUT_COLOR_COMPRESSION, val, NULL); 477 } 478 479 static int thp7312_init_mode(struct thp7312_device *thp7312, 480 struct v4l2_subdev_state *sd_state) 481 { 482 const struct thp7312_mode_info *mode; 483 const struct thp7312_frame_rate *rate; 484 struct v4l2_mbus_framefmt *fmt; 485 struct v4l2_fract *interval; 486 int ret; 487 488 /* 489 * TODO: The mode and rate should be cached in the subdev state, once 490 * support for extending states will be available. 491 */ 492 fmt = v4l2_subdev_state_get_format(sd_state, 0); 493 interval = v4l2_subdev_state_get_interval(sd_state, 0); 494 495 mode = thp7312_find_mode(fmt->width, fmt->height, false); 496 rate = thp7312_find_rate(mode, interval->denominator, false); 497 498 if (WARN_ON(!mode || !rate)) 499 return -EINVAL; 500 501 ret = thp7312_set_framefmt(thp7312, fmt); 502 if (ret) 503 return ret; 504 505 return thp7312_change_mode(thp7312, mode, rate); 506 } 507 508 static int thp7312_stream_enable(struct thp7312_device *thp7312, bool enable) 509 { 510 return cci_write(thp7312->regmap, THP7312_REG_SET_OUTPUT_ENABLE, 511 enable ? THP7312_OUTPUT_ENABLE : THP7312_OUTPUT_DISABLE, 512 NULL); 513 } 514 515 static int thp7312_check_status_stream_mode(struct thp7312_device *thp7312) 516 { 517 struct device *dev = thp7312->dev; 518 u64 status = 0; 519 int ret; 520 521 while (status != 0x80) { 522 ret = cci_read(thp7312->regmap, THP7312_REG_CAMERA_STATUS, 523 &status, NULL); 524 if (ret) 525 return ret; 526 527 if (status == 0x80) { 528 dev_dbg(dev, "Camera initialization done\n"); 529 return 0; 530 } 531 532 if (status != 0x00) { 533 dev_err(dev, "Invalid camera status %llx\n", status); 534 return -EINVAL; 535 } 536 537 dev_dbg(dev, "Camera initializing...\n"); 538 usleep_range(70000, 80000); 539 } 540 541 return 0; 542 } 543 544 static void thp7312_reset(struct thp7312_device *thp7312) 545 { 546 unsigned long rate; 547 548 gpiod_set_value_cansleep(thp7312->reset_gpio, 1); 549 550 /* 551 * The minimum reset duration is 8 clock cycles, make it 10 to provide 552 * a safety margin. 553 */ 554 rate = clk_get_rate(thp7312->iclk); 555 fsleep(DIV_ROUND_UP(10 * USEC_PER_SEC, rate)); 556 557 gpiod_set_value_cansleep(thp7312->reset_gpio, 0); 558 559 /* 560 * TODO: The documentation states that the device needs 2ms to 561 * initialize after reset is deasserted. It then proceeds to load the 562 * firmware from the flash memory, which takes an unspecified amount of 563 * time. Check if this delay could be reduced. 564 */ 565 fsleep(300000); 566 } 567 568 /* ----------------------------------------------------------------------------- 569 * Power Management 570 */ 571 572 static void __thp7312_power_off(struct thp7312_device *thp7312) 573 { 574 regulator_bulk_disable(ARRAY_SIZE(thp7312->supplies), thp7312->supplies); 575 clk_disable_unprepare(thp7312->iclk); 576 } 577 578 static void thp7312_power_off(struct thp7312_device *thp7312) 579 { 580 __thp7312_power_off(thp7312); 581 } 582 583 static int __thp7312_power_on(struct thp7312_device *thp7312) 584 { 585 struct device *dev = thp7312->dev; 586 int ret; 587 588 ret = regulator_bulk_enable(ARRAY_SIZE(thp7312->supplies), 589 thp7312->supplies); 590 if (ret < 0) 591 return ret; 592 593 ret = clk_prepare_enable(thp7312->iclk); 594 if (ret < 0) { 595 dev_err(dev, "clk prepare enable failed\n"); 596 regulator_bulk_disable(ARRAY_SIZE(thp7312->supplies), 597 thp7312->supplies); 598 return ret; 599 } 600 601 /* 602 * We cannot assume that turning off and on again will reset, so do a 603 * software reset on power up. 604 */ 605 thp7312_reset(thp7312); 606 607 return 0; 608 } 609 610 static int thp7312_power_on(struct thp7312_device *thp7312) 611 { 612 int ret; 613 614 ret = __thp7312_power_on(thp7312); 615 if (ret < 0) 616 return ret; 617 618 ret = thp7312_check_status_stream_mode(thp7312); 619 if (ret < 0) 620 goto error; 621 622 ret = thp7312_set_mipi_lanes(thp7312); 623 if (ret) 624 goto error; 625 626 return 0; 627 628 error: 629 thp7312_power_off(thp7312); 630 return ret; 631 } 632 633 static int __maybe_unused thp7312_pm_runtime_suspend(struct device *dev) 634 { 635 struct v4l2_subdev *sd = dev_get_drvdata(dev); 636 struct thp7312_device *thp7312 = to_thp7312_dev(sd); 637 638 thp7312_power_off(thp7312); 639 640 thp7312->ctrls_applied = false; 641 642 return 0; 643 } 644 645 static int __maybe_unused thp7312_pm_runtime_resume(struct device *dev) 646 { 647 struct v4l2_subdev *sd = dev_get_drvdata(dev); 648 struct thp7312_device *thp7312 = to_thp7312_dev(sd); 649 650 return thp7312_power_on(thp7312); 651 } 652 653 static const struct dev_pm_ops thp7312_pm_ops = { 654 SET_RUNTIME_PM_OPS(thp7312_pm_runtime_suspend, 655 thp7312_pm_runtime_resume, NULL) 656 }; 657 658 /* ----------------------------------------------------------------------------- 659 * V4L2 Subdev Operations 660 */ 661 662 static bool thp7312_find_bus_code(u32 code) 663 { 664 unsigned int i; 665 666 for (i = 0; i < ARRAY_SIZE(thp7312_colour_fmts); ++i) { 667 if (thp7312_colour_fmts[i] == code) 668 return true; 669 } 670 671 return false; 672 } 673 674 static int thp7312_enum_mbus_code(struct v4l2_subdev *sd, 675 struct v4l2_subdev_state *sd_state, 676 struct v4l2_subdev_mbus_code_enum *code) 677 { 678 if (code->index >= ARRAY_SIZE(thp7312_colour_fmts)) 679 return -EINVAL; 680 681 code->code = thp7312_colour_fmts[code->index]; 682 683 return 0; 684 } 685 686 static int thp7312_enum_frame_size(struct v4l2_subdev *sd, 687 struct v4l2_subdev_state *sd_state, 688 struct v4l2_subdev_frame_size_enum *fse) 689 { 690 if (!thp7312_find_bus_code(fse->code)) 691 return -EINVAL; 692 693 if (fse->index >= ARRAY_SIZE(thp7312_mode_info_data)) 694 return -EINVAL; 695 696 fse->min_width = thp7312_mode_info_data[fse->index].width; 697 fse->max_width = fse->min_width; 698 fse->min_height = thp7312_mode_info_data[fse->index].height; 699 fse->max_height = fse->min_height; 700 701 return 0; 702 } 703 704 static int thp7312_enum_frame_interval(struct v4l2_subdev *sd, 705 struct v4l2_subdev_state *sd_state, 706 struct v4l2_subdev_frame_interval_enum *fie) 707 { 708 const struct thp7312_frame_rate *rate; 709 const struct thp7312_mode_info *mode; 710 unsigned int index = fie->index; 711 712 if (!thp7312_find_bus_code(fie->code)) 713 return -EINVAL; 714 715 mode = thp7312_find_mode(fie->width, fie->height, false); 716 if (!mode) 717 return -EINVAL; 718 719 for (rate = mode->rates; rate->fps; ++rate, --index) { 720 if (!index) { 721 fie->interval.numerator = 1; 722 fie->interval.denominator = rate->fps; 723 724 return 0; 725 } 726 } 727 728 return -EINVAL; 729 } 730 731 static int thp7312_set_fmt(struct v4l2_subdev *sd, 732 struct v4l2_subdev_state *sd_state, 733 struct v4l2_subdev_format *format) 734 { 735 struct thp7312_device *thp7312 = to_thp7312_dev(sd); 736 struct v4l2_mbus_framefmt *mbus_fmt = &format->format; 737 struct v4l2_mbus_framefmt *fmt; 738 struct v4l2_fract *interval; 739 const struct thp7312_mode_info *mode; 740 741 if (!thp7312_find_bus_code(mbus_fmt->code)) 742 mbus_fmt->code = thp7312_colour_fmts[0]; 743 744 mode = thp7312_find_mode(mbus_fmt->width, mbus_fmt->height, true); 745 746 fmt = v4l2_subdev_state_get_format(sd_state, 0); 747 748 fmt->code = mbus_fmt->code; 749 fmt->width = mode->width; 750 fmt->height = mode->height; 751 fmt->colorspace = V4L2_COLORSPACE_SRGB; 752 fmt->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt->colorspace); 753 fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE; 754 fmt->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(fmt->colorspace); 755 756 *mbus_fmt = *fmt; 757 758 interval = v4l2_subdev_state_get_interval(sd_state, 0); 759 interval->numerator = 1; 760 interval->denominator = mode->rates[0].fps; 761 762 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) 763 thp7312->link_freq = mode->rates[0].link_freq; 764 765 return 0; 766 } 767 768 static int thp7312_set_frame_interval(struct v4l2_subdev *sd, 769 struct v4l2_subdev_state *sd_state, 770 struct v4l2_subdev_frame_interval *fi) 771 { 772 struct thp7312_device *thp7312 = to_thp7312_dev(sd); 773 const struct thp7312_mode_info *mode; 774 const struct thp7312_frame_rate *rate; 775 const struct v4l2_mbus_framefmt *fmt; 776 struct v4l2_fract *interval; 777 unsigned int fps; 778 779 /* Avoid divisions by 0, pick the highest frame if the interval is 0. */ 780 fps = fi->interval.numerator 781 ? DIV_ROUND_CLOSEST(fi->interval.denominator, fi->interval.numerator) 782 : UINT_MAX; 783 784 fmt = v4l2_subdev_state_get_format(sd_state, 0); 785 mode = thp7312_find_mode(fmt->width, fmt->height, false); 786 rate = thp7312_find_rate(mode, fps, true); 787 788 interval = v4l2_subdev_state_get_interval(sd_state, 0); 789 interval->numerator = 1; 790 interval->denominator = rate->fps; 791 792 if (fi->which == V4L2_SUBDEV_FORMAT_ACTIVE) 793 thp7312->link_freq = rate->link_freq; 794 795 fi->interval = *interval; 796 797 return 0; 798 } 799 800 static int thp7312_s_stream(struct v4l2_subdev *sd, int enable) 801 { 802 struct thp7312_device *thp7312 = to_thp7312_dev(sd); 803 struct v4l2_subdev_state *sd_state; 804 int ret; 805 806 sd_state = v4l2_subdev_lock_and_get_active_state(sd); 807 808 if (!enable) { 809 thp7312_stream_enable(thp7312, false); 810 811 pm_runtime_mark_last_busy(thp7312->dev); 812 pm_runtime_put_autosuspend(thp7312->dev); 813 814 v4l2_subdev_unlock_state(sd_state); 815 816 return 0; 817 } 818 819 ret = pm_runtime_resume_and_get(thp7312->dev); 820 if (ret) 821 goto finish_unlock; 822 823 ret = thp7312_init_mode(thp7312, sd_state); 824 if (ret) 825 goto finish_pm; 826 827 if (!thp7312->ctrls_applied) { 828 ret = __v4l2_ctrl_handler_setup(&thp7312->ctrl_handler); 829 if (ret) 830 goto finish_pm; 831 832 thp7312->ctrls_applied = true; 833 } 834 835 ret = thp7312_stream_enable(thp7312, true); 836 if (ret) 837 goto finish_pm; 838 839 goto finish_unlock; 840 841 finish_pm: 842 pm_runtime_mark_last_busy(thp7312->dev); 843 pm_runtime_put_autosuspend(thp7312->dev); 844 finish_unlock: 845 v4l2_subdev_unlock_state(sd_state); 846 847 return ret; 848 } 849 850 static int thp7312_init_state(struct v4l2_subdev *sd, 851 struct v4l2_subdev_state *sd_state) 852 { 853 const struct thp7312_mode_info *default_mode = &thp7312_mode_info_data[0]; 854 struct v4l2_mbus_framefmt *fmt; 855 struct v4l2_fract *interval; 856 857 fmt = v4l2_subdev_state_get_format(sd_state, 0); 858 interval = v4l2_subdev_state_get_interval(sd_state, 0); 859 860 /* 861 * default init sequence initialize thp7312 to 862 * YUV422 YUYV VGA@30fps 863 */ 864 fmt->code = MEDIA_BUS_FMT_YUYV8_1X16; 865 fmt->colorspace = V4L2_COLORSPACE_SRGB; 866 fmt->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt->colorspace); 867 fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE; 868 fmt->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(fmt->colorspace); 869 fmt->width = default_mode->width; 870 fmt->height = default_mode->height; 871 fmt->field = V4L2_FIELD_NONE; 872 873 interval->numerator = 1; 874 interval->denominator = default_mode->rates[0].fps; 875 876 return 0; 877 } 878 879 static const struct v4l2_subdev_core_ops thp7312_core_ops = { 880 .log_status = v4l2_ctrl_subdev_log_status, 881 }; 882 883 static const struct v4l2_subdev_video_ops thp7312_video_ops = { 884 .s_stream = thp7312_s_stream, 885 }; 886 887 static const struct v4l2_subdev_pad_ops thp7312_pad_ops = { 888 .enum_mbus_code = thp7312_enum_mbus_code, 889 .get_fmt = v4l2_subdev_get_fmt, 890 .set_fmt = thp7312_set_fmt, 891 .get_frame_interval = v4l2_subdev_get_frame_interval, 892 .set_frame_interval = thp7312_set_frame_interval, 893 .enum_frame_size = thp7312_enum_frame_size, 894 .enum_frame_interval = thp7312_enum_frame_interval, 895 }; 896 897 static const struct v4l2_subdev_ops thp7312_subdev_ops = { 898 .core = &thp7312_core_ops, 899 .video = &thp7312_video_ops, 900 .pad = &thp7312_pad_ops, 901 }; 902 903 static const struct v4l2_subdev_internal_ops thp7312_internal_ops = { 904 .init_state = thp7312_init_state, 905 }; 906 907 /* ----------------------------------------------------------------------------- 908 * V4L2 Control Operations 909 */ 910 911 static inline struct thp7312_device *to_thp7312_from_ctrl(struct v4l2_ctrl *ctrl) 912 { 913 return container_of(ctrl->handler, struct thp7312_device, ctrl_handler); 914 } 915 916 /* 0: 3000cm, 18: 8cm */ 917 static const u16 thp7312_focus_values[] = { 918 3000, 1000, 600, 450, 350, 919 290, 240, 200, 170, 150, 920 140, 130, 120, 110, 100, 921 93, 87, 83, 80, 922 }; 923 924 static int thp7312_set_focus(struct thp7312_device *thp7312) 925 { 926 enum thp7312_focus_state new_state = thp7312->focus_state; 927 bool continuous; 928 u8 af_control; 929 u8 af_setting; 930 int ret = 0; 931 932 /* Start by programming the manual focus position if it has changed. */ 933 if (thp7312->focus_absolute->is_new) { 934 unsigned int value; 935 936 value = thp7312_focus_values[thp7312->focus_absolute->val]; 937 938 ret = cci_write(thp7312->regmap, 939 THP7312_REG_MANUAL_FOCUS_POSITION, value, NULL); 940 if (ret) 941 return ret; 942 } 943 944 /* Calculate the new focus state. */ 945 switch (thp7312->focus_state) { 946 case THP7312_FOCUS_STATE_MANUAL: 947 default: 948 if (thp7312->focus_auto->val) 949 new_state = THP7312_FOCUS_STATE_AUTO; 950 else if (thp7312->focus_start->is_new) 951 new_state = THP7312_FOCUS_STATE_ONESHOT; 952 break; 953 954 case THP7312_FOCUS_STATE_AUTO: 955 if (!thp7312->focus_auto->val) 956 new_state = THP7312_FOCUS_STATE_LOCKED; 957 break; 958 959 case THP7312_FOCUS_STATE_LOCKED: 960 if (thp7312->focus_auto->val) 961 new_state = THP7312_FOCUS_STATE_AUTO; 962 else if (thp7312->focus_start->is_new) 963 new_state = THP7312_FOCUS_STATE_ONESHOT; 964 else if (thp7312->focus_absolute->is_new) 965 new_state = THP7312_FOCUS_STATE_MANUAL; 966 break; 967 968 case THP7312_FOCUS_STATE_ONESHOT: 969 if (thp7312->focus_auto->val) 970 new_state = THP7312_FOCUS_STATE_AUTO; 971 else if (thp7312->focus_start->is_new) 972 new_state = THP7312_FOCUS_STATE_ONESHOT; 973 else if (thp7312->focus_absolute->is_new) 974 new_state = THP7312_FOCUS_STATE_MANUAL; 975 break; 976 } 977 978 /* 979 * If neither the state nor the focus method has changed, and no new 980 * one-shot focus is requested, there's nothing new to program to the 981 * hardware. 982 */ 983 if (thp7312->focus_state == new_state && 984 !thp7312->focus_method->is_new && !thp7312->focus_start->is_new) 985 return 0; 986 987 continuous = new_state == THP7312_FOCUS_STATE_MANUAL || 988 new_state == THP7312_FOCUS_STATE_ONESHOT; 989 990 switch (thp7312->focus_method->val) { 991 case THP7312_FOCUS_METHOD_CONTRAST: 992 default: 993 af_setting = continuous 994 ? THP7312_REG_AF_SETTING_CONTINUOUS_CONTRAST 995 : THP7312_REG_AF_SETTING_ONESHOT_CONTRAST; 996 break; 997 case THP7312_FOCUS_METHOD_PDAF: 998 af_setting = continuous 999 ? THP7312_REG_AF_SETTING_CONTINUOUS_PDAF 1000 : THP7312_REG_AF_SETTING_ONESHOT_PDAF; 1001 break; 1002 case THP7312_FOCUS_METHOD_HYBRID: 1003 af_setting = continuous 1004 ? THP7312_REG_AF_SETTING_CONTINUOUS_HYBRID 1005 : THP7312_REG_AF_SETTING_ONESHOT_HYBRID; 1006 break; 1007 } 1008 1009 switch (new_state) { 1010 case THP7312_FOCUS_STATE_MANUAL: 1011 default: 1012 af_control = THP7312_REG_AF_CONTROL_MANUAL; 1013 break; 1014 case THP7312_FOCUS_STATE_AUTO: 1015 case THP7312_FOCUS_STATE_ONESHOT: 1016 af_control = THP7312_REG_AF_CONTROL_AF; 1017 break; 1018 case THP7312_FOCUS_STATE_LOCKED: 1019 af_control = THP7312_REG_AF_CONTROL_LOCK; 1020 break; 1021 } 1022 1023 cci_write(thp7312->regmap, THP7312_REG_AF_SETTING, af_setting, &ret); 1024 1025 if (new_state == THP7312_FOCUS_STATE_MANUAL && 1026 (thp7312->focus_state == THP7312_FOCUS_STATE_AUTO || 1027 thp7312->focus_state == THP7312_FOCUS_STATE_ONESHOT)) { 1028 /* When switching to manual state, lock AF first. */ 1029 cci_write(thp7312->regmap, THP7312_REG_AF_CONTROL, 1030 THP7312_REG_AF_CONTROL_LOCK, &ret); 1031 } 1032 1033 cci_write(thp7312->regmap, THP7312_REG_AF_CONTROL, af_control, &ret); 1034 1035 if (ret) 1036 return ret; 1037 1038 thp7312->focus_state = new_state; 1039 1040 return 0; 1041 } 1042 1043 static int thp7312_s_ctrl(struct v4l2_ctrl *ctrl) 1044 { 1045 struct thp7312_device *thp7312 = to_thp7312_from_ctrl(ctrl); 1046 int ret = 0; 1047 u8 value; 1048 1049 if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE) 1050 return -EINVAL; 1051 1052 if (!pm_runtime_get_if_active(thp7312->dev)) 1053 return 0; 1054 1055 switch (ctrl->id) { 1056 case V4L2_CID_BRIGHTNESS: 1057 cci_write(thp7312->regmap, THP7312_REG_BRIGHTNESS, 1058 ctrl->val + 10, &ret); 1059 break; 1060 1061 case V4L2_CID_THP7312_LOW_LIGHT_COMPENSATION: 1062 /* 0 = Auto adjust frame rate, 1 = Fix frame rate */ 1063 cci_write(thp7312->regmap, THP7312_REG_AE_FIX_FRAME_RATE, 1064 ctrl->val ? 0 : 1, &ret); 1065 break; 1066 1067 case V4L2_CID_FOCUS_AUTO: 1068 case V4L2_CID_FOCUS_ABSOLUTE: 1069 case V4L2_CID_AUTO_FOCUS_START: 1070 case V4L2_CID_THP7312_AUTO_FOCUS_METHOD: 1071 ret = thp7312_set_focus(thp7312); 1072 break; 1073 1074 case V4L2_CID_HFLIP: 1075 case V4L2_CID_VFLIP: 1076 value = (thp7312->hflip->val ? THP7312_REG_FLIP_MIRROR_MIRROR : 0) 1077 | (thp7312->vflip->val ? THP7312_REG_FLIP_MIRROR_FLIP : 0); 1078 1079 cci_write(thp7312->regmap, THP7312_REG_FLIP_MIRROR, value, &ret); 1080 break; 1081 1082 case V4L2_CID_THP7312_NOISE_REDUCTION_AUTO: 1083 case V4L2_CID_THP7312_NOISE_REDUCTION_ABSOLUTE: 1084 value = thp7312->noise_reduction_auto->val ? 0 1085 : THP7312_REG_NOISE_REDUCTION_FIXED | 1086 thp7312->noise_reduction_absolute->val; 1087 1088 cci_write(thp7312->regmap, THP7312_REG_NOISE_REDUCTION, value, 1089 &ret); 1090 break; 1091 1092 case V4L2_CID_AUTO_WHITE_BALANCE: 1093 value = ctrl->val ? THP7312_WB_MODE_AUTO : THP7312_WB_MODE_MANUAL; 1094 1095 cci_write(thp7312->regmap, THP7312_REG_WB_MODE, value, &ret); 1096 break; 1097 1098 case V4L2_CID_RED_BALANCE: 1099 cci_write(thp7312->regmap, THP7312_REG_MANUAL_WB_RED_GAIN, 1100 ctrl->val, &ret); 1101 break; 1102 1103 case V4L2_CID_BLUE_BALANCE: 1104 cci_write(thp7312->regmap, THP7312_REG_MANUAL_WB_BLUE_GAIN, 1105 ctrl->val, &ret); 1106 break; 1107 1108 case V4L2_CID_AUTO_EXPOSURE_BIAS: 1109 cci_write(thp7312->regmap, THP7312_REG_AE_EXPOSURE_COMPENSATION, 1110 ctrl->val, &ret); 1111 break; 1112 1113 case V4L2_CID_POWER_LINE_FREQUENCY: 1114 if (ctrl->val == V4L2_CID_POWER_LINE_FREQUENCY_60HZ) { 1115 value = THP7312_AE_FLICKER_MODE_60; 1116 } else if (ctrl->val == V4L2_CID_POWER_LINE_FREQUENCY_50HZ) { 1117 value = THP7312_AE_FLICKER_MODE_50; 1118 } else { 1119 if (thp7312->fw_version == THP7312_FW_VERSION(40, 3)) { 1120 /* THP7312_AE_FLICKER_MODE_DISABLE is not supported */ 1121 value = THP7312_AE_FLICKER_MODE_50; 1122 } else { 1123 value = THP7312_AE_FLICKER_MODE_DISABLE; 1124 } 1125 } 1126 1127 cci_write(thp7312->regmap, THP7312_REG_AE_FLICKER_MODE, 1128 value, &ret); 1129 break; 1130 1131 case V4L2_CID_SATURATION: 1132 cci_write(thp7312->regmap, THP7312_REG_SATURATION, 1133 ctrl->val, &ret); 1134 break; 1135 1136 case V4L2_CID_CONTRAST: 1137 cci_write(thp7312->regmap, THP7312_REG_CONTRAST, 1138 ctrl->val, &ret); 1139 break; 1140 1141 case V4L2_CID_SHARPNESS: 1142 cci_write(thp7312->regmap, THP7312_REG_SHARPNESS, 1143 ctrl->val, &ret); 1144 break; 1145 1146 default: 1147 break; 1148 } 1149 1150 pm_runtime_mark_last_busy(thp7312->dev); 1151 pm_runtime_put_autosuspend(thp7312->dev); 1152 1153 return ret; 1154 } 1155 1156 static const struct v4l2_ctrl_ops thp7312_ctrl_ops = { 1157 .s_ctrl = thp7312_s_ctrl, 1158 }; 1159 1160 /* 1161 * Refer to Documentation/userspace-api/media/drivers/thp7312.rst for details. 1162 */ 1163 static const struct v4l2_ctrl_config thp7312_ctrl_focus_method_cdaf = { 1164 .ops = &thp7312_ctrl_ops, 1165 .id = V4L2_CID_THP7312_AUTO_FOCUS_METHOD, 1166 .name = "Auto-Focus Method", 1167 .type = V4L2_CTRL_TYPE_INTEGER, 1168 .min = THP7312_FOCUS_METHOD_CONTRAST, 1169 .def = THP7312_FOCUS_METHOD_CONTRAST, 1170 .max = THP7312_FOCUS_METHOD_CONTRAST, 1171 .step = 1, 1172 }; 1173 1174 static const struct v4l2_ctrl_config thp7312_ctrl_focus_method_pdaf = { 1175 .ops = &thp7312_ctrl_ops, 1176 .id = V4L2_CID_THP7312_AUTO_FOCUS_METHOD, 1177 .name = "Auto-Focus Method", 1178 .type = V4L2_CTRL_TYPE_INTEGER, 1179 .min = THP7312_FOCUS_METHOD_CONTRAST, 1180 .def = THP7312_FOCUS_METHOD_HYBRID, 1181 .max = THP7312_FOCUS_METHOD_HYBRID, 1182 .step = 1, 1183 }; 1184 1185 static const struct v4l2_ctrl_config thp7312_v4l2_ctrls_custom[] = { 1186 { 1187 .ops = &thp7312_ctrl_ops, 1188 .id = V4L2_CID_THP7312_LOW_LIGHT_COMPENSATION, 1189 .name = "Low Light Compensation", 1190 .type = V4L2_CTRL_TYPE_BOOLEAN, 1191 .min = 0, 1192 .def = 1, 1193 .max = 1, 1194 .step = 1, 1195 }, { 1196 .ops = &thp7312_ctrl_ops, 1197 .id = V4L2_CID_THP7312_NOISE_REDUCTION_AUTO, 1198 .name = "Noise Reduction Auto", 1199 .type = V4L2_CTRL_TYPE_BOOLEAN, 1200 .min = 0, 1201 .def = 1, 1202 .max = 1, 1203 .step = 1, 1204 }, { 1205 .ops = &thp7312_ctrl_ops, 1206 .id = V4L2_CID_THP7312_NOISE_REDUCTION_ABSOLUTE, 1207 .name = "Noise Reduction Level", 1208 .type = V4L2_CTRL_TYPE_INTEGER, 1209 .min = 0, 1210 .def = 0, 1211 .max = 10, 1212 .step = 1, 1213 }, 1214 }; 1215 1216 static const s64 exp_bias_qmenu[] = { 1217 -2000, -1667, -1333, -1000, -667, -333, 0, 333, 667, 1000, 1333, 1667, 2000 1218 }; 1219 1220 static int thp7312_init_controls(struct thp7312_device *thp7312) 1221 { 1222 struct v4l2_ctrl_handler *hdl = &thp7312->ctrl_handler; 1223 struct device *dev = thp7312->dev; 1224 struct v4l2_fwnode_device_properties props; 1225 struct v4l2_ctrl *link_freq; 1226 unsigned int num_controls; 1227 unsigned int i; 1228 u8 af_support; 1229 int ret; 1230 1231 /* 1232 * Check what auto-focus methods the connected sensor supports, if any. 1233 * Firmwares before v90.03 didn't expose the AF_SUPPORT register, 1234 * consider both CDAF and PDAF as supported in that case. 1235 */ 1236 if (thp7312->fw_version >= THP7312_FW_VERSION(90, 3)) { 1237 u64 val; 1238 1239 ret = cci_read(thp7312->regmap, THP7312_REG_AF_SUPPORT, &val, 1240 NULL); 1241 if (ret) 1242 return ret; 1243 1244 af_support = val & (THP7312_AF_SUPPORT_PDAF | 1245 THP7312_AF_SUPPORT_CONTRAST); 1246 } else { 1247 af_support = THP7312_AF_SUPPORT_PDAF 1248 | THP7312_AF_SUPPORT_CONTRAST; 1249 } 1250 1251 num_controls = 14 + ARRAY_SIZE(thp7312_v4l2_ctrls_custom) 1252 + (af_support ? 4 : 0); 1253 1254 v4l2_ctrl_handler_init(hdl, num_controls); 1255 1256 if (af_support) { 1257 const struct v4l2_ctrl_config *af_method; 1258 1259 af_method = af_support & THP7312_AF_SUPPORT_PDAF 1260 ? &thp7312_ctrl_focus_method_pdaf 1261 : &thp7312_ctrl_focus_method_cdaf; 1262 1263 thp7312->focus_state = THP7312_FOCUS_STATE_MANUAL; 1264 1265 thp7312->focus_auto = 1266 v4l2_ctrl_new_std(hdl, &thp7312_ctrl_ops, 1267 V4L2_CID_FOCUS_AUTO, 1268 0, 1, 1, 1); 1269 thp7312->focus_absolute = 1270 v4l2_ctrl_new_std(hdl, &thp7312_ctrl_ops, 1271 V4L2_CID_FOCUS_ABSOLUTE, 1272 0, ARRAY_SIZE(thp7312_focus_values), 1273 1, 0); 1274 thp7312->focus_method = 1275 v4l2_ctrl_new_custom(hdl, af_method, NULL); 1276 thp7312->focus_start = 1277 v4l2_ctrl_new_std(hdl, &thp7312_ctrl_ops, 1278 V4L2_CID_AUTO_FOCUS_START, 1279 1, 1, 1, 1); 1280 1281 v4l2_ctrl_cluster(4, &thp7312->focus_auto); 1282 } 1283 1284 v4l2_ctrl_new_std(hdl, &thp7312_ctrl_ops, V4L2_CID_AUTO_WHITE_BALANCE, 1285 0, 1, 1, 1); 1286 /* 32: 1x, 255: 7.95x */ 1287 v4l2_ctrl_new_std(hdl, &thp7312_ctrl_ops, V4L2_CID_RED_BALANCE, 1288 32, 255, 1, 64); 1289 /* 32: 1x, 255: 7.95x */ 1290 v4l2_ctrl_new_std(hdl, &thp7312_ctrl_ops, V4L2_CID_BLUE_BALANCE, 1291 32, 255, 1, 50); 1292 1293 v4l2_ctrl_new_std(hdl, &thp7312_ctrl_ops, V4L2_CID_BRIGHTNESS, 1294 -10, 10, 1, 0); 1295 v4l2_ctrl_new_std(hdl, &thp7312_ctrl_ops, V4L2_CID_SATURATION, 1296 0, 31, 1, 10); 1297 v4l2_ctrl_new_std(hdl, &thp7312_ctrl_ops, V4L2_CID_CONTRAST, 1298 0, 20, 1, 10); 1299 v4l2_ctrl_new_std(hdl, &thp7312_ctrl_ops, V4L2_CID_SHARPNESS, 1300 0, 31, 1, 8); 1301 1302 thp7312->hflip = v4l2_ctrl_new_std(hdl, &thp7312_ctrl_ops, 1303 V4L2_CID_HFLIP, 0, 1, 1, 0); 1304 thp7312->vflip = v4l2_ctrl_new_std(hdl, &thp7312_ctrl_ops, 1305 V4L2_CID_VFLIP, 0, 1, 1, 0); 1306 1307 v4l2_ctrl_cluster(2, &thp7312->hflip); 1308 1309 v4l2_ctrl_new_int_menu(hdl, &thp7312_ctrl_ops, 1310 V4L2_CID_AUTO_EXPOSURE_BIAS, 1311 ARRAY_SIZE(exp_bias_qmenu) - 1, 1312 ARRAY_SIZE(exp_bias_qmenu) / 2, exp_bias_qmenu); 1313 1314 v4l2_ctrl_new_std_menu(hdl, &thp7312_ctrl_ops, 1315 V4L2_CID_POWER_LINE_FREQUENCY, 1316 V4L2_CID_POWER_LINE_FREQUENCY_60HZ, 0, 1317 V4L2_CID_POWER_LINE_FREQUENCY_50HZ); 1318 1319 thp7312->link_freq = thp7312_mode_info_data[0].rates[0].link_freq; 1320 1321 link_freq = v4l2_ctrl_new_int_menu(hdl, &thp7312_ctrl_ops, 1322 V4L2_CID_LINK_FREQ, 0, 0, 1323 &thp7312->link_freq); 1324 1325 /* Set properties from fwnode (e.g. rotation, orientation). */ 1326 ret = v4l2_fwnode_device_parse(dev, &props); 1327 if (ret) { 1328 dev_err(dev, "Failed to parse fwnode: %d\n", ret); 1329 goto error; 1330 } 1331 1332 ret = v4l2_ctrl_new_fwnode_properties(hdl, &thp7312_ctrl_ops, &props); 1333 if (ret) { 1334 dev_err(dev, "Failed to create new v4l2 ctrl for fwnode properties: %d\n", ret); 1335 goto error; 1336 } 1337 1338 for (i = 0; i < ARRAY_SIZE(thp7312_v4l2_ctrls_custom); i++) { 1339 const struct v4l2_ctrl_config *ctrl_cfg = 1340 &thp7312_v4l2_ctrls_custom[i]; 1341 struct v4l2_ctrl *ctrl; 1342 1343 ctrl = v4l2_ctrl_new_custom(hdl, ctrl_cfg, NULL); 1344 1345 if (ctrl_cfg->id == V4L2_CID_THP7312_NOISE_REDUCTION_AUTO) 1346 thp7312->noise_reduction_auto = ctrl; 1347 else if (ctrl_cfg->id == V4L2_CID_THP7312_NOISE_REDUCTION_ABSOLUTE) 1348 thp7312->noise_reduction_absolute = ctrl; 1349 } 1350 1351 v4l2_ctrl_cluster(2, &thp7312->noise_reduction_auto); 1352 1353 if (hdl->error) { 1354 dev_err(dev, "v4l2_ctrl_handler error\n"); 1355 ret = hdl->error; 1356 goto error; 1357 } 1358 1359 link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; 1360 1361 return ret; 1362 1363 error: 1364 v4l2_ctrl_handler_free(hdl); 1365 return ret; 1366 } 1367 1368 /* ----------------------------------------------------------------------------- 1369 * Firmware Update 1370 */ 1371 1372 /* 1373 * The firmware data is made of 128kB of RAM firmware, followed by a 1374 * variable-size "header". Both are stored in flash memory. 1375 */ 1376 #define THP7312_FW_RAM_SIZE (128 * 1024) 1377 #define THP7312_FW_MIN_SIZE (THP7312_FW_RAM_SIZE + 4) 1378 #define THP7312_FW_MAX_SIZE (THP7312_FW_RAM_SIZE + 64 * 1024) 1379 1380 /* 1381 * Data is first uploaded to the THP7312 128kB SRAM, and then written to flash. 1382 * The SRAM is exposed over I2C as 32kB banks, and up to 4kB of data can be 1383 * transferred in a single I2C write. 1384 */ 1385 #define THP7312_RAM_BANK_SIZE (32 * 1024) 1386 #define THP7312_FW_DOWNLOAD_UNIT (4 * 1024) 1387 1388 #define THP7312_FLASH_MEMORY_ERASE_TIMEOUT 40 1389 1390 #define THP7312_FLASH_MAX_REG_READ_SIZE 10 1391 #define THP7312_FLASH_MAX_REG_DATA_SIZE 10 1392 1393 static const u8 thp7312_cmd_config_flash_mem_if[] = { 1394 0xd5, 0x18, 0x00, 0x00, 0x00, 0x80 1395 }; 1396 1397 static const u8 thp7312_cmd_write_to_reg[] = { 1398 0xd5, 0x0c, 0x80, 0x00, 0x00, 0x00 1399 }; 1400 1401 static const u8 thp7312_cmd_read_reg[] = { 1402 0xd5, 0x04 1403 }; 1404 1405 /* 1406 * THP7312 Write data from RAM to Flash Memory 1407 * Command ID FF700F 1408 * Format: FF700F AA AA AA BB BB BB 1409 * AA AA AA: destination start address 1410 * BB BB BB: (write size - 1) 1411 * Source address always starts from 0 1412 */ 1413 static const u8 thp7312_cmd_write_ram_to_flash[] = { 0xff, 0x70, 0x0f }; 1414 1415 /* 1416 * THP7312 Calculate CRC command 1417 * Command ID: FF70 09 1418 * Format: FF70 09 AA AA AA BB BB BB 1419 * AA AA AA: Start address of calculation 1420 * BB BB BB: (calculate size - 1) 1421 */ 1422 static const u8 thp7312_cmd_calc_crc[] = { 0xff, 0x70, 0x09 }; 1423 1424 static const u8 thp7312_jedec_rdid[] = { SPINOR_OP_RDID, 0x00, 0x00, 0x00 }; 1425 static const u8 thp7312_jedec_rdsr[] = { SPINOR_OP_RDSR, 0x00, 0x00, 0x00 }; 1426 static const u8 thp7312_jedec_wen[] = { SPINOR_OP_WREN }; 1427 1428 static int thp7312_read_firmware_version(struct thp7312_device *thp7312) 1429 { 1430 u64 val = 0; 1431 int ret = 0; 1432 u8 major; 1433 u8 minor; 1434 1435 cci_read(thp7312->regmap, THP7312_REG_FIRMWARE_VERSION_1, &val, &ret); 1436 major = val; 1437 1438 cci_read(thp7312->regmap, THP7312_REG_FIRMWARE_VERSION_2, &val, &ret); 1439 minor = val; 1440 1441 thp7312->fw_version = THP7312_FW_VERSION(major, minor); 1442 return ret; 1443 } 1444 1445 static int thp7312_write_buf(struct thp7312_device *thp7312, 1446 const u8 *write_buf, u16 write_size) 1447 { 1448 struct i2c_client *client = to_i2c_client(thp7312->dev); 1449 int ret; 1450 1451 ret = i2c_master_send(client, write_buf, write_size); 1452 return ret >= 0 ? 0 : ret; 1453 } 1454 1455 static int __thp7312_flash_reg_write(struct thp7312_device *thp7312, 1456 const u8 *write_buf, u16 write_size) 1457 { 1458 struct device *dev = thp7312->dev; 1459 u8 temp_write_buf[THP7312_FLASH_MAX_REG_DATA_SIZE + 2]; 1460 int ret; 1461 1462 if (write_size > THP7312_FLASH_MAX_REG_DATA_SIZE) { 1463 dev_err(dev, "%s: Write size error size = %d\n", 1464 __func__, write_size); 1465 return -EINVAL; 1466 } 1467 1468 ret = thp7312_write_buf(thp7312, thp7312_cmd_config_flash_mem_if, 1469 sizeof(thp7312_cmd_config_flash_mem_if)); 1470 if (ret < 0) { 1471 dev_err(dev, "%s: Failed to config flash memory IF: %d\n", 1472 __func__, ret); 1473 return ret; 1474 } 1475 1476 temp_write_buf[0] = 0xd5; 1477 temp_write_buf[1] = 0x00; 1478 memcpy((temp_write_buf + 2), write_buf, write_size); 1479 ret = thp7312_write_buf(thp7312, temp_write_buf, write_size + 2); 1480 if (ret < 0) 1481 return ret; 1482 1483 thp7312_write_buf(thp7312, thp7312_cmd_write_to_reg, 1484 sizeof(thp7312_cmd_write_to_reg)); 1485 1486 return 0; 1487 } 1488 1489 static int __thp7312_flash_reg_read(struct thp7312_device *thp7312, 1490 const u8 *write_buf, u16 write_size, 1491 u8 *read_buf, u16 read_size) 1492 { 1493 struct i2c_client *client = to_i2c_client(thp7312->dev); 1494 struct i2c_msg msgs[2]; 1495 int ret; 1496 1497 ret = __thp7312_flash_reg_write(thp7312, write_buf, write_size); 1498 if (ret) 1499 return ret; 1500 1501 msgs[0].addr = client->addr; 1502 msgs[0].flags = 0; 1503 msgs[0].len = sizeof(thp7312_cmd_read_reg); 1504 msgs[0].buf = (u8 *)thp7312_cmd_read_reg; 1505 1506 msgs[1].addr = client->addr; 1507 msgs[1].flags = I2C_M_RD; 1508 msgs[1].len = read_size; 1509 msgs[1].buf = read_buf; 1510 1511 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); 1512 return ret >= 0 ? 0 : ret; 1513 } 1514 1515 #define thp7312_flash_reg_write(thp7312, wrbuf) \ 1516 __thp7312_flash_reg_write(thp7312, wrbuf, sizeof(wrbuf)) 1517 1518 #define thp7312_flash_reg_read(thp7312, wrbuf, rdbuf) \ 1519 __thp7312_flash_reg_read(thp7312, wrbuf, sizeof(wrbuf), \ 1520 rdbuf, sizeof(rdbuf)) 1521 1522 static enum fw_upload_err thp7312_fw_prepare_config(struct thp7312_device *thp7312) 1523 { 1524 struct device *dev = thp7312->dev; 1525 int ret; 1526 1527 ret = cci_write(thp7312->regmap, THP7312_REG_FW_MEMORY_IO_SETTING, 1528 THP7312_FW_MEMORY_IO_GPIO0, NULL); 1529 if (ret) { 1530 dev_err(dev, "Failed to set flash memory I/O\n"); 1531 return FW_UPLOAD_ERR_HW_ERROR; 1532 } 1533 1534 /* Set max drivability. */ 1535 ret = cci_write(thp7312->regmap, THP7312_REG_FW_DRIVABILITY, 0x00777777, 1536 NULL); 1537 if (ret) { 1538 dev_err(dev, "Failed to set drivability: %d\n", ret); 1539 return FW_UPLOAD_ERR_HW_ERROR; 1540 } 1541 1542 return FW_UPLOAD_ERR_NONE; 1543 } 1544 1545 static enum fw_upload_err thp7312_fw_prepare_check(struct thp7312_device *thp7312) 1546 { 1547 struct device *dev = thp7312->dev; 1548 u8 read_buf[3] = { 0 }; 1549 int ret; 1550 1551 /* Get JEDEC ID */ 1552 ret = thp7312_flash_reg_read(thp7312, thp7312_jedec_rdid, read_buf); 1553 if (ret) { 1554 dev_err(dev, "Failed to get JEDEC ID: %d\n", ret); 1555 return FW_UPLOAD_ERR_HW_ERROR; 1556 } 1557 1558 dev_dbg(dev, "Flash Memory: JEDEC ID = 0x%x 0x%x 0x%x\n", 1559 read_buf[0], read_buf[1], read_buf[2]); 1560 1561 return FW_UPLOAD_ERR_NONE; 1562 } 1563 1564 static enum fw_upload_err thp7312_fw_prepare_reset(struct thp7312_device *thp7312) 1565 { 1566 struct device *dev = thp7312->dev; 1567 int ret; 1568 1569 ret = cci_write(thp7312->regmap, THP7312_REG_FW_RESET_FLASH, 0x81, NULL); 1570 if (ret) { 1571 dev_err(dev, "Failed to reset flash memory: %d\n", ret); 1572 return FW_UPLOAD_ERR_HW_ERROR; 1573 } 1574 1575 return FW_UPLOAD_ERR_NONE; 1576 } 1577 1578 /* TODO: Erase only the amount of blocks necessary */ 1579 static enum fw_upload_err thp7312_flash_erase(struct thp7312_device *thp7312) 1580 { 1581 struct device *dev = thp7312->dev; 1582 u8 read_buf[1] = { 0 }; 1583 unsigned int i; 1584 u8 block; 1585 int ret; 1586 1587 for (block = 0; block < 3; block++) { 1588 const u8 jedec_se[] = { SPINOR_OP_SE, block, 0x00, 0x00 }; 1589 1590 ret = thp7312_flash_reg_write(thp7312, thp7312_jedec_wen); 1591 if (ret < 0) { 1592 dev_err(dev, "Failed to enable flash for writing\n"); 1593 return FW_UPLOAD_ERR_RW_ERROR; 1594 } 1595 1596 ret = thp7312_flash_reg_write(thp7312, jedec_se); 1597 if (ret < 0) { 1598 dev_err(dev, "Failed to erase flash sector\n"); 1599 return FW_UPLOAD_ERR_RW_ERROR; 1600 } 1601 1602 for (i = 0; i < THP7312_FLASH_MEMORY_ERASE_TIMEOUT; i++) { 1603 usleep_range(100000, 101000); 1604 thp7312_flash_reg_read(thp7312, thp7312_jedec_rdsr, 1605 read_buf); 1606 1607 /* Check Busy bit. Busy == 0x0 means erase complete. */ 1608 if (!(read_buf[0] & SR_WIP)) 1609 break; 1610 } 1611 1612 if (i == THP7312_FLASH_MEMORY_ERASE_TIMEOUT) 1613 return FW_UPLOAD_ERR_TIMEOUT; 1614 } 1615 1616 thp7312_flash_reg_read(thp7312, thp7312_jedec_rdsr, read_buf); 1617 1618 /* Check WEL bit. */ 1619 if (read_buf[0] & SR_WEL) 1620 return FW_UPLOAD_ERR_HW_ERROR; 1621 1622 return FW_UPLOAD_ERR_NONE; 1623 } 1624 1625 static enum fw_upload_err 1626 thp7312_write_download_data_by_unit(struct thp7312_device *thp7312, 1627 unsigned int addr, const u8 *data, 1628 unsigned int size) 1629 { 1630 struct device *dev = thp7312->dev; 1631 u8 *write_buf = thp7312->fw_write_buf; 1632 int ret; 1633 1634 dev_dbg(dev, "%s: addr = 0x%04x, data = 0x%p, size = %u\n", 1635 __func__, addr, data, size); 1636 1637 write_buf[0] = (addr >> 8) & 0xff; 1638 write_buf[1] = (addr >> 0) & 0xff; 1639 memcpy(&write_buf[2], data, size); 1640 1641 /* 1642 * THP7312 Firmware download to RAM 1643 * Command ID (address to download): 0x0000 - 0x7fff 1644 * Format:: 0000 XX XX XX ........ XX 1645 */ 1646 ret = thp7312_write_buf(thp7312, write_buf, size + 2); 1647 if (ret < 0) 1648 dev_err(dev, "Unit transfer ERROR %s(): ret = %d\n", __func__, ret); 1649 1650 return ret >= 0 ? FW_UPLOAD_ERR_NONE : FW_UPLOAD_ERR_RW_ERROR; 1651 } 1652 1653 static enum fw_upload_err thp7312_fw_load_to_ram(struct thp7312_device *thp7312, 1654 const u8 *data, u32 size) 1655 { 1656 struct device *dev = thp7312->dev; 1657 enum fw_upload_err ret; 1658 unsigned int num_banks; 1659 unsigned int i, j; 1660 1661 num_banks = DIV_ROUND_UP(size, THP7312_RAM_BANK_SIZE); 1662 1663 dev_dbg(dev, "%s: loading %u bytes in SRAM (%u banks)\n", __func__, 1664 size, num_banks); 1665 1666 for (i = 0; i < num_banks; i++) { 1667 const u32 bank_addr = 0x10000000 | (i * THP7312_RAM_BANK_SIZE); 1668 unsigned int bank_size; 1669 unsigned int num_chunks; 1670 1671 ret = cci_write(thp7312->regmap, THP7312_REG_FW_DEST_BANK_ADDR, 1672 bank_addr, NULL); 1673 if (ret) 1674 return FW_UPLOAD_ERR_HW_ERROR; 1675 1676 bank_size = min_t(u32, size, THP7312_RAM_BANK_SIZE); 1677 num_chunks = DIV_ROUND_UP(bank_size, THP7312_FW_DOWNLOAD_UNIT); 1678 1679 dev_dbg(dev, "%s: loading %u bytes in SRAM bank %u (%u chunks)\n", 1680 __func__, bank_size, i, num_chunks); 1681 1682 for (j = 0 ; j < num_chunks; j++) { 1683 unsigned int chunk_addr; 1684 unsigned int chunk_size; 1685 1686 chunk_addr = j * THP7312_FW_DOWNLOAD_UNIT; 1687 chunk_size = min_t(u32, size, THP7312_FW_DOWNLOAD_UNIT); 1688 1689 ret = thp7312_write_download_data_by_unit(thp7312, chunk_addr, 1690 data, chunk_size); 1691 if (ret != FW_UPLOAD_ERR_NONE) { 1692 dev_err(dev, "Unit transfer ERROR at bank transfer %s(): %d\n", 1693 __func__, j); 1694 return ret; 1695 } 1696 1697 data += chunk_size; 1698 size -= chunk_size; 1699 } 1700 } 1701 1702 return FW_UPLOAD_ERR_NONE; 1703 } 1704 1705 static enum fw_upload_err thp7312_fw_write_to_flash(struct thp7312_device *thp7312, 1706 u32 dest, u32 write_size) 1707 { 1708 u8 command[sizeof(thp7312_cmd_write_ram_to_flash) + 6]; 1709 static const u32 cmd_size = sizeof(thp7312_cmd_write_ram_to_flash); 1710 u64 val; 1711 int ret; 1712 1713 memcpy(command, thp7312_cmd_write_ram_to_flash, cmd_size); 1714 1715 command[cmd_size] = (dest & 0xff0000) >> 16; 1716 command[cmd_size + 1] = (dest & 0x00ff00) >> 8; 1717 command[cmd_size + 2] = (dest & 0x0000ff); 1718 command[cmd_size + 3] = ((write_size - 1) & 0xff0000) >> 16; 1719 command[cmd_size + 4] = ((write_size - 1) & 0x00ff00) >> 8; 1720 command[cmd_size + 5] = ((write_size - 1) & 0x0000ff); 1721 1722 ret = thp7312_write_buf(thp7312, command, sizeof(command)); 1723 if (ret < 0) 1724 return FW_UPLOAD_ERR_RW_ERROR; 1725 1726 usleep_range(8000000, 8100000); 1727 1728 ret = cci_read(thp7312->regmap, THP7312_REG_FW_VERIFY_RESULT, &val, 1729 NULL); 1730 if (ret < 0) 1731 return FW_UPLOAD_ERR_RW_ERROR; 1732 1733 return val ? FW_UPLOAD_ERR_HW_ERROR : FW_UPLOAD_ERR_NONE; 1734 } 1735 1736 static enum fw_upload_err thp7312_fw_check_crc(struct thp7312_device *thp7312, 1737 const u8 *fw_data, u32 fw_size) 1738 { 1739 struct device *dev = thp7312->dev; 1740 u16 header_size = fw_size - THP7312_FW_RAM_SIZE; 1741 u8 command[sizeof(thp7312_cmd_calc_crc) + 6]; 1742 static const u32 cmd_size = sizeof(thp7312_cmd_calc_crc); 1743 u32 size = THP7312_FW_RAM_SIZE - 4; 1744 u32 fw_crc; 1745 u64 crc; 1746 int ret; 1747 1748 memcpy(command, thp7312_cmd_calc_crc, cmd_size); 1749 1750 command[cmd_size] = 0; 1751 command[cmd_size + 1] = (header_size >> 8) & 0xff; 1752 command[cmd_size + 2] = header_size & 0xff; 1753 1754 command[cmd_size + 3] = (size >> 16) & 0xff; 1755 command[cmd_size + 4] = (size >> 8) & 0xff; 1756 command[cmd_size + 5] = size & 0xff; 1757 1758 ret = thp7312_write_buf(thp7312, command, sizeof(command)); 1759 if (ret < 0) 1760 return FW_UPLOAD_ERR_RW_ERROR; 1761 1762 usleep_range(2000000, 2100000); 1763 1764 fw_crc = get_unaligned_be32(&fw_data[fw_size - 4]); 1765 1766 ret = cci_read(thp7312->regmap, THP7312_REG_FW_CRC_RESULT, &crc, NULL); 1767 if (ret < 0) 1768 return FW_UPLOAD_ERR_RW_ERROR; 1769 1770 if (fw_crc != crc) { 1771 dev_err(dev, "CRC mismatch: firmware 0x%08x, flash 0x%08llx\n", 1772 fw_crc, crc); 1773 return FW_UPLOAD_ERR_HW_ERROR; 1774 } 1775 1776 return FW_UPLOAD_ERR_NONE; 1777 } 1778 1779 static enum fw_upload_err thp7312_fw_prepare(struct fw_upload *fw_upload, 1780 const u8 *data, u32 size) 1781 { 1782 struct thp7312_device *thp7312 = fw_upload->dd_handle; 1783 struct device *dev = thp7312->dev; 1784 enum fw_upload_err ret; 1785 1786 mutex_lock(&thp7312->fw_lock); 1787 thp7312->fw_cancel = false; 1788 mutex_unlock(&thp7312->fw_lock); 1789 1790 if (size < THP7312_FW_MIN_SIZE || size > THP7312_FW_MAX_SIZE) { 1791 dev_err(dev, "%s: Invalid firmware size %d; must be between %d and %d\n", 1792 __func__, size, THP7312_FW_MIN_SIZE, THP7312_FW_MAX_SIZE); 1793 return FW_UPLOAD_ERR_INVALID_SIZE; 1794 } 1795 1796 ret = thp7312_fw_prepare_config(thp7312); 1797 if (ret != FW_UPLOAD_ERR_NONE) 1798 return ret; 1799 1800 ret = thp7312_fw_prepare_check(thp7312); 1801 if (ret != FW_UPLOAD_ERR_NONE) 1802 return ret; 1803 1804 ret = thp7312_fw_prepare_reset(thp7312); 1805 if (ret != FW_UPLOAD_ERR_NONE) 1806 return ret; 1807 1808 mutex_lock(&thp7312->fw_lock); 1809 ret = thp7312->fw_cancel ? FW_UPLOAD_ERR_CANCELED : FW_UPLOAD_ERR_NONE; 1810 mutex_unlock(&thp7312->fw_lock); 1811 1812 return ret; 1813 } 1814 1815 static enum fw_upload_err thp7312_fw_write(struct fw_upload *fw_upload, 1816 const u8 *data, u32 offset, 1817 u32 size, u32 *written) 1818 { 1819 struct thp7312_device *thp7312 = fw_upload->dd_handle; 1820 struct device *dev = thp7312->dev; 1821 u16 header_size = size - THP7312_FW_RAM_SIZE; 1822 enum fw_upload_err ret; 1823 bool cancel; 1824 1825 mutex_lock(&thp7312->fw_lock); 1826 cancel = thp7312->fw_cancel; 1827 mutex_unlock(&thp7312->fw_lock); 1828 1829 if (cancel) 1830 return FW_UPLOAD_ERR_CANCELED; 1831 1832 ret = thp7312_flash_erase(thp7312); 1833 if (ret != FW_UPLOAD_ERR_NONE) 1834 return ret; 1835 1836 ret = thp7312_fw_load_to_ram(thp7312, data, THP7312_FW_RAM_SIZE); 1837 if (ret != FW_UPLOAD_ERR_NONE) 1838 return ret; 1839 1840 ret = thp7312_fw_write_to_flash(thp7312, 0, 0x1ffff); 1841 if (ret != FW_UPLOAD_ERR_NONE) 1842 return ret; 1843 1844 ret = thp7312_fw_load_to_ram(thp7312, data + THP7312_FW_RAM_SIZE, header_size); 1845 if (ret != FW_UPLOAD_ERR_NONE) 1846 return ret; 1847 1848 ret = thp7312_fw_write_to_flash(thp7312, 0x20000, header_size - 1); 1849 if (ret != FW_UPLOAD_ERR_NONE) 1850 return ret; 1851 1852 ret = thp7312_fw_check_crc(thp7312, data, size); 1853 if (ret != FW_UPLOAD_ERR_NONE) 1854 return ret; 1855 1856 dev_info(dev, "Successfully wrote firmware\n"); 1857 1858 *written = size; 1859 return FW_UPLOAD_ERR_NONE; 1860 } 1861 1862 static enum fw_upload_err thp7312_fw_poll_complete(struct fw_upload *fw_upload) 1863 { 1864 return FW_UPLOAD_ERR_NONE; 1865 } 1866 1867 /* 1868 * This may be called asynchronously with an on-going update. All other 1869 * functions are called sequentially in a single thread. To avoid contention on 1870 * register accesses, only update the cancel_request flag. Other functions will 1871 * check this flag and handle the cancel request synchronously. 1872 */ 1873 static void thp7312_fw_cancel(struct fw_upload *fw_upload) 1874 { 1875 struct thp7312_device *thp7312 = fw_upload->dd_handle; 1876 1877 mutex_lock(&thp7312->fw_lock); 1878 thp7312->fw_cancel = true; 1879 mutex_unlock(&thp7312->fw_lock); 1880 } 1881 1882 static const struct fw_upload_ops thp7312_fw_upload_ops = { 1883 .prepare = thp7312_fw_prepare, 1884 .write = thp7312_fw_write, 1885 .poll_complete = thp7312_fw_poll_complete, 1886 .cancel = thp7312_fw_cancel, 1887 }; 1888 1889 static int thp7312_register_flash_mode(struct thp7312_device *thp7312) 1890 { 1891 struct device *dev = thp7312->dev; 1892 struct fw_upload *fwl; 1893 u64 val; 1894 int ret; 1895 1896 dev_info(dev, "booted in flash mode\n"); 1897 1898 mutex_init(&thp7312->fw_lock); 1899 1900 thp7312->fw_write_buf = devm_kzalloc(dev, THP7312_FW_DOWNLOAD_UNIT + 2, 1901 GFP_KERNEL); 1902 if (!thp7312->fw_write_buf) 1903 return -ENOMEM; 1904 1905 ret = __thp7312_power_on(thp7312); 1906 if (ret < 0) 1907 return dev_err_probe(dev, ret, "Failed to power on\n"); 1908 1909 ret = cci_read(thp7312->regmap, THP7312_REG_FW_STATUS, &val, NULL); 1910 if (ret) { 1911 dev_err_probe(dev, ret, "Camera status read failed\n"); 1912 goto error; 1913 } 1914 1915 fwl = firmware_upload_register(THIS_MODULE, dev, "thp7312-firmware", 1916 &thp7312_fw_upload_ops, thp7312); 1917 if (IS_ERR(fwl)) { 1918 ret = PTR_ERR(fwl); 1919 dev_err_probe(dev, ret, "Failed to register firmware upload\n"); 1920 goto error; 1921 } 1922 1923 thp7312->fwl = fwl; 1924 return 0; 1925 1926 error: 1927 __thp7312_power_off(thp7312); 1928 return ret; 1929 } 1930 1931 /* ----------------------------------------------------------------------------- 1932 * Probe & Remove 1933 */ 1934 1935 static int thp7312_get_regulators(struct thp7312_device *thp7312) 1936 { 1937 unsigned int i; 1938 1939 for (i = 0; i < ARRAY_SIZE(thp7312->supplies); i++) 1940 thp7312->supplies[i].supply = thp7312_supply_name[i]; 1941 1942 return devm_regulator_bulk_get(thp7312->dev, 1943 ARRAY_SIZE(thp7312->supplies), 1944 thp7312->supplies); 1945 } 1946 1947 static int thp7312_sensor_parse_dt(struct thp7312_device *thp7312, 1948 struct fwnode_handle *node) 1949 { 1950 struct device *dev = thp7312->dev; 1951 struct thp7312_sensor *sensor; 1952 const char *model; 1953 u8 data_lanes[4]; 1954 u32 values[4]; 1955 unsigned int i; 1956 u32 reg; 1957 int ret; 1958 1959 /* Retrieve the sensor index from the reg property. */ 1960 ret = fwnode_property_read_u32(node, "reg", ®); 1961 if (ret < 0) { 1962 dev_err(dev, "'reg' property missing in sensor node\n"); 1963 return -EINVAL; 1964 } 1965 1966 if (reg >= ARRAY_SIZE(thp7312->sensors)) { 1967 dev_err(dev, "Out-of-bounds 'reg' value %u\n", reg); 1968 return -EINVAL; 1969 } 1970 1971 sensor = &thp7312->sensors[reg]; 1972 if (sensor->info) { 1973 dev_err(dev, "Duplicate entry for sensor %u\n", reg); 1974 return -EINVAL; 1975 } 1976 1977 ret = fwnode_property_read_string(node, "thine,model", &model); 1978 if (ret < 0) { 1979 dev_err(dev, "'thine,model' property missing in sensor node\n"); 1980 return -EINVAL; 1981 } 1982 1983 for (i = 0; i < ARRAY_SIZE(thp7312_sensor_info); i++) { 1984 const struct thp7312_sensor_info *info = 1985 &thp7312_sensor_info[i]; 1986 1987 if (!strcmp(info->model, model)) { 1988 sensor->info = info; 1989 break; 1990 } 1991 } 1992 1993 if (!sensor->info) { 1994 dev_err(dev, "Unsupported sensor model %s\n", model); 1995 return -EINVAL; 1996 } 1997 1998 ret = fwnode_property_read_u32_array(node, "data-lanes", values, 1999 ARRAY_SIZE(values)); 2000 if (ret < 0) { 2001 dev_err(dev, "Failed to read property data-lanes: %d\n", ret); 2002 return ret; 2003 } 2004 2005 for (i = 0; i < ARRAY_SIZE(data_lanes); ++i) 2006 data_lanes[i] = values[i]; 2007 2008 ret = thp7312_map_data_lanes(&sensor->lane_remap, data_lanes, 2009 ARRAY_SIZE(data_lanes)); 2010 if (ret) { 2011 dev_err(dev, "Invalid sensor@%u data-lanes value\n", reg); 2012 return ret; 2013 } 2014 2015 return 0; 2016 } 2017 2018 static int thp7312_parse_dt(struct thp7312_device *thp7312) 2019 { 2020 struct v4l2_fwnode_endpoint ep = { 2021 .bus_type = V4L2_MBUS_CSI2_DPHY, 2022 }; 2023 struct device *dev = thp7312->dev; 2024 struct fwnode_handle *endpoint; 2025 struct fwnode_handle *sensors; 2026 unsigned int num_sensors = 0; 2027 struct fwnode_handle *node; 2028 int ret; 2029 2030 endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(dev), NULL); 2031 if (!endpoint) 2032 return dev_err_probe(dev, -EINVAL, "Endpoint node not found\n"); 2033 2034 ret = v4l2_fwnode_endpoint_parse(endpoint, &ep); 2035 fwnode_handle_put(endpoint); 2036 if (ret) 2037 return dev_err_probe(dev, ret, "Could not parse endpoint\n"); 2038 2039 ret = thp7312_map_data_lanes(&thp7312->lane_remap, 2040 ep.bus.mipi_csi2.data_lanes, 2041 ep.bus.mipi_csi2.num_data_lanes); 2042 if (ret) { 2043 dev_err(dev, "Invalid data-lanes value\n"); 2044 return ret; 2045 } 2046 2047 /* 2048 * The thine,boot-mode property is optional and default to 2049 * THP7312_BOOT_MODE_SPI_MASTER (1). 2050 */ 2051 thp7312->boot_mode = THP7312_BOOT_MODE_SPI_MASTER; 2052 ret = device_property_read_u32(dev, "thine,boot-mode", 2053 &thp7312->boot_mode); 2054 if (ret && ret != -EINVAL) 2055 return dev_err_probe(dev, ret, "Property '%s' is invalid\n", 2056 "thine,boot-mode"); 2057 2058 if (thp7312->boot_mode != THP7312_BOOT_MODE_2WIRE_SLAVE && 2059 thp7312->boot_mode != THP7312_BOOT_MODE_SPI_MASTER) 2060 return dev_err_probe(dev, -EINVAL, "Invalid '%s' value %u\n", 2061 "thine,boot-mode", thp7312->boot_mode); 2062 2063 /* Sensors */ 2064 sensors = device_get_named_child_node(dev, "sensors"); 2065 if (!sensors) { 2066 dev_err(dev, "'sensors' child node not found\n"); 2067 return -EINVAL; 2068 } 2069 2070 fwnode_for_each_available_child_node(sensors, node) { 2071 if (fwnode_name_eq(node, "sensor")) { 2072 if (!thp7312_sensor_parse_dt(thp7312, node)) 2073 num_sensors++; 2074 } 2075 } 2076 2077 fwnode_handle_put(sensors); 2078 2079 if (!num_sensors) { 2080 dev_err(dev, "No sensor found\n"); 2081 return -EINVAL; 2082 } 2083 2084 return 0; 2085 } 2086 2087 static int thp7312_probe(struct i2c_client *client) 2088 { 2089 struct device *dev = &client->dev; 2090 struct thp7312_device *thp7312; 2091 int ret; 2092 2093 thp7312 = devm_kzalloc(dev, sizeof(*thp7312), GFP_KERNEL); 2094 if (!thp7312) 2095 return -ENOMEM; 2096 2097 thp7312->dev = dev; 2098 2099 thp7312->regmap = devm_cci_regmap_init_i2c(client, 16); 2100 if (IS_ERR(thp7312->regmap)) 2101 return dev_err_probe(dev, PTR_ERR(thp7312->regmap), 2102 "Unable to initialize I2C\n"); 2103 2104 ret = thp7312_parse_dt(thp7312); 2105 if (ret < 0) 2106 return ret; 2107 2108 ret = thp7312_get_regulators(thp7312); 2109 if (ret) 2110 return dev_err_probe(dev, ret, "Failed to get regulators\n"); 2111 2112 thp7312->iclk = devm_clk_get(dev, NULL); 2113 if (IS_ERR(thp7312->iclk)) 2114 return dev_err_probe(dev, PTR_ERR(thp7312->iclk), 2115 "Failed to get iclk\n"); 2116 2117 thp7312->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); 2118 if (IS_ERR(thp7312->reset_gpio)) 2119 return dev_err_probe(dev, PTR_ERR(thp7312->reset_gpio), 2120 "Failed to get reset gpio\n"); 2121 2122 if (thp7312->boot_mode == THP7312_BOOT_MODE_2WIRE_SLAVE) 2123 return thp7312_register_flash_mode(thp7312); 2124 2125 v4l2_i2c_subdev_init(&thp7312->sd, client, &thp7312_subdev_ops); 2126 thp7312->sd.internal_ops = &thp7312_internal_ops; 2127 thp7312->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 2128 thp7312->pad.flags = MEDIA_PAD_FL_SOURCE; 2129 thp7312->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 2130 2131 ret = media_entity_pads_init(&thp7312->sd.entity, 1, &thp7312->pad); 2132 if (ret) 2133 return ret; 2134 2135 /* 2136 * Enable power management. The driver supports runtime PM, but needs to 2137 * work when runtime PM is disabled in the kernel. To that end, power 2138 * the device manually here. 2139 */ 2140 ret = thp7312_power_on(thp7312); 2141 if (ret) 2142 goto err_entity_cleanup; 2143 2144 ret = thp7312_read_firmware_version(thp7312); 2145 if (ret < 0) { 2146 dev_err(dev, "Camera is not found\n"); 2147 goto err_power_off; 2148 } 2149 2150 ret = thp7312_init_controls(thp7312); 2151 if (ret) { 2152 dev_err(dev, "Failed to initialize controls\n"); 2153 goto err_power_off; 2154 } 2155 2156 thp7312->sd.ctrl_handler = &thp7312->ctrl_handler; 2157 thp7312->sd.state_lock = thp7312->ctrl_handler.lock; 2158 2159 ret = v4l2_subdev_init_finalize(&thp7312->sd); 2160 if (ret < 0) { 2161 dev_err(dev, "Subdev active state initialization failed\n"); 2162 goto err_free_ctrls; 2163 } 2164 2165 /* 2166 * Enable runtime PM with autosuspend. As the device has been powered 2167 * manually, mark it as active, and increase the usage count without 2168 * resuming the device. 2169 */ 2170 pm_runtime_set_active(dev); 2171 pm_runtime_get_noresume(dev); 2172 pm_runtime_enable(dev); 2173 pm_runtime_set_autosuspend_delay(dev, 1000); 2174 pm_runtime_use_autosuspend(dev); 2175 2176 ret = v4l2_async_register_subdev(&thp7312->sd); 2177 if (ret < 0) { 2178 dev_err(dev, "Subdev registration failed\n"); 2179 goto err_pm; 2180 } 2181 2182 /* 2183 * Decrease the PM usage count. The device will get suspended after the 2184 * autosuspend delay, turning the power off. 2185 */ 2186 pm_runtime_mark_last_busy(dev); 2187 pm_runtime_put_autosuspend(dev); 2188 2189 dev_info(dev, "THP7312 firmware version %02u.%02u\n", 2190 THP7312_FW_VERSION_MAJOR(thp7312->fw_version), 2191 THP7312_FW_VERSION_MINOR(thp7312->fw_version)); 2192 2193 return 0; 2194 2195 err_pm: 2196 pm_runtime_disable(dev); 2197 pm_runtime_put_noidle(dev); 2198 v4l2_subdev_cleanup(&thp7312->sd); 2199 err_free_ctrls: 2200 v4l2_ctrl_handler_free(&thp7312->ctrl_handler); 2201 err_power_off: 2202 thp7312_power_off(thp7312); 2203 err_entity_cleanup: 2204 media_entity_cleanup(&thp7312->sd.entity); 2205 return ret; 2206 } 2207 2208 static void thp7312_remove(struct i2c_client *client) 2209 { 2210 struct v4l2_subdev *sd = i2c_get_clientdata(client); 2211 struct thp7312_device *thp7312 = to_thp7312_dev(sd); 2212 2213 if (thp7312->boot_mode == THP7312_BOOT_MODE_2WIRE_SLAVE) { 2214 firmware_upload_unregister(thp7312->fwl); 2215 __thp7312_power_off(thp7312); 2216 return; 2217 } 2218 2219 v4l2_async_unregister_subdev(&thp7312->sd); 2220 v4l2_subdev_cleanup(&thp7312->sd); 2221 media_entity_cleanup(&thp7312->sd.entity); 2222 v4l2_ctrl_handler_free(&thp7312->ctrl_handler); 2223 2224 /* 2225 * Disable runtime PM. In case runtime PM is disabled in the kernel, 2226 * make sure to turn power off manually. 2227 */ 2228 pm_runtime_disable(thp7312->dev); 2229 if (!pm_runtime_status_suspended(thp7312->dev)) 2230 thp7312_power_off(thp7312); 2231 pm_runtime_set_suspended(thp7312->dev); 2232 } 2233 2234 static const struct of_device_id thp7312_dt_ids[] = { 2235 { .compatible = "thine,thp7312" }, 2236 { /* sentinel */ } 2237 }; 2238 MODULE_DEVICE_TABLE(of, thp7312_dt_ids); 2239 2240 static struct i2c_driver thp7312_i2c_driver = { 2241 .driver = { 2242 .name = "thp7312", 2243 .pm = &thp7312_pm_ops, 2244 .of_match_table = thp7312_dt_ids, 2245 }, 2246 .probe = thp7312_probe, 2247 .remove = thp7312_remove, 2248 }; 2249 2250 module_i2c_driver(thp7312_i2c_driver); 2251 2252 MODULE_DESCRIPTION("THP7312 MIPI Camera Subdev Driver"); 2253 MODULE_LICENSE("GPL"); 2254