1 /* 2 * tc358743 - Toshiba HDMI to CSI-2 bridge 3 * 4 * Copyright 2015 Cisco Systems, Inc. and/or its affiliates. All rights 5 * reserved. 6 * 7 * This program is free software; you may redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; version 2 of the License. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 12 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 13 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 14 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 15 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 16 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 17 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 18 * SOFTWARE. 19 * 20 */ 21 22 /* 23 * References (c = chapter, p = page): 24 * REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60 25 * REF_02 - Toshiba, TC358743XBG_HDMI-CSI_Tv11p_nm.xls 26 */ 27 28 #include <linux/kernel.h> 29 #include <linux/module.h> 30 #include <linux/slab.h> 31 #include <linux/i2c.h> 32 #include <linux/clk.h> 33 #include <linux/delay.h> 34 #include <linux/gpio/consumer.h> 35 #include <linux/interrupt.h> 36 #include <linux/videodev2.h> 37 #include <linux/workqueue.h> 38 #include <linux/v4l2-dv-timings.h> 39 #include <linux/hdmi.h> 40 #include <media/v4l2-dv-timings.h> 41 #include <media/v4l2-device.h> 42 #include <media/v4l2-ctrls.h> 43 #include <media/v4l2-event.h> 44 #include <media/v4l2-of.h> 45 #include <media/i2c/tc358743.h> 46 47 #include "tc358743_regs.h" 48 49 static int debug; 50 module_param(debug, int, 0644); 51 MODULE_PARM_DESC(debug, "debug level (0-3)"); 52 53 MODULE_DESCRIPTION("Toshiba TC358743 HDMI to CSI-2 bridge driver"); 54 MODULE_AUTHOR("Ramakrishnan Muthukrishnan <ram@rkrishnan.org>"); 55 MODULE_AUTHOR("Mikhail Khelik <mkhelik@cisco.com>"); 56 MODULE_AUTHOR("Mats Randgaard <matrandg@cisco.com>"); 57 MODULE_LICENSE("GPL"); 58 59 #define EDID_NUM_BLOCKS_MAX 8 60 #define EDID_BLOCK_SIZE 128 61 62 #define I2C_MAX_XFER_SIZE (EDID_BLOCK_SIZE + 2) 63 64 static const struct v4l2_dv_timings_cap tc358743_timings_cap = { 65 .type = V4L2_DV_BT_656_1120, 66 /* keep this initialization for compatibility with GCC < 4.4.6 */ 67 .reserved = { 0 }, 68 /* Pixel clock from REF_01 p. 20. Min/max height/width are unknown */ 69 V4L2_INIT_BT_TIMINGS(1, 10000, 1, 10000, 0, 165000000, 70 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | 71 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT, 72 V4L2_DV_BT_CAP_PROGRESSIVE | 73 V4L2_DV_BT_CAP_REDUCED_BLANKING | 74 V4L2_DV_BT_CAP_CUSTOM) 75 }; 76 77 struct tc358743_state { 78 struct tc358743_platform_data pdata; 79 struct v4l2_of_bus_mipi_csi2 bus; 80 struct v4l2_subdev sd; 81 struct media_pad pad; 82 struct v4l2_ctrl_handler hdl; 83 struct i2c_client *i2c_client; 84 /* CONFCTL is modified in ops and tc358743_hdmi_sys_int_handler */ 85 struct mutex confctl_mutex; 86 87 /* controls */ 88 struct v4l2_ctrl *detect_tx_5v_ctrl; 89 struct v4l2_ctrl *audio_sampling_rate_ctrl; 90 struct v4l2_ctrl *audio_present_ctrl; 91 92 struct delayed_work delayed_work_enable_hotplug; 93 94 /* edid */ 95 u8 edid_blocks_written; 96 97 struct v4l2_dv_timings timings; 98 u32 mbus_fmt_code; 99 u8 csi_lanes_in_use; 100 101 struct gpio_desc *reset_gpio; 102 }; 103 104 static void tc358743_enable_interrupts(struct v4l2_subdev *sd, 105 bool cable_connected); 106 static int tc358743_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd); 107 108 static inline struct tc358743_state *to_state(struct v4l2_subdev *sd) 109 { 110 return container_of(sd, struct tc358743_state, sd); 111 } 112 113 /* --------------- I2C --------------- */ 114 115 static void i2c_rd(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n) 116 { 117 struct tc358743_state *state = to_state(sd); 118 struct i2c_client *client = state->i2c_client; 119 int err; 120 u8 buf[2] = { reg >> 8, reg & 0xff }; 121 struct i2c_msg msgs[] = { 122 { 123 .addr = client->addr, 124 .flags = 0, 125 .len = 2, 126 .buf = buf, 127 }, 128 { 129 .addr = client->addr, 130 .flags = I2C_M_RD, 131 .len = n, 132 .buf = values, 133 }, 134 }; 135 136 err = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); 137 if (err != ARRAY_SIZE(msgs)) { 138 v4l2_err(sd, "%s: reading register 0x%x from 0x%x failed\n", 139 __func__, reg, client->addr); 140 } 141 } 142 143 static void i2c_wr(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n) 144 { 145 struct tc358743_state *state = to_state(sd); 146 struct i2c_client *client = state->i2c_client; 147 int err, i; 148 struct i2c_msg msg; 149 u8 data[I2C_MAX_XFER_SIZE]; 150 151 if ((2 + n) > I2C_MAX_XFER_SIZE) { 152 n = I2C_MAX_XFER_SIZE - 2; 153 v4l2_warn(sd, "i2c wr reg=%04x: len=%d is too big!\n", 154 reg, 2 + n); 155 } 156 157 msg.addr = client->addr; 158 msg.buf = data; 159 msg.len = 2 + n; 160 msg.flags = 0; 161 162 data[0] = reg >> 8; 163 data[1] = reg & 0xff; 164 165 for (i = 0; i < n; i++) 166 data[2 + i] = values[i]; 167 168 err = i2c_transfer(client->adapter, &msg, 1); 169 if (err != 1) { 170 v4l2_err(sd, "%s: writing register 0x%x from 0x%x failed\n", 171 __func__, reg, client->addr); 172 return; 173 } 174 175 if (debug < 3) 176 return; 177 178 switch (n) { 179 case 1: 180 v4l2_info(sd, "I2C write 0x%04x = 0x%02x", 181 reg, data[2]); 182 break; 183 case 2: 184 v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x", 185 reg, data[3], data[2]); 186 break; 187 case 4: 188 v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x%02x%02x", 189 reg, data[5], data[4], data[3], data[2]); 190 break; 191 default: 192 v4l2_info(sd, "I2C write %d bytes from address 0x%04x\n", 193 n, reg); 194 } 195 } 196 197 static noinline u32 i2c_rdreg(struct v4l2_subdev *sd, u16 reg, u32 n) 198 { 199 __le32 val = 0; 200 201 i2c_rd(sd, reg, (u8 __force *)&val, n); 202 203 return le32_to_cpu(val); 204 } 205 206 static noinline void i2c_wrreg(struct v4l2_subdev *sd, u16 reg, u32 val, u32 n) 207 { 208 __le32 raw = cpu_to_le32(val); 209 210 i2c_wr(sd, reg, (u8 __force *)&raw, n); 211 } 212 213 static u8 i2c_rd8(struct v4l2_subdev *sd, u16 reg) 214 { 215 return i2c_rdreg(sd, reg, 1); 216 } 217 218 static void i2c_wr8(struct v4l2_subdev *sd, u16 reg, u8 val) 219 { 220 i2c_wrreg(sd, reg, val, 1); 221 } 222 223 static void i2c_wr8_and_or(struct v4l2_subdev *sd, u16 reg, 224 u8 mask, u8 val) 225 { 226 i2c_wrreg(sd, reg, (i2c_rdreg(sd, reg, 2) & mask) | val, 2); 227 } 228 229 static u16 i2c_rd16(struct v4l2_subdev *sd, u16 reg) 230 { 231 return i2c_rdreg(sd, reg, 2); 232 } 233 234 static void i2c_wr16(struct v4l2_subdev *sd, u16 reg, u16 val) 235 { 236 i2c_wrreg(sd, reg, val, 2); 237 } 238 239 static void i2c_wr16_and_or(struct v4l2_subdev *sd, u16 reg, u16 mask, u16 val) 240 { 241 i2c_wrreg(sd, reg, (i2c_rdreg(sd, reg, 2) & mask) | val, 2); 242 } 243 244 static u32 i2c_rd32(struct v4l2_subdev *sd, u16 reg) 245 { 246 return i2c_rdreg(sd, reg, 4); 247 } 248 249 static void i2c_wr32(struct v4l2_subdev *sd, u16 reg, u32 val) 250 { 251 i2c_wrreg(sd, reg, val, 4); 252 } 253 254 /* --------------- STATUS --------------- */ 255 256 static inline bool is_hdmi(struct v4l2_subdev *sd) 257 { 258 return i2c_rd8(sd, SYS_STATUS) & MASK_S_HDMI; 259 } 260 261 static inline bool tx_5v_power_present(struct v4l2_subdev *sd) 262 { 263 return i2c_rd8(sd, SYS_STATUS) & MASK_S_DDC5V; 264 } 265 266 static inline bool no_signal(struct v4l2_subdev *sd) 267 { 268 return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_TMDS); 269 } 270 271 static inline bool no_sync(struct v4l2_subdev *sd) 272 { 273 return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_SYNC); 274 } 275 276 static inline bool audio_present(struct v4l2_subdev *sd) 277 { 278 return i2c_rd8(sd, AU_STATUS0) & MASK_S_A_SAMPLE; 279 } 280 281 static int get_audio_sampling_rate(struct v4l2_subdev *sd) 282 { 283 static const int code_to_rate[] = { 284 44100, 0, 48000, 32000, 22050, 384000, 24000, 352800, 285 88200, 768000, 96000, 705600, 176400, 0, 192000, 0 286 }; 287 288 /* Register FS_SET is not cleared when the cable is disconnected */ 289 if (no_signal(sd)) 290 return 0; 291 292 return code_to_rate[i2c_rd8(sd, FS_SET) & MASK_FS]; 293 } 294 295 /* --------------- TIMINGS --------------- */ 296 297 static inline unsigned fps(const struct v4l2_bt_timings *t) 298 { 299 if (!V4L2_DV_BT_FRAME_HEIGHT(t) || !V4L2_DV_BT_FRAME_WIDTH(t)) 300 return 0; 301 302 return DIV_ROUND_CLOSEST((unsigned)t->pixelclock, 303 V4L2_DV_BT_FRAME_HEIGHT(t) * V4L2_DV_BT_FRAME_WIDTH(t)); 304 } 305 306 static int tc358743_get_detected_timings(struct v4l2_subdev *sd, 307 struct v4l2_dv_timings *timings) 308 { 309 struct v4l2_bt_timings *bt = &timings->bt; 310 unsigned width, height, frame_width, frame_height, frame_interval, fps; 311 312 memset(timings, 0, sizeof(struct v4l2_dv_timings)); 313 314 if (no_signal(sd)) { 315 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__); 316 return -ENOLINK; 317 } 318 if (no_sync(sd)) { 319 v4l2_dbg(1, debug, sd, "%s: no sync on signal\n", __func__); 320 return -ENOLCK; 321 } 322 323 timings->type = V4L2_DV_BT_656_1120; 324 bt->interlaced = i2c_rd8(sd, VI_STATUS1) & MASK_S_V_INTERLACE ? 325 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE; 326 327 width = ((i2c_rd8(sd, DE_WIDTH_H_HI) & 0x1f) << 8) + 328 i2c_rd8(sd, DE_WIDTH_H_LO); 329 height = ((i2c_rd8(sd, DE_WIDTH_V_HI) & 0x1f) << 8) + 330 i2c_rd8(sd, DE_WIDTH_V_LO); 331 frame_width = ((i2c_rd8(sd, H_SIZE_HI) & 0x1f) << 8) + 332 i2c_rd8(sd, H_SIZE_LO); 333 frame_height = (((i2c_rd8(sd, V_SIZE_HI) & 0x3f) << 8) + 334 i2c_rd8(sd, V_SIZE_LO)) / 2; 335 /* frame interval in milliseconds * 10 336 * Require SYS_FREQ0 and SYS_FREQ1 are precisely set */ 337 frame_interval = ((i2c_rd8(sd, FV_CNT_HI) & 0x3) << 8) + 338 i2c_rd8(sd, FV_CNT_LO); 339 fps = (frame_interval > 0) ? 340 DIV_ROUND_CLOSEST(10000, frame_interval) : 0; 341 342 bt->width = width; 343 bt->height = height; 344 bt->vsync = frame_height - height; 345 bt->hsync = frame_width - width; 346 bt->pixelclock = frame_width * frame_height * fps; 347 if (bt->interlaced == V4L2_DV_INTERLACED) { 348 bt->height *= 2; 349 bt->il_vsync = bt->vsync + 1; 350 bt->pixelclock /= 2; 351 } 352 353 return 0; 354 } 355 356 /* --------------- HOTPLUG / HDCP / EDID --------------- */ 357 358 static void tc358743_delayed_work_enable_hotplug(struct work_struct *work) 359 { 360 struct delayed_work *dwork = to_delayed_work(work); 361 struct tc358743_state *state = container_of(dwork, 362 struct tc358743_state, delayed_work_enable_hotplug); 363 struct v4l2_subdev *sd = &state->sd; 364 365 v4l2_dbg(2, debug, sd, "%s:\n", __func__); 366 367 i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, MASK_HPD_OUT0); 368 } 369 370 static void tc358743_set_hdmi_hdcp(struct v4l2_subdev *sd, bool enable) 371 { 372 v4l2_dbg(2, debug, sd, "%s: %s\n", __func__, enable ? 373 "enable" : "disable"); 374 375 if (enable) { 376 i2c_wr8_and_or(sd, HDCP_REG3, ~KEY_RD_CMD, KEY_RD_CMD); 377 378 i2c_wr8_and_or(sd, HDCP_MODE, ~MASK_MANUAL_AUTHENTICATION, 0); 379 380 i2c_wr8_and_or(sd, HDCP_REG1, 0xff, 381 MASK_AUTH_UNAUTH_SEL_16_FRAMES | 382 MASK_AUTH_UNAUTH_AUTO); 383 384 i2c_wr8_and_or(sd, HDCP_REG2, ~MASK_AUTO_P3_RESET, 385 SET_AUTO_P3_RESET_FRAMES(0x0f)); 386 } else { 387 i2c_wr8_and_or(sd, HDCP_MODE, ~MASK_MANUAL_AUTHENTICATION, 388 MASK_MANUAL_AUTHENTICATION); 389 } 390 } 391 392 static void tc358743_disable_edid(struct v4l2_subdev *sd) 393 { 394 struct tc358743_state *state = to_state(sd); 395 396 v4l2_dbg(2, debug, sd, "%s:\n", __func__); 397 398 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug); 399 400 /* DDC access to EDID is also disabled when hotplug is disabled. See 401 * register DDC_CTL */ 402 i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, 0x0); 403 } 404 405 static void tc358743_enable_edid(struct v4l2_subdev *sd) 406 { 407 struct tc358743_state *state = to_state(sd); 408 409 if (state->edid_blocks_written == 0) { 410 v4l2_dbg(2, debug, sd, "%s: no EDID -> no hotplug\n", __func__); 411 tc358743_s_ctrl_detect_tx_5v(sd); 412 return; 413 } 414 415 v4l2_dbg(2, debug, sd, "%s:\n", __func__); 416 417 /* Enable hotplug after 100 ms. DDC access to EDID is also enabled when 418 * hotplug is enabled. See register DDC_CTL */ 419 schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 10); 420 421 tc358743_enable_interrupts(sd, true); 422 tc358743_s_ctrl_detect_tx_5v(sd); 423 } 424 425 static void tc358743_erase_bksv(struct v4l2_subdev *sd) 426 { 427 int i; 428 429 for (i = 0; i < 5; i++) 430 i2c_wr8(sd, BKSV + i, 0); 431 } 432 433 /* --------------- AVI infoframe --------------- */ 434 435 static void print_avi_infoframe(struct v4l2_subdev *sd) 436 { 437 struct i2c_client *client = v4l2_get_subdevdata(sd); 438 struct device *dev = &client->dev; 439 union hdmi_infoframe frame; 440 u8 buffer[HDMI_INFOFRAME_SIZE(AVI)]; 441 442 if (!is_hdmi(sd)) { 443 v4l2_info(sd, "DVI-D signal - AVI infoframe not supported\n"); 444 return; 445 } 446 447 i2c_rd(sd, PK_AVI_0HEAD, buffer, HDMI_INFOFRAME_SIZE(AVI)); 448 449 if (hdmi_infoframe_unpack(&frame, buffer) < 0) { 450 v4l2_err(sd, "%s: unpack of AVI infoframe failed\n", __func__); 451 return; 452 } 453 454 hdmi_infoframe_log(KERN_INFO, dev, &frame); 455 } 456 457 /* --------------- CTRLS --------------- */ 458 459 static int tc358743_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd) 460 { 461 struct tc358743_state *state = to_state(sd); 462 463 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, 464 tx_5v_power_present(sd)); 465 } 466 467 static int tc358743_s_ctrl_audio_sampling_rate(struct v4l2_subdev *sd) 468 { 469 struct tc358743_state *state = to_state(sd); 470 471 return v4l2_ctrl_s_ctrl(state->audio_sampling_rate_ctrl, 472 get_audio_sampling_rate(sd)); 473 } 474 475 static int tc358743_s_ctrl_audio_present(struct v4l2_subdev *sd) 476 { 477 struct tc358743_state *state = to_state(sd); 478 479 return v4l2_ctrl_s_ctrl(state->audio_present_ctrl, 480 audio_present(sd)); 481 } 482 483 static int tc358743_update_controls(struct v4l2_subdev *sd) 484 { 485 int ret = 0; 486 487 ret |= tc358743_s_ctrl_detect_tx_5v(sd); 488 ret |= tc358743_s_ctrl_audio_sampling_rate(sd); 489 ret |= tc358743_s_ctrl_audio_present(sd); 490 491 return ret; 492 } 493 494 /* --------------- INIT --------------- */ 495 496 static void tc358743_reset_phy(struct v4l2_subdev *sd) 497 { 498 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 499 500 i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, 0); 501 i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, MASK_RESET_CTRL); 502 } 503 504 static void tc358743_reset(struct v4l2_subdev *sd, uint16_t mask) 505 { 506 u16 sysctl = i2c_rd16(sd, SYSCTL); 507 508 i2c_wr16(sd, SYSCTL, sysctl | mask); 509 i2c_wr16(sd, SYSCTL, sysctl & ~mask); 510 } 511 512 static inline void tc358743_sleep_mode(struct v4l2_subdev *sd, bool enable) 513 { 514 i2c_wr16_and_or(sd, SYSCTL, ~MASK_SLEEP, 515 enable ? MASK_SLEEP : 0); 516 } 517 518 static inline void enable_stream(struct v4l2_subdev *sd, bool enable) 519 { 520 struct tc358743_state *state = to_state(sd); 521 522 v4l2_dbg(3, debug, sd, "%s: %sable\n", 523 __func__, enable ? "en" : "dis"); 524 525 if (enable) { 526 /* It is critical for CSI receiver to see lane transition 527 * LP11->HS. Set to non-continuous mode to enable clock lane 528 * LP11 state. */ 529 i2c_wr32(sd, TXOPTIONCNTRL, 0); 530 /* Set to continuous mode to trigger LP11->HS transition */ 531 i2c_wr32(sd, TXOPTIONCNTRL, MASK_CONTCLKMODE); 532 /* Unmute video */ 533 i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE); 534 } else { 535 /* Mute video so that all data lanes go to LSP11 state. 536 * No data is output to CSI Tx block. */ 537 i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE | MASK_VI_MUTE); 538 } 539 540 mutex_lock(&state->confctl_mutex); 541 i2c_wr16_and_or(sd, CONFCTL, ~(MASK_VBUFEN | MASK_ABUFEN), 542 enable ? (MASK_VBUFEN | MASK_ABUFEN) : 0x0); 543 mutex_unlock(&state->confctl_mutex); 544 } 545 546 static void tc358743_set_pll(struct v4l2_subdev *sd) 547 { 548 struct tc358743_state *state = to_state(sd); 549 struct tc358743_platform_data *pdata = &state->pdata; 550 u16 pllctl0 = i2c_rd16(sd, PLLCTL0); 551 u16 pllctl1 = i2c_rd16(sd, PLLCTL1); 552 u16 pllctl0_new = SET_PLL_PRD(pdata->pll_prd) | 553 SET_PLL_FBD(pdata->pll_fbd); 554 u32 hsck = (pdata->refclk_hz / pdata->pll_prd) * pdata->pll_fbd; 555 556 v4l2_dbg(2, debug, sd, "%s:\n", __func__); 557 558 /* Only rewrite when needed (new value or disabled), since rewriting 559 * triggers another format change event. */ 560 if ((pllctl0 != pllctl0_new) || ((pllctl1 & MASK_PLL_EN) == 0)) { 561 u16 pll_frs; 562 563 if (hsck > 500000000) 564 pll_frs = 0x0; 565 else if (hsck > 250000000) 566 pll_frs = 0x1; 567 else if (hsck > 125000000) 568 pll_frs = 0x2; 569 else 570 pll_frs = 0x3; 571 572 v4l2_dbg(1, debug, sd, "%s: updating PLL clock\n", __func__); 573 tc358743_sleep_mode(sd, true); 574 i2c_wr16(sd, PLLCTL0, pllctl0_new); 575 i2c_wr16_and_or(sd, PLLCTL1, 576 ~(MASK_PLL_FRS | MASK_RESETB | MASK_PLL_EN), 577 (SET_PLL_FRS(pll_frs) | MASK_RESETB | 578 MASK_PLL_EN)); 579 udelay(10); /* REF_02, Sheet "Source HDMI" */ 580 i2c_wr16_and_or(sd, PLLCTL1, ~MASK_CKEN, MASK_CKEN); 581 tc358743_sleep_mode(sd, false); 582 } 583 } 584 585 static void tc358743_set_ref_clk(struct v4l2_subdev *sd) 586 { 587 struct tc358743_state *state = to_state(sd); 588 struct tc358743_platform_data *pdata = &state->pdata; 589 u32 sys_freq; 590 u32 lockdet_ref; 591 u16 fh_min; 592 u16 fh_max; 593 594 BUG_ON(!(pdata->refclk_hz == 26000000 || 595 pdata->refclk_hz == 27000000 || 596 pdata->refclk_hz == 42000000)); 597 598 sys_freq = pdata->refclk_hz / 10000; 599 i2c_wr8(sd, SYS_FREQ0, sys_freq & 0x00ff); 600 i2c_wr8(sd, SYS_FREQ1, (sys_freq & 0xff00) >> 8); 601 602 i2c_wr8_and_or(sd, PHY_CTL0, ~MASK_PHY_SYSCLK_IND, 603 (pdata->refclk_hz == 42000000) ? 604 MASK_PHY_SYSCLK_IND : 0x0); 605 606 fh_min = pdata->refclk_hz / 100000; 607 i2c_wr8(sd, FH_MIN0, fh_min & 0x00ff); 608 i2c_wr8(sd, FH_MIN1, (fh_min & 0xff00) >> 8); 609 610 fh_max = (fh_min * 66) / 10; 611 i2c_wr8(sd, FH_MAX0, fh_max & 0x00ff); 612 i2c_wr8(sd, FH_MAX1, (fh_max & 0xff00) >> 8); 613 614 lockdet_ref = pdata->refclk_hz / 100; 615 i2c_wr8(sd, LOCKDET_REF0, lockdet_ref & 0x0000ff); 616 i2c_wr8(sd, LOCKDET_REF1, (lockdet_ref & 0x00ff00) >> 8); 617 i2c_wr8(sd, LOCKDET_REF2, (lockdet_ref & 0x0f0000) >> 16); 618 619 i2c_wr8_and_or(sd, NCO_F0_MOD, ~MASK_NCO_F0_MOD, 620 (pdata->refclk_hz == 27000000) ? 621 MASK_NCO_F0_MOD_27MHZ : 0x0); 622 } 623 624 static void tc358743_set_csi_color_space(struct v4l2_subdev *sd) 625 { 626 struct tc358743_state *state = to_state(sd); 627 628 switch (state->mbus_fmt_code) { 629 case MEDIA_BUS_FMT_UYVY8_1X16: 630 v4l2_dbg(2, debug, sd, "%s: YCbCr 422 16-bit\n", __func__); 631 i2c_wr8_and_or(sd, VOUT_SET2, 632 ~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff, 633 MASK_SEL422 | MASK_VOUT_422FIL_100); 634 i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff, 635 MASK_VOUT_COLOR_601_YCBCR_LIMITED); 636 mutex_lock(&state->confctl_mutex); 637 i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT, 638 MASK_YCBCRFMT_422_8_BIT); 639 mutex_unlock(&state->confctl_mutex); 640 break; 641 case MEDIA_BUS_FMT_RGB888_1X24: 642 v4l2_dbg(2, debug, sd, "%s: RGB 888 24-bit\n", __func__); 643 i2c_wr8_and_or(sd, VOUT_SET2, 644 ~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff, 645 0x00); 646 i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff, 647 MASK_VOUT_COLOR_RGB_FULL); 648 mutex_lock(&state->confctl_mutex); 649 i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT, 0); 650 mutex_unlock(&state->confctl_mutex); 651 break; 652 default: 653 v4l2_dbg(2, debug, sd, "%s: Unsupported format code 0x%x\n", 654 __func__, state->mbus_fmt_code); 655 } 656 } 657 658 static unsigned tc358743_num_csi_lanes_needed(struct v4l2_subdev *sd) 659 { 660 struct tc358743_state *state = to_state(sd); 661 struct v4l2_bt_timings *bt = &state->timings.bt; 662 struct tc358743_platform_data *pdata = &state->pdata; 663 u32 bits_pr_pixel = 664 (state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16) ? 16 : 24; 665 u32 bps = bt->width * bt->height * fps(bt) * bits_pr_pixel; 666 u32 bps_pr_lane = (pdata->refclk_hz / pdata->pll_prd) * pdata->pll_fbd; 667 668 return DIV_ROUND_UP(bps, bps_pr_lane); 669 } 670 671 static void tc358743_set_csi(struct v4l2_subdev *sd) 672 { 673 struct tc358743_state *state = to_state(sd); 674 struct tc358743_platform_data *pdata = &state->pdata; 675 unsigned lanes = tc358743_num_csi_lanes_needed(sd); 676 677 v4l2_dbg(3, debug, sd, "%s:\n", __func__); 678 679 state->csi_lanes_in_use = lanes; 680 681 tc358743_reset(sd, MASK_CTXRST); 682 683 if (lanes < 1) 684 i2c_wr32(sd, CLW_CNTRL, MASK_CLW_LANEDISABLE); 685 if (lanes < 1) 686 i2c_wr32(sd, D0W_CNTRL, MASK_D0W_LANEDISABLE); 687 if (lanes < 2) 688 i2c_wr32(sd, D1W_CNTRL, MASK_D1W_LANEDISABLE); 689 if (lanes < 3) 690 i2c_wr32(sd, D2W_CNTRL, MASK_D2W_LANEDISABLE); 691 if (lanes < 4) 692 i2c_wr32(sd, D3W_CNTRL, MASK_D3W_LANEDISABLE); 693 694 i2c_wr32(sd, LINEINITCNT, pdata->lineinitcnt); 695 i2c_wr32(sd, LPTXTIMECNT, pdata->lptxtimecnt); 696 i2c_wr32(sd, TCLK_HEADERCNT, pdata->tclk_headercnt); 697 i2c_wr32(sd, TCLK_TRAILCNT, pdata->tclk_trailcnt); 698 i2c_wr32(sd, THS_HEADERCNT, pdata->ths_headercnt); 699 i2c_wr32(sd, TWAKEUP, pdata->twakeup); 700 i2c_wr32(sd, TCLK_POSTCNT, pdata->tclk_postcnt); 701 i2c_wr32(sd, THS_TRAILCNT, pdata->ths_trailcnt); 702 i2c_wr32(sd, HSTXVREGCNT, pdata->hstxvregcnt); 703 704 i2c_wr32(sd, HSTXVREGEN, 705 ((lanes > 0) ? MASK_CLM_HSTXVREGEN : 0x0) | 706 ((lanes > 0) ? MASK_D0M_HSTXVREGEN : 0x0) | 707 ((lanes > 1) ? MASK_D1M_HSTXVREGEN : 0x0) | 708 ((lanes > 2) ? MASK_D2M_HSTXVREGEN : 0x0) | 709 ((lanes > 3) ? MASK_D3M_HSTXVREGEN : 0x0)); 710 711 i2c_wr32(sd, TXOPTIONCNTRL, (state->bus.flags & 712 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK) ? MASK_CONTCLKMODE : 0); 713 i2c_wr32(sd, STARTCNTRL, MASK_START); 714 i2c_wr32(sd, CSI_START, MASK_STRT); 715 716 i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET | 717 MASK_ADDRESS_CSI_CONTROL | 718 MASK_CSI_MODE | 719 MASK_TXHSMD | 720 ((lanes == 4) ? MASK_NOL_4 : 721 (lanes == 3) ? MASK_NOL_3 : 722 (lanes == 2) ? MASK_NOL_2 : MASK_NOL_1)); 723 724 i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET | 725 MASK_ADDRESS_CSI_ERR_INTENA | MASK_TXBRK | MASK_QUNK | 726 MASK_WCER | MASK_INER); 727 728 i2c_wr32(sd, CSI_CONFW, MASK_MODE_CLEAR | 729 MASK_ADDRESS_CSI_ERR_HALT | MASK_TXBRK | MASK_QUNK); 730 731 i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET | 732 MASK_ADDRESS_CSI_INT_ENA | MASK_INTER); 733 } 734 735 static void tc358743_set_hdmi_phy(struct v4l2_subdev *sd) 736 { 737 struct tc358743_state *state = to_state(sd); 738 struct tc358743_platform_data *pdata = &state->pdata; 739 740 /* Default settings from REF_02, sheet "Source HDMI" 741 * and custom settings as platform data */ 742 i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, 0x0); 743 i2c_wr8(sd, PHY_CTL1, SET_PHY_AUTO_RST1_US(1600) | 744 SET_FREQ_RANGE_MODE_CYCLES(1)); 745 i2c_wr8_and_or(sd, PHY_CTL2, ~MASK_PHY_AUTO_RSTn, 746 (pdata->hdmi_phy_auto_reset_tmds_detected ? 747 MASK_PHY_AUTO_RST2 : 0) | 748 (pdata->hdmi_phy_auto_reset_tmds_in_range ? 749 MASK_PHY_AUTO_RST3 : 0) | 750 (pdata->hdmi_phy_auto_reset_tmds_valid ? 751 MASK_PHY_AUTO_RST4 : 0)); 752 i2c_wr8(sd, PHY_BIAS, 0x40); 753 i2c_wr8(sd, PHY_CSQ, SET_CSQ_CNT_LEVEL(0x0a)); 754 i2c_wr8(sd, AVM_CTL, 45); 755 i2c_wr8_and_or(sd, HDMI_DET, ~MASK_HDMI_DET_V, 756 pdata->hdmi_detection_delay << 4); 757 i2c_wr8_and_or(sd, HV_RST, ~(MASK_H_PI_RST | MASK_V_PI_RST), 758 (pdata->hdmi_phy_auto_reset_hsync_out_of_range ? 759 MASK_H_PI_RST : 0) | 760 (pdata->hdmi_phy_auto_reset_vsync_out_of_range ? 761 MASK_V_PI_RST : 0)); 762 i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, MASK_ENABLE_PHY); 763 } 764 765 static void tc358743_set_hdmi_audio(struct v4l2_subdev *sd) 766 { 767 struct tc358743_state *state = to_state(sd); 768 769 /* Default settings from REF_02, sheet "Source HDMI" */ 770 i2c_wr8(sd, FORCE_MUTE, 0x00); 771 i2c_wr8(sd, AUTO_CMD0, MASK_AUTO_MUTE7 | MASK_AUTO_MUTE6 | 772 MASK_AUTO_MUTE5 | MASK_AUTO_MUTE4 | 773 MASK_AUTO_MUTE1 | MASK_AUTO_MUTE0); 774 i2c_wr8(sd, AUTO_CMD1, MASK_AUTO_MUTE9); 775 i2c_wr8(sd, AUTO_CMD2, MASK_AUTO_PLAY3 | MASK_AUTO_PLAY2); 776 i2c_wr8(sd, BUFINIT_START, SET_BUFINIT_START_MS(500)); 777 i2c_wr8(sd, FS_MUTE, 0x00); 778 i2c_wr8(sd, FS_IMODE, MASK_NLPCM_SMODE | MASK_FS_SMODE); 779 i2c_wr8(sd, ACR_MODE, MASK_CTS_MODE); 780 i2c_wr8(sd, ACR_MDF0, MASK_ACR_L2MDF_1976_PPM | MASK_ACR_L1MDF_976_PPM); 781 i2c_wr8(sd, ACR_MDF1, MASK_ACR_L3MDF_3906_PPM); 782 i2c_wr8(sd, SDO_MODE1, MASK_SDO_FMT_I2S); 783 i2c_wr8(sd, DIV_MODE, SET_DIV_DLY_MS(100)); 784 785 mutex_lock(&state->confctl_mutex); 786 i2c_wr16_and_or(sd, CONFCTL, 0xffff, MASK_AUDCHNUM_2 | 787 MASK_AUDOUTSEL_I2S | MASK_AUTOINDEX); 788 mutex_unlock(&state->confctl_mutex); 789 } 790 791 static void tc358743_set_hdmi_info_frame_mode(struct v4l2_subdev *sd) 792 { 793 /* Default settings from REF_02, sheet "Source HDMI" */ 794 i2c_wr8(sd, PK_INT_MODE, MASK_ISRC2_INT_MODE | MASK_ISRC_INT_MODE | 795 MASK_ACP_INT_MODE | MASK_VS_INT_MODE | 796 MASK_SPD_INT_MODE | MASK_MS_INT_MODE | 797 MASK_AUD_INT_MODE | MASK_AVI_INT_MODE); 798 i2c_wr8(sd, NO_PKT_LIMIT, 0x2c); 799 i2c_wr8(sd, NO_PKT_CLR, 0x53); 800 i2c_wr8(sd, ERR_PK_LIMIT, 0x01); 801 i2c_wr8(sd, NO_PKT_LIMIT2, 0x30); 802 i2c_wr8(sd, NO_GDB_LIMIT, 0x10); 803 } 804 805 static void tc358743_initial_setup(struct v4l2_subdev *sd) 806 { 807 struct tc358743_state *state = to_state(sd); 808 struct tc358743_platform_data *pdata = &state->pdata; 809 810 /* CEC and IR are not supported by this driver */ 811 i2c_wr16_and_or(sd, SYSCTL, ~(MASK_CECRST | MASK_IRRST), 812 (MASK_CECRST | MASK_IRRST)); 813 814 tc358743_reset(sd, MASK_CTXRST | MASK_HDMIRST); 815 tc358743_sleep_mode(sd, false); 816 817 i2c_wr16(sd, FIFOCTL, pdata->fifo_level); 818 819 tc358743_set_ref_clk(sd); 820 821 i2c_wr8_and_or(sd, DDC_CTL, ~MASK_DDC5V_MODE, 822 pdata->ddc5v_delay & MASK_DDC5V_MODE); 823 i2c_wr8_and_or(sd, EDID_MODE, ~MASK_EDID_MODE, MASK_EDID_MODE_E_DDC); 824 825 tc358743_set_hdmi_phy(sd); 826 tc358743_set_hdmi_hdcp(sd, pdata->enable_hdcp); 827 tc358743_set_hdmi_audio(sd); 828 tc358743_set_hdmi_info_frame_mode(sd); 829 830 /* All CE and IT formats are detected as RGB full range in DVI mode */ 831 i2c_wr8_and_or(sd, VI_MODE, ~MASK_RGB_DVI, 0); 832 833 i2c_wr8_and_or(sd, VOUT_SET2, ~MASK_VOUTCOLORMODE, 834 MASK_VOUTCOLORMODE_AUTO); 835 i2c_wr8(sd, VOUT_SET3, MASK_VOUT_EXTCNT); 836 } 837 838 /* --------------- IRQ --------------- */ 839 840 static void tc358743_format_change(struct v4l2_subdev *sd) 841 { 842 struct tc358743_state *state = to_state(sd); 843 struct v4l2_dv_timings timings; 844 const struct v4l2_event tc358743_ev_fmt = { 845 .type = V4L2_EVENT_SOURCE_CHANGE, 846 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION, 847 }; 848 849 if (tc358743_get_detected_timings(sd, &timings)) { 850 enable_stream(sd, false); 851 852 v4l2_dbg(1, debug, sd, "%s: No signal\n", 853 __func__); 854 } else { 855 if (!v4l2_match_dv_timings(&state->timings, &timings, 0, false)) 856 enable_stream(sd, false); 857 858 if (debug) 859 v4l2_print_dv_timings(sd->name, 860 "tc358743_format_change: New format: ", 861 &timings, false); 862 } 863 864 if (sd->devnode) 865 v4l2_subdev_notify_event(sd, &tc358743_ev_fmt); 866 } 867 868 static void tc358743_init_interrupts(struct v4l2_subdev *sd) 869 { 870 u16 i; 871 872 /* clear interrupt status registers */ 873 for (i = SYS_INT; i <= KEY_INT; i++) 874 i2c_wr8(sd, i, 0xff); 875 876 i2c_wr16(sd, INTSTATUS, 0xffff); 877 } 878 879 static void tc358743_enable_interrupts(struct v4l2_subdev *sd, 880 bool cable_connected) 881 { 882 v4l2_dbg(2, debug, sd, "%s: cable connected = %d\n", __func__, 883 cable_connected); 884 885 if (cable_connected) { 886 i2c_wr8(sd, SYS_INTM, ~(MASK_M_DDC | MASK_M_DVI_DET | 887 MASK_M_HDMI_DET) & 0xff); 888 i2c_wr8(sd, CLK_INTM, ~MASK_M_IN_DE_CHG); 889 i2c_wr8(sd, CBIT_INTM, ~(MASK_M_CBIT_FS | MASK_M_AF_LOCK | 890 MASK_M_AF_UNLOCK) & 0xff); 891 i2c_wr8(sd, AUDIO_INTM, ~MASK_M_BUFINIT_END); 892 i2c_wr8(sd, MISC_INTM, ~MASK_M_SYNC_CHG); 893 } else { 894 i2c_wr8(sd, SYS_INTM, ~MASK_M_DDC & 0xff); 895 i2c_wr8(sd, CLK_INTM, 0xff); 896 i2c_wr8(sd, CBIT_INTM, 0xff); 897 i2c_wr8(sd, AUDIO_INTM, 0xff); 898 i2c_wr8(sd, MISC_INTM, 0xff); 899 } 900 } 901 902 static void tc358743_hdmi_audio_int_handler(struct v4l2_subdev *sd, 903 bool *handled) 904 { 905 u8 audio_int_mask = i2c_rd8(sd, AUDIO_INTM); 906 u8 audio_int = i2c_rd8(sd, AUDIO_INT) & ~audio_int_mask; 907 908 i2c_wr8(sd, AUDIO_INT, audio_int); 909 910 v4l2_dbg(3, debug, sd, "%s: AUDIO_INT = 0x%02x\n", __func__, audio_int); 911 912 tc358743_s_ctrl_audio_sampling_rate(sd); 913 tc358743_s_ctrl_audio_present(sd); 914 } 915 916 static void tc358743_csi_err_int_handler(struct v4l2_subdev *sd, bool *handled) 917 { 918 v4l2_err(sd, "%s: CSI_ERR = 0x%x\n", __func__, i2c_rd32(sd, CSI_ERR)); 919 920 i2c_wr32(sd, CSI_INT_CLR, MASK_ICRER); 921 } 922 923 static void tc358743_hdmi_misc_int_handler(struct v4l2_subdev *sd, 924 bool *handled) 925 { 926 u8 misc_int_mask = i2c_rd8(sd, MISC_INTM); 927 u8 misc_int = i2c_rd8(sd, MISC_INT) & ~misc_int_mask; 928 929 i2c_wr8(sd, MISC_INT, misc_int); 930 931 v4l2_dbg(3, debug, sd, "%s: MISC_INT = 0x%02x\n", __func__, misc_int); 932 933 if (misc_int & MASK_I_SYNC_CHG) { 934 /* Reset the HDMI PHY to try to trigger proper lock on the 935 * incoming video format. Erase BKSV to prevent that old keys 936 * are used when a new source is connected. */ 937 if (no_sync(sd) || no_signal(sd)) { 938 tc358743_reset_phy(sd); 939 tc358743_erase_bksv(sd); 940 } 941 942 tc358743_format_change(sd); 943 944 misc_int &= ~MASK_I_SYNC_CHG; 945 if (handled) 946 *handled = true; 947 } 948 949 if (misc_int) { 950 v4l2_err(sd, "%s: Unhandled MISC_INT interrupts: 0x%02x\n", 951 __func__, misc_int); 952 } 953 } 954 955 static void tc358743_hdmi_cbit_int_handler(struct v4l2_subdev *sd, 956 bool *handled) 957 { 958 u8 cbit_int_mask = i2c_rd8(sd, CBIT_INTM); 959 u8 cbit_int = i2c_rd8(sd, CBIT_INT) & ~cbit_int_mask; 960 961 i2c_wr8(sd, CBIT_INT, cbit_int); 962 963 v4l2_dbg(3, debug, sd, "%s: CBIT_INT = 0x%02x\n", __func__, cbit_int); 964 965 if (cbit_int & MASK_I_CBIT_FS) { 966 967 v4l2_dbg(1, debug, sd, "%s: Audio sample rate changed\n", 968 __func__); 969 tc358743_s_ctrl_audio_sampling_rate(sd); 970 971 cbit_int &= ~MASK_I_CBIT_FS; 972 if (handled) 973 *handled = true; 974 } 975 976 if (cbit_int & (MASK_I_AF_LOCK | MASK_I_AF_UNLOCK)) { 977 978 v4l2_dbg(1, debug, sd, "%s: Audio present changed\n", 979 __func__); 980 tc358743_s_ctrl_audio_present(sd); 981 982 cbit_int &= ~(MASK_I_AF_LOCK | MASK_I_AF_UNLOCK); 983 if (handled) 984 *handled = true; 985 } 986 987 if (cbit_int) { 988 v4l2_err(sd, "%s: Unhandled CBIT_INT interrupts: 0x%02x\n", 989 __func__, cbit_int); 990 } 991 } 992 993 static void tc358743_hdmi_clk_int_handler(struct v4l2_subdev *sd, bool *handled) 994 { 995 u8 clk_int_mask = i2c_rd8(sd, CLK_INTM); 996 u8 clk_int = i2c_rd8(sd, CLK_INT) & ~clk_int_mask; 997 998 /* Bit 7 and bit 6 are set even when they are masked */ 999 i2c_wr8(sd, CLK_INT, clk_int | 0x80 | MASK_I_OUT_H_CHG); 1000 1001 v4l2_dbg(3, debug, sd, "%s: CLK_INT = 0x%02x\n", __func__, clk_int); 1002 1003 if (clk_int & (MASK_I_IN_DE_CHG)) { 1004 1005 v4l2_dbg(1, debug, sd, "%s: DE size or position has changed\n", 1006 __func__); 1007 1008 /* If the source switch to a new resolution with the same pixel 1009 * frequency as the existing (e.g. 1080p25 -> 720p50), the 1010 * I_SYNC_CHG interrupt is not always triggered, while the 1011 * I_IN_DE_CHG interrupt seems to work fine. Format change 1012 * notifications are only sent when the signal is stable to 1013 * reduce the number of notifications. */ 1014 if (!no_signal(sd) && !no_sync(sd)) 1015 tc358743_format_change(sd); 1016 1017 clk_int &= ~(MASK_I_IN_DE_CHG); 1018 if (handled) 1019 *handled = true; 1020 } 1021 1022 if (clk_int) { 1023 v4l2_err(sd, "%s: Unhandled CLK_INT interrupts: 0x%02x\n", 1024 __func__, clk_int); 1025 } 1026 } 1027 1028 static void tc358743_hdmi_sys_int_handler(struct v4l2_subdev *sd, bool *handled) 1029 { 1030 struct tc358743_state *state = to_state(sd); 1031 u8 sys_int_mask = i2c_rd8(sd, SYS_INTM); 1032 u8 sys_int = i2c_rd8(sd, SYS_INT) & ~sys_int_mask; 1033 1034 i2c_wr8(sd, SYS_INT, sys_int); 1035 1036 v4l2_dbg(3, debug, sd, "%s: SYS_INT = 0x%02x\n", __func__, sys_int); 1037 1038 if (sys_int & MASK_I_DDC) { 1039 bool tx_5v = tx_5v_power_present(sd); 1040 1041 v4l2_dbg(1, debug, sd, "%s: Tx 5V power present: %s\n", 1042 __func__, tx_5v ? "yes" : "no"); 1043 1044 if (tx_5v) { 1045 tc358743_enable_edid(sd); 1046 } else { 1047 tc358743_enable_interrupts(sd, false); 1048 tc358743_disable_edid(sd); 1049 memset(&state->timings, 0, sizeof(state->timings)); 1050 tc358743_erase_bksv(sd); 1051 tc358743_update_controls(sd); 1052 } 1053 1054 sys_int &= ~MASK_I_DDC; 1055 if (handled) 1056 *handled = true; 1057 } 1058 1059 if (sys_int & MASK_I_DVI) { 1060 v4l2_dbg(1, debug, sd, "%s: HDMI->DVI change detected\n", 1061 __func__); 1062 1063 /* Reset the HDMI PHY to try to trigger proper lock on the 1064 * incoming video format. Erase BKSV to prevent that old keys 1065 * are used when a new source is connected. */ 1066 if (no_sync(sd) || no_signal(sd)) { 1067 tc358743_reset_phy(sd); 1068 tc358743_erase_bksv(sd); 1069 } 1070 1071 sys_int &= ~MASK_I_DVI; 1072 if (handled) 1073 *handled = true; 1074 } 1075 1076 if (sys_int & MASK_I_HDMI) { 1077 v4l2_dbg(1, debug, sd, "%s: DVI->HDMI change detected\n", 1078 __func__); 1079 1080 /* Register is reset in DVI mode (REF_01, c. 6.6.41) */ 1081 i2c_wr8(sd, ANA_CTL, MASK_APPL_PCSX_NORMAL | MASK_ANALOG_ON); 1082 1083 sys_int &= ~MASK_I_HDMI; 1084 if (handled) 1085 *handled = true; 1086 } 1087 1088 if (sys_int) { 1089 v4l2_err(sd, "%s: Unhandled SYS_INT interrupts: 0x%02x\n", 1090 __func__, sys_int); 1091 } 1092 } 1093 1094 /* --------------- CORE OPS --------------- */ 1095 1096 static int tc358743_log_status(struct v4l2_subdev *sd) 1097 { 1098 struct tc358743_state *state = to_state(sd); 1099 struct v4l2_dv_timings timings; 1100 uint8_t hdmi_sys_status = i2c_rd8(sd, SYS_STATUS); 1101 uint16_t sysctl = i2c_rd16(sd, SYSCTL); 1102 u8 vi_status3 = i2c_rd8(sd, VI_STATUS3); 1103 const int deep_color_mode[4] = { 8, 10, 12, 16 }; 1104 static const char * const input_color_space[] = { 1105 "RGB", "YCbCr 601", "Adobe RGB", "YCbCr 709", "NA (4)", 1106 "xvYCC 601", "NA(6)", "xvYCC 709", "NA(8)", "sYCC601", 1107 "NA(10)", "NA(11)", "NA(12)", "Adobe YCC 601"}; 1108 1109 v4l2_info(sd, "-----Chip status-----\n"); 1110 v4l2_info(sd, "Chip ID: 0x%02x\n", 1111 (i2c_rd16(sd, CHIPID) & MASK_CHIPID) >> 8); 1112 v4l2_info(sd, "Chip revision: 0x%02x\n", 1113 i2c_rd16(sd, CHIPID) & MASK_REVID); 1114 v4l2_info(sd, "Reset: IR: %d, CEC: %d, CSI TX: %d, HDMI: %d\n", 1115 !!(sysctl & MASK_IRRST), 1116 !!(sysctl & MASK_CECRST), 1117 !!(sysctl & MASK_CTXRST), 1118 !!(sysctl & MASK_HDMIRST)); 1119 v4l2_info(sd, "Sleep mode: %s\n", sysctl & MASK_SLEEP ? "on" : "off"); 1120 v4l2_info(sd, "Cable detected (+5V power): %s\n", 1121 hdmi_sys_status & MASK_S_DDC5V ? "yes" : "no"); 1122 v4l2_info(sd, "DDC lines enabled: %s\n", 1123 (i2c_rd8(sd, EDID_MODE) & MASK_EDID_MODE_E_DDC) ? 1124 "yes" : "no"); 1125 v4l2_info(sd, "Hotplug enabled: %s\n", 1126 (i2c_rd8(sd, HPD_CTL) & MASK_HPD_OUT0) ? 1127 "yes" : "no"); 1128 v4l2_info(sd, "CEC enabled: %s\n", 1129 (i2c_rd16(sd, CECEN) & MASK_CECEN) ? "yes" : "no"); 1130 v4l2_info(sd, "-----Signal status-----\n"); 1131 v4l2_info(sd, "TMDS signal detected: %s\n", 1132 hdmi_sys_status & MASK_S_TMDS ? "yes" : "no"); 1133 v4l2_info(sd, "Stable sync signal: %s\n", 1134 hdmi_sys_status & MASK_S_SYNC ? "yes" : "no"); 1135 v4l2_info(sd, "PHY PLL locked: %s\n", 1136 hdmi_sys_status & MASK_S_PHY_PLL ? "yes" : "no"); 1137 v4l2_info(sd, "PHY DE detected: %s\n", 1138 hdmi_sys_status & MASK_S_PHY_SCDT ? "yes" : "no"); 1139 1140 if (tc358743_get_detected_timings(sd, &timings)) { 1141 v4l2_info(sd, "No video detected\n"); 1142 } else { 1143 v4l2_print_dv_timings(sd->name, "Detected format: ", &timings, 1144 true); 1145 } 1146 v4l2_print_dv_timings(sd->name, "Configured format: ", &state->timings, 1147 true); 1148 1149 v4l2_info(sd, "-----CSI-TX status-----\n"); 1150 v4l2_info(sd, "Lanes needed: %d\n", 1151 tc358743_num_csi_lanes_needed(sd)); 1152 v4l2_info(sd, "Lanes in use: %d\n", 1153 state->csi_lanes_in_use); 1154 v4l2_info(sd, "Waiting for particular sync signal: %s\n", 1155 (i2c_rd16(sd, CSI_STATUS) & MASK_S_WSYNC) ? 1156 "yes" : "no"); 1157 v4l2_info(sd, "Transmit mode: %s\n", 1158 (i2c_rd16(sd, CSI_STATUS) & MASK_S_TXACT) ? 1159 "yes" : "no"); 1160 v4l2_info(sd, "Receive mode: %s\n", 1161 (i2c_rd16(sd, CSI_STATUS) & MASK_S_RXACT) ? 1162 "yes" : "no"); 1163 v4l2_info(sd, "Stopped: %s\n", 1164 (i2c_rd16(sd, CSI_STATUS) & MASK_S_HLT) ? 1165 "yes" : "no"); 1166 v4l2_info(sd, "Color space: %s\n", 1167 state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16 ? 1168 "YCbCr 422 16-bit" : 1169 state->mbus_fmt_code == MEDIA_BUS_FMT_RGB888_1X24 ? 1170 "RGB 888 24-bit" : "Unsupported"); 1171 1172 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D"); 1173 v4l2_info(sd, "HDCP encrypted content: %s\n", 1174 hdmi_sys_status & MASK_S_HDCP ? "yes" : "no"); 1175 v4l2_info(sd, "Input color space: %s %s range\n", 1176 input_color_space[(vi_status3 & MASK_S_V_COLOR) >> 1], 1177 (vi_status3 & MASK_LIMITED) ? "limited" : "full"); 1178 if (!is_hdmi(sd)) 1179 return 0; 1180 v4l2_info(sd, "AV Mute: %s\n", hdmi_sys_status & MASK_S_AVMUTE ? "on" : 1181 "off"); 1182 v4l2_info(sd, "Deep color mode: %d-bits per channel\n", 1183 deep_color_mode[(i2c_rd8(sd, VI_STATUS1) & 1184 MASK_S_DEEPCOLOR) >> 2]); 1185 print_avi_infoframe(sd); 1186 1187 return 0; 1188 } 1189 1190 #ifdef CONFIG_VIDEO_ADV_DEBUG 1191 static void tc358743_print_register_map(struct v4l2_subdev *sd) 1192 { 1193 v4l2_info(sd, "0x0000-0x00FF: Global Control Register\n"); 1194 v4l2_info(sd, "0x0100-0x01FF: CSI2-TX PHY Register\n"); 1195 v4l2_info(sd, "0x0200-0x03FF: CSI2-TX PPI Register\n"); 1196 v4l2_info(sd, "0x0400-0x05FF: Reserved\n"); 1197 v4l2_info(sd, "0x0600-0x06FF: CEC Register\n"); 1198 v4l2_info(sd, "0x0700-0x84FF: Reserved\n"); 1199 v4l2_info(sd, "0x8500-0x85FF: HDMIRX System Control Register\n"); 1200 v4l2_info(sd, "0x8600-0x86FF: HDMIRX Audio Control Register\n"); 1201 v4l2_info(sd, "0x8700-0x87FF: HDMIRX InfoFrame packet data Register\n"); 1202 v4l2_info(sd, "0x8800-0x88FF: HDMIRX HDCP Port Register\n"); 1203 v4l2_info(sd, "0x8900-0x89FF: HDMIRX Video Output Port & 3D Register\n"); 1204 v4l2_info(sd, "0x8A00-0x8BFF: Reserved\n"); 1205 v4l2_info(sd, "0x8C00-0x8FFF: HDMIRX EDID-RAM (1024bytes)\n"); 1206 v4l2_info(sd, "0x9000-0x90FF: HDMIRX GBD Extraction Control\n"); 1207 v4l2_info(sd, "0x9100-0x92FF: HDMIRX GBD RAM read\n"); 1208 v4l2_info(sd, "0x9300- : Reserved\n"); 1209 } 1210 1211 static int tc358743_get_reg_size(u16 address) 1212 { 1213 /* REF_01 p. 66-72 */ 1214 if (address <= 0x00ff) 1215 return 2; 1216 else if ((address >= 0x0100) && (address <= 0x06FF)) 1217 return 4; 1218 else if ((address >= 0x0700) && (address <= 0x84ff)) 1219 return 2; 1220 else 1221 return 1; 1222 } 1223 1224 static int tc358743_g_register(struct v4l2_subdev *sd, 1225 struct v4l2_dbg_register *reg) 1226 { 1227 if (reg->reg > 0xffff) { 1228 tc358743_print_register_map(sd); 1229 return -EINVAL; 1230 } 1231 1232 reg->size = tc358743_get_reg_size(reg->reg); 1233 1234 reg->val = i2c_rdreg(sd, reg->reg, reg->size); 1235 1236 return 0; 1237 } 1238 1239 static int tc358743_s_register(struct v4l2_subdev *sd, 1240 const struct v4l2_dbg_register *reg) 1241 { 1242 if (reg->reg > 0xffff) { 1243 tc358743_print_register_map(sd); 1244 return -EINVAL; 1245 } 1246 1247 /* It should not be possible for the user to enable HDCP with a simple 1248 * v4l2-dbg command. 1249 * 1250 * DO NOT REMOVE THIS unless all other issues with HDCP have been 1251 * resolved. 1252 */ 1253 if (reg->reg == HDCP_MODE || 1254 reg->reg == HDCP_REG1 || 1255 reg->reg == HDCP_REG2 || 1256 reg->reg == HDCP_REG3 || 1257 reg->reg == BCAPS) 1258 return 0; 1259 1260 i2c_wrreg(sd, (u16)reg->reg, reg->val, 1261 tc358743_get_reg_size(reg->reg)); 1262 1263 return 0; 1264 } 1265 #endif 1266 1267 static int tc358743_isr(struct v4l2_subdev *sd, u32 status, bool *handled) 1268 { 1269 u16 intstatus = i2c_rd16(sd, INTSTATUS); 1270 1271 v4l2_dbg(1, debug, sd, "%s: IntStatus = 0x%04x\n", __func__, intstatus); 1272 1273 if (intstatus & MASK_HDMI_INT) { 1274 u8 hdmi_int0 = i2c_rd8(sd, HDMI_INT0); 1275 u8 hdmi_int1 = i2c_rd8(sd, HDMI_INT1); 1276 1277 if (hdmi_int0 & MASK_I_MISC) 1278 tc358743_hdmi_misc_int_handler(sd, handled); 1279 if (hdmi_int1 & MASK_I_CBIT) 1280 tc358743_hdmi_cbit_int_handler(sd, handled); 1281 if (hdmi_int1 & MASK_I_CLK) 1282 tc358743_hdmi_clk_int_handler(sd, handled); 1283 if (hdmi_int1 & MASK_I_SYS) 1284 tc358743_hdmi_sys_int_handler(sd, handled); 1285 if (hdmi_int1 & MASK_I_AUD) 1286 tc358743_hdmi_audio_int_handler(sd, handled); 1287 1288 i2c_wr16(sd, INTSTATUS, MASK_HDMI_INT); 1289 intstatus &= ~MASK_HDMI_INT; 1290 } 1291 1292 if (intstatus & MASK_CSI_INT) { 1293 u32 csi_int = i2c_rd32(sd, CSI_INT); 1294 1295 if (csi_int & MASK_INTER) 1296 tc358743_csi_err_int_handler(sd, handled); 1297 1298 i2c_wr16(sd, INTSTATUS, MASK_CSI_INT); 1299 intstatus &= ~MASK_CSI_INT; 1300 } 1301 1302 intstatus = i2c_rd16(sd, INTSTATUS); 1303 if (intstatus) { 1304 v4l2_dbg(1, debug, sd, 1305 "%s: Unhandled IntStatus interrupts: 0x%02x\n", 1306 __func__, intstatus); 1307 } 1308 1309 return 0; 1310 } 1311 1312 static irqreturn_t tc358743_irq_handler(int irq, void *dev_id) 1313 { 1314 struct tc358743_state *state = dev_id; 1315 bool handled; 1316 1317 tc358743_isr(&state->sd, 0, &handled); 1318 1319 return handled ? IRQ_HANDLED : IRQ_NONE; 1320 } 1321 1322 static int tc358743_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh, 1323 struct v4l2_event_subscription *sub) 1324 { 1325 switch (sub->type) { 1326 case V4L2_EVENT_SOURCE_CHANGE: 1327 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub); 1328 case V4L2_EVENT_CTRL: 1329 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub); 1330 default: 1331 return -EINVAL; 1332 } 1333 } 1334 1335 /* --------------- VIDEO OPS --------------- */ 1336 1337 static int tc358743_g_input_status(struct v4l2_subdev *sd, u32 *status) 1338 { 1339 *status = 0; 1340 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0; 1341 *status |= no_sync(sd) ? V4L2_IN_ST_NO_SYNC : 0; 1342 1343 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status); 1344 1345 return 0; 1346 } 1347 1348 static int tc358743_s_dv_timings(struct v4l2_subdev *sd, 1349 struct v4l2_dv_timings *timings) 1350 { 1351 struct tc358743_state *state = to_state(sd); 1352 1353 if (!timings) 1354 return -EINVAL; 1355 1356 if (debug) 1357 v4l2_print_dv_timings(sd->name, "tc358743_s_dv_timings: ", 1358 timings, false); 1359 1360 if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) { 1361 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__); 1362 return 0; 1363 } 1364 1365 if (!v4l2_valid_dv_timings(timings, 1366 &tc358743_timings_cap, NULL, NULL)) { 1367 v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__); 1368 return -ERANGE; 1369 } 1370 1371 state->timings = *timings; 1372 1373 enable_stream(sd, false); 1374 tc358743_set_pll(sd); 1375 tc358743_set_csi(sd); 1376 1377 return 0; 1378 } 1379 1380 static int tc358743_g_dv_timings(struct v4l2_subdev *sd, 1381 struct v4l2_dv_timings *timings) 1382 { 1383 struct tc358743_state *state = to_state(sd); 1384 1385 *timings = state->timings; 1386 1387 return 0; 1388 } 1389 1390 static int tc358743_enum_dv_timings(struct v4l2_subdev *sd, 1391 struct v4l2_enum_dv_timings *timings) 1392 { 1393 if (timings->pad != 0) 1394 return -EINVAL; 1395 1396 return v4l2_enum_dv_timings_cap(timings, 1397 &tc358743_timings_cap, NULL, NULL); 1398 } 1399 1400 static int tc358743_query_dv_timings(struct v4l2_subdev *sd, 1401 struct v4l2_dv_timings *timings) 1402 { 1403 int ret; 1404 1405 ret = tc358743_get_detected_timings(sd, timings); 1406 if (ret) 1407 return ret; 1408 1409 if (debug) 1410 v4l2_print_dv_timings(sd->name, "tc358743_query_dv_timings: ", 1411 timings, false); 1412 1413 if (!v4l2_valid_dv_timings(timings, 1414 &tc358743_timings_cap, NULL, NULL)) { 1415 v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__); 1416 return -ERANGE; 1417 } 1418 1419 return 0; 1420 } 1421 1422 static int tc358743_dv_timings_cap(struct v4l2_subdev *sd, 1423 struct v4l2_dv_timings_cap *cap) 1424 { 1425 if (cap->pad != 0) 1426 return -EINVAL; 1427 1428 *cap = tc358743_timings_cap; 1429 1430 return 0; 1431 } 1432 1433 static int tc358743_g_mbus_config(struct v4l2_subdev *sd, 1434 struct v4l2_mbus_config *cfg) 1435 { 1436 struct tc358743_state *state = to_state(sd); 1437 1438 cfg->type = V4L2_MBUS_CSI2; 1439 1440 /* Support for non-continuous CSI-2 clock is missing in the driver */ 1441 cfg->flags = V4L2_MBUS_CSI2_CONTINUOUS_CLOCK; 1442 1443 switch (state->csi_lanes_in_use) { 1444 case 1: 1445 cfg->flags |= V4L2_MBUS_CSI2_1_LANE; 1446 break; 1447 case 2: 1448 cfg->flags |= V4L2_MBUS_CSI2_2_LANE; 1449 break; 1450 case 3: 1451 cfg->flags |= V4L2_MBUS_CSI2_3_LANE; 1452 break; 1453 case 4: 1454 cfg->flags |= V4L2_MBUS_CSI2_4_LANE; 1455 break; 1456 default: 1457 return -EINVAL; 1458 } 1459 1460 return 0; 1461 } 1462 1463 static int tc358743_s_stream(struct v4l2_subdev *sd, int enable) 1464 { 1465 enable_stream(sd, enable); 1466 if (!enable) { 1467 /* Put all lanes in PL-11 state (STOPSTATE) */ 1468 tc358743_set_csi(sd); 1469 } 1470 1471 return 0; 1472 } 1473 1474 /* --------------- PAD OPS --------------- */ 1475 1476 static int tc358743_get_fmt(struct v4l2_subdev *sd, 1477 struct v4l2_subdev_pad_config *cfg, 1478 struct v4l2_subdev_format *format) 1479 { 1480 struct tc358743_state *state = to_state(sd); 1481 u8 vi_rep = i2c_rd8(sd, VI_REP); 1482 1483 if (format->pad != 0) 1484 return -EINVAL; 1485 1486 format->format.code = state->mbus_fmt_code; 1487 format->format.width = state->timings.bt.width; 1488 format->format.height = state->timings.bt.height; 1489 format->format.field = V4L2_FIELD_NONE; 1490 1491 switch (vi_rep & MASK_VOUT_COLOR_SEL) { 1492 case MASK_VOUT_COLOR_RGB_FULL: 1493 case MASK_VOUT_COLOR_RGB_LIMITED: 1494 format->format.colorspace = V4L2_COLORSPACE_SRGB; 1495 break; 1496 case MASK_VOUT_COLOR_601_YCBCR_LIMITED: 1497 case MASK_VOUT_COLOR_601_YCBCR_FULL: 1498 format->format.colorspace = V4L2_COLORSPACE_SMPTE170M; 1499 break; 1500 case MASK_VOUT_COLOR_709_YCBCR_FULL: 1501 case MASK_VOUT_COLOR_709_YCBCR_LIMITED: 1502 format->format.colorspace = V4L2_COLORSPACE_REC709; 1503 break; 1504 default: 1505 format->format.colorspace = 0; 1506 break; 1507 } 1508 1509 return 0; 1510 } 1511 1512 static int tc358743_set_fmt(struct v4l2_subdev *sd, 1513 struct v4l2_subdev_pad_config *cfg, 1514 struct v4l2_subdev_format *format) 1515 { 1516 struct tc358743_state *state = to_state(sd); 1517 1518 u32 code = format->format.code; /* is overwritten by get_fmt */ 1519 int ret = tc358743_get_fmt(sd, cfg, format); 1520 1521 format->format.code = code; 1522 1523 if (ret) 1524 return ret; 1525 1526 switch (code) { 1527 case MEDIA_BUS_FMT_RGB888_1X24: 1528 case MEDIA_BUS_FMT_UYVY8_1X16: 1529 break; 1530 default: 1531 return -EINVAL; 1532 } 1533 1534 if (format->which == V4L2_SUBDEV_FORMAT_TRY) 1535 return 0; 1536 1537 state->mbus_fmt_code = format->format.code; 1538 1539 enable_stream(sd, false); 1540 tc358743_set_pll(sd); 1541 tc358743_set_csi(sd); 1542 tc358743_set_csi_color_space(sd); 1543 1544 return 0; 1545 } 1546 1547 static int tc358743_g_edid(struct v4l2_subdev *sd, 1548 struct v4l2_subdev_edid *edid) 1549 { 1550 struct tc358743_state *state = to_state(sd); 1551 1552 memset(edid->reserved, 0, sizeof(edid->reserved)); 1553 1554 if (edid->pad != 0) 1555 return -EINVAL; 1556 1557 if (edid->start_block == 0 && edid->blocks == 0) { 1558 edid->blocks = state->edid_blocks_written; 1559 return 0; 1560 } 1561 1562 if (state->edid_blocks_written == 0) 1563 return -ENODATA; 1564 1565 if (edid->start_block >= state->edid_blocks_written || 1566 edid->blocks == 0) 1567 return -EINVAL; 1568 1569 if (edid->start_block + edid->blocks > state->edid_blocks_written) 1570 edid->blocks = state->edid_blocks_written - edid->start_block; 1571 1572 i2c_rd(sd, EDID_RAM + (edid->start_block * EDID_BLOCK_SIZE), edid->edid, 1573 edid->blocks * EDID_BLOCK_SIZE); 1574 1575 return 0; 1576 } 1577 1578 static int tc358743_s_edid(struct v4l2_subdev *sd, 1579 struct v4l2_subdev_edid *edid) 1580 { 1581 struct tc358743_state *state = to_state(sd); 1582 u16 edid_len = edid->blocks * EDID_BLOCK_SIZE; 1583 int i; 1584 1585 v4l2_dbg(2, debug, sd, "%s, pad %d, start block %d, blocks %d\n", 1586 __func__, edid->pad, edid->start_block, edid->blocks); 1587 1588 memset(edid->reserved, 0, sizeof(edid->reserved)); 1589 1590 if (edid->pad != 0) 1591 return -EINVAL; 1592 1593 if (edid->start_block != 0) 1594 return -EINVAL; 1595 1596 if (edid->blocks > EDID_NUM_BLOCKS_MAX) { 1597 edid->blocks = EDID_NUM_BLOCKS_MAX; 1598 return -E2BIG; 1599 } 1600 1601 tc358743_disable_edid(sd); 1602 1603 i2c_wr8(sd, EDID_LEN1, edid_len & 0xff); 1604 i2c_wr8(sd, EDID_LEN2, edid_len >> 8); 1605 1606 if (edid->blocks == 0) { 1607 state->edid_blocks_written = 0; 1608 return 0; 1609 } 1610 1611 for (i = 0; i < edid_len; i += EDID_BLOCK_SIZE) 1612 i2c_wr(sd, EDID_RAM + i, edid->edid + i, EDID_BLOCK_SIZE); 1613 1614 state->edid_blocks_written = edid->blocks; 1615 1616 if (tx_5v_power_present(sd)) 1617 tc358743_enable_edid(sd); 1618 1619 return 0; 1620 } 1621 1622 /* -------------------------------------------------------------------------- */ 1623 1624 static const struct v4l2_subdev_core_ops tc358743_core_ops = { 1625 .log_status = tc358743_log_status, 1626 #ifdef CONFIG_VIDEO_ADV_DEBUG 1627 .g_register = tc358743_g_register, 1628 .s_register = tc358743_s_register, 1629 #endif 1630 .interrupt_service_routine = tc358743_isr, 1631 .subscribe_event = tc358743_subscribe_event, 1632 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 1633 }; 1634 1635 static const struct v4l2_subdev_video_ops tc358743_video_ops = { 1636 .g_input_status = tc358743_g_input_status, 1637 .s_dv_timings = tc358743_s_dv_timings, 1638 .g_dv_timings = tc358743_g_dv_timings, 1639 .query_dv_timings = tc358743_query_dv_timings, 1640 .g_mbus_config = tc358743_g_mbus_config, 1641 .s_stream = tc358743_s_stream, 1642 }; 1643 1644 static const struct v4l2_subdev_pad_ops tc358743_pad_ops = { 1645 .set_fmt = tc358743_set_fmt, 1646 .get_fmt = tc358743_get_fmt, 1647 .get_edid = tc358743_g_edid, 1648 .set_edid = tc358743_s_edid, 1649 .enum_dv_timings = tc358743_enum_dv_timings, 1650 .dv_timings_cap = tc358743_dv_timings_cap, 1651 }; 1652 1653 static const struct v4l2_subdev_ops tc358743_ops = { 1654 .core = &tc358743_core_ops, 1655 .video = &tc358743_video_ops, 1656 .pad = &tc358743_pad_ops, 1657 }; 1658 1659 /* --------------- CUSTOM CTRLS --------------- */ 1660 1661 static const struct v4l2_ctrl_config tc358743_ctrl_audio_sampling_rate = { 1662 .id = TC358743_CID_AUDIO_SAMPLING_RATE, 1663 .name = "Audio sampling rate", 1664 .type = V4L2_CTRL_TYPE_INTEGER, 1665 .min = 0, 1666 .max = 768000, 1667 .step = 1, 1668 .def = 0, 1669 .flags = V4L2_CTRL_FLAG_READ_ONLY, 1670 }; 1671 1672 static const struct v4l2_ctrl_config tc358743_ctrl_audio_present = { 1673 .id = TC358743_CID_AUDIO_PRESENT, 1674 .name = "Audio present", 1675 .type = V4L2_CTRL_TYPE_BOOLEAN, 1676 .min = 0, 1677 .max = 1, 1678 .step = 1, 1679 .def = 0, 1680 .flags = V4L2_CTRL_FLAG_READ_ONLY, 1681 }; 1682 1683 /* --------------- PROBE / REMOVE --------------- */ 1684 1685 #ifdef CONFIG_OF 1686 static void tc358743_gpio_reset(struct tc358743_state *state) 1687 { 1688 usleep_range(5000, 10000); 1689 gpiod_set_value(state->reset_gpio, 1); 1690 usleep_range(1000, 2000); 1691 gpiod_set_value(state->reset_gpio, 0); 1692 msleep(20); 1693 } 1694 1695 static int tc358743_probe_of(struct tc358743_state *state) 1696 { 1697 struct device *dev = &state->i2c_client->dev; 1698 struct v4l2_of_endpoint *endpoint; 1699 struct device_node *ep; 1700 struct clk *refclk; 1701 u32 bps_pr_lane; 1702 int ret = -EINVAL; 1703 1704 refclk = devm_clk_get(dev, "refclk"); 1705 if (IS_ERR(refclk)) { 1706 if (PTR_ERR(refclk) != -EPROBE_DEFER) 1707 dev_err(dev, "failed to get refclk: %ld\n", 1708 PTR_ERR(refclk)); 1709 return PTR_ERR(refclk); 1710 } 1711 1712 ep = of_graph_get_next_endpoint(dev->of_node, NULL); 1713 if (!ep) { 1714 dev_err(dev, "missing endpoint node\n"); 1715 return -EINVAL; 1716 } 1717 1718 endpoint = v4l2_of_alloc_parse_endpoint(ep); 1719 if (IS_ERR(endpoint)) { 1720 dev_err(dev, "failed to parse endpoint\n"); 1721 return PTR_ERR(endpoint); 1722 } 1723 1724 if (endpoint->bus_type != V4L2_MBUS_CSI2 || 1725 endpoint->bus.mipi_csi2.num_data_lanes == 0 || 1726 endpoint->nr_of_link_frequencies == 0) { 1727 dev_err(dev, "missing CSI-2 properties in endpoint\n"); 1728 goto free_endpoint; 1729 } 1730 1731 state->bus = endpoint->bus.mipi_csi2; 1732 1733 clk_prepare_enable(refclk); 1734 1735 state->pdata.refclk_hz = clk_get_rate(refclk); 1736 state->pdata.ddc5v_delay = DDC5V_DELAY_100_MS; 1737 state->pdata.enable_hdcp = false; 1738 /* A FIFO level of 16 should be enough for 2-lane 720p60 at 594 MHz. */ 1739 state->pdata.fifo_level = 16; 1740 /* 1741 * The PLL input clock is obtained by dividing refclk by pll_prd. 1742 * It must be between 6 MHz and 40 MHz, lower frequency is better. 1743 */ 1744 switch (state->pdata.refclk_hz) { 1745 case 26000000: 1746 case 27000000: 1747 case 42000000: 1748 state->pdata.pll_prd = state->pdata.refclk_hz / 6000000; 1749 break; 1750 default: 1751 dev_err(dev, "unsupported refclk rate: %u Hz\n", 1752 state->pdata.refclk_hz); 1753 goto disable_clk; 1754 } 1755 1756 /* 1757 * The CSI bps per lane must be between 62.5 Mbps and 1 Gbps. 1758 * The default is 594 Mbps for 4-lane 1080p60 or 2-lane 720p60. 1759 */ 1760 bps_pr_lane = 2 * endpoint->link_frequencies[0]; 1761 if (bps_pr_lane < 62500000U || bps_pr_lane > 1000000000U) { 1762 dev_err(dev, "unsupported bps per lane: %u bps\n", bps_pr_lane); 1763 goto disable_clk; 1764 } 1765 1766 /* The CSI speed per lane is refclk / pll_prd * pll_fbd */ 1767 state->pdata.pll_fbd = bps_pr_lane / 1768 state->pdata.refclk_hz * state->pdata.pll_prd; 1769 1770 /* 1771 * FIXME: These timings are from REF_02 for 594 Mbps per lane (297 MHz 1772 * link frequency). In principle it should be possible to calculate 1773 * them based on link frequency and resolution. 1774 */ 1775 if (bps_pr_lane != 594000000U) 1776 dev_warn(dev, "untested bps per lane: %u bps\n", bps_pr_lane); 1777 state->pdata.lineinitcnt = 0xe80; 1778 state->pdata.lptxtimecnt = 0x003; 1779 /* tclk-preparecnt: 3, tclk-zerocnt: 20 */ 1780 state->pdata.tclk_headercnt = 0x1403; 1781 state->pdata.tclk_trailcnt = 0x00; 1782 /* ths-preparecnt: 3, ths-zerocnt: 1 */ 1783 state->pdata.ths_headercnt = 0x0103; 1784 state->pdata.twakeup = 0x4882; 1785 state->pdata.tclk_postcnt = 0x008; 1786 state->pdata.ths_trailcnt = 0x2; 1787 state->pdata.hstxvregcnt = 0; 1788 1789 state->reset_gpio = devm_gpiod_get_optional(dev, "reset", 1790 GPIOD_OUT_LOW); 1791 if (IS_ERR(state->reset_gpio)) { 1792 dev_err(dev, "failed to get reset gpio\n"); 1793 ret = PTR_ERR(state->reset_gpio); 1794 goto disable_clk; 1795 } 1796 1797 if (state->reset_gpio) 1798 tc358743_gpio_reset(state); 1799 1800 ret = 0; 1801 goto free_endpoint; 1802 1803 disable_clk: 1804 clk_disable_unprepare(refclk); 1805 free_endpoint: 1806 v4l2_of_free_endpoint(endpoint); 1807 return ret; 1808 } 1809 #else 1810 static inline int tc358743_probe_of(struct tc358743_state *state) 1811 { 1812 return -ENODEV; 1813 } 1814 #endif 1815 1816 static int tc358743_probe(struct i2c_client *client, 1817 const struct i2c_device_id *id) 1818 { 1819 static struct v4l2_dv_timings default_timing = 1820 V4L2_DV_BT_CEA_640X480P59_94; 1821 struct tc358743_state *state; 1822 struct tc358743_platform_data *pdata = client->dev.platform_data; 1823 struct v4l2_subdev *sd; 1824 int err; 1825 1826 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 1827 return -EIO; 1828 v4l_dbg(1, debug, client, "chip found @ 0x%x (%s)\n", 1829 client->addr << 1, client->adapter->name); 1830 1831 state = devm_kzalloc(&client->dev, sizeof(struct tc358743_state), 1832 GFP_KERNEL); 1833 if (!state) 1834 return -ENOMEM; 1835 1836 state->i2c_client = client; 1837 1838 /* platform data */ 1839 if (pdata) { 1840 state->pdata = *pdata; 1841 state->bus.flags = V4L2_MBUS_CSI2_CONTINUOUS_CLOCK; 1842 } else { 1843 err = tc358743_probe_of(state); 1844 if (err == -ENODEV) 1845 v4l_err(client, "No platform data!\n"); 1846 if (err) 1847 return err; 1848 } 1849 1850 sd = &state->sd; 1851 v4l2_i2c_subdev_init(sd, client, &tc358743_ops); 1852 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; 1853 1854 /* i2c access */ 1855 if ((i2c_rd16(sd, CHIPID) & MASK_CHIPID) != 0) { 1856 v4l2_info(sd, "not a TC358743 on address 0x%x\n", 1857 client->addr << 1); 1858 return -ENODEV; 1859 } 1860 1861 /* control handlers */ 1862 v4l2_ctrl_handler_init(&state->hdl, 3); 1863 1864 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(&state->hdl, NULL, 1865 V4L2_CID_DV_RX_POWER_PRESENT, 0, 1, 0, 0); 1866 1867 /* custom controls */ 1868 state->audio_sampling_rate_ctrl = v4l2_ctrl_new_custom(&state->hdl, 1869 &tc358743_ctrl_audio_sampling_rate, NULL); 1870 1871 state->audio_present_ctrl = v4l2_ctrl_new_custom(&state->hdl, 1872 &tc358743_ctrl_audio_present, NULL); 1873 1874 sd->ctrl_handler = &state->hdl; 1875 if (state->hdl.error) { 1876 err = state->hdl.error; 1877 goto err_hdl; 1878 } 1879 1880 if (tc358743_update_controls(sd)) { 1881 err = -ENODEV; 1882 goto err_hdl; 1883 } 1884 1885 state->pad.flags = MEDIA_PAD_FL_SOURCE; 1886 err = media_entity_pads_init(&sd->entity, 1, &state->pad); 1887 if (err < 0) 1888 goto err_hdl; 1889 1890 sd->dev = &client->dev; 1891 err = v4l2_async_register_subdev(sd); 1892 if (err < 0) 1893 goto err_hdl; 1894 1895 mutex_init(&state->confctl_mutex); 1896 1897 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug, 1898 tc358743_delayed_work_enable_hotplug); 1899 1900 tc358743_initial_setup(sd); 1901 1902 tc358743_s_dv_timings(sd, &default_timing); 1903 1904 state->mbus_fmt_code = MEDIA_BUS_FMT_RGB888_1X24; 1905 tc358743_set_csi_color_space(sd); 1906 1907 tc358743_init_interrupts(sd); 1908 1909 if (state->i2c_client->irq) { 1910 err = devm_request_threaded_irq(&client->dev, 1911 state->i2c_client->irq, 1912 NULL, tc358743_irq_handler, 1913 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 1914 "tc358743", state); 1915 if (err) 1916 goto err_work_queues; 1917 } 1918 1919 tc358743_enable_interrupts(sd, tx_5v_power_present(sd)); 1920 i2c_wr16(sd, INTMASK, ~(MASK_HDMI_MSK | MASK_CSI_MSK) & 0xffff); 1921 1922 err = v4l2_ctrl_handler_setup(sd->ctrl_handler); 1923 if (err) 1924 goto err_work_queues; 1925 1926 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name, 1927 client->addr << 1, client->adapter->name); 1928 1929 return 0; 1930 1931 err_work_queues: 1932 cancel_delayed_work(&state->delayed_work_enable_hotplug); 1933 mutex_destroy(&state->confctl_mutex); 1934 err_hdl: 1935 media_entity_cleanup(&sd->entity); 1936 v4l2_ctrl_handler_free(&state->hdl); 1937 return err; 1938 } 1939 1940 static int tc358743_remove(struct i2c_client *client) 1941 { 1942 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1943 struct tc358743_state *state = to_state(sd); 1944 1945 cancel_delayed_work(&state->delayed_work_enable_hotplug); 1946 v4l2_async_unregister_subdev(sd); 1947 v4l2_device_unregister_subdev(sd); 1948 mutex_destroy(&state->confctl_mutex); 1949 media_entity_cleanup(&sd->entity); 1950 v4l2_ctrl_handler_free(&state->hdl); 1951 1952 return 0; 1953 } 1954 1955 static struct i2c_device_id tc358743_id[] = { 1956 {"tc358743", 0}, 1957 {} 1958 }; 1959 1960 MODULE_DEVICE_TABLE(i2c, tc358743_id); 1961 1962 #if IS_ENABLED(CONFIG_OF) 1963 static const struct of_device_id tc358743_of_match[] = { 1964 { .compatible = "toshiba,tc358743" }, 1965 {}, 1966 }; 1967 MODULE_DEVICE_TABLE(of, tc358743_of_match); 1968 #endif 1969 1970 static struct i2c_driver tc358743_driver = { 1971 .driver = { 1972 .name = "tc358743", 1973 .of_match_table = of_match_ptr(tc358743_of_match), 1974 }, 1975 .probe = tc358743_probe, 1976 .remove = tc358743_remove, 1977 .id_table = tc358743_id, 1978 }; 1979 1980 module_i2c_driver(tc358743_driver); 1981