1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * tc358743 - Toshiba HDMI to CSI-2 bridge 4 * 5 * Copyright 2015 Cisco Systems, Inc. and/or its affiliates. All rights 6 * reserved. 7 */ 8 9 /* 10 * References (c = chapter, p = page): 11 * REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60 12 * REF_02 - Toshiba, TC358743XBG_HDMI-CSI_Tv11p_nm.xls 13 */ 14 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/slab.h> 18 #include <linux/i2c.h> 19 #include <linux/clk.h> 20 #include <linux/delay.h> 21 #include <linux/gpio/consumer.h> 22 #include <linux/interrupt.h> 23 #include <linux/timer.h> 24 #include <linux/of_graph.h> 25 #include <linux/videodev2.h> 26 #include <linux/workqueue.h> 27 #include <linux/v4l2-dv-timings.h> 28 #include <linux/hdmi.h> 29 #include <media/cec.h> 30 #include <media/v4l2-dv-timings.h> 31 #include <media/v4l2-device.h> 32 #include <media/v4l2-ctrls.h> 33 #include <media/v4l2-event.h> 34 #include <media/v4l2-fwnode.h> 35 #include <media/i2c/tc358743.h> 36 37 #include "tc358743_regs.h" 38 39 static int debug; 40 module_param(debug, int, 0644); 41 MODULE_PARM_DESC(debug, "debug level (0-3)"); 42 43 MODULE_DESCRIPTION("Toshiba TC358743 HDMI to CSI-2 bridge driver"); 44 MODULE_AUTHOR("Ramakrishnan Muthukrishnan <ram@rkrishnan.org>"); 45 MODULE_AUTHOR("Mikhail Khelik <mkhelik@cisco.com>"); 46 MODULE_AUTHOR("Mats Randgaard <matrandg@cisco.com>"); 47 MODULE_LICENSE("GPL"); 48 49 #define EDID_NUM_BLOCKS_MAX 8 50 #define EDID_BLOCK_SIZE 128 51 52 #define I2C_MAX_XFER_SIZE (EDID_BLOCK_SIZE + 2) 53 54 #define POLL_INTERVAL_CEC_MS 10 55 #define POLL_INTERVAL_MS 1000 56 57 static const struct v4l2_dv_timings_cap tc358743_timings_cap = { 58 .type = V4L2_DV_BT_656_1120, 59 /* keep this initialization for compatibility with GCC < 4.4.6 */ 60 .reserved = { 0 }, 61 /* Pixel clock from REF_01 p. 20. Min/max height/width are unknown */ 62 V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 13000000, 165000000, 63 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | 64 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT, 65 V4L2_DV_BT_CAP_PROGRESSIVE | 66 V4L2_DV_BT_CAP_REDUCED_BLANKING | 67 V4L2_DV_BT_CAP_CUSTOM) 68 }; 69 70 struct tc358743_state { 71 struct tc358743_platform_data pdata; 72 struct v4l2_mbus_config_mipi_csi2 bus; 73 struct v4l2_subdev sd; 74 struct media_pad pad; 75 struct v4l2_ctrl_handler hdl; 76 struct i2c_client *i2c_client; 77 /* CONFCTL is modified in ops and tc358743_hdmi_sys_int_handler */ 78 struct mutex confctl_mutex; 79 80 /* controls */ 81 struct v4l2_ctrl *detect_tx_5v_ctrl; 82 struct v4l2_ctrl *audio_sampling_rate_ctrl; 83 struct v4l2_ctrl *audio_present_ctrl; 84 85 struct delayed_work delayed_work_enable_hotplug; 86 87 struct timer_list timer; 88 struct work_struct work_i2c_poll; 89 90 /* debugfs */ 91 struct dentry *debugfs_dir; 92 struct v4l2_debugfs_if *infoframes; 93 94 /* edid */ 95 u8 edid_blocks_written; 96 97 struct v4l2_dv_timings timings; 98 u32 mbus_fmt_code; 99 u8 csi_lanes_in_use; 100 101 struct gpio_desc *reset_gpio; 102 103 struct cec_adapter *cec_adap; 104 }; 105 106 static void tc358743_enable_interrupts(struct v4l2_subdev *sd, 107 bool cable_connected); 108 static int tc358743_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd); 109 110 static inline struct tc358743_state *to_state(struct v4l2_subdev *sd) 111 { 112 return container_of(sd, struct tc358743_state, sd); 113 } 114 115 /* --------------- I2C --------------- */ 116 117 static void i2c_rd(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n) 118 { 119 struct tc358743_state *state = to_state(sd); 120 struct i2c_client *client = state->i2c_client; 121 int err; 122 u8 buf[2] = { reg >> 8, reg & 0xff }; 123 struct i2c_msg msgs[] = { 124 { 125 .addr = client->addr, 126 .flags = 0, 127 .len = 2, 128 .buf = buf, 129 }, 130 { 131 .addr = client->addr, 132 .flags = I2C_M_RD, 133 .len = n, 134 .buf = values, 135 }, 136 }; 137 138 err = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); 139 if (err != ARRAY_SIZE(msgs)) { 140 v4l2_err(sd, "%s: reading register 0x%x from 0x%x failed: %d\n", 141 __func__, reg, client->addr, err); 142 } 143 } 144 145 static void i2c_wr(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n) 146 { 147 struct tc358743_state *state = to_state(sd); 148 struct i2c_client *client = state->i2c_client; 149 int err, i; 150 struct i2c_msg msg; 151 u8 data[I2C_MAX_XFER_SIZE]; 152 153 if ((2 + n) > I2C_MAX_XFER_SIZE) { 154 n = I2C_MAX_XFER_SIZE - 2; 155 v4l2_warn(sd, "i2c wr reg=%04x: len=%d is too big!\n", 156 reg, 2 + n); 157 } 158 159 msg.addr = client->addr; 160 msg.buf = data; 161 msg.len = 2 + n; 162 msg.flags = 0; 163 164 data[0] = reg >> 8; 165 data[1] = reg & 0xff; 166 167 for (i = 0; i < n; i++) 168 data[2 + i] = values[i]; 169 170 err = i2c_transfer(client->adapter, &msg, 1); 171 if (err != 1) { 172 v4l2_err(sd, "%s: writing register 0x%x from 0x%x failed: %d\n", 173 __func__, reg, client->addr, err); 174 return; 175 } 176 177 if (debug < 3) 178 return; 179 180 switch (n) { 181 case 1: 182 v4l2_info(sd, "I2C write 0x%04x = 0x%02x", 183 reg, data[2]); 184 break; 185 case 2: 186 v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x", 187 reg, data[3], data[2]); 188 break; 189 case 4: 190 v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x%02x%02x", 191 reg, data[5], data[4], data[3], data[2]); 192 break; 193 default: 194 v4l2_info(sd, "I2C write %d bytes from address 0x%04x\n", 195 n, reg); 196 } 197 } 198 199 static noinline u32 i2c_rdreg(struct v4l2_subdev *sd, u16 reg, u32 n) 200 { 201 __le32 val = 0; 202 203 i2c_rd(sd, reg, (u8 __force *)&val, n); 204 205 return le32_to_cpu(val); 206 } 207 208 static noinline void i2c_wrreg(struct v4l2_subdev *sd, u16 reg, u32 val, u32 n) 209 { 210 __le32 raw = cpu_to_le32(val); 211 212 i2c_wr(sd, reg, (u8 __force *)&raw, n); 213 } 214 215 static u8 i2c_rd8(struct v4l2_subdev *sd, u16 reg) 216 { 217 return i2c_rdreg(sd, reg, 1); 218 } 219 220 static void i2c_wr8(struct v4l2_subdev *sd, u16 reg, u8 val) 221 { 222 i2c_wrreg(sd, reg, val, 1); 223 } 224 225 static void i2c_wr8_and_or(struct v4l2_subdev *sd, u16 reg, 226 u8 mask, u8 val) 227 { 228 i2c_wrreg(sd, reg, (i2c_rdreg(sd, reg, 1) & mask) | val, 1); 229 } 230 231 static u16 i2c_rd16(struct v4l2_subdev *sd, u16 reg) 232 { 233 return i2c_rdreg(sd, reg, 2); 234 } 235 236 static void i2c_wr16(struct v4l2_subdev *sd, u16 reg, u16 val) 237 { 238 i2c_wrreg(sd, reg, val, 2); 239 } 240 241 static void i2c_wr16_and_or(struct v4l2_subdev *sd, u16 reg, u16 mask, u16 val) 242 { 243 i2c_wrreg(sd, reg, (i2c_rdreg(sd, reg, 2) & mask) | val, 2); 244 } 245 246 static u32 i2c_rd32(struct v4l2_subdev *sd, u16 reg) 247 { 248 return i2c_rdreg(sd, reg, 4); 249 } 250 251 static void i2c_wr32(struct v4l2_subdev *sd, u16 reg, u32 val) 252 { 253 i2c_wrreg(sd, reg, val, 4); 254 } 255 256 /* --------------- STATUS --------------- */ 257 258 static inline bool is_hdmi(struct v4l2_subdev *sd) 259 { 260 return i2c_rd8(sd, SYS_STATUS) & MASK_S_HDMI; 261 } 262 263 static inline bool tx_5v_power_present(struct v4l2_subdev *sd) 264 { 265 return i2c_rd8(sd, SYS_STATUS) & MASK_S_DDC5V; 266 } 267 268 static inline bool no_signal(struct v4l2_subdev *sd) 269 { 270 return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_TMDS); 271 } 272 273 static inline bool no_sync(struct v4l2_subdev *sd) 274 { 275 return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_SYNC); 276 } 277 278 static inline bool audio_present(struct v4l2_subdev *sd) 279 { 280 return i2c_rd8(sd, AU_STATUS0) & MASK_S_A_SAMPLE; 281 } 282 283 static int get_audio_sampling_rate(struct v4l2_subdev *sd) 284 { 285 static const int code_to_rate[] = { 286 44100, 0, 48000, 32000, 22050, 384000, 24000, 352800, 287 88200, 768000, 96000, 705600, 176400, 0, 192000, 0 288 }; 289 290 /* Register FS_SET is not cleared when the cable is disconnected */ 291 if (no_signal(sd)) 292 return 0; 293 294 return code_to_rate[i2c_rd8(sd, FS_SET) & MASK_FS]; 295 } 296 297 /* --------------- TIMINGS --------------- */ 298 299 static inline unsigned fps(const struct v4l2_bt_timings *t) 300 { 301 if (!V4L2_DV_BT_FRAME_HEIGHT(t) || !V4L2_DV_BT_FRAME_WIDTH(t)) 302 return 0; 303 304 return DIV_ROUND_CLOSEST((unsigned)t->pixelclock, 305 V4L2_DV_BT_FRAME_HEIGHT(t) * V4L2_DV_BT_FRAME_WIDTH(t)); 306 } 307 308 static int tc358743_get_detected_timings(struct v4l2_subdev *sd, 309 struct v4l2_dv_timings *timings) 310 { 311 struct v4l2_bt_timings *bt = &timings->bt; 312 unsigned width, height, frame_width, frame_height, frame_interval, fps; 313 314 memset(timings, 0, sizeof(struct v4l2_dv_timings)); 315 316 /* if HPD is low, ignore any video */ 317 if (!(i2c_rd8(sd, HPD_CTL) & MASK_HPD_OUT0)) 318 return -ENOLINK; 319 320 if (no_signal(sd)) { 321 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__); 322 return -ENOLINK; 323 } 324 if (no_sync(sd)) { 325 v4l2_dbg(1, debug, sd, "%s: no sync on signal\n", __func__); 326 return -ENOLCK; 327 } 328 329 timings->type = V4L2_DV_BT_656_1120; 330 bt->interlaced = i2c_rd8(sd, VI_STATUS1) & MASK_S_V_INTERLACE ? 331 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE; 332 333 width = ((i2c_rd8(sd, DE_WIDTH_H_HI) & 0x1f) << 8) + 334 i2c_rd8(sd, DE_WIDTH_H_LO); 335 height = ((i2c_rd8(sd, DE_WIDTH_V_HI) & 0x1f) << 8) + 336 i2c_rd8(sd, DE_WIDTH_V_LO); 337 frame_width = ((i2c_rd8(sd, H_SIZE_HI) & 0x1f) << 8) + 338 i2c_rd8(sd, H_SIZE_LO); 339 frame_height = (((i2c_rd8(sd, V_SIZE_HI) & 0x3f) << 8) + 340 i2c_rd8(sd, V_SIZE_LO)) / 2; 341 /* frame interval in milliseconds * 10 342 * Require SYS_FREQ0 and SYS_FREQ1 are precisely set */ 343 frame_interval = ((i2c_rd8(sd, FV_CNT_HI) & 0x3) << 8) + 344 i2c_rd8(sd, FV_CNT_LO); 345 fps = (frame_interval > 0) ? 346 DIV_ROUND_CLOSEST(10000, frame_interval) : 0; 347 348 bt->width = width; 349 bt->height = height; 350 bt->vsync = frame_height - height; 351 bt->hsync = frame_width - width; 352 bt->pixelclock = frame_width * frame_height * fps; 353 if (bt->interlaced == V4L2_DV_INTERLACED) { 354 bt->height *= 2; 355 bt->il_vsync = bt->vsync + 1; 356 bt->pixelclock /= 2; 357 } 358 359 return 0; 360 } 361 362 /* --------------- HOTPLUG / HDCP / EDID --------------- */ 363 364 static void tc358743_delayed_work_enable_hotplug(struct work_struct *work) 365 { 366 struct delayed_work *dwork = to_delayed_work(work); 367 struct tc358743_state *state = container_of(dwork, 368 struct tc358743_state, delayed_work_enable_hotplug); 369 struct v4l2_subdev *sd = &state->sd; 370 371 v4l2_dbg(2, debug, sd, "%s:\n", __func__); 372 373 i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, MASK_HPD_OUT0); 374 } 375 376 static void tc358743_set_hdmi_hdcp(struct v4l2_subdev *sd, bool enable) 377 { 378 v4l2_dbg(2, debug, sd, "%s: %s\n", __func__, enable ? 379 "enable" : "disable"); 380 381 if (enable) { 382 i2c_wr8_and_or(sd, HDCP_REG3, ~KEY_RD_CMD, KEY_RD_CMD); 383 384 i2c_wr8_and_or(sd, HDCP_MODE, ~MASK_MANUAL_AUTHENTICATION, 0); 385 386 i2c_wr8_and_or(sd, HDCP_REG1, 0xff, 387 MASK_AUTH_UNAUTH_SEL_16_FRAMES | 388 MASK_AUTH_UNAUTH_AUTO); 389 390 i2c_wr8_and_or(sd, HDCP_REG2, ~MASK_AUTO_P3_RESET, 391 SET_AUTO_P3_RESET_FRAMES(0x0f)); 392 } else { 393 i2c_wr8_and_or(sd, HDCP_MODE, ~MASK_MANUAL_AUTHENTICATION, 394 MASK_MANUAL_AUTHENTICATION); 395 } 396 } 397 398 static void tc358743_disable_edid(struct v4l2_subdev *sd) 399 { 400 struct tc358743_state *state = to_state(sd); 401 402 v4l2_dbg(2, debug, sd, "%s:\n", __func__); 403 404 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug); 405 406 /* DDC access to EDID is also disabled when hotplug is disabled. See 407 * register DDC_CTL */ 408 i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, 0x0); 409 } 410 411 static void tc358743_enable_edid(struct v4l2_subdev *sd) 412 { 413 struct tc358743_state *state = to_state(sd); 414 415 if (state->edid_blocks_written == 0) { 416 v4l2_dbg(2, debug, sd, "%s: no EDID -> no hotplug\n", __func__); 417 tc358743_s_ctrl_detect_tx_5v(sd); 418 return; 419 } 420 421 v4l2_dbg(2, debug, sd, "%s:\n", __func__); 422 423 /* Enable hotplug after 100 ms. DDC access to EDID is also enabled when 424 * hotplug is enabled. See register DDC_CTL */ 425 schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 10); 426 427 tc358743_enable_interrupts(sd, true); 428 tc358743_s_ctrl_detect_tx_5v(sd); 429 } 430 431 static void tc358743_erase_bksv(struct v4l2_subdev *sd) 432 { 433 int i; 434 435 for (i = 0; i < 5; i++) 436 i2c_wr8(sd, BKSV + i, 0); 437 } 438 439 /* --------------- AVI infoframe --------------- */ 440 441 static ssize_t 442 tc358743_debugfs_if_read(u32 type, void *priv, struct file *filp, 443 char __user *ubuf, size_t count, loff_t *ppos) 444 { 445 u8 buf[V4L2_DEBUGFS_IF_MAX_LEN] = {}; 446 struct v4l2_subdev *sd = priv; 447 int len; 448 449 if (!is_hdmi(sd)) 450 return 0; 451 452 if (type != V4L2_DEBUGFS_IF_AVI) 453 return 0; 454 455 i2c_rd(sd, PK_AVI_0HEAD, buf, PK_AVI_16BYTE - PK_AVI_0HEAD + 1); 456 len = buf[2] + 4; 457 if (len > V4L2_DEBUGFS_IF_MAX_LEN) 458 len = -ENOENT; 459 if (len > 0) 460 len = simple_read_from_buffer(ubuf, count, ppos, buf, len); 461 return len < 0 ? 0 : len; 462 } 463 464 static void print_avi_infoframe(struct v4l2_subdev *sd) 465 { 466 struct i2c_client *client = v4l2_get_subdevdata(sd); 467 struct device *dev = &client->dev; 468 union hdmi_infoframe frame; 469 u8 buffer[HDMI_INFOFRAME_SIZE(AVI)] = {}; 470 471 if (!is_hdmi(sd)) { 472 v4l2_info(sd, "DVI-D signal - AVI infoframe not supported\n"); 473 return; 474 } 475 476 i2c_rd(sd, PK_AVI_0HEAD, buffer, HDMI_INFOFRAME_SIZE(AVI)); 477 478 if (hdmi_infoframe_unpack(&frame, buffer, sizeof(buffer)) < 0) { 479 v4l2_err(sd, "%s: unpack of AVI infoframe failed\n", __func__); 480 return; 481 } 482 483 hdmi_infoframe_log(KERN_INFO, dev, &frame); 484 } 485 486 /* --------------- CTRLS --------------- */ 487 488 static int tc358743_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd) 489 { 490 struct tc358743_state *state = to_state(sd); 491 492 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, 493 tx_5v_power_present(sd)); 494 } 495 496 static int tc358743_s_ctrl_audio_sampling_rate(struct v4l2_subdev *sd) 497 { 498 struct tc358743_state *state = to_state(sd); 499 500 return v4l2_ctrl_s_ctrl(state->audio_sampling_rate_ctrl, 501 get_audio_sampling_rate(sd)); 502 } 503 504 static int tc358743_s_ctrl_audio_present(struct v4l2_subdev *sd) 505 { 506 struct tc358743_state *state = to_state(sd); 507 508 return v4l2_ctrl_s_ctrl(state->audio_present_ctrl, 509 audio_present(sd)); 510 } 511 512 static int tc358743_update_controls(struct v4l2_subdev *sd) 513 { 514 int ret = 0; 515 516 ret |= tc358743_s_ctrl_detect_tx_5v(sd); 517 ret |= tc358743_s_ctrl_audio_sampling_rate(sd); 518 ret |= tc358743_s_ctrl_audio_present(sd); 519 520 return ret; 521 } 522 523 /* --------------- INIT --------------- */ 524 525 static void tc358743_reset_phy(struct v4l2_subdev *sd) 526 { 527 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 528 529 i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, 0); 530 i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, MASK_RESET_CTRL); 531 } 532 533 static void tc358743_reset(struct v4l2_subdev *sd, uint16_t mask) 534 { 535 u16 sysctl = i2c_rd16(sd, SYSCTL); 536 537 i2c_wr16(sd, SYSCTL, sysctl | mask); 538 i2c_wr16(sd, SYSCTL, sysctl & ~mask); 539 } 540 541 static inline void tc358743_sleep_mode(struct v4l2_subdev *sd, bool enable) 542 { 543 i2c_wr16_and_or(sd, SYSCTL, ~MASK_SLEEP, 544 enable ? MASK_SLEEP : 0); 545 } 546 547 static inline void enable_stream(struct v4l2_subdev *sd, bool enable) 548 { 549 struct tc358743_state *state = to_state(sd); 550 551 v4l2_dbg(3, debug, sd, "%s: %sable\n", 552 __func__, enable ? "en" : "dis"); 553 554 if (enable) { 555 /* It is critical for CSI receiver to see lane transition 556 * LP11->HS. Set to non-continuous mode to enable clock lane 557 * LP11 state. */ 558 i2c_wr32(sd, TXOPTIONCNTRL, 0); 559 /* Set to continuous mode to trigger LP11->HS transition */ 560 i2c_wr32(sd, TXOPTIONCNTRL, MASK_CONTCLKMODE); 561 /* Unmute video */ 562 i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE); 563 } else { 564 /* Mute video so that all data lanes go to LSP11 state. 565 * No data is output to CSI Tx block. */ 566 i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE | MASK_VI_MUTE); 567 } 568 569 mutex_lock(&state->confctl_mutex); 570 i2c_wr16_and_or(sd, CONFCTL, ~(MASK_VBUFEN | MASK_ABUFEN), 571 enable ? (MASK_VBUFEN | MASK_ABUFEN) : 0x0); 572 mutex_unlock(&state->confctl_mutex); 573 } 574 575 static void tc358743_set_pll(struct v4l2_subdev *sd) 576 { 577 struct tc358743_state *state = to_state(sd); 578 struct tc358743_platform_data *pdata = &state->pdata; 579 u16 pllctl0 = i2c_rd16(sd, PLLCTL0); 580 u16 pllctl1 = i2c_rd16(sd, PLLCTL1); 581 u16 pllctl0_new = SET_PLL_PRD(pdata->pll_prd) | 582 SET_PLL_FBD(pdata->pll_fbd); 583 u32 hsck = (pdata->refclk_hz / pdata->pll_prd) * pdata->pll_fbd; 584 585 v4l2_dbg(2, debug, sd, "%s:\n", __func__); 586 587 /* Only rewrite when needed (new value or disabled), since rewriting 588 * triggers another format change event. */ 589 if ((pllctl0 != pllctl0_new) || ((pllctl1 & MASK_PLL_EN) == 0)) { 590 u16 pll_frs; 591 592 if (hsck > 500000000) 593 pll_frs = 0x0; 594 else if (hsck > 250000000) 595 pll_frs = 0x1; 596 else if (hsck > 125000000) 597 pll_frs = 0x2; 598 else 599 pll_frs = 0x3; 600 601 v4l2_dbg(1, debug, sd, "%s: updating PLL clock\n", __func__); 602 tc358743_sleep_mode(sd, true); 603 i2c_wr16(sd, PLLCTL0, pllctl0_new); 604 i2c_wr16_and_or(sd, PLLCTL1, 605 ~(MASK_PLL_FRS | MASK_RESETB | MASK_PLL_EN), 606 (SET_PLL_FRS(pll_frs) | MASK_RESETB | 607 MASK_PLL_EN)); 608 udelay(10); /* REF_02, Sheet "Source HDMI" */ 609 i2c_wr16_and_or(sd, PLLCTL1, ~MASK_CKEN, MASK_CKEN); 610 tc358743_sleep_mode(sd, false); 611 } 612 } 613 614 static void tc358743_set_ref_clk(struct v4l2_subdev *sd) 615 { 616 struct tc358743_state *state = to_state(sd); 617 struct tc358743_platform_data *pdata = &state->pdata; 618 u32 sys_freq; 619 u32 lockdet_ref; 620 u32 cec_freq; 621 u16 fh_min; 622 u16 fh_max; 623 624 BUG_ON(!(pdata->refclk_hz == 26000000 || 625 pdata->refclk_hz == 27000000 || 626 pdata->refclk_hz == 42000000)); 627 628 sys_freq = pdata->refclk_hz / 10000; 629 i2c_wr8(sd, SYS_FREQ0, sys_freq & 0x00ff); 630 i2c_wr8(sd, SYS_FREQ1, (sys_freq & 0xff00) >> 8); 631 632 i2c_wr8_and_or(sd, PHY_CTL0, ~MASK_PHY_SYSCLK_IND, 633 (pdata->refclk_hz == 42000000) ? 634 MASK_PHY_SYSCLK_IND : 0x0); 635 636 fh_min = pdata->refclk_hz / 100000; 637 i2c_wr8(sd, FH_MIN0, fh_min & 0x00ff); 638 i2c_wr8(sd, FH_MIN1, (fh_min & 0xff00) >> 8); 639 640 fh_max = (fh_min * 66) / 10; 641 i2c_wr8(sd, FH_MAX0, fh_max & 0x00ff); 642 i2c_wr8(sd, FH_MAX1, (fh_max & 0xff00) >> 8); 643 644 lockdet_ref = pdata->refclk_hz / 100; 645 i2c_wr8(sd, LOCKDET_REF0, lockdet_ref & 0x0000ff); 646 i2c_wr8(sd, LOCKDET_REF1, (lockdet_ref & 0x00ff00) >> 8); 647 i2c_wr8(sd, LOCKDET_REF2, (lockdet_ref & 0x0f0000) >> 16); 648 649 i2c_wr8_and_or(sd, NCO_F0_MOD, ~MASK_NCO_F0_MOD, 650 (pdata->refclk_hz == 27000000) ? 651 MASK_NCO_F0_MOD_27MHZ : 0x0); 652 653 /* 654 * Trial and error suggests that the default register value 655 * of 656 is for a 42 MHz reference clock. Use that to derive 656 * a new value based on the actual reference clock. 657 */ 658 cec_freq = (656 * sys_freq) / 4200; 659 i2c_wr16(sd, CECHCLK, cec_freq); 660 i2c_wr16(sd, CECLCLK, cec_freq); 661 } 662 663 static void tc358743_set_csi_color_space(struct v4l2_subdev *sd) 664 { 665 struct tc358743_state *state = to_state(sd); 666 667 switch (state->mbus_fmt_code) { 668 case MEDIA_BUS_FMT_UYVY8_1X16: 669 v4l2_dbg(2, debug, sd, "%s: YCbCr 422 16-bit\n", __func__); 670 i2c_wr8_and_or(sd, VOUT_SET2, 671 ~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff, 672 MASK_SEL422 | MASK_VOUT_422FIL_100); 673 i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff, 674 MASK_VOUT_COLOR_601_YCBCR_LIMITED); 675 mutex_lock(&state->confctl_mutex); 676 i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT, 677 MASK_YCBCRFMT_422_8_BIT); 678 mutex_unlock(&state->confctl_mutex); 679 break; 680 case MEDIA_BUS_FMT_RGB888_1X24: 681 v4l2_dbg(2, debug, sd, "%s: RGB 888 24-bit\n", __func__); 682 i2c_wr8_and_or(sd, VOUT_SET2, 683 ~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff, 684 0x00); 685 i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff, 686 MASK_VOUT_COLOR_RGB_FULL); 687 mutex_lock(&state->confctl_mutex); 688 i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT, 0); 689 mutex_unlock(&state->confctl_mutex); 690 break; 691 default: 692 v4l2_dbg(2, debug, sd, "%s: Unsupported format code 0x%x\n", 693 __func__, state->mbus_fmt_code); 694 } 695 } 696 697 static unsigned tc358743_num_csi_lanes_needed(struct v4l2_subdev *sd) 698 { 699 struct tc358743_state *state = to_state(sd); 700 struct v4l2_bt_timings *bt = &state->timings.bt; 701 struct tc358743_platform_data *pdata = &state->pdata; 702 u32 bits_pr_pixel = 703 (state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16) ? 16 : 24; 704 u32 bps = bt->width * bt->height * fps(bt) * bits_pr_pixel; 705 u32 bps_pr_lane = (pdata->refclk_hz / pdata->pll_prd) * pdata->pll_fbd; 706 707 return DIV_ROUND_UP(bps, bps_pr_lane); 708 } 709 710 static void tc358743_set_csi(struct v4l2_subdev *sd) 711 { 712 struct tc358743_state *state = to_state(sd); 713 struct tc358743_platform_data *pdata = &state->pdata; 714 unsigned lanes = tc358743_num_csi_lanes_needed(sd); 715 716 v4l2_dbg(3, debug, sd, "%s:\n", __func__); 717 718 state->csi_lanes_in_use = lanes; 719 720 tc358743_reset(sd, MASK_CTXRST); 721 722 if (lanes < 1) 723 i2c_wr32(sd, CLW_CNTRL, MASK_CLW_LANEDISABLE); 724 if (lanes < 1) 725 i2c_wr32(sd, D0W_CNTRL, MASK_D0W_LANEDISABLE); 726 if (lanes < 2) 727 i2c_wr32(sd, D1W_CNTRL, MASK_D1W_LANEDISABLE); 728 if (lanes < 3) 729 i2c_wr32(sd, D2W_CNTRL, MASK_D2W_LANEDISABLE); 730 if (lanes < 4) 731 i2c_wr32(sd, D3W_CNTRL, MASK_D3W_LANEDISABLE); 732 733 i2c_wr32(sd, LINEINITCNT, pdata->lineinitcnt); 734 i2c_wr32(sd, LPTXTIMECNT, pdata->lptxtimecnt); 735 i2c_wr32(sd, TCLK_HEADERCNT, pdata->tclk_headercnt); 736 i2c_wr32(sd, TCLK_TRAILCNT, pdata->tclk_trailcnt); 737 i2c_wr32(sd, THS_HEADERCNT, pdata->ths_headercnt); 738 i2c_wr32(sd, TWAKEUP, pdata->twakeup); 739 i2c_wr32(sd, TCLK_POSTCNT, pdata->tclk_postcnt); 740 i2c_wr32(sd, THS_TRAILCNT, pdata->ths_trailcnt); 741 i2c_wr32(sd, HSTXVREGCNT, pdata->hstxvregcnt); 742 743 i2c_wr32(sd, HSTXVREGEN, 744 ((lanes > 0) ? MASK_CLM_HSTXVREGEN : 0x0) | 745 ((lanes > 0) ? MASK_D0M_HSTXVREGEN : 0x0) | 746 ((lanes > 1) ? MASK_D1M_HSTXVREGEN : 0x0) | 747 ((lanes > 2) ? MASK_D2M_HSTXVREGEN : 0x0) | 748 ((lanes > 3) ? MASK_D3M_HSTXVREGEN : 0x0)); 749 750 i2c_wr32(sd, TXOPTIONCNTRL, (state->bus.flags & 751 V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK) ? 0 : MASK_CONTCLKMODE); 752 i2c_wr32(sd, STARTCNTRL, MASK_START); 753 i2c_wr32(sd, CSI_START, MASK_STRT); 754 755 i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET | 756 MASK_ADDRESS_CSI_CONTROL | 757 MASK_CSI_MODE | 758 MASK_TXHSMD | 759 ((lanes == 4) ? MASK_NOL_4 : 760 (lanes == 3) ? MASK_NOL_3 : 761 (lanes == 2) ? MASK_NOL_2 : MASK_NOL_1)); 762 763 i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET | 764 MASK_ADDRESS_CSI_ERR_INTENA | MASK_TXBRK | MASK_QUNK | 765 MASK_WCER | MASK_INER); 766 767 i2c_wr32(sd, CSI_CONFW, MASK_MODE_CLEAR | 768 MASK_ADDRESS_CSI_ERR_HALT | MASK_TXBRK | MASK_QUNK); 769 770 i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET | 771 MASK_ADDRESS_CSI_INT_ENA | MASK_INTER); 772 } 773 774 static void tc358743_set_hdmi_phy(struct v4l2_subdev *sd) 775 { 776 struct tc358743_state *state = to_state(sd); 777 struct tc358743_platform_data *pdata = &state->pdata; 778 779 /* Default settings from REF_02, sheet "Source HDMI" 780 * and custom settings as platform data */ 781 i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, 0x0); 782 i2c_wr8(sd, PHY_CTL1, SET_PHY_AUTO_RST1_US(1600) | 783 SET_FREQ_RANGE_MODE_CYCLES(1)); 784 i2c_wr8_and_or(sd, PHY_CTL2, ~MASK_PHY_AUTO_RSTn, 785 (pdata->hdmi_phy_auto_reset_tmds_detected ? 786 MASK_PHY_AUTO_RST2 : 0) | 787 (pdata->hdmi_phy_auto_reset_tmds_in_range ? 788 MASK_PHY_AUTO_RST3 : 0) | 789 (pdata->hdmi_phy_auto_reset_tmds_valid ? 790 MASK_PHY_AUTO_RST4 : 0)); 791 i2c_wr8(sd, PHY_BIAS, 0x40); 792 i2c_wr8(sd, PHY_CSQ, SET_CSQ_CNT_LEVEL(0x0a)); 793 i2c_wr8(sd, AVM_CTL, 45); 794 i2c_wr8_and_or(sd, HDMI_DET, ~MASK_HDMI_DET_V, 795 pdata->hdmi_detection_delay << 4); 796 i2c_wr8_and_or(sd, HV_RST, ~(MASK_H_PI_RST | MASK_V_PI_RST), 797 (pdata->hdmi_phy_auto_reset_hsync_out_of_range ? 798 MASK_H_PI_RST : 0) | 799 (pdata->hdmi_phy_auto_reset_vsync_out_of_range ? 800 MASK_V_PI_RST : 0)); 801 i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, MASK_ENABLE_PHY); 802 } 803 804 static void tc358743_set_hdmi_audio(struct v4l2_subdev *sd) 805 { 806 struct tc358743_state *state = to_state(sd); 807 808 /* Default settings from REF_02, sheet "Source HDMI" */ 809 i2c_wr8(sd, FORCE_MUTE, 0x00); 810 i2c_wr8(sd, AUTO_CMD0, MASK_AUTO_MUTE7 | MASK_AUTO_MUTE6 | 811 MASK_AUTO_MUTE5 | MASK_AUTO_MUTE4 | 812 MASK_AUTO_MUTE1 | MASK_AUTO_MUTE0); 813 i2c_wr8(sd, AUTO_CMD1, MASK_AUTO_MUTE9); 814 i2c_wr8(sd, AUTO_CMD2, MASK_AUTO_PLAY3 | MASK_AUTO_PLAY2); 815 i2c_wr8(sd, BUFINIT_START, SET_BUFINIT_START_MS(500)); 816 i2c_wr8(sd, FS_MUTE, 0x00); 817 i2c_wr8(sd, FS_IMODE, MASK_NLPCM_SMODE | MASK_FS_SMODE); 818 i2c_wr8(sd, ACR_MODE, MASK_CTS_MODE); 819 i2c_wr8(sd, ACR_MDF0, MASK_ACR_L2MDF_1976_PPM | MASK_ACR_L1MDF_976_PPM); 820 i2c_wr8(sd, ACR_MDF1, MASK_ACR_L3MDF_3906_PPM); 821 i2c_wr8(sd, SDO_MODE1, MASK_SDO_FMT_I2S); 822 i2c_wr8(sd, DIV_MODE, SET_DIV_DLY_MS(100)); 823 824 mutex_lock(&state->confctl_mutex); 825 i2c_wr16_and_or(sd, CONFCTL, 0xffff, MASK_AUDCHNUM_2 | 826 MASK_AUDOUTSEL_I2S | MASK_AUTOINDEX); 827 mutex_unlock(&state->confctl_mutex); 828 } 829 830 static void tc358743_set_hdmi_info_frame_mode(struct v4l2_subdev *sd) 831 { 832 /* Default settings from REF_02, sheet "Source HDMI" */ 833 i2c_wr8(sd, PK_INT_MODE, MASK_ISRC2_INT_MODE | MASK_ISRC_INT_MODE | 834 MASK_ACP_INT_MODE | MASK_VS_INT_MODE | 835 MASK_SPD_INT_MODE | MASK_MS_INT_MODE | 836 MASK_AUD_INT_MODE | MASK_AVI_INT_MODE); 837 i2c_wr8(sd, NO_PKT_LIMIT, 0x2c); 838 i2c_wr8(sd, NO_PKT_CLR, 0x53); 839 i2c_wr8(sd, ERR_PK_LIMIT, 0x01); 840 i2c_wr8(sd, NO_PKT_LIMIT2, 0x30); 841 i2c_wr8(sd, NO_GDB_LIMIT, 0x10); 842 } 843 844 static void tc358743_initial_setup(struct v4l2_subdev *sd) 845 { 846 struct tc358743_state *state = to_state(sd); 847 struct tc358743_platform_data *pdata = &state->pdata; 848 849 /* 850 * IR is not supported by this driver. 851 * CEC is only enabled if needed. 852 */ 853 i2c_wr16_and_or(sd, SYSCTL, ~(MASK_IRRST | MASK_CECRST), 854 (MASK_IRRST | MASK_CECRST)); 855 856 tc358743_reset(sd, MASK_CTXRST | MASK_HDMIRST); 857 #ifdef CONFIG_VIDEO_TC358743_CEC 858 tc358743_reset(sd, MASK_CECRST); 859 #endif 860 tc358743_sleep_mode(sd, false); 861 862 i2c_wr16(sd, FIFOCTL, pdata->fifo_level); 863 864 tc358743_set_ref_clk(sd); 865 866 i2c_wr8_and_or(sd, DDC_CTL, ~MASK_DDC5V_MODE, 867 pdata->ddc5v_delay & MASK_DDC5V_MODE); 868 i2c_wr8_and_or(sd, EDID_MODE, ~MASK_EDID_MODE, MASK_EDID_MODE_E_DDC); 869 870 tc358743_set_hdmi_phy(sd); 871 tc358743_set_hdmi_hdcp(sd, pdata->enable_hdcp); 872 tc358743_set_hdmi_audio(sd); 873 tc358743_set_hdmi_info_frame_mode(sd); 874 875 /* All CE and IT formats are detected as RGB full range in DVI mode */ 876 i2c_wr8_and_or(sd, VI_MODE, ~MASK_RGB_DVI, 0); 877 878 i2c_wr8_and_or(sd, VOUT_SET2, ~MASK_VOUTCOLORMODE, 879 MASK_VOUTCOLORMODE_AUTO); 880 i2c_wr8(sd, VOUT_SET3, MASK_VOUT_EXTCNT); 881 } 882 883 /* --------------- CEC --------------- */ 884 885 #ifdef CONFIG_VIDEO_TC358743_CEC 886 static int tc358743_cec_adap_enable(struct cec_adapter *adap, bool enable) 887 { 888 struct tc358743_state *state = adap->priv; 889 struct v4l2_subdev *sd = &state->sd; 890 891 i2c_wr32(sd, CECIMSK, enable ? MASK_CECTIM | MASK_CECRIM : 0); 892 i2c_wr32(sd, CECICLR, MASK_CECTICLR | MASK_CECRICLR); 893 i2c_wr32(sd, CECEN, enable); 894 if (enable) 895 i2c_wr32(sd, CECREN, MASK_CECREN); 896 return 0; 897 } 898 899 static int tc358743_cec_adap_monitor_all_enable(struct cec_adapter *adap, 900 bool enable) 901 { 902 struct tc358743_state *state = adap->priv; 903 struct v4l2_subdev *sd = &state->sd; 904 u32 reg; 905 906 reg = i2c_rd32(sd, CECRCTL1); 907 if (enable) 908 reg |= MASK_CECOTH; 909 else 910 reg &= ~MASK_CECOTH; 911 i2c_wr32(sd, CECRCTL1, reg); 912 return 0; 913 } 914 915 static int tc358743_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr) 916 { 917 struct tc358743_state *state = adap->priv; 918 struct v4l2_subdev *sd = &state->sd; 919 unsigned int la = 0; 920 921 if (log_addr != CEC_LOG_ADDR_INVALID) { 922 la = i2c_rd32(sd, CECADD); 923 la |= 1 << log_addr; 924 } 925 i2c_wr32(sd, CECADD, la); 926 return 0; 927 } 928 929 static int tc358743_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, 930 u32 signal_free_time, struct cec_msg *msg) 931 { 932 struct tc358743_state *state = adap->priv; 933 struct v4l2_subdev *sd = &state->sd; 934 unsigned int i; 935 936 i2c_wr32(sd, CECTCTL, 937 (cec_msg_is_broadcast(msg) ? MASK_CECBRD : 0) | 938 (signal_free_time - 1)); 939 for (i = 0; i < msg->len; i++) 940 i2c_wr32(sd, CECTBUF1 + i * 4, 941 msg->msg[i] | ((i == msg->len - 1) ? MASK_CECTEOM : 0)); 942 i2c_wr32(sd, CECTEN, MASK_CECTEN); 943 return 0; 944 } 945 946 static const struct cec_adap_ops tc358743_cec_adap_ops = { 947 .adap_enable = tc358743_cec_adap_enable, 948 .adap_log_addr = tc358743_cec_adap_log_addr, 949 .adap_transmit = tc358743_cec_adap_transmit, 950 .adap_monitor_all_enable = tc358743_cec_adap_monitor_all_enable, 951 }; 952 953 static void tc358743_cec_handler(struct v4l2_subdev *sd, u16 intstatus, 954 bool *handled) 955 { 956 struct tc358743_state *state = to_state(sd); 957 unsigned int cec_rxint, cec_txint; 958 unsigned int clr = 0; 959 960 cec_rxint = i2c_rd32(sd, CECRSTAT); 961 cec_txint = i2c_rd32(sd, CECTSTAT); 962 963 if (intstatus & MASK_CEC_RINT) 964 clr |= MASK_CECRICLR; 965 if (intstatus & MASK_CEC_TINT) 966 clr |= MASK_CECTICLR; 967 i2c_wr32(sd, CECICLR, clr); 968 969 if ((intstatus & MASK_CEC_TINT) && cec_txint) { 970 if (cec_txint & MASK_CECTIEND) 971 cec_transmit_attempt_done(state->cec_adap, 972 CEC_TX_STATUS_OK); 973 else if (cec_txint & MASK_CECTIAL) 974 cec_transmit_attempt_done(state->cec_adap, 975 CEC_TX_STATUS_ARB_LOST); 976 else if (cec_txint & MASK_CECTIACK) 977 cec_transmit_attempt_done(state->cec_adap, 978 CEC_TX_STATUS_NACK); 979 else if (cec_txint & MASK_CECTIUR) { 980 /* 981 * Not sure when this bit is set. Treat 982 * it as an error for now. 983 */ 984 cec_transmit_attempt_done(state->cec_adap, 985 CEC_TX_STATUS_ERROR); 986 } 987 if (handled) 988 *handled = true; 989 } 990 if ((intstatus & MASK_CEC_RINT) && 991 (cec_rxint & MASK_CECRIEND)) { 992 struct cec_msg msg = {}; 993 unsigned int i; 994 unsigned int v; 995 996 v = i2c_rd32(sd, CECRCTR); 997 msg.len = v & 0x1f; 998 if (msg.len > CEC_MAX_MSG_SIZE) 999 msg.len = CEC_MAX_MSG_SIZE; 1000 for (i = 0; i < msg.len; i++) { 1001 v = i2c_rd32(sd, CECRBUF1 + i * 4); 1002 msg.msg[i] = v & 0xff; 1003 } 1004 cec_received_msg(state->cec_adap, &msg); 1005 if (handled) 1006 *handled = true; 1007 } 1008 i2c_wr16(sd, INTSTATUS, 1009 intstatus & (MASK_CEC_RINT | MASK_CEC_TINT)); 1010 } 1011 1012 #endif 1013 1014 /* --------------- IRQ --------------- */ 1015 1016 static void tc358743_format_change(struct v4l2_subdev *sd) 1017 { 1018 struct tc358743_state *state = to_state(sd); 1019 struct v4l2_dv_timings timings; 1020 const struct v4l2_event tc358743_ev_fmt = { 1021 .type = V4L2_EVENT_SOURCE_CHANGE, 1022 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION, 1023 }; 1024 1025 if (tc358743_get_detected_timings(sd, &timings)) { 1026 enable_stream(sd, false); 1027 1028 v4l2_dbg(1, debug, sd, "%s: No signal\n", 1029 __func__); 1030 } else { 1031 if (!v4l2_match_dv_timings(&state->timings, &timings, 0, false)) 1032 enable_stream(sd, false); 1033 1034 if (debug) 1035 v4l2_print_dv_timings(sd->name, 1036 "tc358743_format_change: New format: ", 1037 &timings, false); 1038 } 1039 1040 if (sd->devnode) 1041 v4l2_subdev_notify_event(sd, &tc358743_ev_fmt); 1042 } 1043 1044 static void tc358743_init_interrupts(struct v4l2_subdev *sd) 1045 { 1046 u16 i; 1047 1048 /* clear interrupt status registers */ 1049 for (i = SYS_INT; i <= KEY_INT; i++) 1050 i2c_wr8(sd, i, 0xff); 1051 1052 i2c_wr16(sd, INTSTATUS, 0xffff); 1053 } 1054 1055 static void tc358743_enable_interrupts(struct v4l2_subdev *sd, 1056 bool cable_connected) 1057 { 1058 v4l2_dbg(2, debug, sd, "%s: cable connected = %d\n", __func__, 1059 cable_connected); 1060 1061 if (cable_connected) { 1062 i2c_wr8(sd, SYS_INTM, ~(MASK_M_DDC | MASK_M_DVI_DET | 1063 MASK_M_HDMI_DET) & 0xff); 1064 i2c_wr8(sd, CLK_INTM, ~MASK_M_IN_DE_CHG); 1065 i2c_wr8(sd, CBIT_INTM, ~(MASK_M_CBIT_FS | MASK_M_AF_LOCK | 1066 MASK_M_AF_UNLOCK) & 0xff); 1067 i2c_wr8(sd, AUDIO_INTM, ~MASK_M_BUFINIT_END); 1068 i2c_wr8(sd, MISC_INTM, ~MASK_M_SYNC_CHG); 1069 } else { 1070 i2c_wr8(sd, SYS_INTM, ~MASK_M_DDC & 0xff); 1071 i2c_wr8(sd, CLK_INTM, 0xff); 1072 i2c_wr8(sd, CBIT_INTM, 0xff); 1073 i2c_wr8(sd, AUDIO_INTM, 0xff); 1074 i2c_wr8(sd, MISC_INTM, 0xff); 1075 } 1076 } 1077 1078 static void tc358743_hdmi_audio_int_handler(struct v4l2_subdev *sd, 1079 bool *handled) 1080 { 1081 u8 audio_int_mask = i2c_rd8(sd, AUDIO_INTM); 1082 u8 audio_int = i2c_rd8(sd, AUDIO_INT) & ~audio_int_mask; 1083 1084 i2c_wr8(sd, AUDIO_INT, audio_int); 1085 1086 v4l2_dbg(3, debug, sd, "%s: AUDIO_INT = 0x%02x\n", __func__, audio_int); 1087 1088 tc358743_s_ctrl_audio_sampling_rate(sd); 1089 tc358743_s_ctrl_audio_present(sd); 1090 } 1091 1092 static void tc358743_csi_err_int_handler(struct v4l2_subdev *sd, bool *handled) 1093 { 1094 v4l2_err(sd, "%s: CSI_ERR = 0x%x\n", __func__, i2c_rd32(sd, CSI_ERR)); 1095 1096 i2c_wr32(sd, CSI_INT_CLR, MASK_ICRER); 1097 } 1098 1099 static void tc358743_hdmi_misc_int_handler(struct v4l2_subdev *sd, 1100 bool *handled) 1101 { 1102 u8 misc_int_mask = i2c_rd8(sd, MISC_INTM); 1103 u8 misc_int = i2c_rd8(sd, MISC_INT) & ~misc_int_mask; 1104 1105 i2c_wr8(sd, MISC_INT, misc_int); 1106 1107 v4l2_dbg(3, debug, sd, "%s: MISC_INT = 0x%02x\n", __func__, misc_int); 1108 1109 if (misc_int & MASK_I_SYNC_CHG) { 1110 /* Reset the HDMI PHY to try to trigger proper lock on the 1111 * incoming video format. Erase BKSV to prevent that old keys 1112 * are used when a new source is connected. */ 1113 if (no_sync(sd) || no_signal(sd)) { 1114 tc358743_reset_phy(sd); 1115 tc358743_erase_bksv(sd); 1116 } 1117 1118 tc358743_format_change(sd); 1119 1120 misc_int &= ~MASK_I_SYNC_CHG; 1121 if (handled) 1122 *handled = true; 1123 } 1124 1125 if (misc_int) { 1126 v4l2_err(sd, "%s: Unhandled MISC_INT interrupts: 0x%02x\n", 1127 __func__, misc_int); 1128 } 1129 } 1130 1131 static void tc358743_hdmi_cbit_int_handler(struct v4l2_subdev *sd, 1132 bool *handled) 1133 { 1134 u8 cbit_int_mask = i2c_rd8(sd, CBIT_INTM); 1135 u8 cbit_int = i2c_rd8(sd, CBIT_INT) & ~cbit_int_mask; 1136 1137 i2c_wr8(sd, CBIT_INT, cbit_int); 1138 1139 v4l2_dbg(3, debug, sd, "%s: CBIT_INT = 0x%02x\n", __func__, cbit_int); 1140 1141 if (cbit_int & MASK_I_CBIT_FS) { 1142 1143 v4l2_dbg(1, debug, sd, "%s: Audio sample rate changed\n", 1144 __func__); 1145 tc358743_s_ctrl_audio_sampling_rate(sd); 1146 1147 cbit_int &= ~MASK_I_CBIT_FS; 1148 if (handled) 1149 *handled = true; 1150 } 1151 1152 if (cbit_int & (MASK_I_AF_LOCK | MASK_I_AF_UNLOCK)) { 1153 1154 v4l2_dbg(1, debug, sd, "%s: Audio present changed\n", 1155 __func__); 1156 tc358743_s_ctrl_audio_present(sd); 1157 1158 cbit_int &= ~(MASK_I_AF_LOCK | MASK_I_AF_UNLOCK); 1159 if (handled) 1160 *handled = true; 1161 } 1162 1163 if (cbit_int) { 1164 v4l2_err(sd, "%s: Unhandled CBIT_INT interrupts: 0x%02x\n", 1165 __func__, cbit_int); 1166 } 1167 } 1168 1169 static void tc358743_hdmi_clk_int_handler(struct v4l2_subdev *sd, bool *handled) 1170 { 1171 u8 clk_int_mask = i2c_rd8(sd, CLK_INTM); 1172 u8 clk_int = i2c_rd8(sd, CLK_INT) & ~clk_int_mask; 1173 1174 /* Bit 7 and bit 6 are set even when they are masked */ 1175 i2c_wr8(sd, CLK_INT, clk_int | 0x80 | MASK_I_OUT_H_CHG); 1176 1177 v4l2_dbg(3, debug, sd, "%s: CLK_INT = 0x%02x\n", __func__, clk_int); 1178 1179 if (clk_int & (MASK_I_IN_DE_CHG)) { 1180 1181 v4l2_dbg(1, debug, sd, "%s: DE size or position has changed\n", 1182 __func__); 1183 1184 /* If the source switch to a new resolution with the same pixel 1185 * frequency as the existing (e.g. 1080p25 -> 720p50), the 1186 * I_SYNC_CHG interrupt is not always triggered, while the 1187 * I_IN_DE_CHG interrupt seems to work fine. Format change 1188 * notifications are only sent when the signal is stable to 1189 * reduce the number of notifications. */ 1190 if (!no_signal(sd) && !no_sync(sd)) 1191 tc358743_format_change(sd); 1192 1193 clk_int &= ~(MASK_I_IN_DE_CHG); 1194 if (handled) 1195 *handled = true; 1196 } 1197 1198 if (clk_int) { 1199 v4l2_err(sd, "%s: Unhandled CLK_INT interrupts: 0x%02x\n", 1200 __func__, clk_int); 1201 } 1202 } 1203 1204 static void tc358743_hdmi_sys_int_handler(struct v4l2_subdev *sd, bool *handled) 1205 { 1206 struct tc358743_state *state = to_state(sd); 1207 u8 sys_int_mask = i2c_rd8(sd, SYS_INTM); 1208 u8 sys_int = i2c_rd8(sd, SYS_INT) & ~sys_int_mask; 1209 1210 i2c_wr8(sd, SYS_INT, sys_int); 1211 1212 v4l2_dbg(3, debug, sd, "%s: SYS_INT = 0x%02x\n", __func__, sys_int); 1213 1214 if (sys_int & MASK_I_DDC) { 1215 bool tx_5v = tx_5v_power_present(sd); 1216 1217 v4l2_dbg(1, debug, sd, "%s: Tx 5V power present: %s\n", 1218 __func__, tx_5v ? "yes" : "no"); 1219 1220 if (tx_5v) { 1221 tc358743_enable_edid(sd); 1222 } else { 1223 tc358743_enable_interrupts(sd, false); 1224 tc358743_disable_edid(sd); 1225 memset(&state->timings, 0, sizeof(state->timings)); 1226 tc358743_erase_bksv(sd); 1227 tc358743_update_controls(sd); 1228 } 1229 1230 sys_int &= ~MASK_I_DDC; 1231 if (handled) 1232 *handled = true; 1233 } 1234 1235 if (sys_int & MASK_I_DVI) { 1236 v4l2_dbg(1, debug, sd, "%s: HDMI->DVI change detected\n", 1237 __func__); 1238 1239 /* Reset the HDMI PHY to try to trigger proper lock on the 1240 * incoming video format. Erase BKSV to prevent that old keys 1241 * are used when a new source is connected. */ 1242 if (no_sync(sd) || no_signal(sd)) { 1243 tc358743_reset_phy(sd); 1244 tc358743_erase_bksv(sd); 1245 } 1246 1247 sys_int &= ~MASK_I_DVI; 1248 if (handled) 1249 *handled = true; 1250 } 1251 1252 if (sys_int & MASK_I_HDMI) { 1253 v4l2_dbg(1, debug, sd, "%s: DVI->HDMI change detected\n", 1254 __func__); 1255 1256 /* Register is reset in DVI mode (REF_01, c. 6.6.41) */ 1257 i2c_wr8(sd, ANA_CTL, MASK_APPL_PCSX_NORMAL | MASK_ANALOG_ON); 1258 1259 sys_int &= ~MASK_I_HDMI; 1260 if (handled) 1261 *handled = true; 1262 } 1263 1264 if (sys_int) { 1265 v4l2_err(sd, "%s: Unhandled SYS_INT interrupts: 0x%02x\n", 1266 __func__, sys_int); 1267 } 1268 } 1269 1270 /* --------------- CORE OPS --------------- */ 1271 1272 static int tc358743_log_status(struct v4l2_subdev *sd) 1273 { 1274 struct tc358743_state *state = to_state(sd); 1275 struct v4l2_dv_timings timings; 1276 uint8_t hdmi_sys_status = i2c_rd8(sd, SYS_STATUS); 1277 uint16_t sysctl = i2c_rd16(sd, SYSCTL); 1278 u8 vi_status3 = i2c_rd8(sd, VI_STATUS3); 1279 const int deep_color_mode[4] = { 8, 10, 12, 16 }; 1280 static const char * const input_color_space[] = { 1281 "RGB", "YCbCr 601", "opRGB", "YCbCr 709", "NA (4)", 1282 "xvYCC 601", "NA(6)", "xvYCC 709", "NA(8)", "sYCC601", 1283 "NA(10)", "NA(11)", "NA(12)", "opYCC 601"}; 1284 1285 v4l2_info(sd, "-----Chip status-----\n"); 1286 v4l2_info(sd, "Chip ID: 0x%02x\n", 1287 (i2c_rd16(sd, CHIPID) & MASK_CHIPID) >> 8); 1288 v4l2_info(sd, "Chip revision: 0x%02x\n", 1289 i2c_rd16(sd, CHIPID) & MASK_REVID); 1290 v4l2_info(sd, "Reset: IR: %d, CEC: %d, CSI TX: %d, HDMI: %d\n", 1291 !!(sysctl & MASK_IRRST), 1292 !!(sysctl & MASK_CECRST), 1293 !!(sysctl & MASK_CTXRST), 1294 !!(sysctl & MASK_HDMIRST)); 1295 v4l2_info(sd, "Sleep mode: %s\n", sysctl & MASK_SLEEP ? "on" : "off"); 1296 v4l2_info(sd, "Cable detected (+5V power): %s\n", 1297 hdmi_sys_status & MASK_S_DDC5V ? "yes" : "no"); 1298 v4l2_info(sd, "DDC lines enabled: %s\n", 1299 (i2c_rd8(sd, EDID_MODE) & MASK_EDID_MODE_E_DDC) ? 1300 "yes" : "no"); 1301 v4l2_info(sd, "Hotplug enabled: %s\n", 1302 (i2c_rd8(sd, HPD_CTL) & MASK_HPD_OUT0) ? 1303 "yes" : "no"); 1304 v4l2_info(sd, "CEC enabled: %s\n", 1305 (i2c_rd16(sd, CECEN) & MASK_CECEN) ? "yes" : "no"); 1306 v4l2_info(sd, "-----Signal status-----\n"); 1307 v4l2_info(sd, "TMDS signal detected: %s\n", 1308 hdmi_sys_status & MASK_S_TMDS ? "yes" : "no"); 1309 v4l2_info(sd, "Stable sync signal: %s\n", 1310 hdmi_sys_status & MASK_S_SYNC ? "yes" : "no"); 1311 v4l2_info(sd, "PHY PLL locked: %s\n", 1312 hdmi_sys_status & MASK_S_PHY_PLL ? "yes" : "no"); 1313 v4l2_info(sd, "PHY DE detected: %s\n", 1314 hdmi_sys_status & MASK_S_PHY_SCDT ? "yes" : "no"); 1315 1316 if (tc358743_get_detected_timings(sd, &timings)) { 1317 v4l2_info(sd, "No video detected\n"); 1318 } else { 1319 v4l2_print_dv_timings(sd->name, "Detected format: ", &timings, 1320 true); 1321 } 1322 v4l2_print_dv_timings(sd->name, "Configured format: ", &state->timings, 1323 true); 1324 1325 v4l2_info(sd, "-----CSI-TX status-----\n"); 1326 v4l2_info(sd, "Lanes needed: %d\n", 1327 tc358743_num_csi_lanes_needed(sd)); 1328 v4l2_info(sd, "Lanes in use: %d\n", 1329 state->csi_lanes_in_use); 1330 v4l2_info(sd, "Waiting for particular sync signal: %s\n", 1331 (i2c_rd16(sd, CSI_STATUS) & MASK_S_WSYNC) ? 1332 "yes" : "no"); 1333 v4l2_info(sd, "Transmit mode: %s\n", 1334 (i2c_rd16(sd, CSI_STATUS) & MASK_S_TXACT) ? 1335 "yes" : "no"); 1336 v4l2_info(sd, "Receive mode: %s\n", 1337 (i2c_rd16(sd, CSI_STATUS) & MASK_S_RXACT) ? 1338 "yes" : "no"); 1339 v4l2_info(sd, "Stopped: %s\n", 1340 (i2c_rd16(sd, CSI_STATUS) & MASK_S_HLT) ? 1341 "yes" : "no"); 1342 v4l2_info(sd, "Color space: %s\n", 1343 state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16 ? 1344 "YCbCr 422 16-bit" : 1345 state->mbus_fmt_code == MEDIA_BUS_FMT_RGB888_1X24 ? 1346 "RGB 888 24-bit" : "Unsupported"); 1347 1348 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D"); 1349 v4l2_info(sd, "HDCP encrypted content: %s\n", 1350 hdmi_sys_status & MASK_S_HDCP ? "yes" : "no"); 1351 v4l2_info(sd, "Input color space: %s %s range\n", 1352 input_color_space[(vi_status3 & MASK_S_V_COLOR) >> 1], 1353 (vi_status3 & MASK_LIMITED) ? "limited" : "full"); 1354 if (!is_hdmi(sd)) 1355 return 0; 1356 v4l2_info(sd, "AV Mute: %s\n", hdmi_sys_status & MASK_S_AVMUTE ? "on" : 1357 "off"); 1358 v4l2_info(sd, "Deep color mode: %d-bits per channel\n", 1359 deep_color_mode[(i2c_rd8(sd, VI_STATUS1) & 1360 MASK_S_DEEPCOLOR) >> 2]); 1361 print_avi_infoframe(sd); 1362 1363 return 0; 1364 } 1365 1366 #ifdef CONFIG_VIDEO_ADV_DEBUG 1367 static void tc358743_print_register_map(struct v4l2_subdev *sd) 1368 { 1369 v4l2_info(sd, "0x0000-0x00FF: Global Control Register\n"); 1370 v4l2_info(sd, "0x0100-0x01FF: CSI2-TX PHY Register\n"); 1371 v4l2_info(sd, "0x0200-0x03FF: CSI2-TX PPI Register\n"); 1372 v4l2_info(sd, "0x0400-0x05FF: Reserved\n"); 1373 v4l2_info(sd, "0x0600-0x06FF: CEC Register\n"); 1374 v4l2_info(sd, "0x0700-0x84FF: Reserved\n"); 1375 v4l2_info(sd, "0x8500-0x85FF: HDMIRX System Control Register\n"); 1376 v4l2_info(sd, "0x8600-0x86FF: HDMIRX Audio Control Register\n"); 1377 v4l2_info(sd, "0x8700-0x87FF: HDMIRX InfoFrame packet data Register\n"); 1378 v4l2_info(sd, "0x8800-0x88FF: HDMIRX HDCP Port Register\n"); 1379 v4l2_info(sd, "0x8900-0x89FF: HDMIRX Video Output Port & 3D Register\n"); 1380 v4l2_info(sd, "0x8A00-0x8BFF: Reserved\n"); 1381 v4l2_info(sd, "0x8C00-0x8FFF: HDMIRX EDID-RAM (1024bytes)\n"); 1382 v4l2_info(sd, "0x9000-0x90FF: HDMIRX GBD Extraction Control\n"); 1383 v4l2_info(sd, "0x9100-0x92FF: HDMIRX GBD RAM read\n"); 1384 v4l2_info(sd, "0x9300- : Reserved\n"); 1385 } 1386 1387 static int tc358743_get_reg_size(u16 address) 1388 { 1389 /* REF_01 p. 66-72 */ 1390 if (address <= 0x00ff) 1391 return 2; 1392 else if ((address >= 0x0100) && (address <= 0x06FF)) 1393 return 4; 1394 else if ((address >= 0x0700) && (address <= 0x84ff)) 1395 return 2; 1396 else 1397 return 1; 1398 } 1399 1400 static int tc358743_g_register(struct v4l2_subdev *sd, 1401 struct v4l2_dbg_register *reg) 1402 { 1403 if (reg->reg > 0xffff) { 1404 tc358743_print_register_map(sd); 1405 return -EINVAL; 1406 } 1407 1408 reg->size = tc358743_get_reg_size(reg->reg); 1409 1410 reg->val = i2c_rdreg(sd, reg->reg, reg->size); 1411 1412 return 0; 1413 } 1414 1415 static int tc358743_s_register(struct v4l2_subdev *sd, 1416 const struct v4l2_dbg_register *reg) 1417 { 1418 if (reg->reg > 0xffff) { 1419 tc358743_print_register_map(sd); 1420 return -EINVAL; 1421 } 1422 1423 /* It should not be possible for the user to enable HDCP with a simple 1424 * v4l2-dbg command. 1425 * 1426 * DO NOT REMOVE THIS unless all other issues with HDCP have been 1427 * resolved. 1428 */ 1429 if (reg->reg == HDCP_MODE || 1430 reg->reg == HDCP_REG1 || 1431 reg->reg == HDCP_REG2 || 1432 reg->reg == HDCP_REG3 || 1433 reg->reg == BCAPS) 1434 return 0; 1435 1436 i2c_wrreg(sd, (u16)reg->reg, reg->val, 1437 tc358743_get_reg_size(reg->reg)); 1438 1439 return 0; 1440 } 1441 #endif 1442 1443 static int tc358743_isr(struct v4l2_subdev *sd, u32 status, bool *handled) 1444 { 1445 u16 intstatus = i2c_rd16(sd, INTSTATUS); 1446 1447 v4l2_dbg(1, debug, sd, "%s: IntStatus = 0x%04x\n", __func__, intstatus); 1448 1449 if (intstatus & MASK_HDMI_INT) { 1450 u8 hdmi_int0 = i2c_rd8(sd, HDMI_INT0); 1451 u8 hdmi_int1 = i2c_rd8(sd, HDMI_INT1); 1452 1453 if (hdmi_int0 & MASK_I_MISC) 1454 tc358743_hdmi_misc_int_handler(sd, handled); 1455 if (hdmi_int1 & MASK_I_CBIT) 1456 tc358743_hdmi_cbit_int_handler(sd, handled); 1457 if (hdmi_int1 & MASK_I_CLK) 1458 tc358743_hdmi_clk_int_handler(sd, handled); 1459 if (hdmi_int1 & MASK_I_SYS) 1460 tc358743_hdmi_sys_int_handler(sd, handled); 1461 if (hdmi_int1 & MASK_I_AUD) 1462 tc358743_hdmi_audio_int_handler(sd, handled); 1463 1464 i2c_wr16(sd, INTSTATUS, MASK_HDMI_INT); 1465 intstatus &= ~MASK_HDMI_INT; 1466 } 1467 1468 #ifdef CONFIG_VIDEO_TC358743_CEC 1469 if (intstatus & (MASK_CEC_RINT | MASK_CEC_TINT)) { 1470 tc358743_cec_handler(sd, intstatus, handled); 1471 i2c_wr16(sd, INTSTATUS, 1472 intstatus & (MASK_CEC_RINT | MASK_CEC_TINT)); 1473 intstatus &= ~(MASK_CEC_RINT | MASK_CEC_TINT); 1474 } 1475 #endif 1476 1477 if (intstatus & MASK_CSI_INT) { 1478 u32 csi_int = i2c_rd32(sd, CSI_INT); 1479 1480 if (csi_int & MASK_INTER) 1481 tc358743_csi_err_int_handler(sd, handled); 1482 1483 i2c_wr16(sd, INTSTATUS, MASK_CSI_INT); 1484 } 1485 1486 intstatus = i2c_rd16(sd, INTSTATUS); 1487 if (intstatus) { 1488 v4l2_dbg(1, debug, sd, 1489 "%s: Unhandled IntStatus interrupts: 0x%02x\n", 1490 __func__, intstatus); 1491 } 1492 1493 return 0; 1494 } 1495 1496 static irqreturn_t tc358743_irq_handler(int irq, void *dev_id) 1497 { 1498 struct tc358743_state *state = dev_id; 1499 bool handled = false; 1500 1501 tc358743_isr(&state->sd, 0, &handled); 1502 1503 return handled ? IRQ_HANDLED : IRQ_NONE; 1504 } 1505 1506 static void tc358743_irq_poll_timer(struct timer_list *t) 1507 { 1508 struct tc358743_state *state = timer_container_of(state, t, timer); 1509 unsigned int msecs; 1510 1511 schedule_work(&state->work_i2c_poll); 1512 /* 1513 * If CEC is present, then we need to poll more frequently, 1514 * otherwise we will miss CEC messages. 1515 */ 1516 msecs = state->cec_adap ? POLL_INTERVAL_CEC_MS : POLL_INTERVAL_MS; 1517 mod_timer(&state->timer, jiffies + msecs_to_jiffies(msecs)); 1518 } 1519 1520 static void tc358743_work_i2c_poll(struct work_struct *work) 1521 { 1522 struct tc358743_state *state = container_of(work, 1523 struct tc358743_state, work_i2c_poll); 1524 bool handled; 1525 1526 tc358743_isr(&state->sd, 0, &handled); 1527 } 1528 1529 static int tc358743_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh, 1530 struct v4l2_event_subscription *sub) 1531 { 1532 switch (sub->type) { 1533 case V4L2_EVENT_SOURCE_CHANGE: 1534 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub); 1535 case V4L2_EVENT_CTRL: 1536 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub); 1537 default: 1538 return -EINVAL; 1539 } 1540 } 1541 1542 /* --------------- VIDEO OPS --------------- */ 1543 1544 static int tc358743_g_input_status(struct v4l2_subdev *sd, u32 *status) 1545 { 1546 *status = 0; 1547 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0; 1548 *status |= no_sync(sd) ? V4L2_IN_ST_NO_SYNC : 0; 1549 1550 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status); 1551 1552 return 0; 1553 } 1554 1555 static int tc358743_s_dv_timings(struct v4l2_subdev *sd, unsigned int pad, 1556 struct v4l2_dv_timings *timings) 1557 { 1558 struct tc358743_state *state = to_state(sd); 1559 1560 if (pad != 0) 1561 return -EINVAL; 1562 1563 if (!timings) 1564 return -EINVAL; 1565 1566 if (debug) 1567 v4l2_print_dv_timings(sd->name, "tc358743_s_dv_timings: ", 1568 timings, false); 1569 1570 if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) { 1571 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__); 1572 return 0; 1573 } 1574 1575 if (!v4l2_valid_dv_timings(timings, 1576 &tc358743_timings_cap, NULL, NULL)) { 1577 v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__); 1578 return -ERANGE; 1579 } 1580 1581 state->timings = *timings; 1582 1583 enable_stream(sd, false); 1584 tc358743_set_pll(sd); 1585 tc358743_set_csi(sd); 1586 1587 return 0; 1588 } 1589 1590 static int tc358743_g_dv_timings(struct v4l2_subdev *sd, unsigned int pad, 1591 struct v4l2_dv_timings *timings) 1592 { 1593 struct tc358743_state *state = to_state(sd); 1594 1595 if (pad != 0) 1596 return -EINVAL; 1597 1598 *timings = state->timings; 1599 1600 return 0; 1601 } 1602 1603 static int tc358743_enum_dv_timings(struct v4l2_subdev *sd, 1604 struct v4l2_enum_dv_timings *timings) 1605 { 1606 if (timings->pad != 0) 1607 return -EINVAL; 1608 1609 return v4l2_enum_dv_timings_cap(timings, 1610 &tc358743_timings_cap, NULL, NULL); 1611 } 1612 1613 static int tc358743_query_dv_timings(struct v4l2_subdev *sd, unsigned int pad, 1614 struct v4l2_dv_timings *timings) 1615 { 1616 int ret; 1617 1618 if (pad != 0) 1619 return -EINVAL; 1620 1621 ret = tc358743_get_detected_timings(sd, timings); 1622 if (ret) 1623 return ret; 1624 1625 if (debug) 1626 v4l2_print_dv_timings(sd->name, "tc358743_query_dv_timings: ", 1627 timings, false); 1628 1629 if (!v4l2_valid_dv_timings(timings, 1630 &tc358743_timings_cap, NULL, NULL)) { 1631 v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__); 1632 return -ERANGE; 1633 } 1634 1635 return 0; 1636 } 1637 1638 static int tc358743_dv_timings_cap(struct v4l2_subdev *sd, 1639 struct v4l2_dv_timings_cap *cap) 1640 { 1641 if (cap->pad != 0) 1642 return -EINVAL; 1643 1644 *cap = tc358743_timings_cap; 1645 1646 return 0; 1647 } 1648 1649 static int tc358743_get_mbus_config(struct v4l2_subdev *sd, 1650 unsigned int pad, 1651 struct v4l2_mbus_config *cfg) 1652 { 1653 struct tc358743_state *state = to_state(sd); 1654 1655 cfg->type = V4L2_MBUS_CSI2_DPHY; 1656 1657 /* Support for non-continuous CSI-2 clock is missing in the driver */ 1658 cfg->bus.mipi_csi2.flags = 0; 1659 cfg->bus.mipi_csi2.num_data_lanes = state->csi_lanes_in_use; 1660 1661 return 0; 1662 } 1663 1664 static int tc358743_s_stream(struct v4l2_subdev *sd, int enable) 1665 { 1666 enable_stream(sd, enable); 1667 if (!enable) { 1668 /* Put all lanes in LP-11 state (STOPSTATE) */ 1669 tc358743_set_csi(sd); 1670 } 1671 1672 return 0; 1673 } 1674 1675 /* --------------- PAD OPS --------------- */ 1676 1677 static int tc358743_enum_mbus_code(struct v4l2_subdev *sd, 1678 struct v4l2_subdev_state *sd_state, 1679 struct v4l2_subdev_mbus_code_enum *code) 1680 { 1681 switch (code->index) { 1682 case 0: 1683 code->code = MEDIA_BUS_FMT_RGB888_1X24; 1684 break; 1685 case 1: 1686 code->code = MEDIA_BUS_FMT_UYVY8_1X16; 1687 break; 1688 default: 1689 return -EINVAL; 1690 } 1691 return 0; 1692 } 1693 1694 static int tc358743_get_fmt(struct v4l2_subdev *sd, 1695 struct v4l2_subdev_state *sd_state, 1696 struct v4l2_subdev_format *format) 1697 { 1698 struct tc358743_state *state = to_state(sd); 1699 u8 vi_rep = i2c_rd8(sd, VI_REP); 1700 1701 if (format->pad != 0) 1702 return -EINVAL; 1703 1704 format->format.code = state->mbus_fmt_code; 1705 format->format.width = state->timings.bt.width; 1706 format->format.height = state->timings.bt.height; 1707 format->format.field = V4L2_FIELD_NONE; 1708 1709 switch (vi_rep & MASK_VOUT_COLOR_SEL) { 1710 case MASK_VOUT_COLOR_RGB_FULL: 1711 case MASK_VOUT_COLOR_RGB_LIMITED: 1712 format->format.colorspace = V4L2_COLORSPACE_SRGB; 1713 break; 1714 case MASK_VOUT_COLOR_601_YCBCR_LIMITED: 1715 case MASK_VOUT_COLOR_601_YCBCR_FULL: 1716 format->format.colorspace = V4L2_COLORSPACE_SMPTE170M; 1717 break; 1718 case MASK_VOUT_COLOR_709_YCBCR_FULL: 1719 case MASK_VOUT_COLOR_709_YCBCR_LIMITED: 1720 format->format.colorspace = V4L2_COLORSPACE_REC709; 1721 break; 1722 default: 1723 format->format.colorspace = 0; 1724 break; 1725 } 1726 1727 return 0; 1728 } 1729 1730 static int tc358743_set_fmt(struct v4l2_subdev *sd, 1731 struct v4l2_subdev_state *sd_state, 1732 struct v4l2_subdev_format *format) 1733 { 1734 struct tc358743_state *state = to_state(sd); 1735 1736 u32 code = format->format.code; /* is overwritten by get_fmt */ 1737 int ret = tc358743_get_fmt(sd, sd_state, format); 1738 1739 format->format.code = code; 1740 1741 if (ret) 1742 return ret; 1743 1744 switch (code) { 1745 case MEDIA_BUS_FMT_RGB888_1X24: 1746 case MEDIA_BUS_FMT_UYVY8_1X16: 1747 break; 1748 default: 1749 return -EINVAL; 1750 } 1751 1752 if (format->which == V4L2_SUBDEV_FORMAT_TRY) 1753 return 0; 1754 1755 state->mbus_fmt_code = format->format.code; 1756 1757 enable_stream(sd, false); 1758 tc358743_set_pll(sd); 1759 tc358743_set_csi(sd); 1760 tc358743_set_csi_color_space(sd); 1761 1762 return 0; 1763 } 1764 1765 static int tc358743_g_edid(struct v4l2_subdev *sd, 1766 struct v4l2_subdev_edid *edid) 1767 { 1768 struct tc358743_state *state = to_state(sd); 1769 1770 memset(edid->reserved, 0, sizeof(edid->reserved)); 1771 1772 if (edid->pad != 0) 1773 return -EINVAL; 1774 1775 if (edid->start_block == 0 && edid->blocks == 0) { 1776 edid->blocks = state->edid_blocks_written; 1777 return 0; 1778 } 1779 1780 if (state->edid_blocks_written == 0) 1781 return -ENODATA; 1782 1783 if (edid->start_block >= state->edid_blocks_written || 1784 edid->blocks == 0) 1785 return -EINVAL; 1786 1787 if (edid->start_block + edid->blocks > state->edid_blocks_written) 1788 edid->blocks = state->edid_blocks_written - edid->start_block; 1789 1790 i2c_rd(sd, EDID_RAM + (edid->start_block * EDID_BLOCK_SIZE), edid->edid, 1791 edid->blocks * EDID_BLOCK_SIZE); 1792 1793 return 0; 1794 } 1795 1796 static int tc358743_s_edid(struct v4l2_subdev *sd, 1797 struct v4l2_subdev_edid *edid) 1798 { 1799 struct tc358743_state *state = to_state(sd); 1800 u16 edid_len = edid->blocks * EDID_BLOCK_SIZE; 1801 u16 pa; 1802 int err; 1803 int i; 1804 1805 v4l2_dbg(2, debug, sd, "%s, pad %d, start block %d, blocks %d\n", 1806 __func__, edid->pad, edid->start_block, edid->blocks); 1807 1808 memset(edid->reserved, 0, sizeof(edid->reserved)); 1809 1810 if (edid->pad != 0) 1811 return -EINVAL; 1812 1813 if (edid->start_block != 0) 1814 return -EINVAL; 1815 1816 if (edid->blocks > EDID_NUM_BLOCKS_MAX) { 1817 edid->blocks = EDID_NUM_BLOCKS_MAX; 1818 return -E2BIG; 1819 } 1820 pa = cec_get_edid_phys_addr(edid->edid, edid->blocks * 128, NULL); 1821 err = v4l2_phys_addr_validate(pa, &pa, NULL); 1822 if (err) 1823 return err; 1824 1825 cec_phys_addr_invalidate(state->cec_adap); 1826 1827 tc358743_disable_edid(sd); 1828 1829 i2c_wr8(sd, EDID_LEN1, edid_len & 0xff); 1830 i2c_wr8(sd, EDID_LEN2, edid_len >> 8); 1831 1832 if (edid->blocks == 0) { 1833 state->edid_blocks_written = 0; 1834 return 0; 1835 } 1836 1837 for (i = 0; i < edid_len; i += EDID_BLOCK_SIZE) 1838 i2c_wr(sd, EDID_RAM + i, edid->edid + i, EDID_BLOCK_SIZE); 1839 1840 state->edid_blocks_written = edid->blocks; 1841 1842 cec_s_phys_addr(state->cec_adap, pa, false); 1843 1844 if (tx_5v_power_present(sd)) 1845 tc358743_enable_edid(sd); 1846 1847 return 0; 1848 } 1849 1850 /* -------------------------------------------------------------------------- */ 1851 1852 static const struct v4l2_subdev_core_ops tc358743_core_ops = { 1853 .log_status = tc358743_log_status, 1854 #ifdef CONFIG_VIDEO_ADV_DEBUG 1855 .g_register = tc358743_g_register, 1856 .s_register = tc358743_s_register, 1857 #endif 1858 .interrupt_service_routine = tc358743_isr, 1859 .subscribe_event = tc358743_subscribe_event, 1860 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 1861 }; 1862 1863 static const struct v4l2_subdev_video_ops tc358743_video_ops = { 1864 .g_input_status = tc358743_g_input_status, 1865 .s_stream = tc358743_s_stream, 1866 }; 1867 1868 static const struct v4l2_subdev_pad_ops tc358743_pad_ops = { 1869 .enum_mbus_code = tc358743_enum_mbus_code, 1870 .set_fmt = tc358743_set_fmt, 1871 .get_fmt = tc358743_get_fmt, 1872 .get_edid = tc358743_g_edid, 1873 .set_edid = tc358743_s_edid, 1874 .s_dv_timings = tc358743_s_dv_timings, 1875 .g_dv_timings = tc358743_g_dv_timings, 1876 .query_dv_timings = tc358743_query_dv_timings, 1877 .enum_dv_timings = tc358743_enum_dv_timings, 1878 .dv_timings_cap = tc358743_dv_timings_cap, 1879 .get_mbus_config = tc358743_get_mbus_config, 1880 }; 1881 1882 static const struct v4l2_subdev_ops tc358743_ops = { 1883 .core = &tc358743_core_ops, 1884 .video = &tc358743_video_ops, 1885 .pad = &tc358743_pad_ops, 1886 }; 1887 1888 /* --------------- CUSTOM CTRLS --------------- */ 1889 1890 static const struct v4l2_ctrl_config tc358743_ctrl_audio_sampling_rate = { 1891 .id = TC358743_CID_AUDIO_SAMPLING_RATE, 1892 .name = "Audio sampling rate", 1893 .type = V4L2_CTRL_TYPE_INTEGER, 1894 .min = 0, 1895 .max = 768000, 1896 .step = 1, 1897 .def = 0, 1898 .flags = V4L2_CTRL_FLAG_READ_ONLY, 1899 }; 1900 1901 static const struct v4l2_ctrl_config tc358743_ctrl_audio_present = { 1902 .id = TC358743_CID_AUDIO_PRESENT, 1903 .name = "Audio present", 1904 .type = V4L2_CTRL_TYPE_BOOLEAN, 1905 .min = 0, 1906 .max = 1, 1907 .step = 1, 1908 .def = 0, 1909 .flags = V4L2_CTRL_FLAG_READ_ONLY, 1910 }; 1911 1912 /* --------------- PROBE / REMOVE --------------- */ 1913 1914 #ifdef CONFIG_OF 1915 static void tc358743_gpio_reset(struct tc358743_state *state) 1916 { 1917 usleep_range(5000, 10000); 1918 gpiod_set_value(state->reset_gpio, 1); 1919 usleep_range(1000, 2000); 1920 gpiod_set_value(state->reset_gpio, 0); 1921 msleep(20); 1922 } 1923 1924 static int tc358743_probe_of(struct tc358743_state *state) 1925 { 1926 struct device *dev = &state->i2c_client->dev; 1927 struct v4l2_fwnode_endpoint endpoint = { .bus_type = 0 }; 1928 struct device_node *ep; 1929 struct clk *refclk; 1930 u32 bps_pr_lane; 1931 int ret; 1932 1933 refclk = devm_clk_get(dev, "refclk"); 1934 if (IS_ERR(refclk)) 1935 return dev_err_probe(dev, PTR_ERR(refclk), 1936 "failed to get refclk\n"); 1937 1938 ep = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1); 1939 if (!ep) { 1940 dev_err(dev, "missing endpoint node\n"); 1941 return -EINVAL; 1942 } 1943 1944 ret = v4l2_fwnode_endpoint_alloc_parse(of_fwnode_handle(ep), &endpoint); 1945 if (ret) { 1946 dev_err(dev, "failed to parse endpoint\n"); 1947 goto put_node; 1948 } 1949 1950 if (endpoint.bus_type != V4L2_MBUS_CSI2_DPHY || 1951 endpoint.bus.mipi_csi2.num_data_lanes == 0 || 1952 endpoint.nr_of_link_frequencies == 0) { 1953 dev_err(dev, "missing CSI-2 properties in endpoint\n"); 1954 ret = -EINVAL; 1955 goto free_endpoint; 1956 } 1957 1958 if (endpoint.bus.mipi_csi2.num_data_lanes > 4) { 1959 dev_err(dev, "invalid number of lanes\n"); 1960 ret = -EINVAL; 1961 goto free_endpoint; 1962 } 1963 1964 state->bus = endpoint.bus.mipi_csi2; 1965 1966 ret = clk_prepare_enable(refclk); 1967 if (ret) { 1968 dev_err(dev, "Failed! to enable clock\n"); 1969 goto free_endpoint; 1970 } 1971 1972 state->pdata.refclk_hz = clk_get_rate(refclk); 1973 state->pdata.ddc5v_delay = DDC5V_DELAY_100_MS; 1974 state->pdata.enable_hdcp = false; 1975 /* A FIFO level of 16 should be enough for 2-lane 720p60 at 594 MHz. */ 1976 state->pdata.fifo_level = 16; 1977 /* 1978 * The PLL input clock is obtained by dividing refclk by pll_prd. 1979 * It must be between 6 MHz and 40 MHz, lower frequency is better. 1980 */ 1981 switch (state->pdata.refclk_hz) { 1982 case 26000000: 1983 case 27000000: 1984 case 42000000: 1985 state->pdata.pll_prd = state->pdata.refclk_hz / 6000000; 1986 break; 1987 default: 1988 dev_err(dev, "unsupported refclk rate: %u Hz\n", 1989 state->pdata.refclk_hz); 1990 goto disable_clk; 1991 } 1992 1993 /* 1994 * The CSI bps per lane must be between 62.5 Mbps and 1 Gbps. 1995 * The default is 594 Mbps for 4-lane 1080p60 or 2-lane 720p60. 1996 */ 1997 bps_pr_lane = 2 * endpoint.link_frequencies[0]; 1998 if (bps_pr_lane < 62500000U || bps_pr_lane > 1000000000U) { 1999 dev_err(dev, "unsupported bps per lane: %u bps\n", bps_pr_lane); 2000 ret = -EINVAL; 2001 goto disable_clk; 2002 } 2003 2004 /* The CSI speed per lane is refclk / pll_prd * pll_fbd */ 2005 state->pdata.pll_fbd = bps_pr_lane / 2006 state->pdata.refclk_hz * state->pdata.pll_prd; 2007 2008 /* 2009 * FIXME: These timings are from REF_02 for 594 Mbps per lane (297 MHz 2010 * link frequency). In principle it should be possible to calculate 2011 * them based on link frequency and resolution. 2012 */ 2013 if (bps_pr_lane != 594000000U) 2014 dev_warn(dev, "untested bps per lane: %u bps\n", bps_pr_lane); 2015 state->pdata.lineinitcnt = 0xe80; 2016 state->pdata.lptxtimecnt = 0x003; 2017 /* tclk-preparecnt: 3, tclk-zerocnt: 20 */ 2018 state->pdata.tclk_headercnt = 0x1403; 2019 state->pdata.tclk_trailcnt = 0x00; 2020 /* ths-preparecnt: 3, ths-zerocnt: 1 */ 2021 state->pdata.ths_headercnt = 0x0103; 2022 state->pdata.twakeup = 0x4882; 2023 state->pdata.tclk_postcnt = 0x008; 2024 state->pdata.ths_trailcnt = 0x2; 2025 state->pdata.hstxvregcnt = 0; 2026 2027 state->reset_gpio = devm_gpiod_get_optional(dev, "reset", 2028 GPIOD_OUT_LOW); 2029 if (IS_ERR(state->reset_gpio)) { 2030 dev_err(dev, "failed to get reset gpio\n"); 2031 ret = PTR_ERR(state->reset_gpio); 2032 goto disable_clk; 2033 } 2034 2035 if (state->reset_gpio) 2036 tc358743_gpio_reset(state); 2037 2038 ret = 0; 2039 goto free_endpoint; 2040 2041 disable_clk: 2042 clk_disable_unprepare(refclk); 2043 free_endpoint: 2044 v4l2_fwnode_endpoint_free(&endpoint); 2045 put_node: 2046 of_node_put(ep); 2047 return ret; 2048 } 2049 #else 2050 static inline int tc358743_probe_of(struct tc358743_state *state) 2051 { 2052 return -ENODEV; 2053 } 2054 #endif 2055 2056 static int tc358743_probe(struct i2c_client *client) 2057 { 2058 static struct v4l2_dv_timings default_timing = 2059 V4L2_DV_BT_CEA_640X480P59_94; 2060 struct tc358743_state *state; 2061 struct tc358743_platform_data *pdata = client->dev.platform_data; 2062 struct v4l2_subdev *sd; 2063 u16 irq_mask = MASK_HDMI_MSK | MASK_CSI_MSK; 2064 int err; 2065 2066 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 2067 return -EIO; 2068 v4l_dbg(1, debug, client, "chip found @ 0x%x (%s)\n", 2069 client->addr << 1, client->adapter->name); 2070 2071 state = devm_kzalloc(&client->dev, sizeof(struct tc358743_state), 2072 GFP_KERNEL); 2073 if (!state) 2074 return -ENOMEM; 2075 2076 state->i2c_client = client; 2077 2078 /* platform data */ 2079 if (pdata) { 2080 state->pdata = *pdata; 2081 state->bus.flags = 0; 2082 } else { 2083 err = tc358743_probe_of(state); 2084 if (err == -ENODEV) 2085 v4l_err(client, "No platform data!\n"); 2086 if (err) 2087 return err; 2088 } 2089 2090 sd = &state->sd; 2091 v4l2_i2c_subdev_init(sd, client, &tc358743_ops); 2092 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; 2093 2094 /* i2c access */ 2095 if ((i2c_rd16(sd, CHIPID) & MASK_CHIPID) != 0) { 2096 v4l2_info(sd, "not a TC358743 on address 0x%x\n", 2097 client->addr << 1); 2098 return -ENODEV; 2099 } 2100 2101 /* control handlers */ 2102 v4l2_ctrl_handler_init(&state->hdl, 3); 2103 2104 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(&state->hdl, NULL, 2105 V4L2_CID_DV_RX_POWER_PRESENT, 0, 1, 0, 0); 2106 2107 /* custom controls */ 2108 state->audio_sampling_rate_ctrl = v4l2_ctrl_new_custom(&state->hdl, 2109 &tc358743_ctrl_audio_sampling_rate, NULL); 2110 2111 state->audio_present_ctrl = v4l2_ctrl_new_custom(&state->hdl, 2112 &tc358743_ctrl_audio_present, NULL); 2113 2114 sd->ctrl_handler = &state->hdl; 2115 if (state->hdl.error) { 2116 err = state->hdl.error; 2117 goto err_hdl; 2118 } 2119 2120 if (tc358743_update_controls(sd)) { 2121 err = -ENODEV; 2122 goto err_hdl; 2123 } 2124 2125 state->pad.flags = MEDIA_PAD_FL_SOURCE; 2126 sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE; 2127 err = media_entity_pads_init(&sd->entity, 1, &state->pad); 2128 if (err < 0) 2129 goto err_hdl; 2130 2131 state->mbus_fmt_code = MEDIA_BUS_FMT_RGB888_1X24; 2132 2133 sd->dev = &client->dev; 2134 2135 mutex_init(&state->confctl_mutex); 2136 2137 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug, 2138 tc358743_delayed_work_enable_hotplug); 2139 2140 #ifdef CONFIG_VIDEO_TC358743_CEC 2141 state->cec_adap = cec_allocate_adapter(&tc358743_cec_adap_ops, 2142 state, dev_name(&client->dev), 2143 CEC_CAP_DEFAULTS | CEC_CAP_MONITOR_ALL, CEC_MAX_LOG_ADDRS); 2144 if (IS_ERR(state->cec_adap)) { 2145 err = PTR_ERR(state->cec_adap); 2146 goto err_hdl; 2147 } 2148 irq_mask |= MASK_CEC_RMSK | MASK_CEC_TMSK; 2149 #endif 2150 2151 tc358743_initial_setup(sd); 2152 2153 tc358743_s_dv_timings(sd, 0, &default_timing); 2154 2155 tc358743_set_csi_color_space(sd); 2156 2157 tc358743_init_interrupts(sd); 2158 2159 if (state->i2c_client->irq) { 2160 err = devm_request_threaded_irq(&client->dev, 2161 state->i2c_client->irq, 2162 NULL, tc358743_irq_handler, 2163 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 2164 "tc358743", state); 2165 if (err) 2166 goto err_work_queues; 2167 } else { 2168 INIT_WORK(&state->work_i2c_poll, 2169 tc358743_work_i2c_poll); 2170 timer_setup(&state->timer, tc358743_irq_poll_timer, 0); 2171 state->timer.expires = jiffies + 2172 msecs_to_jiffies(POLL_INTERVAL_MS); 2173 add_timer(&state->timer); 2174 } 2175 2176 err = cec_register_adapter(state->cec_adap, &client->dev); 2177 if (err < 0) { 2178 pr_err("%s: failed to register the cec device\n", __func__); 2179 cec_delete_adapter(state->cec_adap); 2180 state->cec_adap = NULL; 2181 goto err_work_queues; 2182 } 2183 2184 tc358743_enable_interrupts(sd, tx_5v_power_present(sd)); 2185 i2c_wr16(sd, INTMASK, ~irq_mask); 2186 2187 err = v4l2_ctrl_handler_setup(sd->ctrl_handler); 2188 if (err) 2189 goto err_work_queues; 2190 2191 err = v4l2_async_register_subdev(sd); 2192 if (err < 0) 2193 goto err_work_queues; 2194 2195 state->debugfs_dir = debugfs_create_dir(sd->name, v4l2_debugfs_root()); 2196 state->infoframes = v4l2_debugfs_if_alloc(state->debugfs_dir, 2197 V4L2_DEBUGFS_IF_AVI, sd, 2198 tc358743_debugfs_if_read); 2199 2200 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name, 2201 client->addr << 1, client->adapter->name); 2202 2203 return 0; 2204 2205 err_work_queues: 2206 cec_unregister_adapter(state->cec_adap); 2207 if (!state->i2c_client->irq) { 2208 timer_delete(&state->timer); 2209 flush_work(&state->work_i2c_poll); 2210 } 2211 cancel_delayed_work(&state->delayed_work_enable_hotplug); 2212 mutex_destroy(&state->confctl_mutex); 2213 err_hdl: 2214 media_entity_cleanup(&sd->entity); 2215 v4l2_ctrl_handler_free(&state->hdl); 2216 return err; 2217 } 2218 2219 static void tc358743_remove(struct i2c_client *client) 2220 { 2221 struct v4l2_subdev *sd = i2c_get_clientdata(client); 2222 struct tc358743_state *state = to_state(sd); 2223 2224 if (!state->i2c_client->irq) { 2225 timer_delete_sync(&state->timer); 2226 flush_work(&state->work_i2c_poll); 2227 } 2228 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug); 2229 v4l2_debugfs_if_free(state->infoframes); 2230 debugfs_remove_recursive(state->debugfs_dir); 2231 cec_unregister_adapter(state->cec_adap); 2232 v4l2_async_unregister_subdev(sd); 2233 v4l2_device_unregister_subdev(sd); 2234 mutex_destroy(&state->confctl_mutex); 2235 media_entity_cleanup(&sd->entity); 2236 v4l2_ctrl_handler_free(&state->hdl); 2237 } 2238 2239 static const struct i2c_device_id tc358743_id[] = { 2240 { "tc358743" }, 2241 {} 2242 }; 2243 2244 MODULE_DEVICE_TABLE(i2c, tc358743_id); 2245 2246 #if IS_ENABLED(CONFIG_OF) 2247 static const struct of_device_id tc358743_of_match[] = { 2248 { .compatible = "toshiba,tc358743" }, 2249 {}, 2250 }; 2251 MODULE_DEVICE_TABLE(of, tc358743_of_match); 2252 #endif 2253 2254 static struct i2c_driver tc358743_driver = { 2255 .driver = { 2256 .name = "tc358743", 2257 .of_match_table = of_match_ptr(tc358743_of_match), 2258 }, 2259 .probe = tc358743_probe, 2260 .remove = tc358743_remove, 2261 .id_table = tc358743_id, 2262 }; 2263 2264 module_i2c_driver(tc358743_driver); 2265