1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * tc358743 - Toshiba HDMI to CSI-2 bridge 4 * 5 * Copyright 2015 Cisco Systems, Inc. and/or its affiliates. All rights 6 * reserved. 7 */ 8 9 /* 10 * References (c = chapter, p = page): 11 * REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60 12 * REF_02 - Toshiba, TC358743XBG_HDMI-CSI_Tv11p_nm.xls 13 */ 14 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/slab.h> 18 #include <linux/i2c.h> 19 #include <linux/clk.h> 20 #include <linux/delay.h> 21 #include <linux/gpio/consumer.h> 22 #include <linux/interrupt.h> 23 #include <linux/timer.h> 24 #include <linux/of_graph.h> 25 #include <linux/videodev2.h> 26 #include <linux/workqueue.h> 27 #include <linux/v4l2-dv-timings.h> 28 #include <linux/hdmi.h> 29 #include <media/cec.h> 30 #include <media/v4l2-dv-timings.h> 31 #include <media/v4l2-device.h> 32 #include <media/v4l2-ctrls.h> 33 #include <media/v4l2-event.h> 34 #include <media/v4l2-fwnode.h> 35 #include <media/i2c/tc358743.h> 36 37 #include "tc358743_regs.h" 38 39 static int debug; 40 module_param(debug, int, 0644); 41 MODULE_PARM_DESC(debug, "debug level (0-3)"); 42 43 MODULE_DESCRIPTION("Toshiba TC358743 HDMI to CSI-2 bridge driver"); 44 MODULE_AUTHOR("Ramakrishnan Muthukrishnan <ram@rkrishnan.org>"); 45 MODULE_AUTHOR("Mikhail Khelik <mkhelik@cisco.com>"); 46 MODULE_AUTHOR("Mats Randgaard <matrandg@cisco.com>"); 47 MODULE_LICENSE("GPL"); 48 49 #define EDID_NUM_BLOCKS_MAX 8 50 #define EDID_BLOCK_SIZE 128 51 52 #define I2C_MAX_XFER_SIZE (EDID_BLOCK_SIZE + 2) 53 54 #define POLL_INTERVAL_CEC_MS 10 55 #define POLL_INTERVAL_MS 1000 56 57 static const struct v4l2_dv_timings_cap tc358743_timings_cap = { 58 .type = V4L2_DV_BT_656_1120, 59 /* keep this initialization for compatibility with GCC < 4.4.6 */ 60 .reserved = { 0 }, 61 /* Pixel clock from REF_01 p. 20. Min/max height/width are unknown */ 62 V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 13000000, 165000000, 63 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | 64 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT, 65 V4L2_DV_BT_CAP_PROGRESSIVE | 66 V4L2_DV_BT_CAP_REDUCED_BLANKING | 67 V4L2_DV_BT_CAP_CUSTOM) 68 }; 69 70 struct tc358743_state { 71 struct tc358743_platform_data pdata; 72 struct v4l2_mbus_config_mipi_csi2 bus; 73 struct v4l2_subdev sd; 74 struct media_pad pad; 75 struct v4l2_ctrl_handler hdl; 76 struct i2c_client *i2c_client; 77 /* CONFCTL is modified in ops and tc358743_hdmi_sys_int_handler */ 78 struct mutex confctl_mutex; 79 80 /* controls */ 81 struct v4l2_ctrl *detect_tx_5v_ctrl; 82 struct v4l2_ctrl *audio_sampling_rate_ctrl; 83 struct v4l2_ctrl *audio_present_ctrl; 84 85 struct delayed_work delayed_work_enable_hotplug; 86 87 struct timer_list timer; 88 struct work_struct work_i2c_poll; 89 90 /* debugfs */ 91 struct dentry *debugfs_dir; 92 struct v4l2_debugfs_if *infoframes; 93 94 /* edid */ 95 u8 edid_blocks_written; 96 97 struct v4l2_dv_timings timings; 98 u32 mbus_fmt_code; 99 u8 csi_lanes_in_use; 100 101 struct gpio_desc *reset_gpio; 102 103 struct cec_adapter *cec_adap; 104 }; 105 106 static void tc358743_enable_interrupts(struct v4l2_subdev *sd, 107 bool cable_connected); 108 static int tc358743_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd); 109 110 static inline struct tc358743_state *to_state(struct v4l2_subdev *sd) 111 { 112 return container_of(sd, struct tc358743_state, sd); 113 } 114 115 /* --------------- I2C --------------- */ 116 117 static int i2c_rd(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n) 118 { 119 struct tc358743_state *state = to_state(sd); 120 struct i2c_client *client = state->i2c_client; 121 int err; 122 u8 buf[2] = { reg >> 8, reg & 0xff }; 123 struct i2c_msg msgs[] = { 124 { 125 .addr = client->addr, 126 .flags = 0, 127 .len = 2, 128 .buf = buf, 129 }, 130 { 131 .addr = client->addr, 132 .flags = I2C_M_RD, 133 .len = n, 134 .buf = values, 135 }, 136 }; 137 138 err = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); 139 if (err != ARRAY_SIZE(msgs)) { 140 v4l2_err(sd, "%s: reading register 0x%x from 0x%x failed: %d\n", 141 __func__, reg, client->addr, err); 142 } 143 return err != ARRAY_SIZE(msgs); 144 } 145 146 static void i2c_wr(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n) 147 { 148 struct tc358743_state *state = to_state(sd); 149 struct i2c_client *client = state->i2c_client; 150 int err, i; 151 struct i2c_msg msg; 152 u8 data[I2C_MAX_XFER_SIZE]; 153 154 if ((2 + n) > I2C_MAX_XFER_SIZE) { 155 n = I2C_MAX_XFER_SIZE - 2; 156 v4l2_warn(sd, "i2c wr reg=%04x: len=%d is too big!\n", 157 reg, 2 + n); 158 } 159 160 msg.addr = client->addr; 161 msg.buf = data; 162 msg.len = 2 + n; 163 msg.flags = 0; 164 165 data[0] = reg >> 8; 166 data[1] = reg & 0xff; 167 168 for (i = 0; i < n; i++) 169 data[2 + i] = values[i]; 170 171 err = i2c_transfer(client->adapter, &msg, 1); 172 if (err != 1) { 173 v4l2_err(sd, "%s: writing register 0x%x from 0x%x failed: %d\n", 174 __func__, reg, client->addr, err); 175 return; 176 } 177 178 if (debug < 3) 179 return; 180 181 switch (n) { 182 case 1: 183 v4l2_info(sd, "I2C write 0x%04x = 0x%02x", 184 reg, data[2]); 185 break; 186 case 2: 187 v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x", 188 reg, data[3], data[2]); 189 break; 190 case 4: 191 v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x%02x%02x", 192 reg, data[5], data[4], data[3], data[2]); 193 break; 194 default: 195 v4l2_info(sd, "I2C write %d bytes from address 0x%04x\n", 196 n, reg); 197 } 198 } 199 200 static noinline u32 i2c_rdreg_err(struct v4l2_subdev *sd, u16 reg, u32 n, 201 int *err) 202 { 203 int error; 204 __le32 val = 0; 205 206 error = i2c_rd(sd, reg, (u8 __force *)&val, n); 207 if (err) 208 *err = error; 209 210 return le32_to_cpu(val); 211 } 212 213 static inline u32 i2c_rdreg(struct v4l2_subdev *sd, u16 reg, u32 n) 214 { 215 return i2c_rdreg_err(sd, reg, n, NULL); 216 } 217 218 static noinline void i2c_wrreg(struct v4l2_subdev *sd, u16 reg, u32 val, u32 n) 219 { 220 __le32 raw = cpu_to_le32(val); 221 222 i2c_wr(sd, reg, (u8 __force *)&raw, n); 223 } 224 225 static u8 i2c_rd8(struct v4l2_subdev *sd, u16 reg) 226 { 227 return i2c_rdreg(sd, reg, 1); 228 } 229 230 static void i2c_wr8(struct v4l2_subdev *sd, u16 reg, u8 val) 231 { 232 i2c_wrreg(sd, reg, val, 1); 233 } 234 235 static void i2c_wr8_and_or(struct v4l2_subdev *sd, u16 reg, 236 u8 mask, u8 val) 237 { 238 i2c_wrreg(sd, reg, (i2c_rdreg(sd, reg, 1) & mask) | val, 1); 239 } 240 241 static u16 i2c_rd16(struct v4l2_subdev *sd, u16 reg) 242 { 243 return i2c_rdreg(sd, reg, 2); 244 } 245 246 static int i2c_rd16_err(struct v4l2_subdev *sd, u16 reg, u16 *value) 247 { 248 int err; 249 *value = i2c_rdreg_err(sd, reg, 2, &err); 250 return err; 251 } 252 253 static void i2c_wr16(struct v4l2_subdev *sd, u16 reg, u16 val) 254 { 255 i2c_wrreg(sd, reg, val, 2); 256 } 257 258 static void i2c_wr16_and_or(struct v4l2_subdev *sd, u16 reg, u16 mask, u16 val) 259 { 260 i2c_wrreg(sd, reg, (i2c_rdreg(sd, reg, 2) & mask) | val, 2); 261 } 262 263 static u32 i2c_rd32(struct v4l2_subdev *sd, u16 reg) 264 { 265 return i2c_rdreg(sd, reg, 4); 266 } 267 268 static void i2c_wr32(struct v4l2_subdev *sd, u16 reg, u32 val) 269 { 270 i2c_wrreg(sd, reg, val, 4); 271 } 272 273 /* --------------- STATUS --------------- */ 274 275 static inline bool is_hdmi(struct v4l2_subdev *sd) 276 { 277 return i2c_rd8(sd, SYS_STATUS) & MASK_S_HDMI; 278 } 279 280 static inline bool tx_5v_power_present(struct v4l2_subdev *sd) 281 { 282 return i2c_rd8(sd, SYS_STATUS) & MASK_S_DDC5V; 283 } 284 285 static inline bool no_signal(struct v4l2_subdev *sd) 286 { 287 return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_TMDS); 288 } 289 290 static inline bool no_sync(struct v4l2_subdev *sd) 291 { 292 return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_SYNC); 293 } 294 295 static inline bool audio_present(struct v4l2_subdev *sd) 296 { 297 return i2c_rd8(sd, AU_STATUS0) & MASK_S_A_SAMPLE; 298 } 299 300 static int get_audio_sampling_rate(struct v4l2_subdev *sd) 301 { 302 static const int code_to_rate[] = { 303 44100, 0, 48000, 32000, 22050, 384000, 24000, 352800, 304 88200, 768000, 96000, 705600, 176400, 0, 192000, 0 305 }; 306 307 /* Register FS_SET is not cleared when the cable is disconnected */ 308 if (no_signal(sd)) 309 return 0; 310 311 return code_to_rate[i2c_rd8(sd, FS_SET) & MASK_FS]; 312 } 313 314 /* --------------- TIMINGS --------------- */ 315 316 static inline unsigned fps(const struct v4l2_bt_timings *t) 317 { 318 if (!V4L2_DV_BT_FRAME_HEIGHT(t) || !V4L2_DV_BT_FRAME_WIDTH(t)) 319 return 0; 320 321 return DIV_ROUND_CLOSEST((unsigned)t->pixelclock, 322 V4L2_DV_BT_FRAME_HEIGHT(t) * V4L2_DV_BT_FRAME_WIDTH(t)); 323 } 324 325 static int tc358743_get_detected_timings(struct v4l2_subdev *sd, 326 struct v4l2_dv_timings *timings) 327 { 328 struct v4l2_bt_timings *bt = &timings->bt; 329 unsigned width, height, frame_width, frame_height, frame_interval, fps; 330 331 memset(timings, 0, sizeof(struct v4l2_dv_timings)); 332 333 /* if HPD is low, ignore any video */ 334 if (!(i2c_rd8(sd, HPD_CTL) & MASK_HPD_OUT0)) 335 return -ENOLINK; 336 337 if (no_signal(sd)) { 338 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__); 339 return -ENOLINK; 340 } 341 if (no_sync(sd)) { 342 v4l2_dbg(1, debug, sd, "%s: no sync on signal\n", __func__); 343 return -ENOLCK; 344 } 345 346 timings->type = V4L2_DV_BT_656_1120; 347 bt->interlaced = i2c_rd8(sd, VI_STATUS1) & MASK_S_V_INTERLACE ? 348 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE; 349 350 width = ((i2c_rd8(sd, DE_WIDTH_H_HI) & 0x1f) << 8) + 351 i2c_rd8(sd, DE_WIDTH_H_LO); 352 height = ((i2c_rd8(sd, DE_WIDTH_V_HI) & 0x1f) << 8) + 353 i2c_rd8(sd, DE_WIDTH_V_LO); 354 frame_width = ((i2c_rd8(sd, H_SIZE_HI) & 0x1f) << 8) + 355 i2c_rd8(sd, H_SIZE_LO); 356 frame_height = (((i2c_rd8(sd, V_SIZE_HI) & 0x3f) << 8) + 357 i2c_rd8(sd, V_SIZE_LO)) / 2; 358 /* frame interval in milliseconds * 10 359 * Require SYS_FREQ0 and SYS_FREQ1 are precisely set */ 360 frame_interval = ((i2c_rd8(sd, FV_CNT_HI) & 0x3) << 8) + 361 i2c_rd8(sd, FV_CNT_LO); 362 fps = (frame_interval > 0) ? 363 DIV_ROUND_CLOSEST(10000, frame_interval) : 0; 364 365 bt->width = width; 366 bt->height = height; 367 bt->vsync = frame_height - height; 368 bt->hsync = frame_width - width; 369 bt->pixelclock = frame_width * frame_height * fps; 370 if (bt->interlaced == V4L2_DV_INTERLACED) { 371 bt->height *= 2; 372 bt->il_vsync = bt->vsync + 1; 373 bt->pixelclock /= 2; 374 } 375 376 return 0; 377 } 378 379 /* --------------- HOTPLUG / HDCP / EDID --------------- */ 380 381 static void tc358743_delayed_work_enable_hotplug(struct work_struct *work) 382 { 383 struct delayed_work *dwork = to_delayed_work(work); 384 struct tc358743_state *state = container_of(dwork, 385 struct tc358743_state, delayed_work_enable_hotplug); 386 struct v4l2_subdev *sd = &state->sd; 387 388 v4l2_dbg(2, debug, sd, "%s:\n", __func__); 389 390 i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, MASK_HPD_OUT0); 391 } 392 393 static void tc358743_set_hdmi_hdcp(struct v4l2_subdev *sd, bool enable) 394 { 395 v4l2_dbg(2, debug, sd, "%s: %s\n", __func__, enable ? 396 "enable" : "disable"); 397 398 if (enable) { 399 i2c_wr8_and_or(sd, HDCP_REG3, ~KEY_RD_CMD, KEY_RD_CMD); 400 401 i2c_wr8_and_or(sd, HDCP_MODE, ~MASK_MANUAL_AUTHENTICATION, 0); 402 403 i2c_wr8_and_or(sd, HDCP_REG1, 0xff, 404 MASK_AUTH_UNAUTH_SEL_16_FRAMES | 405 MASK_AUTH_UNAUTH_AUTO); 406 407 i2c_wr8_and_or(sd, HDCP_REG2, ~MASK_AUTO_P3_RESET, 408 SET_AUTO_P3_RESET_FRAMES(0x0f)); 409 } else { 410 i2c_wr8_and_or(sd, HDCP_MODE, ~MASK_MANUAL_AUTHENTICATION, 411 MASK_MANUAL_AUTHENTICATION); 412 } 413 } 414 415 static void tc358743_disable_edid(struct v4l2_subdev *sd) 416 { 417 struct tc358743_state *state = to_state(sd); 418 419 v4l2_dbg(2, debug, sd, "%s:\n", __func__); 420 421 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug); 422 423 /* DDC access to EDID is also disabled when hotplug is disabled. See 424 * register DDC_CTL */ 425 i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, 0x0); 426 } 427 428 static void tc358743_enable_edid(struct v4l2_subdev *sd) 429 { 430 struct tc358743_state *state = to_state(sd); 431 432 if (state->edid_blocks_written == 0) { 433 v4l2_dbg(2, debug, sd, "%s: no EDID -> no hotplug\n", __func__); 434 tc358743_s_ctrl_detect_tx_5v(sd); 435 return; 436 } 437 438 v4l2_dbg(2, debug, sd, "%s:\n", __func__); 439 440 /* Enable hotplug after 143 ms. DDC access to EDID is also enabled when 441 * hotplug is enabled. See register DDC_CTL */ 442 schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 7); 443 444 tc358743_enable_interrupts(sd, true); 445 tc358743_s_ctrl_detect_tx_5v(sd); 446 } 447 448 static void tc358743_erase_bksv(struct v4l2_subdev *sd) 449 { 450 int i; 451 452 for (i = 0; i < 5; i++) 453 i2c_wr8(sd, BKSV + i, 0); 454 } 455 456 /* --------------- AVI infoframe --------------- */ 457 458 static ssize_t 459 tc358743_debugfs_if_read(u32 type, void *priv, struct file *filp, 460 char __user *ubuf, size_t count, loff_t *ppos) 461 { 462 u8 buf[V4L2_DEBUGFS_IF_MAX_LEN] = {}; 463 struct v4l2_subdev *sd = priv; 464 int len; 465 466 if (!is_hdmi(sd)) 467 return 0; 468 469 if (type != V4L2_DEBUGFS_IF_AVI) 470 return 0; 471 472 i2c_rd(sd, PK_AVI_0HEAD, buf, PK_AVI_16BYTE - PK_AVI_0HEAD + 1); 473 len = buf[2] + 4; 474 if (len > V4L2_DEBUGFS_IF_MAX_LEN) 475 len = -ENOENT; 476 if (len > 0) 477 len = simple_read_from_buffer(ubuf, count, ppos, buf, len); 478 return len < 0 ? 0 : len; 479 } 480 481 static void print_avi_infoframe(struct v4l2_subdev *sd) 482 { 483 struct i2c_client *client = v4l2_get_subdevdata(sd); 484 struct device *dev = &client->dev; 485 union hdmi_infoframe frame; 486 u8 buffer[HDMI_INFOFRAME_SIZE(AVI)] = {}; 487 488 if (!is_hdmi(sd)) { 489 v4l2_info(sd, "DVI-D signal - AVI infoframe not supported\n"); 490 return; 491 } 492 493 i2c_rd(sd, PK_AVI_0HEAD, buffer, HDMI_INFOFRAME_SIZE(AVI)); 494 495 if (hdmi_infoframe_unpack(&frame, buffer, sizeof(buffer)) < 0) { 496 v4l2_err(sd, "%s: unpack of AVI infoframe failed\n", __func__); 497 return; 498 } 499 500 hdmi_infoframe_log(KERN_INFO, dev, &frame); 501 } 502 503 /* --------------- CTRLS --------------- */ 504 505 static int tc358743_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd) 506 { 507 struct tc358743_state *state = to_state(sd); 508 509 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, 510 tx_5v_power_present(sd)); 511 } 512 513 static int tc358743_s_ctrl_audio_sampling_rate(struct v4l2_subdev *sd) 514 { 515 struct tc358743_state *state = to_state(sd); 516 517 return v4l2_ctrl_s_ctrl(state->audio_sampling_rate_ctrl, 518 get_audio_sampling_rate(sd)); 519 } 520 521 static int tc358743_s_ctrl_audio_present(struct v4l2_subdev *sd) 522 { 523 struct tc358743_state *state = to_state(sd); 524 525 return v4l2_ctrl_s_ctrl(state->audio_present_ctrl, 526 audio_present(sd)); 527 } 528 529 static int tc358743_update_controls(struct v4l2_subdev *sd) 530 { 531 int ret = 0; 532 533 ret |= tc358743_s_ctrl_detect_tx_5v(sd); 534 ret |= tc358743_s_ctrl_audio_sampling_rate(sd); 535 ret |= tc358743_s_ctrl_audio_present(sd); 536 537 return ret; 538 } 539 540 /* --------------- INIT --------------- */ 541 542 static void tc358743_reset_phy(struct v4l2_subdev *sd) 543 { 544 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 545 546 i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, 0); 547 i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, MASK_RESET_CTRL); 548 } 549 550 static void tc358743_reset(struct v4l2_subdev *sd, uint16_t mask) 551 { 552 u16 sysctl = i2c_rd16(sd, SYSCTL); 553 554 i2c_wr16(sd, SYSCTL, sysctl | mask); 555 i2c_wr16(sd, SYSCTL, sysctl & ~mask); 556 } 557 558 static inline void tc358743_sleep_mode(struct v4l2_subdev *sd, bool enable) 559 { 560 i2c_wr16_and_or(sd, SYSCTL, ~MASK_SLEEP, 561 enable ? MASK_SLEEP : 0); 562 } 563 564 static inline void enable_stream(struct v4l2_subdev *sd, bool enable) 565 { 566 struct tc358743_state *state = to_state(sd); 567 568 v4l2_dbg(3, debug, sd, "%s: %sable\n", 569 __func__, enable ? "en" : "dis"); 570 571 if (enable) { 572 /* It is critical for CSI receiver to see lane transition 573 * LP11->HS. Set to non-continuous mode to enable clock lane 574 * LP11 state. */ 575 i2c_wr32(sd, TXOPTIONCNTRL, 0); 576 /* Set to continuous mode to trigger LP11->HS transition */ 577 i2c_wr32(sd, TXOPTIONCNTRL, MASK_CONTCLKMODE); 578 /* Unmute video */ 579 i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE); 580 } else { 581 /* Mute video so that all data lanes go to LSP11 state. 582 * No data is output to CSI Tx block. */ 583 i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE | MASK_VI_MUTE); 584 } 585 586 mutex_lock(&state->confctl_mutex); 587 i2c_wr16_and_or(sd, CONFCTL, ~(MASK_VBUFEN | MASK_ABUFEN), 588 enable ? (MASK_VBUFEN | MASK_ABUFEN) : 0x0); 589 mutex_unlock(&state->confctl_mutex); 590 } 591 592 static void tc358743_set_pll(struct v4l2_subdev *sd) 593 { 594 struct tc358743_state *state = to_state(sd); 595 struct tc358743_platform_data *pdata = &state->pdata; 596 u16 pllctl0 = i2c_rd16(sd, PLLCTL0); 597 u16 pllctl1 = i2c_rd16(sd, PLLCTL1); 598 u16 pllctl0_new = SET_PLL_PRD(pdata->pll_prd) | 599 SET_PLL_FBD(pdata->pll_fbd); 600 u32 hsck = (pdata->refclk_hz / pdata->pll_prd) * pdata->pll_fbd; 601 602 v4l2_dbg(2, debug, sd, "%s:\n", __func__); 603 604 /* Only rewrite when needed (new value or disabled), since rewriting 605 * triggers another format change event. */ 606 if ((pllctl0 != pllctl0_new) || ((pllctl1 & MASK_PLL_EN) == 0)) { 607 u16 pll_frs; 608 609 if (hsck > 500000000) 610 pll_frs = 0x0; 611 else if (hsck > 250000000) 612 pll_frs = 0x1; 613 else if (hsck > 125000000) 614 pll_frs = 0x2; 615 else 616 pll_frs = 0x3; 617 618 v4l2_dbg(1, debug, sd, "%s: updating PLL clock\n", __func__); 619 tc358743_sleep_mode(sd, true); 620 i2c_wr16(sd, PLLCTL0, pllctl0_new); 621 i2c_wr16_and_or(sd, PLLCTL1, 622 ~(MASK_PLL_FRS | MASK_RESETB | MASK_PLL_EN), 623 (SET_PLL_FRS(pll_frs) | MASK_RESETB | 624 MASK_PLL_EN)); 625 udelay(10); /* REF_02, Sheet "Source HDMI" */ 626 i2c_wr16_and_or(sd, PLLCTL1, ~MASK_CKEN, MASK_CKEN); 627 tc358743_sleep_mode(sd, false); 628 } 629 } 630 631 static void tc358743_set_ref_clk(struct v4l2_subdev *sd) 632 { 633 struct tc358743_state *state = to_state(sd); 634 struct tc358743_platform_data *pdata = &state->pdata; 635 u32 sys_freq; 636 u32 lockdet_ref; 637 u32 cec_freq; 638 u16 fh_min; 639 u16 fh_max; 640 641 BUG_ON(!(pdata->refclk_hz == 26000000 || 642 pdata->refclk_hz == 27000000 || 643 pdata->refclk_hz == 42000000)); 644 645 sys_freq = pdata->refclk_hz / 10000; 646 i2c_wr8(sd, SYS_FREQ0, sys_freq & 0x00ff); 647 i2c_wr8(sd, SYS_FREQ1, (sys_freq & 0xff00) >> 8); 648 649 i2c_wr8_and_or(sd, PHY_CTL0, ~MASK_PHY_SYSCLK_IND, 650 (pdata->refclk_hz == 42000000) ? 651 MASK_PHY_SYSCLK_IND : 0x0); 652 653 fh_min = pdata->refclk_hz / 100000; 654 i2c_wr8(sd, FH_MIN0, fh_min & 0x00ff); 655 i2c_wr8(sd, FH_MIN1, (fh_min & 0xff00) >> 8); 656 657 fh_max = (fh_min * 66) / 10; 658 i2c_wr8(sd, FH_MAX0, fh_max & 0x00ff); 659 i2c_wr8(sd, FH_MAX1, (fh_max & 0xff00) >> 8); 660 661 lockdet_ref = pdata->refclk_hz / 100; 662 i2c_wr8(sd, LOCKDET_REF0, lockdet_ref & 0x0000ff); 663 i2c_wr8(sd, LOCKDET_REF1, (lockdet_ref & 0x00ff00) >> 8); 664 i2c_wr8(sd, LOCKDET_REF2, (lockdet_ref & 0x0f0000) >> 16); 665 666 i2c_wr8_and_or(sd, NCO_F0_MOD, ~MASK_NCO_F0_MOD, 667 (pdata->refclk_hz == 27000000) ? 668 MASK_NCO_F0_MOD_27MHZ : 0x0); 669 670 /* 671 * Trial and error suggests that the default register value 672 * of 656 is for a 42 MHz reference clock. Use that to derive 673 * a new value based on the actual reference clock. 674 */ 675 cec_freq = (656 * sys_freq) / 4200; 676 i2c_wr16(sd, CECHCLK, cec_freq); 677 i2c_wr16(sd, CECLCLK, cec_freq); 678 } 679 680 static void tc358743_set_csi_color_space(struct v4l2_subdev *sd) 681 { 682 struct tc358743_state *state = to_state(sd); 683 684 switch (state->mbus_fmt_code) { 685 case MEDIA_BUS_FMT_UYVY8_1X16: 686 v4l2_dbg(2, debug, sd, "%s: YCbCr 422 16-bit\n", __func__); 687 i2c_wr8_and_or(sd, VOUT_SET2, 688 ~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff, 689 MASK_SEL422 | MASK_VOUT_422FIL_100); 690 i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff, 691 MASK_VOUT_COLOR_601_YCBCR_LIMITED); 692 mutex_lock(&state->confctl_mutex); 693 i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT, 694 MASK_YCBCRFMT_422_8_BIT); 695 mutex_unlock(&state->confctl_mutex); 696 break; 697 case MEDIA_BUS_FMT_RGB888_1X24: 698 v4l2_dbg(2, debug, sd, "%s: RGB 888 24-bit\n", __func__); 699 i2c_wr8_and_or(sd, VOUT_SET2, 700 ~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff, 701 0x00); 702 i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff, 703 MASK_VOUT_COLOR_RGB_FULL); 704 mutex_lock(&state->confctl_mutex); 705 i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT, 0); 706 mutex_unlock(&state->confctl_mutex); 707 break; 708 default: 709 v4l2_dbg(2, debug, sd, "%s: Unsupported format code 0x%x\n", 710 __func__, state->mbus_fmt_code); 711 } 712 } 713 714 static unsigned tc358743_num_csi_lanes_needed(struct v4l2_subdev *sd) 715 { 716 struct tc358743_state *state = to_state(sd); 717 struct v4l2_bt_timings *bt = &state->timings.bt; 718 struct tc358743_platform_data *pdata = &state->pdata; 719 u32 bits_pr_pixel = 720 (state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16) ? 16 : 24; 721 u32 bps = bt->width * bt->height * fps(bt) * bits_pr_pixel; 722 u32 bps_pr_lane = (pdata->refclk_hz / pdata->pll_prd) * pdata->pll_fbd; 723 724 return DIV_ROUND_UP(bps, bps_pr_lane); 725 } 726 727 static void tc358743_set_csi(struct v4l2_subdev *sd) 728 { 729 struct tc358743_state *state = to_state(sd); 730 struct tc358743_platform_data *pdata = &state->pdata; 731 unsigned lanes = tc358743_num_csi_lanes_needed(sd); 732 733 v4l2_dbg(3, debug, sd, "%s:\n", __func__); 734 735 state->csi_lanes_in_use = lanes; 736 737 tc358743_reset(sd, MASK_CTXRST); 738 739 if (lanes < 1) 740 i2c_wr32(sd, CLW_CNTRL, MASK_CLW_LANEDISABLE); 741 if (lanes < 1) 742 i2c_wr32(sd, D0W_CNTRL, MASK_D0W_LANEDISABLE); 743 if (lanes < 2) 744 i2c_wr32(sd, D1W_CNTRL, MASK_D1W_LANEDISABLE); 745 if (lanes < 3) 746 i2c_wr32(sd, D2W_CNTRL, MASK_D2W_LANEDISABLE); 747 if (lanes < 4) 748 i2c_wr32(sd, D3W_CNTRL, MASK_D3W_LANEDISABLE); 749 750 i2c_wr32(sd, LINEINITCNT, pdata->lineinitcnt); 751 i2c_wr32(sd, LPTXTIMECNT, pdata->lptxtimecnt); 752 i2c_wr32(sd, TCLK_HEADERCNT, pdata->tclk_headercnt); 753 i2c_wr32(sd, TCLK_TRAILCNT, pdata->tclk_trailcnt); 754 i2c_wr32(sd, THS_HEADERCNT, pdata->ths_headercnt); 755 i2c_wr32(sd, TWAKEUP, pdata->twakeup); 756 i2c_wr32(sd, TCLK_POSTCNT, pdata->tclk_postcnt); 757 i2c_wr32(sd, THS_TRAILCNT, pdata->ths_trailcnt); 758 i2c_wr32(sd, HSTXVREGCNT, pdata->hstxvregcnt); 759 760 i2c_wr32(sd, HSTXVREGEN, 761 ((lanes > 0) ? MASK_CLM_HSTXVREGEN : 0x0) | 762 ((lanes > 0) ? MASK_D0M_HSTXVREGEN : 0x0) | 763 ((lanes > 1) ? MASK_D1M_HSTXVREGEN : 0x0) | 764 ((lanes > 2) ? MASK_D2M_HSTXVREGEN : 0x0) | 765 ((lanes > 3) ? MASK_D3M_HSTXVREGEN : 0x0)); 766 767 i2c_wr32(sd, TXOPTIONCNTRL, (state->bus.flags & 768 V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK) ? 0 : MASK_CONTCLKMODE); 769 i2c_wr32(sd, STARTCNTRL, MASK_START); 770 i2c_wr32(sd, CSI_START, MASK_STRT); 771 772 i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET | 773 MASK_ADDRESS_CSI_CONTROL | 774 MASK_CSI_MODE | 775 MASK_TXHSMD | 776 ((lanes == 4) ? MASK_NOL_4 : 777 (lanes == 3) ? MASK_NOL_3 : 778 (lanes == 2) ? MASK_NOL_2 : MASK_NOL_1)); 779 780 i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET | 781 MASK_ADDRESS_CSI_ERR_INTENA | MASK_TXBRK | MASK_QUNK | 782 MASK_WCER | MASK_INER); 783 784 i2c_wr32(sd, CSI_CONFW, MASK_MODE_CLEAR | 785 MASK_ADDRESS_CSI_ERR_HALT | MASK_TXBRK | MASK_QUNK); 786 787 i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET | 788 MASK_ADDRESS_CSI_INT_ENA | MASK_INTER); 789 } 790 791 static void tc358743_set_hdmi_phy(struct v4l2_subdev *sd) 792 { 793 struct tc358743_state *state = to_state(sd); 794 struct tc358743_platform_data *pdata = &state->pdata; 795 796 /* Default settings from REF_02, sheet "Source HDMI" 797 * and custom settings as platform data */ 798 i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, 0x0); 799 i2c_wr8(sd, PHY_CTL1, SET_PHY_AUTO_RST1_US(1600) | 800 SET_FREQ_RANGE_MODE_CYCLES(1)); 801 i2c_wr8_and_or(sd, PHY_CTL2, ~MASK_PHY_AUTO_RSTn, 802 (pdata->hdmi_phy_auto_reset_tmds_detected ? 803 MASK_PHY_AUTO_RST2 : 0) | 804 (pdata->hdmi_phy_auto_reset_tmds_in_range ? 805 MASK_PHY_AUTO_RST3 : 0) | 806 (pdata->hdmi_phy_auto_reset_tmds_valid ? 807 MASK_PHY_AUTO_RST4 : 0)); 808 i2c_wr8(sd, PHY_BIAS, 0x40); 809 i2c_wr8(sd, PHY_CSQ, SET_CSQ_CNT_LEVEL(0x0a)); 810 i2c_wr8(sd, AVM_CTL, 45); 811 i2c_wr8_and_or(sd, HDMI_DET, ~MASK_HDMI_DET_V, 812 pdata->hdmi_detection_delay << 4); 813 i2c_wr8_and_or(sd, HV_RST, ~(MASK_H_PI_RST | MASK_V_PI_RST), 814 (pdata->hdmi_phy_auto_reset_hsync_out_of_range ? 815 MASK_H_PI_RST : 0) | 816 (pdata->hdmi_phy_auto_reset_vsync_out_of_range ? 817 MASK_V_PI_RST : 0)); 818 i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, MASK_ENABLE_PHY); 819 } 820 821 static void tc358743_set_hdmi_audio(struct v4l2_subdev *sd) 822 { 823 struct tc358743_state *state = to_state(sd); 824 825 /* Default settings from REF_02, sheet "Source HDMI" */ 826 i2c_wr8(sd, FORCE_MUTE, 0x00); 827 i2c_wr8(sd, AUTO_CMD0, MASK_AUTO_MUTE7 | MASK_AUTO_MUTE6 | 828 MASK_AUTO_MUTE5 | MASK_AUTO_MUTE4 | 829 MASK_AUTO_MUTE1 | MASK_AUTO_MUTE0); 830 i2c_wr8(sd, AUTO_CMD1, MASK_AUTO_MUTE9); 831 i2c_wr8(sd, AUTO_CMD2, MASK_AUTO_PLAY3 | MASK_AUTO_PLAY2); 832 i2c_wr8(sd, BUFINIT_START, SET_BUFINIT_START_MS(500)); 833 i2c_wr8(sd, FS_MUTE, 0x00); 834 i2c_wr8(sd, FS_IMODE, MASK_NLPCM_SMODE | MASK_FS_SMODE); 835 i2c_wr8(sd, ACR_MODE, MASK_CTS_MODE); 836 i2c_wr8(sd, ACR_MDF0, MASK_ACR_L2MDF_1976_PPM | MASK_ACR_L1MDF_976_PPM); 837 i2c_wr8(sd, ACR_MDF1, MASK_ACR_L3MDF_3906_PPM); 838 i2c_wr8(sd, SDO_MODE1, MASK_SDO_FMT_I2S); 839 i2c_wr8(sd, DIV_MODE, SET_DIV_DLY_MS(100)); 840 841 mutex_lock(&state->confctl_mutex); 842 i2c_wr16_and_or(sd, CONFCTL, 0xffff, MASK_AUDCHNUM_2 | 843 MASK_AUDOUTSEL_I2S | MASK_AUTOINDEX); 844 mutex_unlock(&state->confctl_mutex); 845 } 846 847 static void tc358743_set_hdmi_info_frame_mode(struct v4l2_subdev *sd) 848 { 849 /* Default settings from REF_02, sheet "Source HDMI" */ 850 i2c_wr8(sd, PK_INT_MODE, MASK_ISRC2_INT_MODE | MASK_ISRC_INT_MODE | 851 MASK_ACP_INT_MODE | MASK_VS_INT_MODE | 852 MASK_SPD_INT_MODE | MASK_MS_INT_MODE | 853 MASK_AUD_INT_MODE | MASK_AVI_INT_MODE); 854 i2c_wr8(sd, NO_PKT_LIMIT, 0x2c); 855 i2c_wr8(sd, NO_PKT_CLR, 0x53); 856 i2c_wr8(sd, ERR_PK_LIMIT, 0x01); 857 i2c_wr8(sd, NO_PKT_LIMIT2, 0x30); 858 i2c_wr8(sd, NO_GDB_LIMIT, 0x10); 859 } 860 861 static void tc358743_initial_setup(struct v4l2_subdev *sd) 862 { 863 struct tc358743_state *state = to_state(sd); 864 struct tc358743_platform_data *pdata = &state->pdata; 865 866 /* 867 * IR is not supported by this driver. 868 * CEC is only enabled if needed. 869 */ 870 i2c_wr16_and_or(sd, SYSCTL, ~(MASK_IRRST | MASK_CECRST), 871 (MASK_IRRST | MASK_CECRST)); 872 873 tc358743_reset(sd, MASK_CTXRST | MASK_HDMIRST); 874 #ifdef CONFIG_VIDEO_TC358743_CEC 875 tc358743_reset(sd, MASK_CECRST); 876 #endif 877 tc358743_sleep_mode(sd, false); 878 879 i2c_wr16(sd, FIFOCTL, pdata->fifo_level); 880 881 tc358743_set_ref_clk(sd); 882 883 i2c_wr8_and_or(sd, DDC_CTL, ~MASK_DDC5V_MODE, 884 pdata->ddc5v_delay & MASK_DDC5V_MODE); 885 i2c_wr8_and_or(sd, EDID_MODE, ~MASK_EDID_MODE, MASK_EDID_MODE_E_DDC); 886 887 tc358743_set_hdmi_phy(sd); 888 tc358743_set_hdmi_hdcp(sd, pdata->enable_hdcp); 889 tc358743_set_hdmi_audio(sd); 890 tc358743_set_hdmi_info_frame_mode(sd); 891 892 /* All CE and IT formats are detected as RGB full range in DVI mode */ 893 i2c_wr8_and_or(sd, VI_MODE, ~MASK_RGB_DVI, 0); 894 895 i2c_wr8_and_or(sd, VOUT_SET2, ~MASK_VOUTCOLORMODE, 896 MASK_VOUTCOLORMODE_AUTO); 897 i2c_wr8(sd, VOUT_SET3, MASK_VOUT_EXTCNT); 898 } 899 900 /* --------------- CEC --------------- */ 901 902 #ifdef CONFIG_VIDEO_TC358743_CEC 903 static int tc358743_cec_adap_enable(struct cec_adapter *adap, bool enable) 904 { 905 struct tc358743_state *state = adap->priv; 906 struct v4l2_subdev *sd = &state->sd; 907 908 i2c_wr32(sd, CECIMSK, enable ? MASK_CECTIM | MASK_CECRIM : 0); 909 i2c_wr32(sd, CECICLR, MASK_CECTICLR | MASK_CECRICLR); 910 i2c_wr32(sd, CECEN, enable); 911 if (enable) 912 i2c_wr32(sd, CECREN, MASK_CECREN); 913 return 0; 914 } 915 916 static int tc358743_cec_adap_monitor_all_enable(struct cec_adapter *adap, 917 bool enable) 918 { 919 struct tc358743_state *state = adap->priv; 920 struct v4l2_subdev *sd = &state->sd; 921 u32 reg; 922 923 reg = i2c_rd32(sd, CECRCTL1); 924 if (enable) 925 reg |= MASK_CECOTH; 926 else 927 reg &= ~MASK_CECOTH; 928 i2c_wr32(sd, CECRCTL1, reg); 929 return 0; 930 } 931 932 static int tc358743_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr) 933 { 934 struct tc358743_state *state = adap->priv; 935 struct v4l2_subdev *sd = &state->sd; 936 unsigned int la = 0; 937 938 if (log_addr != CEC_LOG_ADDR_INVALID) { 939 la = i2c_rd32(sd, CECADD); 940 la |= 1 << log_addr; 941 } 942 i2c_wr32(sd, CECADD, la); 943 return 0; 944 } 945 946 static int tc358743_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, 947 u32 signal_free_time, struct cec_msg *msg) 948 { 949 struct tc358743_state *state = adap->priv; 950 struct v4l2_subdev *sd = &state->sd; 951 unsigned int i; 952 953 i2c_wr32(sd, CECTCTL, 954 (cec_msg_is_broadcast(msg) ? MASK_CECBRD : 0) | 955 (signal_free_time - 1)); 956 for (i = 0; i < msg->len; i++) 957 i2c_wr32(sd, CECTBUF1 + i * 4, 958 msg->msg[i] | ((i == msg->len - 1) ? MASK_CECTEOM : 0)); 959 i2c_wr32(sd, CECTEN, MASK_CECTEN); 960 return 0; 961 } 962 963 static const struct cec_adap_ops tc358743_cec_adap_ops = { 964 .adap_enable = tc358743_cec_adap_enable, 965 .adap_log_addr = tc358743_cec_adap_log_addr, 966 .adap_transmit = tc358743_cec_adap_transmit, 967 .adap_monitor_all_enable = tc358743_cec_adap_monitor_all_enable, 968 }; 969 970 static void tc358743_cec_handler(struct v4l2_subdev *sd, u16 intstatus, 971 bool *handled) 972 { 973 struct tc358743_state *state = to_state(sd); 974 unsigned int cec_rxint, cec_txint; 975 unsigned int clr = 0; 976 977 cec_rxint = i2c_rd32(sd, CECRSTAT); 978 cec_txint = i2c_rd32(sd, CECTSTAT); 979 980 if (intstatus & MASK_CEC_RINT) 981 clr |= MASK_CECRICLR; 982 if (intstatus & MASK_CEC_TINT) 983 clr |= MASK_CECTICLR; 984 i2c_wr32(sd, CECICLR, clr); 985 986 if ((intstatus & MASK_CEC_TINT) && cec_txint) { 987 if (cec_txint & MASK_CECTIEND) 988 cec_transmit_attempt_done(state->cec_adap, 989 CEC_TX_STATUS_OK); 990 else if (cec_txint & MASK_CECTIAL) 991 cec_transmit_attempt_done(state->cec_adap, 992 CEC_TX_STATUS_ARB_LOST); 993 else if (cec_txint & MASK_CECTIACK) 994 cec_transmit_attempt_done(state->cec_adap, 995 CEC_TX_STATUS_NACK); 996 else if (cec_txint & MASK_CECTIUR) { 997 /* 998 * Not sure when this bit is set. Treat 999 * it as an error for now. 1000 */ 1001 cec_transmit_attempt_done(state->cec_adap, 1002 CEC_TX_STATUS_ERROR); 1003 } 1004 if (handled) 1005 *handled = true; 1006 } 1007 if ((intstatus & MASK_CEC_RINT) && 1008 (cec_rxint & MASK_CECRIEND)) { 1009 struct cec_msg msg = {}; 1010 unsigned int i; 1011 unsigned int v; 1012 1013 v = i2c_rd32(sd, CECRCTR); 1014 msg.len = v & 0x1f; 1015 if (msg.len > CEC_MAX_MSG_SIZE) 1016 msg.len = CEC_MAX_MSG_SIZE; 1017 for (i = 0; i < msg.len; i++) { 1018 v = i2c_rd32(sd, CECRBUF1 + i * 4); 1019 msg.msg[i] = v & 0xff; 1020 } 1021 cec_received_msg(state->cec_adap, &msg); 1022 if (handled) 1023 *handled = true; 1024 } 1025 i2c_wr16(sd, INTSTATUS, 1026 intstatus & (MASK_CEC_RINT | MASK_CEC_TINT)); 1027 } 1028 1029 #endif 1030 1031 /* --------------- IRQ --------------- */ 1032 1033 static void tc358743_format_change(struct v4l2_subdev *sd) 1034 { 1035 struct tc358743_state *state = to_state(sd); 1036 struct v4l2_dv_timings timings; 1037 const struct v4l2_event tc358743_ev_fmt = { 1038 .type = V4L2_EVENT_SOURCE_CHANGE, 1039 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION, 1040 }; 1041 1042 if (tc358743_get_detected_timings(sd, &timings)) { 1043 enable_stream(sd, false); 1044 1045 v4l2_dbg(1, debug, sd, "%s: No signal\n", 1046 __func__); 1047 } else { 1048 if (!v4l2_match_dv_timings(&state->timings, &timings, 0, false)) 1049 enable_stream(sd, false); 1050 1051 if (debug) 1052 v4l2_print_dv_timings(sd->name, 1053 "tc358743_format_change: New format: ", 1054 &timings, false); 1055 } 1056 1057 if (sd->devnode) 1058 v4l2_subdev_notify_event(sd, &tc358743_ev_fmt); 1059 } 1060 1061 static void tc358743_init_interrupts(struct v4l2_subdev *sd) 1062 { 1063 u16 i; 1064 1065 /* clear interrupt status registers */ 1066 for (i = SYS_INT; i <= KEY_INT; i++) 1067 i2c_wr8(sd, i, 0xff); 1068 1069 i2c_wr16(sd, INTSTATUS, 0xffff); 1070 } 1071 1072 static void tc358743_enable_interrupts(struct v4l2_subdev *sd, 1073 bool cable_connected) 1074 { 1075 v4l2_dbg(2, debug, sd, "%s: cable connected = %d\n", __func__, 1076 cable_connected); 1077 1078 if (cable_connected) { 1079 i2c_wr8(sd, SYS_INTM, ~(MASK_M_DDC | MASK_M_DVI_DET | 1080 MASK_M_HDMI_DET) & 0xff); 1081 i2c_wr8(sd, CLK_INTM, ~MASK_M_IN_DE_CHG); 1082 i2c_wr8(sd, CBIT_INTM, ~(MASK_M_CBIT_FS | MASK_M_AF_LOCK | 1083 MASK_M_AF_UNLOCK) & 0xff); 1084 i2c_wr8(sd, AUDIO_INTM, ~MASK_M_BUFINIT_END); 1085 i2c_wr8(sd, MISC_INTM, ~MASK_M_SYNC_CHG); 1086 } else { 1087 i2c_wr8(sd, SYS_INTM, ~MASK_M_DDC & 0xff); 1088 i2c_wr8(sd, CLK_INTM, 0xff); 1089 i2c_wr8(sd, CBIT_INTM, 0xff); 1090 i2c_wr8(sd, AUDIO_INTM, 0xff); 1091 i2c_wr8(sd, MISC_INTM, 0xff); 1092 } 1093 } 1094 1095 static void tc358743_hdmi_audio_int_handler(struct v4l2_subdev *sd, 1096 bool *handled) 1097 { 1098 u8 audio_int_mask = i2c_rd8(sd, AUDIO_INTM); 1099 u8 audio_int = i2c_rd8(sd, AUDIO_INT) & ~audio_int_mask; 1100 1101 i2c_wr8(sd, AUDIO_INT, audio_int); 1102 1103 v4l2_dbg(3, debug, sd, "%s: AUDIO_INT = 0x%02x\n", __func__, audio_int); 1104 1105 tc358743_s_ctrl_audio_sampling_rate(sd); 1106 tc358743_s_ctrl_audio_present(sd); 1107 } 1108 1109 static void tc358743_csi_err_int_handler(struct v4l2_subdev *sd, bool *handled) 1110 { 1111 v4l2_err(sd, "%s: CSI_ERR = 0x%x\n", __func__, i2c_rd32(sd, CSI_ERR)); 1112 1113 i2c_wr32(sd, CSI_INT_CLR, MASK_ICRER); 1114 } 1115 1116 static void tc358743_hdmi_misc_int_handler(struct v4l2_subdev *sd, 1117 bool *handled) 1118 { 1119 u8 misc_int_mask = i2c_rd8(sd, MISC_INTM); 1120 u8 misc_int = i2c_rd8(sd, MISC_INT) & ~misc_int_mask; 1121 1122 i2c_wr8(sd, MISC_INT, misc_int); 1123 1124 v4l2_dbg(3, debug, sd, "%s: MISC_INT = 0x%02x\n", __func__, misc_int); 1125 1126 if (misc_int & MASK_I_SYNC_CHG) { 1127 /* Reset the HDMI PHY to try to trigger proper lock on the 1128 * incoming video format. Erase BKSV to prevent that old keys 1129 * are used when a new source is connected. */ 1130 if (no_sync(sd) || no_signal(sd)) { 1131 tc358743_reset_phy(sd); 1132 tc358743_erase_bksv(sd); 1133 } 1134 1135 tc358743_format_change(sd); 1136 1137 misc_int &= ~MASK_I_SYNC_CHG; 1138 if (handled) 1139 *handled = true; 1140 } 1141 1142 if (misc_int) { 1143 v4l2_err(sd, "%s: Unhandled MISC_INT interrupts: 0x%02x\n", 1144 __func__, misc_int); 1145 } 1146 } 1147 1148 static void tc358743_hdmi_cbit_int_handler(struct v4l2_subdev *sd, 1149 bool *handled) 1150 { 1151 u8 cbit_int_mask = i2c_rd8(sd, CBIT_INTM); 1152 u8 cbit_int = i2c_rd8(sd, CBIT_INT) & ~cbit_int_mask; 1153 1154 i2c_wr8(sd, CBIT_INT, cbit_int); 1155 1156 v4l2_dbg(3, debug, sd, "%s: CBIT_INT = 0x%02x\n", __func__, cbit_int); 1157 1158 if (cbit_int & MASK_I_CBIT_FS) { 1159 1160 v4l2_dbg(1, debug, sd, "%s: Audio sample rate changed\n", 1161 __func__); 1162 tc358743_s_ctrl_audio_sampling_rate(sd); 1163 1164 cbit_int &= ~MASK_I_CBIT_FS; 1165 if (handled) 1166 *handled = true; 1167 } 1168 1169 if (cbit_int & (MASK_I_AF_LOCK | MASK_I_AF_UNLOCK)) { 1170 1171 v4l2_dbg(1, debug, sd, "%s: Audio present changed\n", 1172 __func__); 1173 tc358743_s_ctrl_audio_present(sd); 1174 1175 cbit_int &= ~(MASK_I_AF_LOCK | MASK_I_AF_UNLOCK); 1176 if (handled) 1177 *handled = true; 1178 } 1179 1180 if (cbit_int) { 1181 v4l2_err(sd, "%s: Unhandled CBIT_INT interrupts: 0x%02x\n", 1182 __func__, cbit_int); 1183 } 1184 } 1185 1186 static void tc358743_hdmi_clk_int_handler(struct v4l2_subdev *sd, bool *handled) 1187 { 1188 u8 clk_int_mask = i2c_rd8(sd, CLK_INTM); 1189 u8 clk_int = i2c_rd8(sd, CLK_INT) & ~clk_int_mask; 1190 1191 /* Bit 7 and bit 6 are set even when they are masked */ 1192 i2c_wr8(sd, CLK_INT, clk_int | 0x80 | MASK_I_OUT_H_CHG); 1193 1194 v4l2_dbg(3, debug, sd, "%s: CLK_INT = 0x%02x\n", __func__, clk_int); 1195 1196 if (clk_int & (MASK_I_IN_DE_CHG)) { 1197 1198 v4l2_dbg(1, debug, sd, "%s: DE size or position has changed\n", 1199 __func__); 1200 1201 /* If the source switch to a new resolution with the same pixel 1202 * frequency as the existing (e.g. 1080p25 -> 720p50), the 1203 * I_SYNC_CHG interrupt is not always triggered, while the 1204 * I_IN_DE_CHG interrupt seems to work fine. Format change 1205 * notifications are only sent when the signal is stable to 1206 * reduce the number of notifications. */ 1207 if (!no_signal(sd) && !no_sync(sd)) 1208 tc358743_format_change(sd); 1209 1210 clk_int &= ~(MASK_I_IN_DE_CHG); 1211 if (handled) 1212 *handled = true; 1213 } 1214 1215 if (clk_int) { 1216 v4l2_err(sd, "%s: Unhandled CLK_INT interrupts: 0x%02x\n", 1217 __func__, clk_int); 1218 } 1219 } 1220 1221 static void tc358743_hdmi_sys_int_handler(struct v4l2_subdev *sd, bool *handled) 1222 { 1223 struct tc358743_state *state = to_state(sd); 1224 u8 sys_int_mask = i2c_rd8(sd, SYS_INTM); 1225 u8 sys_int = i2c_rd8(sd, SYS_INT) & ~sys_int_mask; 1226 1227 i2c_wr8(sd, SYS_INT, sys_int); 1228 1229 v4l2_dbg(3, debug, sd, "%s: SYS_INT = 0x%02x\n", __func__, sys_int); 1230 1231 if (sys_int & MASK_I_DDC) { 1232 bool tx_5v = tx_5v_power_present(sd); 1233 1234 v4l2_dbg(1, debug, sd, "%s: Tx 5V power present: %s\n", 1235 __func__, tx_5v ? "yes" : "no"); 1236 1237 if (tx_5v) { 1238 tc358743_enable_edid(sd); 1239 } else { 1240 tc358743_enable_interrupts(sd, false); 1241 tc358743_disable_edid(sd); 1242 memset(&state->timings, 0, sizeof(state->timings)); 1243 tc358743_erase_bksv(sd); 1244 tc358743_update_controls(sd); 1245 } 1246 1247 sys_int &= ~MASK_I_DDC; 1248 if (handled) 1249 *handled = true; 1250 } 1251 1252 if (sys_int & MASK_I_DVI) { 1253 v4l2_dbg(1, debug, sd, "%s: HDMI->DVI change detected\n", 1254 __func__); 1255 1256 /* Reset the HDMI PHY to try to trigger proper lock on the 1257 * incoming video format. Erase BKSV to prevent that old keys 1258 * are used when a new source is connected. */ 1259 if (no_sync(sd) || no_signal(sd)) { 1260 tc358743_reset_phy(sd); 1261 tc358743_erase_bksv(sd); 1262 } 1263 1264 sys_int &= ~MASK_I_DVI; 1265 if (handled) 1266 *handled = true; 1267 } 1268 1269 if (sys_int & MASK_I_HDMI) { 1270 v4l2_dbg(1, debug, sd, "%s: DVI->HDMI change detected\n", 1271 __func__); 1272 1273 /* Register is reset in DVI mode (REF_01, c. 6.6.41) */ 1274 i2c_wr8(sd, ANA_CTL, MASK_APPL_PCSX_NORMAL | MASK_ANALOG_ON); 1275 1276 sys_int &= ~MASK_I_HDMI; 1277 if (handled) 1278 *handled = true; 1279 } 1280 1281 if (sys_int) { 1282 v4l2_err(sd, "%s: Unhandled SYS_INT interrupts: 0x%02x\n", 1283 __func__, sys_int); 1284 } 1285 } 1286 1287 /* --------------- CORE OPS --------------- */ 1288 1289 static int tc358743_log_status(struct v4l2_subdev *sd) 1290 { 1291 struct tc358743_state *state = to_state(sd); 1292 struct v4l2_dv_timings timings; 1293 uint8_t hdmi_sys_status = i2c_rd8(sd, SYS_STATUS); 1294 uint16_t sysctl = i2c_rd16(sd, SYSCTL); 1295 u8 vi_status3 = i2c_rd8(sd, VI_STATUS3); 1296 const int deep_color_mode[4] = { 8, 10, 12, 16 }; 1297 static const char * const input_color_space[] = { 1298 "RGB", "YCbCr 601", "opRGB", "YCbCr 709", "NA (4)", 1299 "xvYCC 601", "NA(6)", "xvYCC 709", "NA(8)", "sYCC601", 1300 "NA(10)", "NA(11)", "NA(12)", "opYCC 601"}; 1301 1302 v4l2_info(sd, "-----Chip status-----\n"); 1303 v4l2_info(sd, "Chip ID: 0x%02x\n", 1304 (i2c_rd16(sd, CHIPID) & MASK_CHIPID) >> 8); 1305 v4l2_info(sd, "Chip revision: 0x%02x\n", 1306 i2c_rd16(sd, CHIPID) & MASK_REVID); 1307 v4l2_info(sd, "Reset: IR: %d, CEC: %d, CSI TX: %d, HDMI: %d\n", 1308 !!(sysctl & MASK_IRRST), 1309 !!(sysctl & MASK_CECRST), 1310 !!(sysctl & MASK_CTXRST), 1311 !!(sysctl & MASK_HDMIRST)); 1312 v4l2_info(sd, "Sleep mode: %s\n", sysctl & MASK_SLEEP ? "on" : "off"); 1313 v4l2_info(sd, "Cable detected (+5V power): %s\n", 1314 hdmi_sys_status & MASK_S_DDC5V ? "yes" : "no"); 1315 v4l2_info(sd, "DDC lines enabled: %s\n", 1316 (i2c_rd8(sd, EDID_MODE) & MASK_EDID_MODE_E_DDC) ? 1317 "yes" : "no"); 1318 v4l2_info(sd, "Hotplug enabled: %s\n", 1319 (i2c_rd8(sd, HPD_CTL) & MASK_HPD_OUT0) ? 1320 "yes" : "no"); 1321 v4l2_info(sd, "CEC enabled: %s\n", 1322 (i2c_rd16(sd, CECEN) & MASK_CECEN) ? "yes" : "no"); 1323 v4l2_info(sd, "-----Signal status-----\n"); 1324 v4l2_info(sd, "TMDS signal detected: %s\n", 1325 hdmi_sys_status & MASK_S_TMDS ? "yes" : "no"); 1326 v4l2_info(sd, "Stable sync signal: %s\n", 1327 hdmi_sys_status & MASK_S_SYNC ? "yes" : "no"); 1328 v4l2_info(sd, "PHY PLL locked: %s\n", 1329 hdmi_sys_status & MASK_S_PHY_PLL ? "yes" : "no"); 1330 v4l2_info(sd, "PHY DE detected: %s\n", 1331 hdmi_sys_status & MASK_S_PHY_SCDT ? "yes" : "no"); 1332 1333 if (tc358743_get_detected_timings(sd, &timings)) { 1334 v4l2_info(sd, "No video detected\n"); 1335 } else { 1336 v4l2_print_dv_timings(sd->name, "Detected format: ", &timings, 1337 true); 1338 } 1339 v4l2_print_dv_timings(sd->name, "Configured format: ", &state->timings, 1340 true); 1341 1342 v4l2_info(sd, "-----CSI-TX status-----\n"); 1343 v4l2_info(sd, "Lanes needed: %d\n", 1344 tc358743_num_csi_lanes_needed(sd)); 1345 v4l2_info(sd, "Lanes in use: %d\n", 1346 state->csi_lanes_in_use); 1347 v4l2_info(sd, "Waiting for particular sync signal: %s\n", 1348 (i2c_rd16(sd, CSI_STATUS) & MASK_S_WSYNC) ? 1349 "yes" : "no"); 1350 v4l2_info(sd, "Transmit mode: %s\n", 1351 (i2c_rd16(sd, CSI_STATUS) & MASK_S_TXACT) ? 1352 "yes" : "no"); 1353 v4l2_info(sd, "Receive mode: %s\n", 1354 (i2c_rd16(sd, CSI_STATUS) & MASK_S_RXACT) ? 1355 "yes" : "no"); 1356 v4l2_info(sd, "Stopped: %s\n", 1357 (i2c_rd16(sd, CSI_STATUS) & MASK_S_HLT) ? 1358 "yes" : "no"); 1359 v4l2_info(sd, "Color space: %s\n", 1360 state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16 ? 1361 "YCbCr 422 16-bit" : 1362 state->mbus_fmt_code == MEDIA_BUS_FMT_RGB888_1X24 ? 1363 "RGB 888 24-bit" : "Unsupported"); 1364 1365 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D"); 1366 v4l2_info(sd, "HDCP encrypted content: %s\n", 1367 hdmi_sys_status & MASK_S_HDCP ? "yes" : "no"); 1368 v4l2_info(sd, "Input color space: %s %s range\n", 1369 input_color_space[(vi_status3 & MASK_S_V_COLOR) >> 1], 1370 (vi_status3 & MASK_LIMITED) ? "limited" : "full"); 1371 if (!is_hdmi(sd)) 1372 return 0; 1373 v4l2_info(sd, "AV Mute: %s\n", hdmi_sys_status & MASK_S_AVMUTE ? "on" : 1374 "off"); 1375 v4l2_info(sd, "Deep color mode: %d-bits per channel\n", 1376 deep_color_mode[(i2c_rd8(sd, VI_STATUS1) & 1377 MASK_S_DEEPCOLOR) >> 2]); 1378 print_avi_infoframe(sd); 1379 1380 return 0; 1381 } 1382 1383 #ifdef CONFIG_VIDEO_ADV_DEBUG 1384 static void tc358743_print_register_map(struct v4l2_subdev *sd) 1385 { 1386 v4l2_info(sd, "0x0000-0x00FF: Global Control Register\n"); 1387 v4l2_info(sd, "0x0100-0x01FF: CSI2-TX PHY Register\n"); 1388 v4l2_info(sd, "0x0200-0x03FF: CSI2-TX PPI Register\n"); 1389 v4l2_info(sd, "0x0400-0x05FF: Reserved\n"); 1390 v4l2_info(sd, "0x0600-0x06FF: CEC Register\n"); 1391 v4l2_info(sd, "0x0700-0x84FF: Reserved\n"); 1392 v4l2_info(sd, "0x8500-0x85FF: HDMIRX System Control Register\n"); 1393 v4l2_info(sd, "0x8600-0x86FF: HDMIRX Audio Control Register\n"); 1394 v4l2_info(sd, "0x8700-0x87FF: HDMIRX InfoFrame packet data Register\n"); 1395 v4l2_info(sd, "0x8800-0x88FF: HDMIRX HDCP Port Register\n"); 1396 v4l2_info(sd, "0x8900-0x89FF: HDMIRX Video Output Port & 3D Register\n"); 1397 v4l2_info(sd, "0x8A00-0x8BFF: Reserved\n"); 1398 v4l2_info(sd, "0x8C00-0x8FFF: HDMIRX EDID-RAM (1024bytes)\n"); 1399 v4l2_info(sd, "0x9000-0x90FF: HDMIRX GBD Extraction Control\n"); 1400 v4l2_info(sd, "0x9100-0x92FF: HDMIRX GBD RAM read\n"); 1401 v4l2_info(sd, "0x9300- : Reserved\n"); 1402 } 1403 1404 static int tc358743_get_reg_size(u16 address) 1405 { 1406 /* REF_01 p. 66-72 */ 1407 if (address <= 0x00ff) 1408 return 2; 1409 else if ((address >= 0x0100) && (address <= 0x06FF)) 1410 return 4; 1411 else if ((address >= 0x0700) && (address <= 0x84ff)) 1412 return 2; 1413 else 1414 return 1; 1415 } 1416 1417 static int tc358743_g_register(struct v4l2_subdev *sd, 1418 struct v4l2_dbg_register *reg) 1419 { 1420 if (reg->reg > 0xffff) { 1421 tc358743_print_register_map(sd); 1422 return -EINVAL; 1423 } 1424 1425 reg->size = tc358743_get_reg_size(reg->reg); 1426 1427 reg->val = i2c_rdreg(sd, reg->reg, reg->size); 1428 1429 return 0; 1430 } 1431 1432 static int tc358743_s_register(struct v4l2_subdev *sd, 1433 const struct v4l2_dbg_register *reg) 1434 { 1435 if (reg->reg > 0xffff) { 1436 tc358743_print_register_map(sd); 1437 return -EINVAL; 1438 } 1439 1440 /* It should not be possible for the user to enable HDCP with a simple 1441 * v4l2-dbg command. 1442 * 1443 * DO NOT REMOVE THIS unless all other issues with HDCP have been 1444 * resolved. 1445 */ 1446 if (reg->reg == HDCP_MODE || 1447 reg->reg == HDCP_REG1 || 1448 reg->reg == HDCP_REG2 || 1449 reg->reg == HDCP_REG3 || 1450 reg->reg == BCAPS) 1451 return 0; 1452 1453 i2c_wrreg(sd, (u16)reg->reg, reg->val, 1454 tc358743_get_reg_size(reg->reg)); 1455 1456 return 0; 1457 } 1458 #endif 1459 1460 static int tc358743_isr(struct v4l2_subdev *sd, u32 status, bool *handled) 1461 { 1462 u16 intstatus = i2c_rd16(sd, INTSTATUS); 1463 1464 v4l2_dbg(1, debug, sd, "%s: IntStatus = 0x%04x\n", __func__, intstatus); 1465 1466 if (intstatus & MASK_HDMI_INT) { 1467 u8 hdmi_int0 = i2c_rd8(sd, HDMI_INT0); 1468 u8 hdmi_int1 = i2c_rd8(sd, HDMI_INT1); 1469 1470 if (hdmi_int0 & MASK_I_MISC) 1471 tc358743_hdmi_misc_int_handler(sd, handled); 1472 if (hdmi_int1 & MASK_I_CBIT) 1473 tc358743_hdmi_cbit_int_handler(sd, handled); 1474 if (hdmi_int1 & MASK_I_CLK) 1475 tc358743_hdmi_clk_int_handler(sd, handled); 1476 if (hdmi_int1 & MASK_I_SYS) 1477 tc358743_hdmi_sys_int_handler(sd, handled); 1478 if (hdmi_int1 & MASK_I_AUD) 1479 tc358743_hdmi_audio_int_handler(sd, handled); 1480 1481 i2c_wr16(sd, INTSTATUS, MASK_HDMI_INT); 1482 intstatus &= ~MASK_HDMI_INT; 1483 } 1484 1485 #ifdef CONFIG_VIDEO_TC358743_CEC 1486 if (intstatus & (MASK_CEC_RINT | MASK_CEC_TINT)) { 1487 tc358743_cec_handler(sd, intstatus, handled); 1488 i2c_wr16(sd, INTSTATUS, 1489 intstatus & (MASK_CEC_RINT | MASK_CEC_TINT)); 1490 intstatus &= ~(MASK_CEC_RINT | MASK_CEC_TINT); 1491 } 1492 #endif 1493 1494 if (intstatus & MASK_CSI_INT) { 1495 u32 csi_int = i2c_rd32(sd, CSI_INT); 1496 1497 if (csi_int & MASK_INTER) 1498 tc358743_csi_err_int_handler(sd, handled); 1499 1500 i2c_wr16(sd, INTSTATUS, MASK_CSI_INT); 1501 } 1502 1503 intstatus = i2c_rd16(sd, INTSTATUS); 1504 if (intstatus) { 1505 v4l2_dbg(1, debug, sd, 1506 "%s: Unhandled IntStatus interrupts: 0x%02x\n", 1507 __func__, intstatus); 1508 } 1509 1510 return 0; 1511 } 1512 1513 static irqreturn_t tc358743_irq_handler(int irq, void *dev_id) 1514 { 1515 struct tc358743_state *state = dev_id; 1516 bool handled = false; 1517 1518 tc358743_isr(&state->sd, 0, &handled); 1519 1520 return handled ? IRQ_HANDLED : IRQ_NONE; 1521 } 1522 1523 static void tc358743_irq_poll_timer(struct timer_list *t) 1524 { 1525 struct tc358743_state *state = timer_container_of(state, t, timer); 1526 unsigned int msecs; 1527 1528 schedule_work(&state->work_i2c_poll); 1529 /* 1530 * If CEC is present, then we need to poll more frequently, 1531 * otherwise we will miss CEC messages. 1532 */ 1533 msecs = state->cec_adap ? POLL_INTERVAL_CEC_MS : POLL_INTERVAL_MS; 1534 mod_timer(&state->timer, jiffies + msecs_to_jiffies(msecs)); 1535 } 1536 1537 static void tc358743_work_i2c_poll(struct work_struct *work) 1538 { 1539 struct tc358743_state *state = container_of(work, 1540 struct tc358743_state, work_i2c_poll); 1541 bool handled; 1542 1543 tc358743_isr(&state->sd, 0, &handled); 1544 } 1545 1546 static int tc358743_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh, 1547 struct v4l2_event_subscription *sub) 1548 { 1549 switch (sub->type) { 1550 case V4L2_EVENT_SOURCE_CHANGE: 1551 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub); 1552 case V4L2_EVENT_CTRL: 1553 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub); 1554 default: 1555 return -EINVAL; 1556 } 1557 } 1558 1559 /* --------------- VIDEO OPS --------------- */ 1560 1561 static int tc358743_g_input_status(struct v4l2_subdev *sd, u32 *status) 1562 { 1563 *status = 0; 1564 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0; 1565 *status |= no_sync(sd) ? V4L2_IN_ST_NO_SYNC : 0; 1566 1567 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status); 1568 1569 return 0; 1570 } 1571 1572 static int tc358743_s_dv_timings(struct v4l2_subdev *sd, unsigned int pad, 1573 struct v4l2_dv_timings *timings) 1574 { 1575 struct tc358743_state *state = to_state(sd); 1576 1577 if (pad != 0) 1578 return -EINVAL; 1579 1580 if (!timings) 1581 return -EINVAL; 1582 1583 if (debug) 1584 v4l2_print_dv_timings(sd->name, "tc358743_s_dv_timings: ", 1585 timings, false); 1586 1587 if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) { 1588 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__); 1589 return 0; 1590 } 1591 1592 if (!v4l2_valid_dv_timings(timings, 1593 &tc358743_timings_cap, NULL, NULL)) { 1594 v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__); 1595 return -ERANGE; 1596 } 1597 1598 state->timings = *timings; 1599 1600 enable_stream(sd, false); 1601 tc358743_set_pll(sd); 1602 tc358743_set_csi(sd); 1603 1604 return 0; 1605 } 1606 1607 static int tc358743_g_dv_timings(struct v4l2_subdev *sd, unsigned int pad, 1608 struct v4l2_dv_timings *timings) 1609 { 1610 struct tc358743_state *state = to_state(sd); 1611 1612 if (pad != 0) 1613 return -EINVAL; 1614 1615 *timings = state->timings; 1616 1617 return 0; 1618 } 1619 1620 static int tc358743_enum_dv_timings(struct v4l2_subdev *sd, 1621 struct v4l2_enum_dv_timings *timings) 1622 { 1623 if (timings->pad != 0) 1624 return -EINVAL; 1625 1626 return v4l2_enum_dv_timings_cap(timings, 1627 &tc358743_timings_cap, NULL, NULL); 1628 } 1629 1630 static int tc358743_query_dv_timings(struct v4l2_subdev *sd, unsigned int pad, 1631 struct v4l2_dv_timings *timings) 1632 { 1633 int ret; 1634 1635 if (pad != 0) 1636 return -EINVAL; 1637 1638 ret = tc358743_get_detected_timings(sd, timings); 1639 if (ret) 1640 return ret; 1641 1642 if (debug) 1643 v4l2_print_dv_timings(sd->name, "tc358743_query_dv_timings: ", 1644 timings, false); 1645 1646 if (!v4l2_valid_dv_timings(timings, 1647 &tc358743_timings_cap, NULL, NULL)) { 1648 v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__); 1649 return -ERANGE; 1650 } 1651 1652 return 0; 1653 } 1654 1655 static int tc358743_dv_timings_cap(struct v4l2_subdev *sd, 1656 struct v4l2_dv_timings_cap *cap) 1657 { 1658 if (cap->pad != 0) 1659 return -EINVAL; 1660 1661 *cap = tc358743_timings_cap; 1662 1663 return 0; 1664 } 1665 1666 static int tc358743_get_mbus_config(struct v4l2_subdev *sd, 1667 unsigned int pad, 1668 struct v4l2_mbus_config *cfg) 1669 { 1670 struct tc358743_state *state = to_state(sd); 1671 1672 cfg->type = V4L2_MBUS_CSI2_DPHY; 1673 1674 /* Support for non-continuous CSI-2 clock is missing in the driver */ 1675 cfg->bus.mipi_csi2.flags = 0; 1676 cfg->bus.mipi_csi2.num_data_lanes = state->csi_lanes_in_use; 1677 1678 return 0; 1679 } 1680 1681 static int tc358743_s_stream(struct v4l2_subdev *sd, int enable) 1682 { 1683 enable_stream(sd, enable); 1684 if (!enable) { 1685 /* Put all lanes in LP-11 state (STOPSTATE) */ 1686 tc358743_set_csi(sd); 1687 } 1688 1689 return 0; 1690 } 1691 1692 /* --------------- PAD OPS --------------- */ 1693 1694 static int tc358743_enum_mbus_code(struct v4l2_subdev *sd, 1695 struct v4l2_subdev_state *sd_state, 1696 struct v4l2_subdev_mbus_code_enum *code) 1697 { 1698 switch (code->index) { 1699 case 0: 1700 code->code = MEDIA_BUS_FMT_RGB888_1X24; 1701 break; 1702 case 1: 1703 code->code = MEDIA_BUS_FMT_UYVY8_1X16; 1704 break; 1705 default: 1706 return -EINVAL; 1707 } 1708 return 0; 1709 } 1710 1711 static u32 tc358743_g_colorspace(u32 code) 1712 { 1713 switch (code) { 1714 case MEDIA_BUS_FMT_RGB888_1X24: 1715 return V4L2_COLORSPACE_SRGB; 1716 case MEDIA_BUS_FMT_UYVY8_1X16: 1717 return V4L2_COLORSPACE_SMPTE170M; 1718 default: 1719 return 0; 1720 } 1721 } 1722 1723 static int tc358743_get_fmt(struct v4l2_subdev *sd, 1724 struct v4l2_subdev_state *sd_state, 1725 struct v4l2_subdev_format *format) 1726 { 1727 struct tc358743_state *state = to_state(sd); 1728 1729 if (format->pad != 0) 1730 return -EINVAL; 1731 1732 format->format.code = state->mbus_fmt_code; 1733 format->format.width = state->timings.bt.width; 1734 format->format.height = state->timings.bt.height; 1735 format->format.field = V4L2_FIELD_NONE; 1736 1737 format->format.colorspace = tc358743_g_colorspace(format->format.code); 1738 1739 return 0; 1740 } 1741 1742 static int tc358743_set_fmt(struct v4l2_subdev *sd, 1743 struct v4l2_subdev_state *sd_state, 1744 struct v4l2_subdev_format *format) 1745 { 1746 struct tc358743_state *state = to_state(sd); 1747 1748 u32 code = format->format.code; /* is overwritten by get_fmt */ 1749 int ret = tc358743_get_fmt(sd, sd_state, format); 1750 1751 if (code == MEDIA_BUS_FMT_RGB888_1X24 || 1752 code == MEDIA_BUS_FMT_UYVY8_1X16) 1753 format->format.code = code; 1754 format->format.colorspace = tc358743_g_colorspace(format->format.code); 1755 1756 if (ret) 1757 return ret; 1758 1759 if (format->which == V4L2_SUBDEV_FORMAT_TRY) 1760 return 0; 1761 1762 state->mbus_fmt_code = format->format.code; 1763 1764 enable_stream(sd, false); 1765 tc358743_set_pll(sd); 1766 tc358743_set_csi(sd); 1767 tc358743_set_csi_color_space(sd); 1768 1769 return 0; 1770 } 1771 1772 static int tc358743_g_edid(struct v4l2_subdev *sd, 1773 struct v4l2_subdev_edid *edid) 1774 { 1775 struct tc358743_state *state = to_state(sd); 1776 1777 memset(edid->reserved, 0, sizeof(edid->reserved)); 1778 1779 if (edid->pad != 0) 1780 return -EINVAL; 1781 1782 if (edid->start_block == 0 && edid->blocks == 0) { 1783 edid->blocks = state->edid_blocks_written; 1784 return 0; 1785 } 1786 1787 if (state->edid_blocks_written == 0) 1788 return -ENODATA; 1789 1790 if (edid->start_block >= state->edid_blocks_written || 1791 edid->blocks == 0) 1792 return -EINVAL; 1793 1794 if (edid->start_block + edid->blocks > state->edid_blocks_written) 1795 edid->blocks = state->edid_blocks_written - edid->start_block; 1796 1797 i2c_rd(sd, EDID_RAM + (edid->start_block * EDID_BLOCK_SIZE), edid->edid, 1798 edid->blocks * EDID_BLOCK_SIZE); 1799 1800 return 0; 1801 } 1802 1803 static int tc358743_s_edid(struct v4l2_subdev *sd, 1804 struct v4l2_subdev_edid *edid) 1805 { 1806 struct tc358743_state *state = to_state(sd); 1807 u16 edid_len = edid->blocks * EDID_BLOCK_SIZE; 1808 u16 pa; 1809 int err; 1810 int i; 1811 1812 v4l2_dbg(2, debug, sd, "%s, pad %d, start block %d, blocks %d\n", 1813 __func__, edid->pad, edid->start_block, edid->blocks); 1814 1815 memset(edid->reserved, 0, sizeof(edid->reserved)); 1816 1817 if (edid->pad != 0) 1818 return -EINVAL; 1819 1820 if (edid->start_block != 0) 1821 return -EINVAL; 1822 1823 if (edid->blocks > EDID_NUM_BLOCKS_MAX) { 1824 edid->blocks = EDID_NUM_BLOCKS_MAX; 1825 return -E2BIG; 1826 } 1827 pa = cec_get_edid_phys_addr(edid->edid, edid->blocks * 128, NULL); 1828 err = v4l2_phys_addr_validate(pa, &pa, NULL); 1829 if (err) 1830 return err; 1831 1832 cec_phys_addr_invalidate(state->cec_adap); 1833 1834 tc358743_disable_edid(sd); 1835 1836 i2c_wr8(sd, EDID_LEN1, edid_len & 0xff); 1837 i2c_wr8(sd, EDID_LEN2, edid_len >> 8); 1838 1839 if (edid->blocks == 0) { 1840 state->edid_blocks_written = 0; 1841 return 0; 1842 } 1843 1844 for (i = 0; i < edid_len; i += EDID_BLOCK_SIZE) 1845 i2c_wr(sd, EDID_RAM + i, edid->edid + i, EDID_BLOCK_SIZE); 1846 1847 state->edid_blocks_written = edid->blocks; 1848 1849 cec_s_phys_addr(state->cec_adap, pa, false); 1850 1851 if (tx_5v_power_present(sd)) 1852 tc358743_enable_edid(sd); 1853 1854 return 0; 1855 } 1856 1857 /* -------------------------------------------------------------------------- */ 1858 1859 static const struct v4l2_subdev_core_ops tc358743_core_ops = { 1860 .log_status = tc358743_log_status, 1861 #ifdef CONFIG_VIDEO_ADV_DEBUG 1862 .g_register = tc358743_g_register, 1863 .s_register = tc358743_s_register, 1864 #endif 1865 .interrupt_service_routine = tc358743_isr, 1866 .subscribe_event = tc358743_subscribe_event, 1867 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 1868 }; 1869 1870 static const struct v4l2_subdev_video_ops tc358743_video_ops = { 1871 .g_input_status = tc358743_g_input_status, 1872 .s_stream = tc358743_s_stream, 1873 }; 1874 1875 static const struct v4l2_subdev_pad_ops tc358743_pad_ops = { 1876 .enum_mbus_code = tc358743_enum_mbus_code, 1877 .set_fmt = tc358743_set_fmt, 1878 .get_fmt = tc358743_get_fmt, 1879 .get_edid = tc358743_g_edid, 1880 .set_edid = tc358743_s_edid, 1881 .s_dv_timings = tc358743_s_dv_timings, 1882 .g_dv_timings = tc358743_g_dv_timings, 1883 .query_dv_timings = tc358743_query_dv_timings, 1884 .enum_dv_timings = tc358743_enum_dv_timings, 1885 .dv_timings_cap = tc358743_dv_timings_cap, 1886 .get_mbus_config = tc358743_get_mbus_config, 1887 }; 1888 1889 static const struct v4l2_subdev_ops tc358743_ops = { 1890 .core = &tc358743_core_ops, 1891 .video = &tc358743_video_ops, 1892 .pad = &tc358743_pad_ops, 1893 }; 1894 1895 /* --------------- CUSTOM CTRLS --------------- */ 1896 1897 static const struct v4l2_ctrl_config tc358743_ctrl_audio_sampling_rate = { 1898 .id = TC358743_CID_AUDIO_SAMPLING_RATE, 1899 .name = "Audio sampling rate", 1900 .type = V4L2_CTRL_TYPE_INTEGER, 1901 .min = 0, 1902 .max = 768000, 1903 .step = 1, 1904 .def = 0, 1905 .flags = V4L2_CTRL_FLAG_READ_ONLY, 1906 }; 1907 1908 static const struct v4l2_ctrl_config tc358743_ctrl_audio_present = { 1909 .id = TC358743_CID_AUDIO_PRESENT, 1910 .name = "Audio present", 1911 .type = V4L2_CTRL_TYPE_BOOLEAN, 1912 .min = 0, 1913 .max = 1, 1914 .step = 1, 1915 .def = 0, 1916 .flags = V4L2_CTRL_FLAG_READ_ONLY, 1917 }; 1918 1919 /* --------------- PROBE / REMOVE --------------- */ 1920 1921 #ifdef CONFIG_OF 1922 static void tc358743_gpio_reset(struct tc358743_state *state) 1923 { 1924 usleep_range(5000, 10000); 1925 gpiod_set_value(state->reset_gpio, 1); 1926 usleep_range(1000, 2000); 1927 gpiod_set_value(state->reset_gpio, 0); 1928 msleep(20); 1929 } 1930 1931 static int tc358743_probe_of(struct tc358743_state *state) 1932 { 1933 struct device *dev = &state->i2c_client->dev; 1934 struct v4l2_fwnode_endpoint endpoint = { .bus_type = 0 }; 1935 struct device_node *ep; 1936 struct clk *refclk; 1937 u32 bps_pr_lane; 1938 int ret; 1939 1940 refclk = devm_clk_get(dev, "refclk"); 1941 if (IS_ERR(refclk)) 1942 return dev_err_probe(dev, PTR_ERR(refclk), 1943 "failed to get refclk\n"); 1944 1945 ep = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1); 1946 if (!ep) { 1947 dev_err(dev, "missing endpoint node\n"); 1948 return -EINVAL; 1949 } 1950 1951 ret = v4l2_fwnode_endpoint_alloc_parse(of_fwnode_handle(ep), &endpoint); 1952 if (ret) { 1953 dev_err(dev, "failed to parse endpoint\n"); 1954 goto put_node; 1955 } 1956 1957 if (endpoint.bus_type != V4L2_MBUS_CSI2_DPHY || 1958 endpoint.bus.mipi_csi2.num_data_lanes == 0 || 1959 endpoint.nr_of_link_frequencies == 0) { 1960 dev_err(dev, "missing CSI-2 properties in endpoint\n"); 1961 ret = -EINVAL; 1962 goto free_endpoint; 1963 } 1964 1965 if (endpoint.bus.mipi_csi2.num_data_lanes > 4) { 1966 dev_err(dev, "invalid number of lanes\n"); 1967 ret = -EINVAL; 1968 goto free_endpoint; 1969 } 1970 1971 state->bus = endpoint.bus.mipi_csi2; 1972 1973 ret = clk_prepare_enable(refclk); 1974 if (ret) { 1975 dev_err(dev, "Failed! to enable clock\n"); 1976 goto free_endpoint; 1977 } 1978 1979 state->pdata.refclk_hz = clk_get_rate(refclk); 1980 state->pdata.ddc5v_delay = DDC5V_DELAY_100_MS; 1981 state->pdata.enable_hdcp = false; 1982 /* 1983 * Ideally the FIFO trigger level should be set based on the input and 1984 * output data rates, but the calculations required are buried in 1985 * Toshiba's register settings spreadsheet. 1986 * A value of 16 works with a 594Mbps data rate for 720p60 (using 2 1987 * lanes) and 1080p60 (using 4 lanes), but fails when the data rate 1988 * is increased, or a lower pixel clock is used that result in CSI 1989 * reading out faster than the data is arriving. 1990 * 1991 * A value of 374 works with both those modes at 594Mbps, and with most 1992 * modes on 972Mbps. 1993 */ 1994 state->pdata.fifo_level = 374; 1995 /* 1996 * The PLL input clock is obtained by dividing refclk by pll_prd. 1997 * It must be between 6 MHz and 40 MHz, lower frequency is better. 1998 */ 1999 switch (state->pdata.refclk_hz) { 2000 case 26000000: 2001 case 27000000: 2002 case 42000000: 2003 state->pdata.pll_prd = state->pdata.refclk_hz / 6000000; 2004 break; 2005 default: 2006 dev_err(dev, "unsupported refclk rate: %u Hz\n", 2007 state->pdata.refclk_hz); 2008 goto disable_clk; 2009 } 2010 2011 /* 2012 * The CSI bps per lane must be between 62.5 Mbps and 1 Gbps. 2013 * The default is 594 Mbps for 4-lane 1080p60 or 2-lane 720p60. 2014 * 972 Mbps allows 1080P50 UYVY over 2-lane. 2015 */ 2016 bps_pr_lane = 2 * endpoint.link_frequencies[0]; 2017 if (bps_pr_lane < 62500000U || bps_pr_lane > 1000000000U) { 2018 dev_err(dev, "unsupported bps per lane: %u bps\n", bps_pr_lane); 2019 ret = -EINVAL; 2020 goto disable_clk; 2021 } 2022 2023 /* The CSI speed per lane is refclk / pll_prd * pll_fbd */ 2024 state->pdata.pll_fbd = bps_pr_lane / 2025 state->pdata.refclk_hz * state->pdata.pll_prd; 2026 2027 /* 2028 * FIXME: These timings are from REF_02 for 594 or 972 Mbps per lane 2029 * (297 MHz or 486 MHz link frequency). 2030 * In principle it should be possible to calculate 2031 * them based on link frequency and resolution. 2032 */ 2033 switch (bps_pr_lane) { 2034 default: 2035 dev_warn(dev, "untested bps per lane: %u bps\n", bps_pr_lane); 2036 fallthrough; 2037 case 594000000U: 2038 state->pdata.lineinitcnt = 0xe80; 2039 state->pdata.lptxtimecnt = 0x003; 2040 /* tclk-preparecnt: 3, tclk-zerocnt: 20 */ 2041 state->pdata.tclk_headercnt = 0x1403; 2042 state->pdata.tclk_trailcnt = 0x00; 2043 /* ths-preparecnt: 3, ths-zerocnt: 1 */ 2044 state->pdata.ths_headercnt = 0x0103; 2045 state->pdata.twakeup = 0x4882; 2046 state->pdata.tclk_postcnt = 0x008; 2047 state->pdata.ths_trailcnt = 0x2; 2048 state->pdata.hstxvregcnt = 0; 2049 break; 2050 case 972000000U: 2051 state->pdata.lineinitcnt = 0x1b58; 2052 state->pdata.lptxtimecnt = 0x007; 2053 /* tclk-preparecnt: 6, tclk-zerocnt: 40 */ 2054 state->pdata.tclk_headercnt = 0x2806; 2055 state->pdata.tclk_trailcnt = 0x00; 2056 /* ths-preparecnt: 6, ths-zerocnt: 8 */ 2057 state->pdata.ths_headercnt = 0x0806; 2058 state->pdata.twakeup = 0x4268; 2059 state->pdata.tclk_postcnt = 0x008; 2060 state->pdata.ths_trailcnt = 0x5; 2061 state->pdata.hstxvregcnt = 0; 2062 break; 2063 } 2064 2065 state->reset_gpio = devm_gpiod_get_optional(dev, "reset", 2066 GPIOD_OUT_LOW); 2067 if (IS_ERR(state->reset_gpio)) { 2068 dev_err(dev, "failed to get reset gpio\n"); 2069 ret = PTR_ERR(state->reset_gpio); 2070 goto disable_clk; 2071 } 2072 2073 if (state->reset_gpio) 2074 tc358743_gpio_reset(state); 2075 2076 ret = 0; 2077 goto free_endpoint; 2078 2079 disable_clk: 2080 clk_disable_unprepare(refclk); 2081 free_endpoint: 2082 v4l2_fwnode_endpoint_free(&endpoint); 2083 put_node: 2084 of_node_put(ep); 2085 return ret; 2086 } 2087 #else 2088 static inline int tc358743_probe_of(struct tc358743_state *state) 2089 { 2090 return -ENODEV; 2091 } 2092 #endif 2093 2094 static int tc358743_probe(struct i2c_client *client) 2095 { 2096 static struct v4l2_dv_timings default_timing = 2097 V4L2_DV_BT_CEA_640X480P59_94; 2098 struct tc358743_state *state; 2099 struct tc358743_platform_data *pdata = client->dev.platform_data; 2100 struct v4l2_subdev *sd; 2101 u16 irq_mask = MASK_HDMI_MSK | MASK_CSI_MSK; 2102 u16 chipid; 2103 int err; 2104 2105 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 2106 return -EIO; 2107 v4l_dbg(1, debug, client, "chip found @ 0x%x (%s)\n", 2108 client->addr << 1, client->adapter->name); 2109 2110 state = devm_kzalloc(&client->dev, sizeof(struct tc358743_state), 2111 GFP_KERNEL); 2112 if (!state) 2113 return -ENOMEM; 2114 2115 state->i2c_client = client; 2116 2117 /* platform data */ 2118 if (pdata) { 2119 state->pdata = *pdata; 2120 state->bus.flags = 0; 2121 } else { 2122 err = tc358743_probe_of(state); 2123 if (err == -ENODEV) 2124 v4l_err(client, "No platform data!\n"); 2125 if (err) 2126 return err; 2127 } 2128 2129 sd = &state->sd; 2130 v4l2_i2c_subdev_init(sd, client, &tc358743_ops); 2131 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; 2132 2133 /* i2c access */ 2134 if (i2c_rd16_err(sd, CHIPID, &chipid) || 2135 (chipid & MASK_CHIPID) != 0) { 2136 v4l2_info(sd, "not a TC358743 on address 0x%x\n", 2137 client->addr << 1); 2138 return -ENODEV; 2139 } 2140 2141 /* control handlers */ 2142 v4l2_ctrl_handler_init(&state->hdl, 3); 2143 2144 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(&state->hdl, NULL, 2145 V4L2_CID_DV_RX_POWER_PRESENT, 0, 1, 0, 0); 2146 2147 /* custom controls */ 2148 state->audio_sampling_rate_ctrl = v4l2_ctrl_new_custom(&state->hdl, 2149 &tc358743_ctrl_audio_sampling_rate, NULL); 2150 2151 state->audio_present_ctrl = v4l2_ctrl_new_custom(&state->hdl, 2152 &tc358743_ctrl_audio_present, NULL); 2153 2154 sd->ctrl_handler = &state->hdl; 2155 if (state->hdl.error) { 2156 err = state->hdl.error; 2157 goto err_hdl; 2158 } 2159 2160 if (tc358743_update_controls(sd)) { 2161 err = -ENODEV; 2162 goto err_hdl; 2163 } 2164 2165 state->pad.flags = MEDIA_PAD_FL_SOURCE; 2166 sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE; 2167 err = media_entity_pads_init(&sd->entity, 1, &state->pad); 2168 if (err < 0) 2169 goto err_hdl; 2170 2171 state->mbus_fmt_code = MEDIA_BUS_FMT_RGB888_1X24; 2172 2173 sd->dev = &client->dev; 2174 2175 mutex_init(&state->confctl_mutex); 2176 2177 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug, 2178 tc358743_delayed_work_enable_hotplug); 2179 2180 #ifdef CONFIG_VIDEO_TC358743_CEC 2181 state->cec_adap = cec_allocate_adapter(&tc358743_cec_adap_ops, 2182 state, dev_name(&client->dev), 2183 CEC_CAP_DEFAULTS | CEC_CAP_MONITOR_ALL, CEC_MAX_LOG_ADDRS); 2184 if (IS_ERR(state->cec_adap)) { 2185 err = PTR_ERR(state->cec_adap); 2186 goto err_hdl; 2187 } 2188 irq_mask |= MASK_CEC_RMSK | MASK_CEC_TMSK; 2189 #endif 2190 2191 tc358743_initial_setup(sd); 2192 2193 tc358743_s_dv_timings(sd, 0, &default_timing); 2194 2195 tc358743_set_csi_color_space(sd); 2196 2197 tc358743_init_interrupts(sd); 2198 2199 if (state->i2c_client->irq) { 2200 err = devm_request_threaded_irq(&client->dev, 2201 state->i2c_client->irq, 2202 NULL, tc358743_irq_handler, 2203 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 2204 "tc358743", state); 2205 if (err) 2206 goto err_work_queues; 2207 } else { 2208 INIT_WORK(&state->work_i2c_poll, 2209 tc358743_work_i2c_poll); 2210 timer_setup(&state->timer, tc358743_irq_poll_timer, 0); 2211 state->timer.expires = jiffies + 2212 msecs_to_jiffies(POLL_INTERVAL_MS); 2213 add_timer(&state->timer); 2214 } 2215 2216 err = cec_register_adapter(state->cec_adap, &client->dev); 2217 if (err < 0) { 2218 pr_err("%s: failed to register the cec device\n", __func__); 2219 cec_delete_adapter(state->cec_adap); 2220 state->cec_adap = NULL; 2221 goto err_work_queues; 2222 } 2223 2224 tc358743_enable_interrupts(sd, tx_5v_power_present(sd)); 2225 i2c_wr16(sd, INTMASK, ~irq_mask); 2226 2227 err = v4l2_ctrl_handler_setup(sd->ctrl_handler); 2228 if (err) 2229 goto err_work_queues; 2230 2231 err = v4l2_async_register_subdev(sd); 2232 if (err < 0) 2233 goto err_work_queues; 2234 2235 state->debugfs_dir = debugfs_create_dir(sd->name, v4l2_debugfs_root()); 2236 state->infoframes = v4l2_debugfs_if_alloc(state->debugfs_dir, 2237 V4L2_DEBUGFS_IF_AVI, sd, 2238 tc358743_debugfs_if_read); 2239 2240 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name, 2241 client->addr << 1, client->adapter->name); 2242 2243 return 0; 2244 2245 err_work_queues: 2246 cec_unregister_adapter(state->cec_adap); 2247 if (!state->i2c_client->irq) { 2248 timer_delete(&state->timer); 2249 flush_work(&state->work_i2c_poll); 2250 } 2251 cancel_delayed_work(&state->delayed_work_enable_hotplug); 2252 mutex_destroy(&state->confctl_mutex); 2253 err_hdl: 2254 media_entity_cleanup(&sd->entity); 2255 v4l2_ctrl_handler_free(&state->hdl); 2256 return err; 2257 } 2258 2259 static void tc358743_remove(struct i2c_client *client) 2260 { 2261 struct v4l2_subdev *sd = i2c_get_clientdata(client); 2262 struct tc358743_state *state = to_state(sd); 2263 2264 if (!state->i2c_client->irq) { 2265 timer_delete_sync(&state->timer); 2266 flush_work(&state->work_i2c_poll); 2267 } 2268 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug); 2269 v4l2_debugfs_if_free(state->infoframes); 2270 debugfs_remove_recursive(state->debugfs_dir); 2271 cec_unregister_adapter(state->cec_adap); 2272 v4l2_async_unregister_subdev(sd); 2273 v4l2_device_unregister_subdev(sd); 2274 mutex_destroy(&state->confctl_mutex); 2275 media_entity_cleanup(&sd->entity); 2276 v4l2_ctrl_handler_free(&state->hdl); 2277 } 2278 2279 static const struct i2c_device_id tc358743_id[] = { 2280 { "tc358743" }, 2281 {} 2282 }; 2283 2284 MODULE_DEVICE_TABLE(i2c, tc358743_id); 2285 2286 #if IS_ENABLED(CONFIG_OF) 2287 static const struct of_device_id tc358743_of_match[] = { 2288 { .compatible = "toshiba,tc358743" }, 2289 {}, 2290 }; 2291 MODULE_DEVICE_TABLE(of, tc358743_of_match); 2292 #endif 2293 2294 static struct i2c_driver tc358743_driver = { 2295 .driver = { 2296 .name = "tc358743", 2297 .of_match_table = of_match_ptr(tc358743_of_match), 2298 }, 2299 .probe = tc358743_probe, 2300 .remove = tc358743_remove, 2301 .id_table = tc358743_id, 2302 }; 2303 2304 module_i2c_driver(tc358743_driver); 2305