1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for ST MIPID02 CSI-2 to PARALLEL bridge 4 * 5 * Copyright (C) STMicroelectronics SA 2019 6 * Authors: Mickael Guene <mickael.guene@st.com> 7 * for STMicroelectronics. 8 * 9 * 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/gpio/consumer.h> 15 #include <linux/i2c.h> 16 #include <linux/module.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/of_graph.h> 19 #include <linux/regulator/consumer.h> 20 #include <media/mipi-csi2.h> 21 #include <media/v4l2-async.h> 22 #include <media/v4l2-cci.h> 23 #include <media/v4l2-ctrls.h> 24 #include <media/v4l2-device.h> 25 #include <media/v4l2-fwnode.h> 26 #include <media/v4l2-subdev.h> 27 28 #define MIPID02_CLK_LANE_WR_REG1 CCI_REG8(0x01) 29 #define MIPID02_CLK_LANE_REG1 CCI_REG8(0x02) 30 #define MIPID02_CLK_LANE_REG3 CCI_REG8(0x04) 31 #define MIPID02_DATA_LANE0_REG1 CCI_REG8(0x05) 32 #define MIPID02_DATA_LANE0_REG2 CCI_REG8(0x06) 33 #define MIPID02_DATA_LANE1_REG1 CCI_REG8(0x09) 34 #define MIPID02_DATA_LANE1_REG2 CCI_REG8(0x0a) 35 #define MIPID02_MODE_REG1 CCI_REG8(0x14) 36 #define MIPID02_MODE_REG2 CCI_REG8(0x15) 37 #define MIPID02_DATA_ID_RREG CCI_REG8(0x17) 38 #define MIPID02_DATA_SELECTION_CTRL CCI_REG8(0x19) 39 #define MIPID02_PIX_WIDTH_CTRL CCI_REG8(0x1e) 40 #define MIPID02_PIX_WIDTH_CTRL_EMB CCI_REG8(0x1f) 41 42 /* Bits definition for MIPID02_CLK_LANE_REG1 */ 43 #define CLK_ENABLE BIT(0) 44 /* Bits definition for MIPID02_CLK_LANE_REG3 */ 45 #define CLK_MIPI_CSI BIT(1) 46 /* Bits definition for MIPID02_DATA_LANE0_REG1 */ 47 #define DATA_ENABLE BIT(0) 48 /* Bits definition for MIPID02_DATA_LANEx_REG2 */ 49 #define DATA_MIPI_CSI BIT(0) 50 /* Bits definition for MIPID02_MODE_REG1 */ 51 #define MODE_DATA_SWAP BIT(2) 52 #define MODE_NO_BYPASS BIT(6) 53 /* Bits definition for MIPID02_MODE_REG2 */ 54 #define MODE_HSYNC_ACTIVE_HIGH BIT(1) 55 #define MODE_VSYNC_ACTIVE_HIGH BIT(2) 56 #define MODE_PCLK_SAMPLE_RISING BIT(3) 57 /* Bits definition for MIPID02_DATA_SELECTION_CTRL */ 58 #define SELECTION_MANUAL_DATA BIT(2) 59 #define SELECTION_MANUAL_WIDTH BIT(3) 60 61 static const u32 mipid02_supported_fmt_codes[] = { 62 MEDIA_BUS_FMT_SBGGR8_1X8, MEDIA_BUS_FMT_SGBRG8_1X8, 63 MEDIA_BUS_FMT_SGRBG8_1X8, MEDIA_BUS_FMT_SRGGB8_1X8, 64 MEDIA_BUS_FMT_SBGGR10_1X10, MEDIA_BUS_FMT_SGBRG10_1X10, 65 MEDIA_BUS_FMT_SGRBG10_1X10, MEDIA_BUS_FMT_SRGGB10_1X10, 66 MEDIA_BUS_FMT_SBGGR12_1X12, MEDIA_BUS_FMT_SGBRG12_1X12, 67 MEDIA_BUS_FMT_SGRBG12_1X12, MEDIA_BUS_FMT_SRGGB12_1X12, 68 MEDIA_BUS_FMT_YUYV8_1X16, MEDIA_BUS_FMT_YVYU8_1X16, 69 MEDIA_BUS_FMT_UYVY8_1X16, MEDIA_BUS_FMT_VYUY8_1X16, 70 MEDIA_BUS_FMT_RGB565_1X16, MEDIA_BUS_FMT_BGR888_1X24, 71 MEDIA_BUS_FMT_Y8_1X8, MEDIA_BUS_FMT_JPEG_1X8 72 }; 73 74 /* regulator supplies */ 75 static const char * const mipid02_supply_name[] = { 76 "VDDE", /* 1.8V digital I/O supply */ 77 "VDDIN", /* 1V8 voltage regulator supply */ 78 }; 79 80 #define MIPID02_NUM_SUPPLIES ARRAY_SIZE(mipid02_supply_name) 81 82 #define MIPID02_SINK_0 0 83 #define MIPID02_SINK_1 1 84 #define MIPID02_SOURCE 2 85 #define MIPID02_PAD_NB 3 86 87 struct mipid02_dev { 88 struct i2c_client *i2c_client; 89 struct regulator_bulk_data supplies[MIPID02_NUM_SUPPLIES]; 90 struct v4l2_subdev sd; 91 struct regmap *regmap; 92 struct media_pad pad[MIPID02_PAD_NB]; 93 struct clk *xclk; 94 struct gpio_desc *reset_gpio; 95 /* endpoints info */ 96 struct v4l2_fwnode_endpoint rx; 97 struct v4l2_fwnode_endpoint tx; 98 /* remote source */ 99 struct v4l2_async_notifier notifier; 100 struct v4l2_subdev *s_subdev; 101 u16 s_subdev_pad_id; 102 /* registers */ 103 struct { 104 u8 clk_lane_reg1; 105 u8 data_lane0_reg1; 106 u8 data_lane1_reg1; 107 u8 mode_reg1; 108 u8 mode_reg2; 109 u8 data_selection_ctrl; 110 u8 data_id_rreg; 111 u8 pix_width_ctrl; 112 u8 pix_width_ctrl_emb; 113 } r; 114 }; 115 116 static int bpp_from_code(__u32 code) 117 { 118 switch (code) { 119 case MEDIA_BUS_FMT_SBGGR8_1X8: 120 case MEDIA_BUS_FMT_SGBRG8_1X8: 121 case MEDIA_BUS_FMT_SGRBG8_1X8: 122 case MEDIA_BUS_FMT_SRGGB8_1X8: 123 case MEDIA_BUS_FMT_Y8_1X8: 124 return 8; 125 case MEDIA_BUS_FMT_SBGGR10_1X10: 126 case MEDIA_BUS_FMT_SGBRG10_1X10: 127 case MEDIA_BUS_FMT_SGRBG10_1X10: 128 case MEDIA_BUS_FMT_SRGGB10_1X10: 129 return 10; 130 case MEDIA_BUS_FMT_SBGGR12_1X12: 131 case MEDIA_BUS_FMT_SGBRG12_1X12: 132 case MEDIA_BUS_FMT_SGRBG12_1X12: 133 case MEDIA_BUS_FMT_SRGGB12_1X12: 134 return 12; 135 case MEDIA_BUS_FMT_YUYV8_1X16: 136 case MEDIA_BUS_FMT_YVYU8_1X16: 137 case MEDIA_BUS_FMT_UYVY8_1X16: 138 case MEDIA_BUS_FMT_VYUY8_1X16: 139 case MEDIA_BUS_FMT_RGB565_1X16: 140 return 16; 141 case MEDIA_BUS_FMT_BGR888_1X24: 142 return 24; 143 default: 144 return 0; 145 } 146 } 147 148 static u8 data_type_from_code(__u32 code) 149 { 150 switch (code) { 151 case MEDIA_BUS_FMT_SBGGR8_1X8: 152 case MEDIA_BUS_FMT_SGBRG8_1X8: 153 case MEDIA_BUS_FMT_SGRBG8_1X8: 154 case MEDIA_BUS_FMT_SRGGB8_1X8: 155 case MEDIA_BUS_FMT_Y8_1X8: 156 return MIPI_CSI2_DT_RAW8; 157 case MEDIA_BUS_FMT_SBGGR10_1X10: 158 case MEDIA_BUS_FMT_SGBRG10_1X10: 159 case MEDIA_BUS_FMT_SGRBG10_1X10: 160 case MEDIA_BUS_FMT_SRGGB10_1X10: 161 return MIPI_CSI2_DT_RAW10; 162 case MEDIA_BUS_FMT_SBGGR12_1X12: 163 case MEDIA_BUS_FMT_SGBRG12_1X12: 164 case MEDIA_BUS_FMT_SGRBG12_1X12: 165 case MEDIA_BUS_FMT_SRGGB12_1X12: 166 return MIPI_CSI2_DT_RAW12; 167 case MEDIA_BUS_FMT_YUYV8_1X16: 168 case MEDIA_BUS_FMT_YVYU8_1X16: 169 case MEDIA_BUS_FMT_UYVY8_1X16: 170 case MEDIA_BUS_FMT_VYUY8_1X16: 171 return MIPI_CSI2_DT_YUV422_8B; 172 case MEDIA_BUS_FMT_BGR888_1X24: 173 return MIPI_CSI2_DT_RGB888; 174 case MEDIA_BUS_FMT_RGB565_1X16: 175 return MIPI_CSI2_DT_RGB565; 176 default: 177 return 0; 178 } 179 } 180 181 static __u32 get_fmt_code(__u32 code) 182 { 183 unsigned int i; 184 185 for (i = 0; i < ARRAY_SIZE(mipid02_supported_fmt_codes); i++) { 186 if (code == mipid02_supported_fmt_codes[i]) 187 return code; 188 } 189 190 return mipid02_supported_fmt_codes[0]; 191 } 192 193 static __u32 serial_to_parallel_code(__u32 serial) 194 { 195 if (serial == MEDIA_BUS_FMT_RGB565_1X16) 196 return MEDIA_BUS_FMT_RGB565_2X8_LE; 197 if (serial == MEDIA_BUS_FMT_YUYV8_1X16) 198 return MEDIA_BUS_FMT_YUYV8_2X8; 199 if (serial == MEDIA_BUS_FMT_YVYU8_1X16) 200 return MEDIA_BUS_FMT_YVYU8_2X8; 201 if (serial == MEDIA_BUS_FMT_UYVY8_1X16) 202 return MEDIA_BUS_FMT_UYVY8_2X8; 203 if (serial == MEDIA_BUS_FMT_VYUY8_1X16) 204 return MEDIA_BUS_FMT_VYUY8_2X8; 205 if (serial == MEDIA_BUS_FMT_BGR888_1X24) 206 return MEDIA_BUS_FMT_BGR888_3X8; 207 208 return serial; 209 } 210 211 static inline struct mipid02_dev *to_mipid02_dev(struct v4l2_subdev *sd) 212 { 213 return container_of(sd, struct mipid02_dev, sd); 214 } 215 216 static int mipid02_get_regulators(struct mipid02_dev *bridge) 217 { 218 unsigned int i; 219 220 for (i = 0; i < MIPID02_NUM_SUPPLIES; i++) 221 bridge->supplies[i].supply = mipid02_supply_name[i]; 222 223 return devm_regulator_bulk_get(&bridge->i2c_client->dev, 224 MIPID02_NUM_SUPPLIES, 225 bridge->supplies); 226 } 227 228 static void mipid02_apply_reset(struct mipid02_dev *bridge) 229 { 230 gpiod_set_value_cansleep(bridge->reset_gpio, 0); 231 usleep_range(5000, 10000); 232 gpiod_set_value_cansleep(bridge->reset_gpio, 1); 233 usleep_range(5000, 10000); 234 gpiod_set_value_cansleep(bridge->reset_gpio, 0); 235 usleep_range(5000, 10000); 236 } 237 238 static int mipid02_set_power_on(struct device *dev) 239 { 240 struct v4l2_subdev *sd = dev_get_drvdata(dev); 241 struct mipid02_dev *bridge = to_mipid02_dev(sd); 242 struct i2c_client *client = bridge->i2c_client; 243 int ret; 244 245 ret = clk_prepare_enable(bridge->xclk); 246 if (ret) { 247 dev_err(&client->dev, "%s: failed to enable clock\n", __func__); 248 return ret; 249 } 250 251 ret = regulator_bulk_enable(MIPID02_NUM_SUPPLIES, 252 bridge->supplies); 253 if (ret) { 254 dev_err(&client->dev, "%s: failed to enable regulators\n", 255 __func__); 256 goto xclk_off; 257 } 258 259 if (bridge->reset_gpio) { 260 dev_dbg(&client->dev, "apply reset"); 261 mipid02_apply_reset(bridge); 262 } else { 263 dev_dbg(&client->dev, "don't apply reset"); 264 usleep_range(5000, 10000); 265 } 266 267 return 0; 268 269 xclk_off: 270 clk_disable_unprepare(bridge->xclk); 271 return ret; 272 } 273 274 static int mipid02_set_power_off(struct device *dev) 275 { 276 struct v4l2_subdev *sd = dev_get_drvdata(dev); 277 struct mipid02_dev *bridge = to_mipid02_dev(sd); 278 279 regulator_bulk_disable(MIPID02_NUM_SUPPLIES, bridge->supplies); 280 clk_disable_unprepare(bridge->xclk); 281 282 return 0; 283 } 284 285 static int mipid02_detect(struct mipid02_dev *bridge) 286 { 287 u64 reg; 288 289 /* 290 * There is no version registers. Just try to read register 291 * MIPID02_CLK_LANE_WR_REG1. 292 */ 293 return cci_read(bridge->regmap, MIPID02_CLK_LANE_WR_REG1, ®, NULL); 294 } 295 296 /* 297 * We need to know link frequency to setup clk_lane_reg1 timings. Link frequency 298 * will be retrieve from connected device via v4l2_get_link_freq, bit per pixel 299 * and number of lanes. 300 */ 301 static int mipid02_configure_from_rx_speed(struct mipid02_dev *bridge, 302 struct v4l2_mbus_framefmt *fmt) 303 { 304 struct i2c_client *client = bridge->i2c_client; 305 struct v4l2_subdev *subdev = bridge->s_subdev; 306 struct v4l2_fwnode_endpoint *ep = &bridge->rx; 307 u32 bpp = bpp_from_code(fmt->code); 308 /* 309 * clk_lane_reg1 requires 4 times the unit interval time, and bitrate 310 * is twice the link frequency, hence ui_4 = 1000000000 * 4 / 2 311 */ 312 u64 ui_4 = 2000000000; 313 s64 link_freq; 314 315 link_freq = v4l2_get_link_freq(subdev->ctrl_handler, bpp, 316 2 * ep->bus.mipi_csi2.num_data_lanes); 317 if (link_freq < 0) { 318 dev_err(&client->dev, "Failed to get link frequency"); 319 return -EINVAL; 320 } 321 322 dev_dbg(&client->dev, "detect link_freq = %lld Hz", link_freq); 323 ui_4 = div64_u64(ui_4, link_freq); 324 bridge->r.clk_lane_reg1 |= ui_4 << 2; 325 326 return 0; 327 } 328 329 static int mipid02_configure_clk_lane(struct mipid02_dev *bridge) 330 { 331 struct i2c_client *client = bridge->i2c_client; 332 struct v4l2_fwnode_endpoint *ep = &bridge->rx; 333 bool *polarities = ep->bus.mipi_csi2.lane_polarities; 334 335 /* midid02 doesn't support clock lane remapping */ 336 if (ep->bus.mipi_csi2.clock_lane != 0) { 337 dev_err(&client->dev, "clk lane must be map to lane 0\n"); 338 return -EINVAL; 339 } 340 bridge->r.clk_lane_reg1 |= (polarities[0] << 1) | CLK_ENABLE; 341 342 return 0; 343 } 344 345 static int mipid02_configure_data0_lane(struct mipid02_dev *bridge, int nb, 346 bool are_lanes_swap, bool *polarities) 347 { 348 bool are_pin_swap = are_lanes_swap ? polarities[2] : polarities[1]; 349 350 if (nb == 1 && are_lanes_swap) 351 return 0; 352 353 /* 354 * data lane 0 as pin swap polarity reversed compared to clock and 355 * data lane 1 356 */ 357 if (!are_pin_swap) 358 bridge->r.data_lane0_reg1 = 1 << 1; 359 bridge->r.data_lane0_reg1 |= DATA_ENABLE; 360 361 return 0; 362 } 363 364 static int mipid02_configure_data1_lane(struct mipid02_dev *bridge, int nb, 365 bool are_lanes_swap, bool *polarities) 366 { 367 bool are_pin_swap = are_lanes_swap ? polarities[1] : polarities[2]; 368 369 if (nb == 1 && !are_lanes_swap) 370 return 0; 371 372 if (are_pin_swap) 373 bridge->r.data_lane1_reg1 = 1 << 1; 374 bridge->r.data_lane1_reg1 |= DATA_ENABLE; 375 376 return 0; 377 } 378 379 static int mipid02_configure_from_rx(struct mipid02_dev *bridge, 380 struct v4l2_mbus_framefmt *fmt) 381 { 382 struct v4l2_fwnode_endpoint *ep = &bridge->rx; 383 bool are_lanes_swap = ep->bus.mipi_csi2.data_lanes[0] == 2; 384 bool *polarities = ep->bus.mipi_csi2.lane_polarities; 385 int nb = ep->bus.mipi_csi2.num_data_lanes; 386 int ret; 387 388 ret = mipid02_configure_clk_lane(bridge); 389 if (ret) 390 return ret; 391 392 ret = mipid02_configure_data0_lane(bridge, nb, are_lanes_swap, 393 polarities); 394 if (ret) 395 return ret; 396 397 ret = mipid02_configure_data1_lane(bridge, nb, are_lanes_swap, 398 polarities); 399 if (ret) 400 return ret; 401 402 bridge->r.mode_reg1 |= are_lanes_swap ? MODE_DATA_SWAP : 0; 403 bridge->r.mode_reg1 |= (nb - 1) << 1; 404 405 return mipid02_configure_from_rx_speed(bridge, fmt); 406 } 407 408 static int mipid02_configure_from_tx(struct mipid02_dev *bridge) 409 { 410 struct v4l2_fwnode_endpoint *ep = &bridge->tx; 411 412 bridge->r.data_selection_ctrl = SELECTION_MANUAL_WIDTH; 413 bridge->r.pix_width_ctrl = ep->bus.parallel.bus_width; 414 bridge->r.pix_width_ctrl_emb = ep->bus.parallel.bus_width; 415 if (ep->bus.parallel.flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) 416 bridge->r.mode_reg2 |= MODE_HSYNC_ACTIVE_HIGH; 417 if (ep->bus.parallel.flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) 418 bridge->r.mode_reg2 |= MODE_VSYNC_ACTIVE_HIGH; 419 if (ep->bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_RISING) 420 bridge->r.mode_reg2 |= MODE_PCLK_SAMPLE_RISING; 421 422 return 0; 423 } 424 425 static int mipid02_configure_from_code(struct mipid02_dev *bridge, 426 struct v4l2_mbus_framefmt *fmt) 427 { 428 u8 data_type; 429 430 bridge->r.data_id_rreg = 0; 431 432 if (fmt->code != MEDIA_BUS_FMT_JPEG_1X8) { 433 bridge->r.data_selection_ctrl |= SELECTION_MANUAL_DATA; 434 435 data_type = data_type_from_code(fmt->code); 436 if (!data_type) 437 return -EINVAL; 438 bridge->r.data_id_rreg = data_type; 439 } 440 441 return 0; 442 } 443 444 static int mipid02_disable_streams(struct v4l2_subdev *sd, 445 struct v4l2_subdev_state *state, u32 pad, 446 u64 streams_mask) 447 { 448 struct mipid02_dev *bridge = to_mipid02_dev(sd); 449 struct i2c_client *client = bridge->i2c_client; 450 int ret = -EINVAL; 451 452 if (!bridge->s_subdev) 453 goto error; 454 455 ret = v4l2_subdev_disable_streams(bridge->s_subdev, 456 bridge->s_subdev_pad_id, BIT(0)); 457 if (ret) 458 goto error; 459 460 /* Disable all lanes */ 461 cci_write(bridge->regmap, MIPID02_CLK_LANE_REG1, 0, &ret); 462 cci_write(bridge->regmap, MIPID02_DATA_LANE0_REG1, 0, &ret); 463 cci_write(bridge->regmap, MIPID02_DATA_LANE1_REG1, 0, &ret); 464 if (ret) 465 goto error; 466 467 pm_runtime_mark_last_busy(&client->dev); 468 pm_runtime_put_autosuspend(&client->dev); 469 470 error: 471 if (ret) 472 dev_err(&client->dev, "failed to stream off %d", ret); 473 474 return ret; 475 } 476 477 static int mipid02_enable_streams(struct v4l2_subdev *sd, 478 struct v4l2_subdev_state *state, u32 pad, 479 u64 streams_mask) 480 { 481 struct mipid02_dev *bridge = to_mipid02_dev(sd); 482 struct i2c_client *client = bridge->i2c_client; 483 struct v4l2_mbus_framefmt *fmt; 484 int ret = -EINVAL; 485 486 if (!bridge->s_subdev) 487 return ret; 488 489 memset(&bridge->r, 0, sizeof(bridge->r)); 490 491 fmt = v4l2_subdev_state_get_format(state, MIPID02_SINK_0); 492 493 /* build registers content */ 494 ret = mipid02_configure_from_rx(bridge, fmt); 495 if (ret) 496 return ret; 497 ret = mipid02_configure_from_tx(bridge); 498 if (ret) 499 return ret; 500 ret = mipid02_configure_from_code(bridge, fmt); 501 if (ret) 502 return ret; 503 504 ret = pm_runtime_resume_and_get(&client->dev); 505 if (ret < 0) 506 return ret; 507 508 /* write mipi registers */ 509 cci_write(bridge->regmap, MIPID02_CLK_LANE_REG1, 510 bridge->r.clk_lane_reg1, &ret); 511 cci_write(bridge->regmap, MIPID02_CLK_LANE_REG3, CLK_MIPI_CSI, &ret); 512 cci_write(bridge->regmap, MIPID02_DATA_LANE0_REG1, 513 bridge->r.data_lane0_reg1, &ret); 514 cci_write(bridge->regmap, MIPID02_DATA_LANE0_REG2, DATA_MIPI_CSI, &ret); 515 cci_write(bridge->regmap, MIPID02_DATA_LANE1_REG1, 516 bridge->r.data_lane1_reg1, &ret); 517 cci_write(bridge->regmap, MIPID02_DATA_LANE1_REG2, DATA_MIPI_CSI, &ret); 518 cci_write(bridge->regmap, MIPID02_MODE_REG1, 519 MODE_NO_BYPASS | bridge->r.mode_reg1, &ret); 520 cci_write(bridge->regmap, MIPID02_MODE_REG2, bridge->r.mode_reg2, &ret); 521 cci_write(bridge->regmap, MIPID02_DATA_ID_RREG, bridge->r.data_id_rreg, 522 &ret); 523 cci_write(bridge->regmap, MIPID02_DATA_SELECTION_CTRL, 524 bridge->r.data_selection_ctrl, &ret); 525 cci_write(bridge->regmap, MIPID02_PIX_WIDTH_CTRL, 526 bridge->r.pix_width_ctrl, &ret); 527 cci_write(bridge->regmap, MIPID02_PIX_WIDTH_CTRL_EMB, 528 bridge->r.pix_width_ctrl_emb, &ret); 529 if (ret) 530 goto error; 531 532 ret = v4l2_subdev_enable_streams(bridge->s_subdev, 533 bridge->s_subdev_pad_id, BIT(0)); 534 if (ret) 535 goto error; 536 537 return 0; 538 539 error: 540 cci_write(bridge->regmap, MIPID02_CLK_LANE_REG1, 0, &ret); 541 cci_write(bridge->regmap, MIPID02_DATA_LANE0_REG1, 0, &ret); 542 cci_write(bridge->regmap, MIPID02_DATA_LANE1_REG1, 0, &ret); 543 544 pm_runtime_mark_last_busy(&client->dev); 545 pm_runtime_put_autosuspend(&client->dev); 546 return ret; 547 } 548 549 static const struct v4l2_mbus_framefmt default_fmt = { 550 .code = MEDIA_BUS_FMT_SBGGR8_1X8, 551 .field = V4L2_FIELD_NONE, 552 .colorspace = V4L2_COLORSPACE_SRGB, 553 .ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT, 554 .quantization = V4L2_QUANTIZATION_FULL_RANGE, 555 .xfer_func = V4L2_XFER_FUNC_DEFAULT, 556 .width = 640, 557 .height = 480, 558 }; 559 560 static int mipid02_init_state(struct v4l2_subdev *sd, 561 struct v4l2_subdev_state *state) 562 { 563 *v4l2_subdev_state_get_format(state, MIPID02_SINK_0) = default_fmt; 564 /* MIPID02_SINK_1 isn't supported yet */ 565 *v4l2_subdev_state_get_format(state, MIPID02_SOURCE) = default_fmt; 566 567 return 0; 568 } 569 570 static int mipid02_enum_mbus_code(struct v4l2_subdev *sd, 571 struct v4l2_subdev_state *sd_state, 572 struct v4l2_subdev_mbus_code_enum *code) 573 { 574 struct v4l2_mbus_framefmt *sink_fmt; 575 int ret = 0; 576 577 switch (code->pad) { 578 case MIPID02_SINK_0: 579 if (code->index >= ARRAY_SIZE(mipid02_supported_fmt_codes)) 580 ret = -EINVAL; 581 else 582 code->code = mipid02_supported_fmt_codes[code->index]; 583 break; 584 case MIPID02_SOURCE: 585 if (code->index == 0) { 586 sink_fmt = v4l2_subdev_state_get_format(sd_state, 587 MIPID02_SINK_0); 588 code->code = serial_to_parallel_code(sink_fmt->code); 589 } else { 590 ret = -EINVAL; 591 } 592 break; 593 default: 594 ret = -EINVAL; 595 } 596 597 return ret; 598 } 599 600 static int mipid02_set_fmt(struct v4l2_subdev *sd, 601 struct v4l2_subdev_state *sd_state, 602 struct v4l2_subdev_format *fmt) 603 { 604 struct mipid02_dev *bridge = to_mipid02_dev(sd); 605 struct i2c_client *client = bridge->i2c_client; 606 struct v4l2_mbus_framefmt *pad_fmt; 607 608 dev_dbg(&client->dev, "%s for %d", __func__, fmt->pad); 609 610 /* second CSI-2 pad not yet supported */ 611 if (fmt->pad == MIPID02_SINK_1) 612 return -EINVAL; 613 614 pad_fmt = v4l2_subdev_state_get_format(sd_state, fmt->pad); 615 fmt->format.code = get_fmt_code(fmt->format.code); 616 617 /* code may need to be converted */ 618 if (fmt->pad == MIPID02_SOURCE) 619 fmt->format.code = serial_to_parallel_code(fmt->format.code); 620 621 *pad_fmt = fmt->format; 622 623 /* Propagate the format to the source pad in case of sink pad update */ 624 if (fmt->pad == MIPID02_SINK_0) { 625 pad_fmt = v4l2_subdev_state_get_format(sd_state, 626 MIPID02_SOURCE); 627 *pad_fmt = fmt->format; 628 pad_fmt->code = serial_to_parallel_code(fmt->format.code); 629 } 630 631 return 0; 632 } 633 634 static const struct v4l2_subdev_video_ops mipid02_video_ops = { 635 .s_stream = v4l2_subdev_s_stream_helper, 636 }; 637 638 static const struct v4l2_subdev_pad_ops mipid02_pad_ops = { 639 .enum_mbus_code = mipid02_enum_mbus_code, 640 .get_fmt = v4l2_subdev_get_fmt, 641 .set_fmt = mipid02_set_fmt, 642 .enable_streams = mipid02_enable_streams, 643 .disable_streams = mipid02_disable_streams, 644 }; 645 646 static const struct v4l2_subdev_ops mipid02_subdev_ops = { 647 .video = &mipid02_video_ops, 648 .pad = &mipid02_pad_ops, 649 }; 650 651 static const struct v4l2_subdev_internal_ops mipid02_subdev_internal_ops = { 652 .init_state = mipid02_init_state, 653 }; 654 655 static const struct media_entity_operations mipid02_subdev_entity_ops = { 656 .link_validate = v4l2_subdev_link_validate, 657 }; 658 659 static int mipid02_async_bound(struct v4l2_async_notifier *notifier, 660 struct v4l2_subdev *s_subdev, 661 struct v4l2_async_connection *asd) 662 { 663 struct mipid02_dev *bridge = to_mipid02_dev(notifier->sd); 664 struct i2c_client *client = bridge->i2c_client; 665 int source_pad; 666 int ret; 667 668 dev_dbg(&client->dev, "sensor_async_bound call %p", s_subdev); 669 670 source_pad = media_entity_get_fwnode_pad(&s_subdev->entity, 671 s_subdev->fwnode, 672 MEDIA_PAD_FL_SOURCE); 673 if (source_pad < 0) { 674 dev_err(&client->dev, "Couldn't find output pad for subdev %s\n", 675 s_subdev->name); 676 return source_pad; 677 } 678 679 ret = media_create_pad_link(&s_subdev->entity, source_pad, 680 &bridge->sd.entity, 0, 681 MEDIA_LNK_FL_ENABLED | 682 MEDIA_LNK_FL_IMMUTABLE); 683 if (ret) { 684 dev_err(&client->dev, "Couldn't create media link %d", ret); 685 return ret; 686 } 687 688 bridge->s_subdev = s_subdev; 689 bridge->s_subdev_pad_id = source_pad; 690 691 return 0; 692 } 693 694 static void mipid02_async_unbind(struct v4l2_async_notifier *notifier, 695 struct v4l2_subdev *s_subdev, 696 struct v4l2_async_connection *asd) 697 { 698 struct mipid02_dev *bridge = to_mipid02_dev(notifier->sd); 699 700 bridge->s_subdev = NULL; 701 } 702 703 static const struct v4l2_async_notifier_operations mipid02_notifier_ops = { 704 .bound = mipid02_async_bound, 705 .unbind = mipid02_async_unbind, 706 }; 707 708 static int mipid02_parse_rx_ep(struct mipid02_dev *bridge) 709 { 710 struct v4l2_fwnode_endpoint ep = { .bus_type = V4L2_MBUS_CSI2_DPHY }; 711 struct i2c_client *client = bridge->i2c_client; 712 struct v4l2_async_connection *asd; 713 struct device_node *ep_node; 714 int ret; 715 716 /* parse rx (endpoint 0) */ 717 ep_node = of_graph_get_endpoint_by_regs(bridge->i2c_client->dev.of_node, 718 0, 0); 719 if (!ep_node) { 720 dev_err(&client->dev, "unable to find port0 ep"); 721 ret = -EINVAL; 722 goto error; 723 } 724 725 ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep_node), &ep); 726 if (ret) { 727 dev_err(&client->dev, "Could not parse v4l2 endpoint %d\n", 728 ret); 729 goto error_of_node_put; 730 } 731 732 /* do some sanity checks */ 733 if (ep.bus.mipi_csi2.num_data_lanes > 2) { 734 dev_err(&client->dev, "max supported data lanes is 2 / got %d", 735 ep.bus.mipi_csi2.num_data_lanes); 736 ret = -EINVAL; 737 goto error_of_node_put; 738 } 739 740 /* register it for later use */ 741 bridge->rx = ep; 742 743 /* register async notifier so we get noticed when sensor is connected */ 744 v4l2_async_subdev_nf_init(&bridge->notifier, &bridge->sd); 745 asd = v4l2_async_nf_add_fwnode_remote(&bridge->notifier, 746 of_fwnode_handle(ep_node), 747 struct v4l2_async_connection); 748 of_node_put(ep_node); 749 750 if (IS_ERR(asd)) { 751 dev_err(&client->dev, "fail to register asd to notifier %ld", 752 PTR_ERR(asd)); 753 return PTR_ERR(asd); 754 } 755 bridge->notifier.ops = &mipid02_notifier_ops; 756 757 ret = v4l2_async_nf_register(&bridge->notifier); 758 if (ret) 759 v4l2_async_nf_cleanup(&bridge->notifier); 760 761 return ret; 762 763 error_of_node_put: 764 of_node_put(ep_node); 765 error: 766 767 return ret; 768 } 769 770 static int mipid02_parse_tx_ep(struct mipid02_dev *bridge) 771 { 772 struct v4l2_fwnode_endpoint ep = { .bus_type = V4L2_MBUS_PARALLEL }; 773 struct i2c_client *client = bridge->i2c_client; 774 struct device_node *ep_node; 775 int ret; 776 777 /* parse tx (endpoint 2) */ 778 ep_node = of_graph_get_endpoint_by_regs(bridge->i2c_client->dev.of_node, 779 2, 0); 780 if (!ep_node) { 781 dev_err(&client->dev, "unable to find port1 ep"); 782 ret = -EINVAL; 783 goto error; 784 } 785 786 ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep_node), &ep); 787 if (ret) { 788 dev_err(&client->dev, "Could not parse v4l2 endpoint\n"); 789 goto error_of_node_put; 790 } 791 792 of_node_put(ep_node); 793 bridge->tx = ep; 794 795 return 0; 796 797 error_of_node_put: 798 of_node_put(ep_node); 799 error: 800 801 return -EINVAL; 802 } 803 804 static int mipid02_probe(struct i2c_client *client) 805 { 806 struct device *dev = &client->dev; 807 struct mipid02_dev *bridge; 808 u32 clk_freq; 809 int ret; 810 811 bridge = devm_kzalloc(dev, sizeof(*bridge), GFP_KERNEL); 812 if (!bridge) 813 return -ENOMEM; 814 815 bridge->i2c_client = client; 816 v4l2_i2c_subdev_init(&bridge->sd, client, &mipid02_subdev_ops); 817 818 /* got and check clock */ 819 bridge->xclk = devm_clk_get(dev, "xclk"); 820 if (IS_ERR(bridge->xclk)) { 821 dev_err(dev, "failed to get xclk\n"); 822 return PTR_ERR(bridge->xclk); 823 } 824 825 clk_freq = clk_get_rate(bridge->xclk); 826 if (clk_freq < 6000000 || clk_freq > 27000000) { 827 dev_err(dev, "xclk freq must be in 6-27 Mhz range. got %d Hz\n", 828 clk_freq); 829 return -EINVAL; 830 } 831 832 bridge->reset_gpio = devm_gpiod_get_optional(dev, "reset", 833 GPIOD_OUT_HIGH); 834 835 if (IS_ERR(bridge->reset_gpio)) { 836 dev_err(dev, "failed to get reset GPIO\n"); 837 return PTR_ERR(bridge->reset_gpio); 838 } 839 840 ret = mipid02_get_regulators(bridge); 841 if (ret) { 842 dev_err(dev, "failed to get regulators %d", ret); 843 return ret; 844 } 845 846 /* Initialise the regmap for further cci access */ 847 bridge->regmap = devm_cci_regmap_init_i2c(client, 16); 848 if (IS_ERR(bridge->regmap)) 849 return dev_err_probe(dev, PTR_ERR(bridge->regmap), 850 "failed to get cci regmap\n"); 851 852 bridge->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 853 bridge->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE; 854 bridge->sd.internal_ops = &mipid02_subdev_internal_ops; 855 bridge->sd.entity.ops = &mipid02_subdev_entity_ops; 856 bridge->pad[0].flags = MEDIA_PAD_FL_SINK; 857 bridge->pad[1].flags = MEDIA_PAD_FL_SINK; 858 bridge->pad[2].flags = MEDIA_PAD_FL_SOURCE; 859 ret = media_entity_pads_init(&bridge->sd.entity, MIPID02_PAD_NB, 860 bridge->pad); 861 if (ret) { 862 dev_err(&client->dev, "pads init failed %d", ret); 863 return ret; 864 } 865 866 ret = v4l2_subdev_init_finalize(&bridge->sd); 867 if (ret < 0) { 868 dev_err(dev, "subdev init error: %d\n", ret); 869 goto entity_cleanup; 870 } 871 872 /* enable clock, power and reset device if available */ 873 ret = mipid02_set_power_on(&client->dev); 874 if (ret) 875 goto entity_cleanup; 876 877 ret = mipid02_detect(bridge); 878 if (ret) { 879 dev_err(&client->dev, "failed to detect mipid02 %d", ret); 880 goto power_off; 881 } 882 883 ret = mipid02_parse_tx_ep(bridge); 884 if (ret) { 885 dev_err(&client->dev, "failed to parse tx %d", ret); 886 goto power_off; 887 } 888 889 ret = mipid02_parse_rx_ep(bridge); 890 if (ret) { 891 dev_err(&client->dev, "failed to parse rx %d", ret); 892 goto power_off; 893 } 894 895 /* Enable runtime PM and turn off the device */ 896 pm_runtime_set_active(dev); 897 pm_runtime_get_noresume(&client->dev); 898 pm_runtime_enable(dev); 899 900 pm_runtime_set_autosuspend_delay(&client->dev, 1000); 901 pm_runtime_use_autosuspend(&client->dev); 902 pm_runtime_put_autosuspend(&client->dev); 903 904 ret = v4l2_async_register_subdev(&bridge->sd); 905 if (ret < 0) { 906 dev_err(&client->dev, "v4l2_async_register_subdev failed %d", 907 ret); 908 goto unregister_notifier; 909 } 910 911 dev_info(&client->dev, "mipid02 device probe successfully"); 912 913 return 0; 914 915 unregister_notifier: 916 v4l2_async_nf_unregister(&bridge->notifier); 917 v4l2_async_nf_cleanup(&bridge->notifier); 918 pm_runtime_disable(&client->dev); 919 pm_runtime_set_suspended(&client->dev); 920 power_off: 921 mipid02_set_power_off(&client->dev); 922 entity_cleanup: 923 media_entity_cleanup(&bridge->sd.entity); 924 925 return ret; 926 } 927 928 static void mipid02_remove(struct i2c_client *client) 929 { 930 struct v4l2_subdev *sd = i2c_get_clientdata(client); 931 struct mipid02_dev *bridge = to_mipid02_dev(sd); 932 933 v4l2_async_nf_unregister(&bridge->notifier); 934 v4l2_async_nf_cleanup(&bridge->notifier); 935 v4l2_async_unregister_subdev(&bridge->sd); 936 937 pm_runtime_disable(&client->dev); 938 if (!pm_runtime_status_suspended(&client->dev)) 939 mipid02_set_power_off(&client->dev); 940 pm_runtime_set_suspended(&client->dev); 941 media_entity_cleanup(&bridge->sd.entity); 942 } 943 944 static const struct of_device_id mipid02_dt_ids[] = { 945 { .compatible = "st,st-mipid02" }, 946 { /* sentinel */ } 947 }; 948 MODULE_DEVICE_TABLE(of, mipid02_dt_ids); 949 950 static const struct dev_pm_ops mipid02_pm_ops = { 951 RUNTIME_PM_OPS(mipid02_set_power_off, mipid02_set_power_on, NULL) 952 }; 953 954 static struct i2c_driver mipid02_i2c_driver = { 955 .driver = { 956 .name = "st-mipid02", 957 .of_match_table = mipid02_dt_ids, 958 .pm = pm_ptr(&mipid02_pm_ops), 959 }, 960 .probe = mipid02_probe, 961 .remove = mipid02_remove, 962 }; 963 964 module_i2c_driver(mipid02_i2c_driver); 965 966 MODULE_AUTHOR("Mickael Guene <mickael.guene@st.com>"); 967 MODULE_DESCRIPTION("STMicroelectronics MIPID02 CSI-2 bridge driver"); 968 MODULE_LICENSE("GPL v2"); 969