1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Driver for Samsung S5K5BAF UXGA 1/5" 2M CMOS Image Sensor 4 * with embedded SoC ISP. 5 * 6 * Copyright (C) 2013, Samsung Electronics Co., Ltd. 7 * Andrzej Hajda <a.hajda@samsung.com> 8 * 9 * Based on S5K6AA driver authored by Sylwester Nawrocki 10 * Copyright (C) 2013, Samsung Electronics Co., Ltd. 11 */ 12 13 #include <linux/clk.h> 14 #include <linux/delay.h> 15 #include <linux/firmware.h> 16 #include <linux/gpio/consumer.h> 17 #include <linux/i2c.h> 18 #include <linux/media.h> 19 #include <linux/module.h> 20 #include <linux/of_graph.h> 21 #include <linux/regulator/consumer.h> 22 #include <linux/slab.h> 23 24 #include <media/media-entity.h> 25 #include <media/v4l2-ctrls.h> 26 #include <media/v4l2-device.h> 27 #include <media/v4l2-subdev.h> 28 #include <media/v4l2-mediabus.h> 29 #include <media/v4l2-fwnode.h> 30 31 static int debug; 32 module_param(debug, int, 0644); 33 34 #define S5K5BAF_DRIVER_NAME "s5k5baf" 35 #define S5K5BAF_DEFAULT_MCLK_FREQ 24000000U 36 #define S5K5BAF_CLK_NAME "mclk" 37 38 #define S5K5BAF_FW_FILENAME "s5k5baf-cfg.bin" 39 #define S5K5BAF_FW_TAG "SF00" 40 #define S5K5BAG_FW_TAG_LEN 2 41 #define S5K5BAG_FW_MAX_COUNT 16 42 43 #define S5K5BAF_CIS_WIDTH 1600 44 #define S5K5BAF_CIS_HEIGHT 1200 45 #define S5K5BAF_WIN_WIDTH_MIN 8 46 #define S5K5BAF_WIN_HEIGHT_MIN 8 47 #define S5K5BAF_GAIN_RED_DEF 127 48 #define S5K5BAF_GAIN_GREEN_DEF 95 49 #define S5K5BAF_GAIN_BLUE_DEF 180 50 /* Default number of MIPI CSI-2 data lanes used */ 51 #define S5K5BAF_DEF_NUM_LANES 1 52 53 #define AHB_MSB_ADDR_PTR 0xfcfc 54 55 /* 56 * Register interface pages (the most significant word of the address) 57 */ 58 #define PAGE_IF_HW 0xd000 59 #define PAGE_IF_SW 0x7000 60 61 /* 62 * H/W register Interface (PAGE_IF_HW) 63 */ 64 #define REG_SW_LOAD_COMPLETE 0x0014 65 #define REG_CMDWR_PAGE 0x0028 66 #define REG_CMDWR_ADDR 0x002a 67 #define REG_CMDRD_PAGE 0x002c 68 #define REG_CMDRD_ADDR 0x002e 69 #define REG_CMD_BUF 0x0f12 70 #define REG_SET_HOST_INT 0x1000 71 #define REG_CLEAR_HOST_INT 0x1030 72 #define REG_PATTERN_SET 0x3100 73 #define REG_PATTERN_WIDTH 0x3118 74 #define REG_PATTERN_HEIGHT 0x311a 75 #define REG_PATTERN_PARAM 0x311c 76 77 /* 78 * S/W register interface (PAGE_IF_SW) 79 */ 80 81 /* Firmware revision information */ 82 #define REG_FW_APIVER 0x012e 83 #define S5K5BAF_FW_APIVER 0x0001 84 #define REG_FW_REVISION 0x0130 85 #define REG_FW_SENSOR_ID 0x0152 86 87 /* Initialization parameters */ 88 /* Master clock frequency in KHz */ 89 #define REG_I_INCLK_FREQ_L 0x01b8 90 #define REG_I_INCLK_FREQ_H 0x01ba 91 #define MIN_MCLK_FREQ_KHZ 6000U 92 #define MAX_MCLK_FREQ_KHZ 48000U 93 #define REG_I_USE_NPVI_CLOCKS 0x01c6 94 #define NPVI_CLOCKS 1 95 #define REG_I_USE_NMIPI_CLOCKS 0x01c8 96 #define NMIPI_CLOCKS 1 97 #define REG_I_BLOCK_INTERNAL_PLL_CALC 0x01ca 98 99 /* Clock configurations, n = 0..2. REG_I_* frequency unit is 4 kHz. */ 100 #define REG_I_OPCLK_4KHZ(n) ((n) * 6 + 0x01cc) 101 #define REG_I_MIN_OUTRATE_4KHZ(n) ((n) * 6 + 0x01ce) 102 #define REG_I_MAX_OUTRATE_4KHZ(n) ((n) * 6 + 0x01d0) 103 #define SCLK_PVI_FREQ 24000 104 #define SCLK_MIPI_FREQ 48000 105 #define PCLK_MIN_FREQ 6000 106 #define PCLK_MAX_FREQ 48000 107 #define REG_I_USE_REGS_API 0x01de 108 #define REG_I_INIT_PARAMS_UPDATED 0x01e0 109 #define REG_I_ERROR_INFO 0x01e2 110 111 /* General purpose parameters */ 112 #define REG_USER_BRIGHTNESS 0x01e4 113 #define REG_USER_CONTRAST 0x01e6 114 #define REG_USER_SATURATION 0x01e8 115 #define REG_USER_SHARPBLUR 0x01ea 116 117 #define REG_G_SPEC_EFFECTS 0x01ee 118 #define REG_G_ENABLE_PREV 0x01f0 119 #define REG_G_ENABLE_PREV_CHG 0x01f2 120 #define REG_G_NEW_CFG_SYNC 0x01f8 121 #define REG_G_PREVREQ_IN_WIDTH 0x01fa 122 #define REG_G_PREVREQ_IN_HEIGHT 0x01fc 123 #define REG_G_PREVREQ_IN_XOFFS 0x01fe 124 #define REG_G_PREVREQ_IN_YOFFS 0x0200 125 #define REG_G_PREVZOOM_IN_WIDTH 0x020a 126 #define REG_G_PREVZOOM_IN_HEIGHT 0x020c 127 #define REG_G_PREVZOOM_IN_XOFFS 0x020e 128 #define REG_G_PREVZOOM_IN_YOFFS 0x0210 129 #define REG_G_INPUTS_CHANGE_REQ 0x021a 130 #define REG_G_ACTIVE_PREV_CFG 0x021c 131 #define REG_G_PREV_CFG_CHG 0x021e 132 #define REG_G_PREV_OPEN_AFTER_CH 0x0220 133 #define REG_G_PREV_CFG_ERROR 0x0222 134 #define CFG_ERROR_RANGE 0x0b 135 #define REG_G_PREV_CFG_BYPASS_CHANGED 0x022a 136 #define REG_G_ACTUAL_P_FR_TIME 0x023a 137 #define REG_G_ACTUAL_P_OUT_RATE 0x023c 138 #define REG_G_ACTUAL_C_FR_TIME 0x023e 139 #define REG_G_ACTUAL_C_OUT_RATE 0x0240 140 141 /* Preview control section. n = 0...4. */ 142 #define PREG(n, x) ((n) * 0x26 + x) 143 #define REG_P_OUT_WIDTH(n) PREG(n, 0x0242) 144 #define REG_P_OUT_HEIGHT(n) PREG(n, 0x0244) 145 #define REG_P_FMT(n) PREG(n, 0x0246) 146 #define REG_P_MAX_OUT_RATE(n) PREG(n, 0x0248) 147 #define REG_P_MIN_OUT_RATE(n) PREG(n, 0x024a) 148 #define REG_P_PVI_MASK(n) PREG(n, 0x024c) 149 #define PVI_MASK_MIPI 0x52 150 #define REG_P_CLK_INDEX(n) PREG(n, 0x024e) 151 #define CLK_PVI_INDEX 0 152 #define CLK_MIPI_INDEX NPVI_CLOCKS 153 #define REG_P_FR_RATE_TYPE(n) PREG(n, 0x0250) 154 #define FR_RATE_DYNAMIC 0 155 #define FR_RATE_FIXED 1 156 #define FR_RATE_FIXED_ACCURATE 2 157 #define REG_P_FR_RATE_Q_TYPE(n) PREG(n, 0x0252) 158 #define FR_RATE_Q_DYNAMIC 0 159 #define FR_RATE_Q_BEST_FRRATE 1 /* Binning enabled */ 160 #define FR_RATE_Q_BEST_QUALITY 2 /* Binning disabled */ 161 /* Frame period in 0.1 ms units */ 162 #define REG_P_MAX_FR_TIME(n) PREG(n, 0x0254) 163 #define REG_P_MIN_FR_TIME(n) PREG(n, 0x0256) 164 #define S5K5BAF_MIN_FR_TIME 333 /* x100 us */ 165 #define S5K5BAF_MAX_FR_TIME 6500 /* x100 us */ 166 /* The below 5 registers are for "device correction" values */ 167 #define REG_P_SATURATION(n) PREG(n, 0x0258) 168 #define REG_P_SHARP_BLUR(n) PREG(n, 0x025a) 169 #define REG_P_GLAMOUR(n) PREG(n, 0x025c) 170 #define REG_P_COLORTEMP(n) PREG(n, 0x025e) 171 #define REG_P_GAMMA_INDEX(n) PREG(n, 0x0260) 172 #define REG_P_PREV_MIRROR(n) PREG(n, 0x0262) 173 #define REG_P_CAP_MIRROR(n) PREG(n, 0x0264) 174 #define REG_P_CAP_ROTATION(n) PREG(n, 0x0266) 175 176 /* Extended image property controls */ 177 /* Exposure time in 10 us units */ 178 #define REG_SF_USR_EXPOSURE_L 0x03bc 179 #define REG_SF_USR_EXPOSURE_H 0x03be 180 #define REG_SF_USR_EXPOSURE_CHG 0x03c0 181 #define REG_SF_USR_TOT_GAIN 0x03c2 182 #define REG_SF_USR_TOT_GAIN_CHG 0x03c4 183 #define REG_SF_RGAIN 0x03c6 184 #define REG_SF_RGAIN_CHG 0x03c8 185 #define REG_SF_GGAIN 0x03ca 186 #define REG_SF_GGAIN_CHG 0x03cc 187 #define REG_SF_BGAIN 0x03ce 188 #define REG_SF_BGAIN_CHG 0x03d0 189 #define REG_SF_WBGAIN_CHG 0x03d2 190 #define REG_SF_FLICKER_QUANT 0x03d4 191 #define REG_SF_FLICKER_QUANT_CHG 0x03d6 192 193 /* Output interface (parallel/MIPI) setup */ 194 #define REG_OIF_EN_MIPI_LANES 0x03f2 195 #define REG_OIF_EN_PACKETS 0x03f4 196 #define EN_PACKETS_CSI2 0xc3 197 #define REG_OIF_CFG_CHG 0x03f6 198 199 /* Auto-algorithms enable mask */ 200 #define REG_DBG_AUTOALG_EN 0x03f8 201 #define AALG_ALL_EN BIT(0) 202 #define AALG_AE_EN BIT(1) 203 #define AALG_DIVLEI_EN BIT(2) 204 #define AALG_WB_EN BIT(3) 205 #define AALG_USE_WB_FOR_ISP BIT(4) 206 #define AALG_FLICKER_EN BIT(5) 207 #define AALG_FIT_EN BIT(6) 208 #define AALG_WRHW_EN BIT(7) 209 210 /* Pointers to color correction matrices */ 211 #define REG_PTR_CCM_HORIZON 0x06d0 212 #define REG_PTR_CCM_INCANDESCENT 0x06d4 213 #define REG_PTR_CCM_WARM_WHITE 0x06d8 214 #define REG_PTR_CCM_COOL_WHITE 0x06dc 215 #define REG_PTR_CCM_DL50 0x06e0 216 #define REG_PTR_CCM_DL65 0x06e4 217 #define REG_PTR_CCM_OUTDOOR 0x06ec 218 219 #define REG_ARR_CCM(n) (0x2800 + 36 * (n)) 220 221 static const char * const s5k5baf_supply_names[] = { 222 "vdda", /* Analog power supply 2.8V (2.6V to 3.0V) */ 223 "vddreg", /* Regulator input power supply 1.8V (1.7V to 1.9V) 224 or 2.8V (2.6V to 3.0) */ 225 "vddio", /* I/O power supply 1.8V (1.65V to 1.95V) 226 or 2.8V (2.5V to 3.1V) */ 227 }; 228 #define S5K5BAF_NUM_SUPPLIES ARRAY_SIZE(s5k5baf_supply_names) 229 230 enum s5k5baf_gpio_id { 231 STBY, 232 RSET, 233 NUM_GPIOS, 234 }; 235 236 #define PAD_CIS 0 237 #define PAD_OUT 1 238 #define NUM_CIS_PADS 1 239 #define NUM_ISP_PADS 2 240 241 struct s5k5baf_pixfmt { 242 u32 code; 243 u32 colorspace; 244 /* REG_P_FMT(x) register value */ 245 u16 reg_p_fmt; 246 }; 247 248 struct s5k5baf_ctrls { 249 struct v4l2_ctrl_handler handler; 250 struct { /* Auto / manual white balance cluster */ 251 struct v4l2_ctrl *awb; 252 struct v4l2_ctrl *gain_red; 253 struct v4l2_ctrl *gain_blue; 254 }; 255 struct { /* Mirror cluster */ 256 struct v4l2_ctrl *hflip; 257 struct v4l2_ctrl *vflip; 258 }; 259 struct { /* Auto exposure / manual exposure and gain cluster */ 260 struct v4l2_ctrl *auto_exp; 261 struct v4l2_ctrl *exposure; 262 struct v4l2_ctrl *gain; 263 }; 264 }; 265 266 enum { 267 S5K5BAF_FW_ID_PATCH, 268 S5K5BAF_FW_ID_CCM, 269 S5K5BAF_FW_ID_CIS, 270 }; 271 272 struct s5k5baf_fw { 273 u16 count; 274 struct { 275 u16 id; 276 u16 offset; 277 } seq[]; 278 }; 279 280 struct s5k5baf { 281 struct gpio_desc *gpios[NUM_GPIOS]; 282 enum v4l2_mbus_type bus_type; 283 u8 nlanes; 284 struct regulator_bulk_data supplies[S5K5BAF_NUM_SUPPLIES]; 285 286 struct clk *clock; 287 288 struct s5k5baf_fw *fw; 289 290 struct v4l2_subdev cis_sd; 291 struct media_pad cis_pad; 292 293 struct v4l2_subdev sd; 294 struct media_pad pads[NUM_ISP_PADS]; 295 296 /* protects the struct members below */ 297 struct mutex lock; 298 299 int error; 300 301 struct v4l2_rect crop_sink; 302 struct v4l2_rect compose; 303 struct v4l2_rect crop_source; 304 /* index to s5k5baf_formats array */ 305 int pixfmt; 306 /* actual frame interval in 100us */ 307 u16 fiv; 308 /* requested frame interval in 100us */ 309 u16 req_fiv; 310 /* cache for REG_DBG_AUTOALG_EN register */ 311 u16 auto_alg; 312 313 struct s5k5baf_ctrls ctrls; 314 315 unsigned int streaming:1; 316 unsigned int apply_cfg:1; 317 unsigned int apply_crop:1; 318 unsigned int valid_auto_alg:1; 319 unsigned int power; 320 }; 321 322 static const struct s5k5baf_pixfmt s5k5baf_formats[] = { 323 { MEDIA_BUS_FMT_VYUY8_2X8, V4L2_COLORSPACE_JPEG, 5 }, 324 /* range 16-240 */ 325 { MEDIA_BUS_FMT_VYUY8_2X8, V4L2_COLORSPACE_REC709, 6 }, 326 { MEDIA_BUS_FMT_RGB565_2X8_BE, V4L2_COLORSPACE_JPEG, 0 }, 327 }; 328 329 static struct v4l2_rect s5k5baf_cis_rect = { 330 0, 0, S5K5BAF_CIS_WIDTH, S5K5BAF_CIS_HEIGHT 331 }; 332 333 /* Setfile contains set of I2C command sequences. Each sequence has its ID. 334 * setfile format: 335 * u8 magic[4]; 336 * u16 count; number of sequences 337 * struct { 338 * u16 id; sequence id 339 * u16 offset; sequence offset in data array 340 * } seq[count]; 341 * u16 data[*]; array containing sequences 342 * 343 */ 344 static int s5k5baf_fw_parse(struct device *dev, struct s5k5baf_fw **fw, 345 size_t count, const __le16 *data) 346 { 347 struct s5k5baf_fw *f; 348 u16 *d, i, *end; 349 int ret; 350 351 if (count < S5K5BAG_FW_TAG_LEN + 1) { 352 dev_err(dev, "firmware file too short (%zu)\n", count); 353 return -EINVAL; 354 } 355 356 ret = memcmp(data, S5K5BAF_FW_TAG, S5K5BAG_FW_TAG_LEN * sizeof(u16)); 357 if (ret != 0) { 358 dev_err(dev, "invalid firmware magic number\n"); 359 return -EINVAL; 360 } 361 362 data += S5K5BAG_FW_TAG_LEN; 363 count -= S5K5BAG_FW_TAG_LEN; 364 365 d = devm_kcalloc(dev, count, sizeof(u16), GFP_KERNEL); 366 if (!d) 367 return -ENOMEM; 368 369 for (i = 0; i < count; ++i) 370 d[i] = le16_to_cpu(data[i]); 371 372 f = (struct s5k5baf_fw *)d; 373 if (count < 1 + 2 * f->count) { 374 dev_err(dev, "invalid firmware header (count=%d size=%zu)\n", 375 f->count, 2 * (count + S5K5BAG_FW_TAG_LEN)); 376 return -EINVAL; 377 } 378 end = d + count; 379 d += 1 + 2 * f->count; 380 381 for (i = 0; i < f->count; ++i) { 382 if (f->seq[i].offset + d <= end) 383 continue; 384 dev_err(dev, "invalid firmware header (seq=%d)\n", i); 385 return -EINVAL; 386 } 387 388 *fw = f; 389 390 return 0; 391 } 392 393 static inline struct v4l2_subdev *ctrl_to_sd(struct v4l2_ctrl *ctrl) 394 { 395 return &container_of(ctrl->handler, struct s5k5baf, ctrls.handler)->sd; 396 } 397 398 static inline bool s5k5baf_is_cis_subdev(struct v4l2_subdev *sd) 399 { 400 return sd->entity.function == MEDIA_ENT_F_CAM_SENSOR; 401 } 402 403 static inline struct s5k5baf *to_s5k5baf(struct v4l2_subdev *sd) 404 { 405 if (s5k5baf_is_cis_subdev(sd)) 406 return container_of(sd, struct s5k5baf, cis_sd); 407 else 408 return container_of(sd, struct s5k5baf, sd); 409 } 410 411 static u16 s5k5baf_i2c_read(struct s5k5baf *state, u16 addr) 412 { 413 struct i2c_client *c = v4l2_get_subdevdata(&state->sd); 414 __be16 w, r; 415 u16 res; 416 struct i2c_msg msg[] = { 417 { .addr = c->addr, .flags = 0, 418 .len = 2, .buf = (u8 *)&w }, 419 { .addr = c->addr, .flags = I2C_M_RD, 420 .len = 2, .buf = (u8 *)&r }, 421 }; 422 int ret; 423 424 if (state->error) 425 return 0; 426 427 w = cpu_to_be16(addr); 428 ret = i2c_transfer(c->adapter, msg, 2); 429 res = be16_to_cpu(r); 430 431 v4l2_dbg(3, debug, c, "i2c_read: 0x%04x : 0x%04x\n", addr, res); 432 433 if (ret != 2) { 434 v4l2_err(c, "i2c_read: error during transfer (%d)\n", ret); 435 state->error = ret; 436 } 437 return res; 438 } 439 440 static void s5k5baf_i2c_write(struct s5k5baf *state, u16 addr, u16 val) 441 { 442 u8 buf[4] = { addr >> 8, addr & 0xFF, val >> 8, val & 0xFF }; 443 struct i2c_client *c = v4l2_get_subdevdata(&state->sd); 444 int ret; 445 446 if (state->error) 447 return; 448 449 ret = i2c_master_send(c, buf, 4); 450 v4l2_dbg(3, debug, c, "i2c_write: 0x%04x : 0x%04x\n", addr, val); 451 452 if (ret != 4) { 453 v4l2_err(c, "i2c_write: error during transfer (%d)\n", ret); 454 state->error = ret; 455 } 456 } 457 458 static u16 s5k5baf_read(struct s5k5baf *state, u16 addr) 459 { 460 s5k5baf_i2c_write(state, REG_CMDRD_ADDR, addr); 461 return s5k5baf_i2c_read(state, REG_CMD_BUF); 462 } 463 464 static void s5k5baf_write(struct s5k5baf *state, u16 addr, u16 val) 465 { 466 s5k5baf_i2c_write(state, REG_CMDWR_ADDR, addr); 467 s5k5baf_i2c_write(state, REG_CMD_BUF, val); 468 } 469 470 static void s5k5baf_write_arr_seq(struct s5k5baf *state, u16 addr, 471 u16 count, const u16 *seq) 472 { 473 struct i2c_client *c = v4l2_get_subdevdata(&state->sd); 474 __be16 buf[65]; 475 476 s5k5baf_i2c_write(state, REG_CMDWR_ADDR, addr); 477 if (state->error) 478 return; 479 480 v4l2_dbg(3, debug, c, "i2c_write_seq(count=%d): %*ph\n", count, 481 min(2 * count, 64), seq); 482 483 buf[0] = cpu_to_be16(REG_CMD_BUF); 484 485 while (count > 0) { 486 int n = min_t(int, count, ARRAY_SIZE(buf) - 1); 487 int ret, i; 488 489 for (i = 1; i <= n; ++i) 490 buf[i] = cpu_to_be16(*seq++); 491 492 i *= 2; 493 ret = i2c_master_send(c, (char *)buf, i); 494 if (ret != i) { 495 v4l2_err(c, "i2c_write_seq: error during transfer (%d)\n", ret); 496 state->error = ret; 497 break; 498 } 499 500 count -= n; 501 } 502 } 503 504 #define s5k5baf_write_seq(state, addr, seq...) \ 505 s5k5baf_write_arr_seq(state, addr, sizeof((char[]){ seq }), \ 506 (const u16 []){ seq }) 507 508 /* add items count at the beginning of the list */ 509 #define NSEQ(seq...) sizeof((char[]){ seq }), seq 510 511 /* 512 * s5k5baf_write_nseq() - Writes sequences of values to sensor memory via i2c 513 * @nseq: sequence of u16 words in format: 514 * (N, address, value[1]...value[N-1])*,0 515 * Ex.: 516 * u16 seq[] = { NSEQ(0x4000, 1, 1), NSEQ(0x4010, 640, 480), 0 }; 517 * ret = s5k5baf_write_nseq(c, seq); 518 */ 519 static void s5k5baf_write_nseq(struct s5k5baf *state, const u16 *nseq) 520 { 521 int count; 522 523 while ((count = *nseq++)) { 524 u16 addr = *nseq++; 525 --count; 526 527 s5k5baf_write_arr_seq(state, addr, count, nseq); 528 nseq += count; 529 } 530 } 531 532 static void s5k5baf_synchronize(struct s5k5baf *state, int timeout, u16 addr) 533 { 534 unsigned long end = jiffies + msecs_to_jiffies(timeout); 535 u16 reg; 536 537 s5k5baf_write(state, addr, 1); 538 do { 539 reg = s5k5baf_read(state, addr); 540 if (state->error || !reg) 541 return; 542 usleep_range(5000, 10000); 543 } while (time_is_after_jiffies(end)); 544 545 v4l2_err(&state->sd, "timeout on register synchronize (%#x)\n", addr); 546 state->error = -ETIMEDOUT; 547 } 548 549 static u16 *s5k5baf_fw_get_seq(struct s5k5baf *state, u16 seq_id) 550 { 551 struct s5k5baf_fw *fw = state->fw; 552 u16 *data; 553 int i; 554 555 if (fw == NULL) 556 return NULL; 557 558 data = &fw->seq[0].id + 2 * fw->count; 559 560 for (i = 0; i < fw->count; ++i) { 561 if (fw->seq[i].id == seq_id) 562 return data + fw->seq[i].offset; 563 } 564 565 return NULL; 566 } 567 568 static void s5k5baf_hw_patch(struct s5k5baf *state) 569 { 570 u16 *seq = s5k5baf_fw_get_seq(state, S5K5BAF_FW_ID_PATCH); 571 572 if (seq) 573 s5k5baf_write_nseq(state, seq); 574 } 575 576 static void s5k5baf_hw_set_clocks(struct s5k5baf *state) 577 { 578 unsigned long mclk = clk_get_rate(state->clock) / 1000; 579 u16 status; 580 static const u16 nseq_clk_cfg[] = { 581 NSEQ(REG_I_USE_NPVI_CLOCKS, 582 NPVI_CLOCKS, NMIPI_CLOCKS, 0, 583 SCLK_PVI_FREQ / 4, PCLK_MIN_FREQ / 4, PCLK_MAX_FREQ / 4, 584 SCLK_MIPI_FREQ / 4, PCLK_MIN_FREQ / 4, PCLK_MAX_FREQ / 4), 585 NSEQ(REG_I_USE_REGS_API, 1), 586 0 587 }; 588 589 s5k5baf_write_seq(state, REG_I_INCLK_FREQ_L, mclk & 0xffff, mclk >> 16); 590 s5k5baf_write_nseq(state, nseq_clk_cfg); 591 592 s5k5baf_synchronize(state, 250, REG_I_INIT_PARAMS_UPDATED); 593 status = s5k5baf_read(state, REG_I_ERROR_INFO); 594 if (!state->error && status) { 595 v4l2_err(&state->sd, "error configuring PLL (%d)\n", status); 596 state->error = -EINVAL; 597 } 598 } 599 600 /* set custom color correction matrices for various illuminations */ 601 static void s5k5baf_hw_set_ccm(struct s5k5baf *state) 602 { 603 u16 *seq = s5k5baf_fw_get_seq(state, S5K5BAF_FW_ID_CCM); 604 605 if (seq) 606 s5k5baf_write_nseq(state, seq); 607 } 608 609 /* CIS sensor tuning, based on undocumented android driver code */ 610 static void s5k5baf_hw_set_cis(struct s5k5baf *state) 611 { 612 u16 *seq = s5k5baf_fw_get_seq(state, S5K5BAF_FW_ID_CIS); 613 614 if (!seq) 615 return; 616 617 s5k5baf_i2c_write(state, REG_CMDWR_PAGE, PAGE_IF_HW); 618 s5k5baf_write_nseq(state, seq); 619 s5k5baf_i2c_write(state, REG_CMDWR_PAGE, PAGE_IF_SW); 620 } 621 622 static void s5k5baf_hw_sync_cfg(struct s5k5baf *state) 623 { 624 s5k5baf_write(state, REG_G_PREV_CFG_CHG, 1); 625 if (state->apply_crop) { 626 s5k5baf_write(state, REG_G_INPUTS_CHANGE_REQ, 1); 627 s5k5baf_write(state, REG_G_PREV_CFG_BYPASS_CHANGED, 1); 628 } 629 s5k5baf_synchronize(state, 500, REG_G_NEW_CFG_SYNC); 630 } 631 /* Set horizontal and vertical image flipping */ 632 static void s5k5baf_hw_set_mirror(struct s5k5baf *state) 633 { 634 u16 flip = state->ctrls.vflip->val | (state->ctrls.vflip->val << 1); 635 636 s5k5baf_write(state, REG_P_PREV_MIRROR(0), flip); 637 if (state->streaming) 638 s5k5baf_hw_sync_cfg(state); 639 } 640 641 static void s5k5baf_hw_set_alg(struct s5k5baf *state, u16 alg, bool enable) 642 { 643 u16 cur_alg, new_alg; 644 645 if (!state->valid_auto_alg) 646 cur_alg = s5k5baf_read(state, REG_DBG_AUTOALG_EN); 647 else 648 cur_alg = state->auto_alg; 649 650 new_alg = enable ? (cur_alg | alg) : (cur_alg & ~alg); 651 652 if (new_alg != cur_alg) 653 s5k5baf_write(state, REG_DBG_AUTOALG_EN, new_alg); 654 655 if (state->error) 656 return; 657 658 state->valid_auto_alg = 1; 659 state->auto_alg = new_alg; 660 } 661 662 /* Configure auto/manual white balance and R/G/B gains */ 663 static void s5k5baf_hw_set_awb(struct s5k5baf *state, int awb) 664 { 665 struct s5k5baf_ctrls *ctrls = &state->ctrls; 666 667 if (!awb) 668 s5k5baf_write_seq(state, REG_SF_RGAIN, 669 ctrls->gain_red->val, 1, 670 S5K5BAF_GAIN_GREEN_DEF, 1, 671 ctrls->gain_blue->val, 1, 672 1); 673 674 s5k5baf_hw_set_alg(state, AALG_WB_EN, awb); 675 } 676 677 /* Program FW with exposure time, 'exposure' in us units */ 678 static void s5k5baf_hw_set_user_exposure(struct s5k5baf *state, int exposure) 679 { 680 unsigned int time = exposure / 10; 681 682 s5k5baf_write_seq(state, REG_SF_USR_EXPOSURE_L, 683 time & 0xffff, time >> 16, 1); 684 } 685 686 static void s5k5baf_hw_set_user_gain(struct s5k5baf *state, int gain) 687 { 688 s5k5baf_write_seq(state, REG_SF_USR_TOT_GAIN, gain, 1); 689 } 690 691 /* Set auto/manual exposure and total gain */ 692 static void s5k5baf_hw_set_auto_exposure(struct s5k5baf *state, int value) 693 { 694 if (value == V4L2_EXPOSURE_AUTO) { 695 s5k5baf_hw_set_alg(state, AALG_AE_EN | AALG_DIVLEI_EN, true); 696 } else { 697 unsigned int exp_time = state->ctrls.exposure->val; 698 699 s5k5baf_hw_set_user_exposure(state, exp_time); 700 s5k5baf_hw_set_user_gain(state, state->ctrls.gain->val); 701 s5k5baf_hw_set_alg(state, AALG_AE_EN | AALG_DIVLEI_EN, false); 702 } 703 } 704 705 static void s5k5baf_hw_set_anti_flicker(struct s5k5baf *state, int v) 706 { 707 if (v == V4L2_CID_POWER_LINE_FREQUENCY_AUTO) { 708 s5k5baf_hw_set_alg(state, AALG_FLICKER_EN, true); 709 } else { 710 /* The V4L2_CID_LINE_FREQUENCY control values match 711 * the register values */ 712 s5k5baf_write_seq(state, REG_SF_FLICKER_QUANT, v, 1); 713 s5k5baf_hw_set_alg(state, AALG_FLICKER_EN, false); 714 } 715 } 716 717 static void s5k5baf_hw_set_colorfx(struct s5k5baf *state, int val) 718 { 719 static const u16 colorfx[] = { 720 [V4L2_COLORFX_NONE] = 0, 721 [V4L2_COLORFX_BW] = 1, 722 [V4L2_COLORFX_NEGATIVE] = 2, 723 [V4L2_COLORFX_SEPIA] = 3, 724 [V4L2_COLORFX_SKY_BLUE] = 4, 725 [V4L2_COLORFX_SKETCH] = 5, 726 }; 727 728 s5k5baf_write(state, REG_G_SPEC_EFFECTS, colorfx[val]); 729 } 730 731 static int s5k5baf_find_pixfmt(struct v4l2_mbus_framefmt *mf) 732 { 733 int i, c = -1; 734 735 for (i = 0; i < ARRAY_SIZE(s5k5baf_formats); i++) { 736 if (mf->colorspace != s5k5baf_formats[i].colorspace) 737 continue; 738 if (mf->code == s5k5baf_formats[i].code) 739 return i; 740 if (c < 0) 741 c = i; 742 } 743 return (c < 0) ? 0 : c; 744 } 745 746 static int s5k5baf_clear_error(struct s5k5baf *state) 747 { 748 int ret = state->error; 749 750 state->error = 0; 751 return ret; 752 } 753 754 static int s5k5baf_hw_set_video_bus(struct s5k5baf *state) 755 { 756 u16 en_pkts; 757 758 if (state->bus_type == V4L2_MBUS_CSI2_DPHY) 759 en_pkts = EN_PACKETS_CSI2; 760 else 761 en_pkts = 0; 762 763 s5k5baf_write_seq(state, REG_OIF_EN_MIPI_LANES, 764 state->nlanes, en_pkts, 1); 765 766 return s5k5baf_clear_error(state); 767 } 768 769 static u16 s5k5baf_get_cfg_error(struct s5k5baf *state) 770 { 771 u16 err = s5k5baf_read(state, REG_G_PREV_CFG_ERROR); 772 if (err) 773 s5k5baf_write(state, REG_G_PREV_CFG_ERROR, 0); 774 return err; 775 } 776 777 static void s5k5baf_hw_set_fiv(struct s5k5baf *state, u16 fiv) 778 { 779 s5k5baf_write(state, REG_P_MAX_FR_TIME(0), fiv); 780 s5k5baf_hw_sync_cfg(state); 781 } 782 783 static void s5k5baf_hw_find_min_fiv(struct s5k5baf *state) 784 { 785 u16 err, fiv; 786 int n; 787 788 fiv = s5k5baf_read(state, REG_G_ACTUAL_P_FR_TIME); 789 if (state->error) 790 return; 791 792 for (n = 5; n > 0; --n) { 793 s5k5baf_hw_set_fiv(state, fiv); 794 err = s5k5baf_get_cfg_error(state); 795 if (state->error) 796 return; 797 switch (err) { 798 case CFG_ERROR_RANGE: 799 ++fiv; 800 break; 801 case 0: 802 state->fiv = fiv; 803 v4l2_info(&state->sd, 804 "found valid frame interval: %d00us\n", fiv); 805 return; 806 default: 807 v4l2_err(&state->sd, 808 "error setting frame interval: %d\n", err); 809 state->error = -EINVAL; 810 } 811 } 812 v4l2_err(&state->sd, "cannot find correct frame interval\n"); 813 state->error = -ERANGE; 814 } 815 816 static void s5k5baf_hw_validate_cfg(struct s5k5baf *state) 817 { 818 u16 err; 819 820 err = s5k5baf_get_cfg_error(state); 821 if (state->error) 822 return; 823 824 switch (err) { 825 case 0: 826 state->apply_cfg = 1; 827 return; 828 case CFG_ERROR_RANGE: 829 s5k5baf_hw_find_min_fiv(state); 830 if (!state->error) 831 state->apply_cfg = 1; 832 return; 833 default: 834 v4l2_err(&state->sd, 835 "error setting format: %d\n", err); 836 state->error = -EINVAL; 837 } 838 } 839 840 static void s5k5baf_rescale(struct v4l2_rect *r, const struct v4l2_rect *v, 841 const struct v4l2_rect *n, 842 const struct v4l2_rect *d) 843 { 844 r->left = v->left * n->width / d->width; 845 r->top = v->top * n->height / d->height; 846 r->width = v->width * n->width / d->width; 847 r->height = v->height * n->height / d->height; 848 } 849 850 static int s5k5baf_hw_set_crop_rects(struct s5k5baf *state) 851 { 852 struct v4l2_rect *p, r; 853 u16 err; 854 int ret; 855 856 p = &state->crop_sink; 857 s5k5baf_write_seq(state, REG_G_PREVREQ_IN_WIDTH, p->width, p->height, 858 p->left, p->top); 859 860 s5k5baf_rescale(&r, &state->crop_source, &state->crop_sink, 861 &state->compose); 862 s5k5baf_write_seq(state, REG_G_PREVZOOM_IN_WIDTH, r.width, r.height, 863 r.left, r.top); 864 865 s5k5baf_synchronize(state, 500, REG_G_INPUTS_CHANGE_REQ); 866 s5k5baf_synchronize(state, 500, REG_G_PREV_CFG_BYPASS_CHANGED); 867 err = s5k5baf_get_cfg_error(state); 868 ret = s5k5baf_clear_error(state); 869 if (ret < 0) 870 return ret; 871 872 switch (err) { 873 case 0: 874 break; 875 case CFG_ERROR_RANGE: 876 /* retry crop with frame interval set to max */ 877 s5k5baf_hw_set_fiv(state, S5K5BAF_MAX_FR_TIME); 878 err = s5k5baf_get_cfg_error(state); 879 ret = s5k5baf_clear_error(state); 880 if (ret < 0) 881 return ret; 882 if (err) { 883 v4l2_err(&state->sd, 884 "crop error on max frame interval: %d\n", err); 885 state->error = -EINVAL; 886 } 887 s5k5baf_hw_set_fiv(state, state->req_fiv); 888 s5k5baf_hw_validate_cfg(state); 889 break; 890 default: 891 v4l2_err(&state->sd, "crop error: %d\n", err); 892 return -EINVAL; 893 } 894 895 if (!state->apply_cfg) 896 return 0; 897 898 p = &state->crop_source; 899 s5k5baf_write_seq(state, REG_P_OUT_WIDTH(0), p->width, p->height); 900 s5k5baf_hw_set_fiv(state, state->req_fiv); 901 s5k5baf_hw_validate_cfg(state); 902 903 return s5k5baf_clear_error(state); 904 } 905 906 static void s5k5baf_hw_set_config(struct s5k5baf *state) 907 { 908 u16 reg_fmt = s5k5baf_formats[state->pixfmt].reg_p_fmt; 909 struct v4l2_rect *r = &state->crop_source; 910 911 s5k5baf_write_seq(state, REG_P_OUT_WIDTH(0), 912 r->width, r->height, reg_fmt, 913 PCLK_MAX_FREQ >> 2, PCLK_MIN_FREQ >> 2, 914 PVI_MASK_MIPI, CLK_MIPI_INDEX, 915 FR_RATE_FIXED, FR_RATE_Q_DYNAMIC, 916 state->req_fiv, S5K5BAF_MIN_FR_TIME); 917 s5k5baf_hw_sync_cfg(state); 918 s5k5baf_hw_validate_cfg(state); 919 } 920 921 922 static void s5k5baf_hw_set_test_pattern(struct s5k5baf *state, int id) 923 { 924 s5k5baf_i2c_write(state, REG_PATTERN_WIDTH, 800); 925 s5k5baf_i2c_write(state, REG_PATTERN_HEIGHT, 511); 926 s5k5baf_i2c_write(state, REG_PATTERN_PARAM, 0); 927 s5k5baf_i2c_write(state, REG_PATTERN_SET, id); 928 } 929 930 static void s5k5baf_gpio_assert(struct s5k5baf *state, int id) 931 { 932 gpiod_set_value_cansleep(state->gpios[id], 1); 933 } 934 935 static void s5k5baf_gpio_deassert(struct s5k5baf *state, int id) 936 { 937 gpiod_set_value_cansleep(state->gpios[id], 0); 938 } 939 940 static int s5k5baf_power_on(struct s5k5baf *state) 941 { 942 int ret; 943 944 ret = regulator_bulk_enable(S5K5BAF_NUM_SUPPLIES, state->supplies); 945 if (ret < 0) 946 goto err; 947 948 ret = clk_prepare_enable(state->clock); 949 if (ret < 0) 950 goto err_reg_dis; 951 952 v4l2_dbg(1, debug, &state->sd, "clock frequency: %ld\n", 953 clk_get_rate(state->clock)); 954 955 s5k5baf_gpio_deassert(state, STBY); 956 usleep_range(50, 100); 957 s5k5baf_gpio_deassert(state, RSET); 958 return 0; 959 960 err_reg_dis: 961 regulator_bulk_disable(S5K5BAF_NUM_SUPPLIES, state->supplies); 962 err: 963 v4l2_err(&state->sd, "%s() failed (%d)\n", __func__, ret); 964 return ret; 965 } 966 967 static int s5k5baf_power_off(struct s5k5baf *state) 968 { 969 int ret; 970 971 state->streaming = 0; 972 state->apply_cfg = 0; 973 state->apply_crop = 0; 974 975 s5k5baf_gpio_assert(state, RSET); 976 s5k5baf_gpio_assert(state, STBY); 977 978 if (!IS_ERR(state->clock)) 979 clk_disable_unprepare(state->clock); 980 981 ret = regulator_bulk_disable(S5K5BAF_NUM_SUPPLIES, 982 state->supplies); 983 if (ret < 0) 984 v4l2_err(&state->sd, "failed to disable regulators\n"); 985 986 return 0; 987 } 988 989 static void s5k5baf_hw_init(struct s5k5baf *state) 990 { 991 s5k5baf_i2c_write(state, AHB_MSB_ADDR_PTR, PAGE_IF_HW); 992 s5k5baf_i2c_write(state, REG_CLEAR_HOST_INT, 0); 993 s5k5baf_i2c_write(state, REG_SW_LOAD_COMPLETE, 1); 994 s5k5baf_i2c_write(state, REG_CMDRD_PAGE, PAGE_IF_SW); 995 s5k5baf_i2c_write(state, REG_CMDWR_PAGE, PAGE_IF_SW); 996 } 997 998 /* 999 * V4L2 subdev core and video operations 1000 */ 1001 1002 static void s5k5baf_initialize_data(struct s5k5baf *state) 1003 { 1004 state->pixfmt = 0; 1005 state->req_fiv = 10000 / 15; 1006 state->fiv = state->req_fiv; 1007 state->valid_auto_alg = 0; 1008 } 1009 1010 static int s5k5baf_load_setfile(struct s5k5baf *state) 1011 { 1012 struct i2c_client *c = v4l2_get_subdevdata(&state->sd); 1013 const struct firmware *fw; 1014 int ret; 1015 1016 ret = request_firmware(&fw, S5K5BAF_FW_FILENAME, &c->dev); 1017 if (ret < 0) { 1018 dev_warn(&c->dev, "firmware file (%s) not loaded\n", 1019 S5K5BAF_FW_FILENAME); 1020 return ret; 1021 } 1022 1023 ret = s5k5baf_fw_parse(&c->dev, &state->fw, fw->size / 2, 1024 (__le16 *)fw->data); 1025 1026 release_firmware(fw); 1027 1028 return ret; 1029 } 1030 1031 static int s5k5baf_set_power(struct v4l2_subdev *sd, int on) 1032 { 1033 struct s5k5baf *state = to_s5k5baf(sd); 1034 int ret = 0; 1035 1036 mutex_lock(&state->lock); 1037 1038 if (state->power != !on) 1039 goto out; 1040 1041 if (on) { 1042 if (state->fw == NULL) 1043 s5k5baf_load_setfile(state); 1044 1045 s5k5baf_initialize_data(state); 1046 ret = s5k5baf_power_on(state); 1047 if (ret < 0) 1048 goto out; 1049 1050 s5k5baf_hw_init(state); 1051 s5k5baf_hw_patch(state); 1052 s5k5baf_i2c_write(state, REG_SET_HOST_INT, 1); 1053 s5k5baf_hw_set_clocks(state); 1054 1055 ret = s5k5baf_hw_set_video_bus(state); 1056 if (ret < 0) 1057 goto out; 1058 1059 s5k5baf_hw_set_cis(state); 1060 s5k5baf_hw_set_ccm(state); 1061 1062 ret = s5k5baf_clear_error(state); 1063 if (!ret) 1064 state->power++; 1065 } else { 1066 s5k5baf_power_off(state); 1067 state->power--; 1068 } 1069 1070 out: 1071 mutex_unlock(&state->lock); 1072 1073 if (!ret && on) 1074 ret = v4l2_ctrl_handler_setup(&state->ctrls.handler); 1075 1076 return ret; 1077 } 1078 1079 static void s5k5baf_hw_set_stream(struct s5k5baf *state, int enable) 1080 { 1081 s5k5baf_write_seq(state, REG_G_ENABLE_PREV, enable, 1); 1082 } 1083 1084 static int s5k5baf_s_stream(struct v4l2_subdev *sd, int on) 1085 { 1086 struct s5k5baf *state = to_s5k5baf(sd); 1087 int ret; 1088 1089 mutex_lock(&state->lock); 1090 1091 if (state->streaming == !!on) { 1092 ret = 0; 1093 goto out; 1094 } 1095 1096 if (on) { 1097 s5k5baf_hw_set_config(state); 1098 ret = s5k5baf_hw_set_crop_rects(state); 1099 if (ret < 0) 1100 goto out; 1101 s5k5baf_hw_set_stream(state, 1); 1102 s5k5baf_i2c_write(state, 0xb0cc, 0x000b); 1103 } else { 1104 s5k5baf_hw_set_stream(state, 0); 1105 } 1106 ret = s5k5baf_clear_error(state); 1107 if (!ret) 1108 state->streaming = !state->streaming; 1109 1110 out: 1111 mutex_unlock(&state->lock); 1112 1113 return ret; 1114 } 1115 1116 static int s5k5baf_get_frame_interval(struct v4l2_subdev *sd, 1117 struct v4l2_subdev_state *sd_state, 1118 struct v4l2_subdev_frame_interval *fi) 1119 { 1120 struct s5k5baf *state = to_s5k5baf(sd); 1121 1122 /* 1123 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2 1124 * subdev active state API. 1125 */ 1126 if (fi->which != V4L2_SUBDEV_FORMAT_ACTIVE) 1127 return -EINVAL; 1128 1129 mutex_lock(&state->lock); 1130 fi->interval.numerator = state->fiv; 1131 fi->interval.denominator = 10000; 1132 mutex_unlock(&state->lock); 1133 1134 return 0; 1135 } 1136 1137 static void __s5k5baf_set_frame_interval(struct s5k5baf *state, 1138 struct v4l2_subdev_frame_interval *fi) 1139 { 1140 struct v4l2_fract *i = &fi->interval; 1141 1142 if (fi->interval.denominator == 0) 1143 state->req_fiv = S5K5BAF_MAX_FR_TIME; 1144 else 1145 state->req_fiv = clamp_t(u32, 1146 i->numerator * 10000 / i->denominator, 1147 S5K5BAF_MIN_FR_TIME, 1148 S5K5BAF_MAX_FR_TIME); 1149 1150 state->fiv = state->req_fiv; 1151 if (state->apply_cfg) { 1152 s5k5baf_hw_set_fiv(state, state->req_fiv); 1153 s5k5baf_hw_validate_cfg(state); 1154 } 1155 *i = (struct v4l2_fract){ state->fiv, 10000 }; 1156 if (state->fiv == state->req_fiv) 1157 v4l2_info(&state->sd, "frame interval changed to %d00us\n", 1158 state->fiv); 1159 } 1160 1161 static int s5k5baf_set_frame_interval(struct v4l2_subdev *sd, 1162 struct v4l2_subdev_state *sd_state, 1163 struct v4l2_subdev_frame_interval *fi) 1164 { 1165 struct s5k5baf *state = to_s5k5baf(sd); 1166 1167 /* 1168 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2 1169 * subdev active state API. 1170 */ 1171 if (fi->which != V4L2_SUBDEV_FORMAT_ACTIVE) 1172 return -EINVAL; 1173 1174 mutex_lock(&state->lock); 1175 __s5k5baf_set_frame_interval(state, fi); 1176 mutex_unlock(&state->lock); 1177 return 0; 1178 } 1179 1180 /* 1181 * V4L2 subdev pad level and video operations 1182 */ 1183 static int s5k5baf_enum_frame_interval(struct v4l2_subdev *sd, 1184 struct v4l2_subdev_state *sd_state, 1185 struct v4l2_subdev_frame_interval_enum *fie) 1186 { 1187 if (fie->index > S5K5BAF_MAX_FR_TIME - S5K5BAF_MIN_FR_TIME || 1188 fie->pad != PAD_CIS) 1189 return -EINVAL; 1190 1191 v4l_bound_align_image(&fie->width, S5K5BAF_WIN_WIDTH_MIN, 1192 S5K5BAF_CIS_WIDTH, 1, 1193 &fie->height, S5K5BAF_WIN_HEIGHT_MIN, 1194 S5K5BAF_CIS_HEIGHT, 1, 0); 1195 1196 fie->interval.numerator = S5K5BAF_MIN_FR_TIME + fie->index; 1197 fie->interval.denominator = 10000; 1198 1199 return 0; 1200 } 1201 1202 static int s5k5baf_enum_mbus_code(struct v4l2_subdev *sd, 1203 struct v4l2_subdev_state *sd_state, 1204 struct v4l2_subdev_mbus_code_enum *code) 1205 { 1206 if (code->pad == PAD_CIS) { 1207 if (code->index > 0) 1208 return -EINVAL; 1209 code->code = MEDIA_BUS_FMT_FIXED; 1210 return 0; 1211 } 1212 1213 if (code->index >= ARRAY_SIZE(s5k5baf_formats)) 1214 return -EINVAL; 1215 1216 code->code = s5k5baf_formats[code->index].code; 1217 return 0; 1218 } 1219 1220 static int s5k5baf_enum_frame_size(struct v4l2_subdev *sd, 1221 struct v4l2_subdev_state *sd_state, 1222 struct v4l2_subdev_frame_size_enum *fse) 1223 { 1224 int i; 1225 1226 if (fse->index > 0) 1227 return -EINVAL; 1228 1229 if (fse->pad == PAD_CIS) { 1230 fse->code = MEDIA_BUS_FMT_FIXED; 1231 fse->min_width = S5K5BAF_CIS_WIDTH; 1232 fse->max_width = S5K5BAF_CIS_WIDTH; 1233 fse->min_height = S5K5BAF_CIS_HEIGHT; 1234 fse->max_height = S5K5BAF_CIS_HEIGHT; 1235 return 0; 1236 } 1237 1238 i = ARRAY_SIZE(s5k5baf_formats); 1239 while (--i) 1240 if (fse->code == s5k5baf_formats[i].code) 1241 break; 1242 fse->code = s5k5baf_formats[i].code; 1243 fse->min_width = S5K5BAF_WIN_WIDTH_MIN; 1244 fse->max_width = S5K5BAF_CIS_WIDTH; 1245 fse->max_height = S5K5BAF_WIN_HEIGHT_MIN; 1246 fse->min_height = S5K5BAF_CIS_HEIGHT; 1247 1248 return 0; 1249 } 1250 1251 static void s5k5baf_try_cis_format(struct v4l2_mbus_framefmt *mf) 1252 { 1253 mf->width = S5K5BAF_CIS_WIDTH; 1254 mf->height = S5K5BAF_CIS_HEIGHT; 1255 mf->code = MEDIA_BUS_FMT_FIXED; 1256 mf->colorspace = V4L2_COLORSPACE_JPEG; 1257 mf->field = V4L2_FIELD_NONE; 1258 } 1259 1260 static int s5k5baf_try_isp_format(struct v4l2_mbus_framefmt *mf) 1261 { 1262 int pixfmt; 1263 1264 v4l_bound_align_image(&mf->width, S5K5BAF_WIN_WIDTH_MIN, 1265 S5K5BAF_CIS_WIDTH, 1, 1266 &mf->height, S5K5BAF_WIN_HEIGHT_MIN, 1267 S5K5BAF_CIS_HEIGHT, 1, 0); 1268 1269 pixfmt = s5k5baf_find_pixfmt(mf); 1270 1271 mf->colorspace = s5k5baf_formats[pixfmt].colorspace; 1272 mf->code = s5k5baf_formats[pixfmt].code; 1273 mf->field = V4L2_FIELD_NONE; 1274 1275 return pixfmt; 1276 } 1277 1278 static int s5k5baf_get_fmt(struct v4l2_subdev *sd, 1279 struct v4l2_subdev_state *sd_state, 1280 struct v4l2_subdev_format *fmt) 1281 { 1282 struct s5k5baf *state = to_s5k5baf(sd); 1283 const struct s5k5baf_pixfmt *pixfmt; 1284 struct v4l2_mbus_framefmt *mf; 1285 1286 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { 1287 mf = v4l2_subdev_state_get_format(sd_state, fmt->pad); 1288 fmt->format = *mf; 1289 return 0; 1290 } 1291 1292 mf = &fmt->format; 1293 if (fmt->pad == PAD_CIS) { 1294 s5k5baf_try_cis_format(mf); 1295 return 0; 1296 } 1297 mf->field = V4L2_FIELD_NONE; 1298 mutex_lock(&state->lock); 1299 pixfmt = &s5k5baf_formats[state->pixfmt]; 1300 mf->width = state->crop_source.width; 1301 mf->height = state->crop_source.height; 1302 mf->code = pixfmt->code; 1303 mf->colorspace = pixfmt->colorspace; 1304 mutex_unlock(&state->lock); 1305 1306 return 0; 1307 } 1308 1309 static int s5k5baf_set_fmt(struct v4l2_subdev *sd, 1310 struct v4l2_subdev_state *sd_state, 1311 struct v4l2_subdev_format *fmt) 1312 { 1313 struct v4l2_mbus_framefmt *mf = &fmt->format; 1314 struct s5k5baf *state = to_s5k5baf(sd); 1315 const struct s5k5baf_pixfmt *pixfmt; 1316 int ret = 0; 1317 1318 mf->field = V4L2_FIELD_NONE; 1319 1320 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { 1321 *v4l2_subdev_state_get_format(sd_state, fmt->pad) = *mf; 1322 return 0; 1323 } 1324 1325 if (fmt->pad == PAD_CIS) { 1326 s5k5baf_try_cis_format(mf); 1327 return 0; 1328 } 1329 1330 mutex_lock(&state->lock); 1331 1332 if (state->streaming) { 1333 mutex_unlock(&state->lock); 1334 return -EBUSY; 1335 } 1336 1337 state->pixfmt = s5k5baf_try_isp_format(mf); 1338 pixfmt = &s5k5baf_formats[state->pixfmt]; 1339 mf->code = pixfmt->code; 1340 mf->colorspace = pixfmt->colorspace; 1341 mf->width = state->crop_source.width; 1342 mf->height = state->crop_source.height; 1343 1344 mutex_unlock(&state->lock); 1345 return ret; 1346 } 1347 1348 enum selection_rect { R_CIS, R_CROP_SINK, R_COMPOSE, R_CROP_SOURCE, R_INVALID }; 1349 1350 static enum selection_rect s5k5baf_get_sel_rect(u32 pad, u32 target) 1351 { 1352 switch (target) { 1353 case V4L2_SEL_TGT_CROP_BOUNDS: 1354 return pad ? R_COMPOSE : R_CIS; 1355 case V4L2_SEL_TGT_CROP: 1356 return pad ? R_CROP_SOURCE : R_CROP_SINK; 1357 case V4L2_SEL_TGT_COMPOSE_BOUNDS: 1358 return pad ? R_INVALID : R_CROP_SINK; 1359 case V4L2_SEL_TGT_COMPOSE: 1360 return pad ? R_INVALID : R_COMPOSE; 1361 default: 1362 return R_INVALID; 1363 } 1364 } 1365 1366 static int s5k5baf_is_bound_target(u32 target) 1367 { 1368 return target == V4L2_SEL_TGT_CROP_BOUNDS || 1369 target == V4L2_SEL_TGT_COMPOSE_BOUNDS; 1370 } 1371 1372 static int s5k5baf_get_selection(struct v4l2_subdev *sd, 1373 struct v4l2_subdev_state *sd_state, 1374 struct v4l2_subdev_selection *sel) 1375 { 1376 enum selection_rect rtype; 1377 struct s5k5baf *state = to_s5k5baf(sd); 1378 1379 rtype = s5k5baf_get_sel_rect(sel->pad, sel->target); 1380 1381 switch (rtype) { 1382 case R_INVALID: 1383 return -EINVAL; 1384 case R_CIS: 1385 sel->r = s5k5baf_cis_rect; 1386 return 0; 1387 default: 1388 break; 1389 } 1390 1391 if (sel->which == V4L2_SUBDEV_FORMAT_TRY) { 1392 if (rtype == R_COMPOSE) 1393 sel->r = *v4l2_subdev_state_get_compose(sd_state, 1394 sel->pad); 1395 else 1396 sel->r = *v4l2_subdev_state_get_crop(sd_state, 1397 sel->pad); 1398 return 0; 1399 } 1400 1401 mutex_lock(&state->lock); 1402 switch (rtype) { 1403 case R_CROP_SINK: 1404 sel->r = state->crop_sink; 1405 break; 1406 case R_COMPOSE: 1407 sel->r = state->compose; 1408 break; 1409 case R_CROP_SOURCE: 1410 sel->r = state->crop_source; 1411 break; 1412 default: 1413 break; 1414 } 1415 if (s5k5baf_is_bound_target(sel->target)) { 1416 sel->r.left = 0; 1417 sel->r.top = 0; 1418 } 1419 mutex_unlock(&state->lock); 1420 1421 return 0; 1422 } 1423 1424 /* bounds range [start, start+len) to [0, max) and aligns to 2 */ 1425 static void s5k5baf_bound_range(u32 *start, u32 *len, u32 max) 1426 { 1427 if (*len > max) 1428 *len = max; 1429 if (*start + *len > max) 1430 *start = max - *len; 1431 *start &= ~1; 1432 *len &= ~1; 1433 if (*len < S5K5BAF_WIN_WIDTH_MIN) 1434 *len = S5K5BAF_WIN_WIDTH_MIN; 1435 } 1436 1437 static void s5k5baf_bound_rect(struct v4l2_rect *r, u32 width, u32 height) 1438 { 1439 s5k5baf_bound_range(&r->left, &r->width, width); 1440 s5k5baf_bound_range(&r->top, &r->height, height); 1441 } 1442 1443 static void s5k5baf_set_rect_and_adjust(struct v4l2_rect **rects, 1444 enum selection_rect first, 1445 struct v4l2_rect *v) 1446 { 1447 struct v4l2_rect *r, *br; 1448 enum selection_rect i = first; 1449 1450 *rects[first] = *v; 1451 do { 1452 r = rects[i]; 1453 br = rects[i - 1]; 1454 s5k5baf_bound_rect(r, br->width, br->height); 1455 } while (++i != R_INVALID); 1456 *v = *rects[first]; 1457 } 1458 1459 static bool s5k5baf_cmp_rect(const struct v4l2_rect *r1, 1460 const struct v4l2_rect *r2) 1461 { 1462 return !memcmp(r1, r2, sizeof(*r1)); 1463 } 1464 1465 static int s5k5baf_set_selection(struct v4l2_subdev *sd, 1466 struct v4l2_subdev_state *sd_state, 1467 struct v4l2_subdev_selection *sel) 1468 { 1469 static enum selection_rect rtype; 1470 struct s5k5baf *state = to_s5k5baf(sd); 1471 struct v4l2_rect **rects; 1472 int ret = 0; 1473 1474 rtype = s5k5baf_get_sel_rect(sel->pad, sel->target); 1475 if (rtype == R_INVALID || s5k5baf_is_bound_target(sel->target)) 1476 return -EINVAL; 1477 1478 /* allow only scaling on compose */ 1479 if (rtype == R_COMPOSE) { 1480 sel->r.left = 0; 1481 sel->r.top = 0; 1482 } 1483 1484 if (sel->which == V4L2_SUBDEV_FORMAT_TRY) { 1485 rects = (struct v4l2_rect * []) { 1486 &s5k5baf_cis_rect, 1487 v4l2_subdev_state_get_crop(sd_state, PAD_CIS), 1488 v4l2_subdev_state_get_compose(sd_state, PAD_CIS), 1489 v4l2_subdev_state_get_crop(sd_state, PAD_OUT) 1490 }; 1491 s5k5baf_set_rect_and_adjust(rects, rtype, &sel->r); 1492 return 0; 1493 } 1494 1495 rects = (struct v4l2_rect * []) { 1496 &s5k5baf_cis_rect, 1497 &state->crop_sink, 1498 &state->compose, 1499 &state->crop_source 1500 }; 1501 mutex_lock(&state->lock); 1502 if (state->streaming) { 1503 /* adjust sel->r to avoid output resolution change */ 1504 if (rtype < R_CROP_SOURCE) { 1505 if (sel->r.width < state->crop_source.width) 1506 sel->r.width = state->crop_source.width; 1507 if (sel->r.height < state->crop_source.height) 1508 sel->r.height = state->crop_source.height; 1509 } else { 1510 sel->r.width = state->crop_source.width; 1511 sel->r.height = state->crop_source.height; 1512 } 1513 } 1514 s5k5baf_set_rect_and_adjust(rects, rtype, &sel->r); 1515 if (!s5k5baf_cmp_rect(&state->crop_sink, &s5k5baf_cis_rect) || 1516 !s5k5baf_cmp_rect(&state->compose, &s5k5baf_cis_rect)) 1517 state->apply_crop = 1; 1518 if (state->streaming) 1519 ret = s5k5baf_hw_set_crop_rects(state); 1520 mutex_unlock(&state->lock); 1521 1522 return ret; 1523 } 1524 1525 static const struct v4l2_subdev_pad_ops s5k5baf_cis_pad_ops = { 1526 .enum_mbus_code = s5k5baf_enum_mbus_code, 1527 .enum_frame_size = s5k5baf_enum_frame_size, 1528 .get_fmt = s5k5baf_get_fmt, 1529 .set_fmt = s5k5baf_set_fmt, 1530 }; 1531 1532 static const struct v4l2_subdev_pad_ops s5k5baf_pad_ops = { 1533 .enum_mbus_code = s5k5baf_enum_mbus_code, 1534 .enum_frame_size = s5k5baf_enum_frame_size, 1535 .enum_frame_interval = s5k5baf_enum_frame_interval, 1536 .get_fmt = s5k5baf_get_fmt, 1537 .set_fmt = s5k5baf_set_fmt, 1538 .get_selection = s5k5baf_get_selection, 1539 .set_selection = s5k5baf_set_selection, 1540 .get_frame_interval = s5k5baf_get_frame_interval, 1541 .set_frame_interval = s5k5baf_set_frame_interval, 1542 }; 1543 1544 static const struct v4l2_subdev_video_ops s5k5baf_video_ops = { 1545 .s_stream = s5k5baf_s_stream, 1546 }; 1547 1548 /* 1549 * V4L2 subdev controls 1550 */ 1551 1552 static int s5k5baf_s_ctrl(struct v4l2_ctrl *ctrl) 1553 { 1554 struct v4l2_subdev *sd = ctrl_to_sd(ctrl); 1555 struct s5k5baf *state = to_s5k5baf(sd); 1556 int ret; 1557 1558 v4l2_dbg(1, debug, sd, "ctrl: %s, value: %d\n", ctrl->name, ctrl->val); 1559 1560 mutex_lock(&state->lock); 1561 1562 if (state->power == 0) 1563 goto unlock; 1564 1565 switch (ctrl->id) { 1566 case V4L2_CID_AUTO_WHITE_BALANCE: 1567 s5k5baf_hw_set_awb(state, ctrl->val); 1568 break; 1569 1570 case V4L2_CID_BRIGHTNESS: 1571 s5k5baf_write(state, REG_USER_BRIGHTNESS, ctrl->val); 1572 break; 1573 1574 case V4L2_CID_COLORFX: 1575 s5k5baf_hw_set_colorfx(state, ctrl->val); 1576 break; 1577 1578 case V4L2_CID_CONTRAST: 1579 s5k5baf_write(state, REG_USER_CONTRAST, ctrl->val); 1580 break; 1581 1582 case V4L2_CID_EXPOSURE_AUTO: 1583 s5k5baf_hw_set_auto_exposure(state, ctrl->val); 1584 break; 1585 1586 case V4L2_CID_HFLIP: 1587 s5k5baf_hw_set_mirror(state); 1588 break; 1589 1590 case V4L2_CID_POWER_LINE_FREQUENCY: 1591 s5k5baf_hw_set_anti_flicker(state, ctrl->val); 1592 break; 1593 1594 case V4L2_CID_SATURATION: 1595 s5k5baf_write(state, REG_USER_SATURATION, ctrl->val); 1596 break; 1597 1598 case V4L2_CID_SHARPNESS: 1599 s5k5baf_write(state, REG_USER_SHARPBLUR, ctrl->val); 1600 break; 1601 1602 case V4L2_CID_WHITE_BALANCE_TEMPERATURE: 1603 s5k5baf_write(state, REG_P_COLORTEMP(0), ctrl->val); 1604 if (state->apply_cfg) 1605 s5k5baf_hw_sync_cfg(state); 1606 break; 1607 1608 case V4L2_CID_TEST_PATTERN: 1609 s5k5baf_hw_set_test_pattern(state, ctrl->val); 1610 break; 1611 } 1612 unlock: 1613 ret = s5k5baf_clear_error(state); 1614 mutex_unlock(&state->lock); 1615 return ret; 1616 } 1617 1618 static const struct v4l2_ctrl_ops s5k5baf_ctrl_ops = { 1619 .s_ctrl = s5k5baf_s_ctrl, 1620 }; 1621 1622 static const char * const s5k5baf_test_pattern_menu[] = { 1623 "Disabled", 1624 "Blank", 1625 "Bars", 1626 "Gradients", 1627 "Textile", 1628 "Textile2", 1629 "Squares" 1630 }; 1631 1632 static int s5k5baf_initialize_ctrls(struct s5k5baf *state) 1633 { 1634 const struct v4l2_ctrl_ops *ops = &s5k5baf_ctrl_ops; 1635 struct s5k5baf_ctrls *ctrls = &state->ctrls; 1636 struct v4l2_ctrl_handler *hdl = &ctrls->handler; 1637 int ret; 1638 1639 ret = v4l2_ctrl_handler_init(hdl, 16); 1640 if (ret < 0) { 1641 v4l2_err(&state->sd, "cannot init ctrl handler (%d)\n", ret); 1642 return ret; 1643 } 1644 1645 /* Auto white balance cluster */ 1646 ctrls->awb = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_AUTO_WHITE_BALANCE, 1647 0, 1, 1, 1); 1648 ctrls->gain_red = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_RED_BALANCE, 1649 0, 255, 1, S5K5BAF_GAIN_RED_DEF); 1650 ctrls->gain_blue = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BLUE_BALANCE, 1651 0, 255, 1, S5K5BAF_GAIN_BLUE_DEF); 1652 v4l2_ctrl_auto_cluster(3, &ctrls->awb, 0, false); 1653 1654 ctrls->hflip = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_HFLIP, 0, 1, 1, 0); 1655 ctrls->vflip = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_VFLIP, 0, 1, 1, 0); 1656 v4l2_ctrl_cluster(2, &ctrls->hflip); 1657 1658 ctrls->auto_exp = v4l2_ctrl_new_std_menu(hdl, ops, 1659 V4L2_CID_EXPOSURE_AUTO, 1660 V4L2_EXPOSURE_MANUAL, 0, V4L2_EXPOSURE_AUTO); 1661 /* Exposure time: x 1 us */ 1662 ctrls->exposure = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_EXPOSURE, 1663 0, 6000000U, 1, 100000U); 1664 /* Total gain: 256 <=> 1x */ 1665 ctrls->gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAIN, 1666 0, 256, 1, 256); 1667 v4l2_ctrl_auto_cluster(3, &ctrls->auto_exp, 0, false); 1668 1669 v4l2_ctrl_new_std_menu(hdl, ops, V4L2_CID_POWER_LINE_FREQUENCY, 1670 V4L2_CID_POWER_LINE_FREQUENCY_AUTO, 0, 1671 V4L2_CID_POWER_LINE_FREQUENCY_AUTO); 1672 1673 v4l2_ctrl_new_std_menu(hdl, ops, V4L2_CID_COLORFX, 1674 V4L2_COLORFX_SKY_BLUE, ~0x6f, V4L2_COLORFX_NONE); 1675 1676 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_WHITE_BALANCE_TEMPERATURE, 1677 0, 256, 1, 0); 1678 1679 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_SATURATION, -127, 127, 1, 0); 1680 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS, -127, 127, 1, 0); 1681 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -127, 127, 1, 0); 1682 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_SHARPNESS, -127, 127, 1, 0); 1683 1684 v4l2_ctrl_new_std_menu_items(hdl, ops, V4L2_CID_TEST_PATTERN, 1685 ARRAY_SIZE(s5k5baf_test_pattern_menu) - 1, 1686 0, 0, s5k5baf_test_pattern_menu); 1687 1688 if (hdl->error) { 1689 v4l2_err(&state->sd, "error creating controls (%d)\n", 1690 hdl->error); 1691 ret = hdl->error; 1692 v4l2_ctrl_handler_free(hdl); 1693 return ret; 1694 } 1695 1696 state->sd.ctrl_handler = hdl; 1697 return 0; 1698 } 1699 1700 /* 1701 * V4L2 subdev internal operations 1702 */ 1703 static int s5k5baf_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) 1704 { 1705 struct v4l2_mbus_framefmt *mf; 1706 1707 mf = v4l2_subdev_state_get_format(fh->state, PAD_CIS); 1708 s5k5baf_try_cis_format(mf); 1709 1710 if (s5k5baf_is_cis_subdev(sd)) 1711 return 0; 1712 1713 mf = v4l2_subdev_state_get_format(fh->state, PAD_OUT); 1714 mf->colorspace = s5k5baf_formats[0].colorspace; 1715 mf->code = s5k5baf_formats[0].code; 1716 mf->width = s5k5baf_cis_rect.width; 1717 mf->height = s5k5baf_cis_rect.height; 1718 mf->field = V4L2_FIELD_NONE; 1719 1720 *v4l2_subdev_state_get_crop(fh->state, PAD_CIS) = s5k5baf_cis_rect; 1721 *v4l2_subdev_state_get_compose(fh->state, PAD_CIS) = s5k5baf_cis_rect; 1722 *v4l2_subdev_state_get_crop(fh->state, PAD_OUT) = s5k5baf_cis_rect; 1723 1724 return 0; 1725 } 1726 1727 static int s5k5baf_check_fw_revision(struct s5k5baf *state) 1728 { 1729 u16 api_ver = 0, fw_rev = 0, s_id = 0; 1730 int ret; 1731 1732 api_ver = s5k5baf_read(state, REG_FW_APIVER); 1733 fw_rev = s5k5baf_read(state, REG_FW_REVISION) & 0xff; 1734 s_id = s5k5baf_read(state, REG_FW_SENSOR_ID); 1735 ret = s5k5baf_clear_error(state); 1736 if (ret < 0) 1737 return ret; 1738 1739 v4l2_info(&state->sd, "FW API=%#x, revision=%#x sensor_id=%#x\n", 1740 api_ver, fw_rev, s_id); 1741 1742 if (api_ver != S5K5BAF_FW_APIVER) { 1743 v4l2_err(&state->sd, "FW API version not supported\n"); 1744 return -ENODEV; 1745 } 1746 1747 return 0; 1748 } 1749 1750 static int s5k5baf_registered(struct v4l2_subdev *sd) 1751 { 1752 struct s5k5baf *state = to_s5k5baf(sd); 1753 int ret; 1754 1755 ret = v4l2_device_register_subdev(sd->v4l2_dev, &state->cis_sd); 1756 if (ret < 0) 1757 v4l2_err(sd, "failed to register subdev %s\n", 1758 state->cis_sd.name); 1759 else 1760 ret = media_create_pad_link(&state->cis_sd.entity, PAD_CIS, 1761 &state->sd.entity, PAD_CIS, 1762 MEDIA_LNK_FL_IMMUTABLE | 1763 MEDIA_LNK_FL_ENABLED); 1764 return ret; 1765 } 1766 1767 static void s5k5baf_unregistered(struct v4l2_subdev *sd) 1768 { 1769 struct s5k5baf *state = to_s5k5baf(sd); 1770 v4l2_device_unregister_subdev(&state->cis_sd); 1771 } 1772 1773 static const struct v4l2_subdev_ops s5k5baf_cis_subdev_ops = { 1774 .pad = &s5k5baf_cis_pad_ops, 1775 }; 1776 1777 static const struct v4l2_subdev_internal_ops s5k5baf_cis_subdev_internal_ops = { 1778 .open = s5k5baf_open, 1779 }; 1780 1781 static const struct v4l2_subdev_internal_ops s5k5baf_subdev_internal_ops = { 1782 .registered = s5k5baf_registered, 1783 .unregistered = s5k5baf_unregistered, 1784 .open = s5k5baf_open, 1785 }; 1786 1787 static const struct v4l2_subdev_core_ops s5k5baf_core_ops = { 1788 .s_power = s5k5baf_set_power, 1789 .log_status = v4l2_ctrl_subdev_log_status, 1790 }; 1791 1792 static const struct v4l2_subdev_ops s5k5baf_subdev_ops = { 1793 .core = &s5k5baf_core_ops, 1794 .pad = &s5k5baf_pad_ops, 1795 .video = &s5k5baf_video_ops, 1796 }; 1797 1798 static int s5k5baf_configure_gpios(struct s5k5baf *state) 1799 { 1800 static const char * const name[] = { "stbyn", "rstn" }; 1801 static const char * const label[] = { "S5K5BAF_STBY", "S5K5BAF_RST" }; 1802 struct i2c_client *c = v4l2_get_subdevdata(&state->sd); 1803 struct gpio_desc *gpio; 1804 int ret, i; 1805 1806 for (i = 0; i < NUM_GPIOS; ++i) { 1807 gpio = devm_gpiod_get(&c->dev, name[i], GPIOD_OUT_HIGH); 1808 ret = PTR_ERR_OR_ZERO(gpio); 1809 if (ret) { 1810 v4l2_err(c, "failed to request gpio %s: %d\n", 1811 name[i], ret); 1812 return ret; 1813 } 1814 1815 ret = gpiod_set_consumer_name(gpio, label[i]); 1816 if (ret) { 1817 v4l2_err(c, "failed to set up name for gpio %s: %d\n", 1818 name[i], ret); 1819 return ret; 1820 } 1821 1822 state->gpios[i] = gpio; 1823 } 1824 return 0; 1825 } 1826 1827 static int s5k5baf_parse_device_node(struct s5k5baf *state, struct device *dev) 1828 { 1829 struct device_node *node = dev->of_node; 1830 struct device_node *node_ep; 1831 struct v4l2_fwnode_endpoint ep = { .bus_type = 0 }; 1832 int ret; 1833 1834 if (!node) { 1835 dev_err(dev, "no device-tree node provided\n"); 1836 return -EINVAL; 1837 } 1838 1839 node_ep = of_graph_get_endpoint_by_regs(node, 0, -1); 1840 if (!node_ep) { 1841 dev_err(dev, "no endpoint defined at node %pOF\n", node); 1842 return -EINVAL; 1843 } 1844 1845 ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(node_ep), &ep); 1846 of_node_put(node_ep); 1847 if (ret) 1848 return ret; 1849 1850 state->bus_type = ep.bus_type; 1851 1852 switch (state->bus_type) { 1853 case V4L2_MBUS_CSI2_DPHY: 1854 state->nlanes = ep.bus.mipi_csi2.num_data_lanes; 1855 break; 1856 case V4L2_MBUS_PARALLEL: 1857 break; 1858 default: 1859 dev_err(dev, "unsupported bus in endpoint defined at node %pOF\n", 1860 node); 1861 return -EINVAL; 1862 } 1863 1864 return 0; 1865 } 1866 1867 static int s5k5baf_configure_subdevs(struct s5k5baf *state, 1868 struct i2c_client *c) 1869 { 1870 struct v4l2_subdev *sd; 1871 int ret; 1872 1873 sd = &state->cis_sd; 1874 v4l2_subdev_init(sd, &s5k5baf_cis_subdev_ops); 1875 sd->owner = THIS_MODULE; 1876 v4l2_set_subdevdata(sd, state); 1877 snprintf(sd->name, sizeof(sd->name), "S5K5BAF-CIS %d-%04x", 1878 i2c_adapter_id(c->adapter), c->addr); 1879 1880 sd->internal_ops = &s5k5baf_cis_subdev_internal_ops; 1881 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1882 1883 state->cis_pad.flags = MEDIA_PAD_FL_SOURCE; 1884 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR; 1885 ret = media_entity_pads_init(&sd->entity, NUM_CIS_PADS, &state->cis_pad); 1886 if (ret < 0) 1887 goto err; 1888 1889 sd = &state->sd; 1890 v4l2_i2c_subdev_init(sd, c, &s5k5baf_subdev_ops); 1891 snprintf(sd->name, sizeof(sd->name), "S5K5BAF-ISP %d-%04x", 1892 i2c_adapter_id(c->adapter), c->addr); 1893 1894 sd->internal_ops = &s5k5baf_subdev_internal_ops; 1895 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1896 1897 state->pads[PAD_CIS].flags = MEDIA_PAD_FL_SINK; 1898 state->pads[PAD_OUT].flags = MEDIA_PAD_FL_SOURCE; 1899 sd->entity.function = MEDIA_ENT_F_V4L2_SUBDEV_UNKNOWN; 1900 ret = media_entity_pads_init(&sd->entity, NUM_ISP_PADS, state->pads); 1901 1902 if (!ret) 1903 return 0; 1904 1905 media_entity_cleanup(&state->cis_sd.entity); 1906 err: 1907 dev_err(&c->dev, "cannot init media entity %s\n", sd->name); 1908 return ret; 1909 } 1910 1911 static int s5k5baf_configure_regulators(struct s5k5baf *state) 1912 { 1913 struct i2c_client *c = v4l2_get_subdevdata(&state->sd); 1914 int ret; 1915 int i; 1916 1917 for (i = 0; i < S5K5BAF_NUM_SUPPLIES; i++) 1918 state->supplies[i].supply = s5k5baf_supply_names[i]; 1919 1920 ret = devm_regulator_bulk_get(&c->dev, S5K5BAF_NUM_SUPPLIES, 1921 state->supplies); 1922 if (ret < 0) 1923 v4l2_err(c, "failed to get regulators\n"); 1924 return ret; 1925 } 1926 1927 static int s5k5baf_probe(struct i2c_client *c) 1928 { 1929 struct s5k5baf *state; 1930 int ret; 1931 1932 state = devm_kzalloc(&c->dev, sizeof(*state), GFP_KERNEL); 1933 if (!state) 1934 return -ENOMEM; 1935 1936 mutex_init(&state->lock); 1937 state->crop_sink = s5k5baf_cis_rect; 1938 state->compose = s5k5baf_cis_rect; 1939 state->crop_source = s5k5baf_cis_rect; 1940 1941 ret = s5k5baf_parse_device_node(state, &c->dev); 1942 if (ret < 0) 1943 return ret; 1944 1945 ret = s5k5baf_configure_subdevs(state, c); 1946 if (ret < 0) 1947 return ret; 1948 1949 ret = s5k5baf_configure_gpios(state); 1950 if (ret < 0) 1951 goto err_me; 1952 1953 ret = s5k5baf_configure_regulators(state); 1954 if (ret < 0) 1955 goto err_me; 1956 1957 state->clock = devm_v4l2_sensor_clk_get_legacy(state->sd.dev, 1958 S5K5BAF_CLK_NAME, false, 1959 S5K5BAF_DEFAULT_MCLK_FREQ); 1960 if (IS_ERR(state->clock)) { 1961 ret = PTR_ERR(state->clock); 1962 goto err_me; 1963 } 1964 1965 ret = s5k5baf_power_on(state); 1966 if (ret < 0) { 1967 ret = -EPROBE_DEFER; 1968 goto err_me; 1969 } 1970 s5k5baf_hw_init(state); 1971 ret = s5k5baf_check_fw_revision(state); 1972 1973 s5k5baf_power_off(state); 1974 if (ret < 0) 1975 goto err_me; 1976 1977 ret = s5k5baf_initialize_ctrls(state); 1978 if (ret < 0) 1979 goto err_me; 1980 1981 ret = v4l2_async_register_subdev(&state->sd); 1982 if (ret < 0) 1983 goto err_ctrl; 1984 1985 return 0; 1986 1987 err_ctrl: 1988 v4l2_ctrl_handler_free(state->sd.ctrl_handler); 1989 err_me: 1990 media_entity_cleanup(&state->sd.entity); 1991 media_entity_cleanup(&state->cis_sd.entity); 1992 return ret; 1993 } 1994 1995 static void s5k5baf_remove(struct i2c_client *c) 1996 { 1997 struct v4l2_subdev *sd = i2c_get_clientdata(c); 1998 struct s5k5baf *state = to_s5k5baf(sd); 1999 2000 v4l2_async_unregister_subdev(sd); 2001 v4l2_ctrl_handler_free(sd->ctrl_handler); 2002 media_entity_cleanup(&sd->entity); 2003 2004 sd = &state->cis_sd; 2005 v4l2_device_unregister_subdev(sd); 2006 media_entity_cleanup(&sd->entity); 2007 } 2008 2009 static const struct i2c_device_id s5k5baf_id[] = { 2010 { S5K5BAF_DRIVER_NAME }, 2011 { } 2012 }; 2013 MODULE_DEVICE_TABLE(i2c, s5k5baf_id); 2014 2015 static const struct of_device_id s5k5baf_of_match[] = { 2016 { .compatible = "samsung,s5k5baf" }, 2017 { } 2018 }; 2019 MODULE_DEVICE_TABLE(of, s5k5baf_of_match); 2020 2021 static struct i2c_driver s5k5baf_i2c_driver = { 2022 .driver = { 2023 .of_match_table = s5k5baf_of_match, 2024 .name = S5K5BAF_DRIVER_NAME 2025 }, 2026 .probe = s5k5baf_probe, 2027 .remove = s5k5baf_remove, 2028 .id_table = s5k5baf_id, 2029 }; 2030 2031 module_i2c_driver(s5k5baf_i2c_driver); 2032 2033 MODULE_DESCRIPTION("Samsung S5K5BAF(X) UXGA camera driver"); 2034 MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>"); 2035 MODULE_LICENSE("GPL v2"); 2036