1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Samsung LSI S5C73M3 8M pixel camera driver 4 * 5 * Copyright (C) 2012, Samsung Electronics, Co., Ltd. 6 * Sylwester Nawrocki <s.nawrocki@samsung.com> 7 * Andrzej Hajda <a.hajda@samsung.com> 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/delay.h> 12 #include <linux/firmware.h> 13 #include <linux/gpio/consumer.h> 14 #include <linux/i2c.h> 15 #include <linux/init.h> 16 #include <linux/media.h> 17 #include <linux/module.h> 18 #include <linux/of_graph.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/sizes.h> 21 #include <linux/slab.h> 22 #include <linux/spi/spi.h> 23 #include <linux/videodev2.h> 24 #include <media/media-entity.h> 25 #include <media/v4l2-ctrls.h> 26 #include <media/v4l2-device.h> 27 #include <media/v4l2-subdev.h> 28 #include <media/v4l2-mediabus.h> 29 #include <media/i2c/s5c73m3.h> 30 #include <media/v4l2-fwnode.h> 31 32 #include "s5c73m3.h" 33 34 int s5c73m3_dbg; 35 module_param_named(debug, s5c73m3_dbg, int, 0644); 36 37 static int boot_from_rom = 1; 38 module_param(boot_from_rom, int, 0644); 39 40 static int update_fw; 41 module_param(update_fw, int, 0644); 42 43 #define S5C73M3_EMBEDDED_DATA_MAXLEN SZ_4K 44 #define S5C73M3_MIPI_DATA_LANES 4 45 #define S5C73M3_CLK_NAME "cis_extclk" 46 47 static const char * const s5c73m3_supply_names[S5C73M3_MAX_SUPPLIES] = { 48 "vdd-int", /* Digital Core supply (1.2V), CAM_ISP_CORE_1.2V */ 49 "vdda", /* Analog Core supply (1.2V), CAM_SENSOR_CORE_1.2V */ 50 "vdd-reg", /* Regulator input supply (2.8V), CAM_SENSOR_A2.8V */ 51 "vddio-host", /* Digital Host I/O power supply (1.8V...2.8V), 52 CAM_ISP_SENSOR_1.8V */ 53 "vddio-cis", /* Digital CIS I/O power (1.2V...1.8V), 54 CAM_ISP_MIPI_1.2V */ 55 "vdd-af", /* Lens, CAM_AF_2.8V */ 56 }; 57 58 static const struct s5c73m3_frame_size s5c73m3_isp_resolutions[] = { 59 { 320, 240, COMM_CHG_MODE_YUV_320_240 }, 60 { 352, 288, COMM_CHG_MODE_YUV_352_288 }, 61 { 640, 480, COMM_CHG_MODE_YUV_640_480 }, 62 { 880, 720, COMM_CHG_MODE_YUV_880_720 }, 63 { 960, 720, COMM_CHG_MODE_YUV_960_720 }, 64 { 1008, 672, COMM_CHG_MODE_YUV_1008_672 }, 65 { 1184, 666, COMM_CHG_MODE_YUV_1184_666 }, 66 { 1280, 720, COMM_CHG_MODE_YUV_1280_720 }, 67 { 1536, 864, COMM_CHG_MODE_YUV_1536_864 }, 68 { 1600, 1200, COMM_CHG_MODE_YUV_1600_1200 }, 69 { 1632, 1224, COMM_CHG_MODE_YUV_1632_1224 }, 70 { 1920, 1080, COMM_CHG_MODE_YUV_1920_1080 }, 71 { 1920, 1440, COMM_CHG_MODE_YUV_1920_1440 }, 72 { 2304, 1296, COMM_CHG_MODE_YUV_2304_1296 }, 73 { 3264, 2448, COMM_CHG_MODE_YUV_3264_2448 }, 74 }; 75 76 static const struct s5c73m3_frame_size s5c73m3_jpeg_resolutions[] = { 77 { 640, 480, COMM_CHG_MODE_JPEG_640_480 }, 78 { 800, 450, COMM_CHG_MODE_JPEG_800_450 }, 79 { 800, 600, COMM_CHG_MODE_JPEG_800_600 }, 80 { 1024, 768, COMM_CHG_MODE_JPEG_1024_768 }, 81 { 1280, 720, COMM_CHG_MODE_JPEG_1280_720 }, 82 { 1280, 960, COMM_CHG_MODE_JPEG_1280_960 }, 83 { 1600, 900, COMM_CHG_MODE_JPEG_1600_900 }, 84 { 1600, 1200, COMM_CHG_MODE_JPEG_1600_1200 }, 85 { 2048, 1152, COMM_CHG_MODE_JPEG_2048_1152 }, 86 { 2048, 1536, COMM_CHG_MODE_JPEG_2048_1536 }, 87 { 2560, 1440, COMM_CHG_MODE_JPEG_2560_1440 }, 88 { 2560, 1920, COMM_CHG_MODE_JPEG_2560_1920 }, 89 { 3264, 1836, COMM_CHG_MODE_JPEG_3264_1836 }, 90 { 3264, 2176, COMM_CHG_MODE_JPEG_3264_2176 }, 91 { 3264, 2448, COMM_CHG_MODE_JPEG_3264_2448 }, 92 }; 93 94 static const struct s5c73m3_frame_size * const s5c73m3_resolutions[] = { 95 [RES_ISP] = s5c73m3_isp_resolutions, 96 [RES_JPEG] = s5c73m3_jpeg_resolutions 97 }; 98 99 static const int s5c73m3_resolutions_len[] = { 100 [RES_ISP] = ARRAY_SIZE(s5c73m3_isp_resolutions), 101 [RES_JPEG] = ARRAY_SIZE(s5c73m3_jpeg_resolutions) 102 }; 103 104 static const struct s5c73m3_interval s5c73m3_intervals[] = { 105 { COMM_FRAME_RATE_FIXED_7FPS, {142857, 1000000}, {3264, 2448} }, 106 { COMM_FRAME_RATE_FIXED_15FPS, {66667, 1000000}, {3264, 2448} }, 107 { COMM_FRAME_RATE_FIXED_20FPS, {50000, 1000000}, {2304, 1296} }, 108 { COMM_FRAME_RATE_FIXED_30FPS, {33333, 1000000}, {2304, 1296} }, 109 }; 110 111 #define S5C73M3_DEFAULT_FRAME_INTERVAL 3 /* 30 fps */ 112 113 static void s5c73m3_fill_mbus_fmt(struct v4l2_mbus_framefmt *mf, 114 const struct s5c73m3_frame_size *fs, 115 u32 code) 116 { 117 mf->width = fs->width; 118 mf->height = fs->height; 119 mf->code = code; 120 mf->colorspace = V4L2_COLORSPACE_JPEG; 121 mf->field = V4L2_FIELD_NONE; 122 } 123 124 static int s5c73m3_i2c_write(struct i2c_client *client, u16 addr, u16 data) 125 { 126 u8 buf[4] = { addr >> 8, addr & 0xff, data >> 8, data & 0xff }; 127 128 int ret = i2c_master_send(client, buf, sizeof(buf)); 129 130 v4l_dbg(4, s5c73m3_dbg, client, "%s: addr 0x%04x, data 0x%04x\n", 131 __func__, addr, data); 132 133 if (ret == 4) 134 return 0; 135 136 return ret < 0 ? ret : -EREMOTEIO; 137 } 138 139 static int s5c73m3_i2c_read(struct i2c_client *client, u16 addr, u16 *data) 140 { 141 int ret; 142 u8 rbuf[2], wbuf[2] = { addr >> 8, addr & 0xff }; 143 struct i2c_msg msg[2] = { 144 { 145 .addr = client->addr, 146 .flags = 0, 147 .len = sizeof(wbuf), 148 .buf = wbuf 149 }, { 150 .addr = client->addr, 151 .flags = I2C_M_RD, 152 .len = sizeof(rbuf), 153 .buf = rbuf 154 } 155 }; 156 /* 157 * Issue repeated START after writing 2 address bytes and 158 * just one STOP only after reading the data bytes. 159 */ 160 ret = i2c_transfer(client->adapter, msg, 2); 161 if (ret == 2) { 162 *data = be16_to_cpup((__be16 *)rbuf); 163 v4l2_dbg(4, s5c73m3_dbg, client, 164 "%s: addr: 0x%04x, data: 0x%04x\n", 165 __func__, addr, *data); 166 return 0; 167 } 168 169 v4l2_err(client, "I2C read failed: addr: %04x, (%d)\n", addr, ret); 170 171 return ret >= 0 ? -EREMOTEIO : ret; 172 } 173 174 int s5c73m3_write(struct s5c73m3 *state, u32 addr, u16 data) 175 { 176 struct i2c_client *client = state->i2c_client; 177 int ret; 178 179 if ((addr ^ state->i2c_write_address) & 0xffff0000) { 180 ret = s5c73m3_i2c_write(client, REG_CMDWR_ADDRH, addr >> 16); 181 if (ret < 0) { 182 state->i2c_write_address = 0; 183 return ret; 184 } 185 } 186 187 if ((addr ^ state->i2c_write_address) & 0xffff) { 188 ret = s5c73m3_i2c_write(client, REG_CMDWR_ADDRL, addr & 0xffff); 189 if (ret < 0) { 190 state->i2c_write_address = 0; 191 return ret; 192 } 193 } 194 195 state->i2c_write_address = addr; 196 197 ret = s5c73m3_i2c_write(client, REG_CMDBUF_ADDR, data); 198 if (ret < 0) 199 return ret; 200 201 state->i2c_write_address += 2; 202 203 return ret; 204 } 205 206 int s5c73m3_read(struct s5c73m3 *state, u32 addr, u16 *data) 207 { 208 struct i2c_client *client = state->i2c_client; 209 int ret; 210 211 if ((addr ^ state->i2c_read_address) & 0xffff0000) { 212 ret = s5c73m3_i2c_write(client, REG_CMDRD_ADDRH, addr >> 16); 213 if (ret < 0) { 214 state->i2c_read_address = 0; 215 return ret; 216 } 217 } 218 219 if ((addr ^ state->i2c_read_address) & 0xffff) { 220 ret = s5c73m3_i2c_write(client, REG_CMDRD_ADDRL, addr & 0xffff); 221 if (ret < 0) { 222 state->i2c_read_address = 0; 223 return ret; 224 } 225 } 226 227 state->i2c_read_address = addr; 228 229 ret = s5c73m3_i2c_read(client, REG_CMDBUF_ADDR, data); 230 if (ret < 0) 231 return ret; 232 233 state->i2c_read_address += 2; 234 235 return ret; 236 } 237 238 static int s5c73m3_check_status(struct s5c73m3 *state, unsigned int value) 239 { 240 unsigned long start = jiffies; 241 unsigned long end = start + msecs_to_jiffies(2000); 242 int ret; 243 u16 status; 244 int count = 0; 245 246 do { 247 ret = s5c73m3_read(state, REG_STATUS, &status); 248 if (ret < 0 || status == value) 249 break; 250 usleep_range(500, 1000); 251 ++count; 252 } while (time_is_after_jiffies(end)); 253 254 if (count > 0) 255 v4l2_dbg(1, s5c73m3_dbg, &state->sensor_sd, 256 "status check took %dms\n", 257 jiffies_to_msecs(jiffies - start)); 258 259 if (ret == 0 && status != value) { 260 u16 i2c_status = 0; 261 u16 i2c_seq_status = 0; 262 263 s5c73m3_read(state, REG_I2C_STATUS, &i2c_status); 264 s5c73m3_read(state, REG_I2C_SEQ_STATUS, &i2c_seq_status); 265 266 v4l2_err(&state->sensor_sd, 267 "wrong status %#x, expected: %#x, i2c_status: %#x/%#x\n", 268 status, value, i2c_status, i2c_seq_status); 269 270 return -ETIMEDOUT; 271 } 272 273 return ret; 274 } 275 276 int s5c73m3_isp_command(struct s5c73m3 *state, u16 command, u16 data) 277 { 278 int ret; 279 280 ret = s5c73m3_check_status(state, REG_STATUS_ISP_COMMAND_COMPLETED); 281 if (ret < 0) 282 return ret; 283 284 ret = s5c73m3_write(state, 0x00095000, command); 285 if (ret < 0) 286 return ret; 287 288 ret = s5c73m3_write(state, 0x00095002, data); 289 if (ret < 0) 290 return ret; 291 292 return s5c73m3_write(state, REG_STATUS, 0x0001); 293 } 294 295 static int s5c73m3_isp_comm_result(struct s5c73m3 *state, u16 command, 296 u16 *data) 297 { 298 return s5c73m3_read(state, COMM_RESULT_OFFSET + command, data); 299 } 300 301 static int s5c73m3_set_af_softlanding(struct s5c73m3 *state) 302 { 303 unsigned long start = jiffies; 304 u16 af_softlanding; 305 int count = 0; 306 int ret; 307 const char *msg; 308 309 ret = s5c73m3_isp_command(state, COMM_AF_SOFTLANDING, 310 COMM_AF_SOFTLANDING_ON); 311 if (ret < 0) { 312 v4l2_info(&state->sensor_sd, "AF soft-landing failed\n"); 313 return ret; 314 } 315 316 for (;;) { 317 ret = s5c73m3_isp_comm_result(state, COMM_AF_SOFTLANDING, 318 &af_softlanding); 319 if (ret < 0) { 320 msg = "failed"; 321 break; 322 } 323 if (af_softlanding == COMM_AF_SOFTLANDING_RES_COMPLETE) { 324 msg = "succeeded"; 325 break; 326 } 327 if (++count > 100) { 328 ret = -ETIME; 329 msg = "timed out"; 330 break; 331 } 332 msleep(25); 333 } 334 335 v4l2_info(&state->sensor_sd, "AF soft-landing %s after %dms\n", 336 msg, jiffies_to_msecs(jiffies - start)); 337 338 return ret; 339 } 340 341 static int s5c73m3_load_fw(struct v4l2_subdev *sd) 342 { 343 struct s5c73m3 *state = sensor_sd_to_s5c73m3(sd); 344 struct i2c_client *client = state->i2c_client; 345 const struct firmware *fw; 346 int ret; 347 char fw_name[20]; 348 349 snprintf(fw_name, sizeof(fw_name), "SlimISP_%.2s.bin", 350 state->fw_file_version); 351 ret = request_firmware(&fw, fw_name, &client->dev); 352 if (ret < 0) { 353 v4l2_err(sd, "Firmware request failed (%s)\n", fw_name); 354 return -EINVAL; 355 } 356 357 v4l2_info(sd, "Loading firmware (%s, %zu B)\n", fw_name, fw->size); 358 359 ret = s5c73m3_spi_write(state, fw->data, fw->size, 64); 360 361 if (ret >= 0) 362 state->isp_ready = 1; 363 else 364 v4l2_err(sd, "SPI write failed\n"); 365 366 release_firmware(fw); 367 368 return ret; 369 } 370 371 static int s5c73m3_set_frame_size(struct s5c73m3 *state) 372 { 373 const struct s5c73m3_frame_size *prev_size = 374 state->sensor_pix_size[RES_ISP]; 375 const struct s5c73m3_frame_size *cap_size = 376 state->sensor_pix_size[RES_JPEG]; 377 unsigned int chg_mode; 378 379 v4l2_dbg(1, s5c73m3_dbg, &state->sensor_sd, 380 "Preview size: %dx%d, reg_val: 0x%x\n", 381 prev_size->width, prev_size->height, prev_size->reg_val); 382 383 chg_mode = prev_size->reg_val | COMM_CHG_MODE_NEW; 384 385 if (state->mbus_code == S5C73M3_JPEG_FMT) { 386 v4l2_dbg(1, s5c73m3_dbg, &state->sensor_sd, 387 "Capture size: %dx%d, reg_val: 0x%x\n", 388 cap_size->width, cap_size->height, cap_size->reg_val); 389 chg_mode |= cap_size->reg_val; 390 } 391 392 return s5c73m3_isp_command(state, COMM_CHG_MODE, chg_mode); 393 } 394 395 static int s5c73m3_set_frame_rate(struct s5c73m3 *state) 396 { 397 int ret; 398 399 if (state->ctrls.stabilization->val) 400 return 0; 401 402 if (WARN_ON(state->fiv == NULL)) 403 return -EINVAL; 404 405 ret = s5c73m3_isp_command(state, COMM_FRAME_RATE, state->fiv->fps_reg); 406 if (!ret) 407 state->apply_fiv = 0; 408 409 return ret; 410 } 411 412 static int __s5c73m3_s_stream(struct s5c73m3 *state, struct v4l2_subdev *sd, 413 int on) 414 { 415 u16 mode; 416 int ret; 417 418 if (on && state->apply_fmt) { 419 if (state->mbus_code == S5C73M3_JPEG_FMT) 420 mode = COMM_IMG_OUTPUT_INTERLEAVED; 421 else 422 mode = COMM_IMG_OUTPUT_YUV; 423 424 ret = s5c73m3_isp_command(state, COMM_IMG_OUTPUT, mode); 425 if (!ret) 426 ret = s5c73m3_set_frame_size(state); 427 if (ret) 428 return ret; 429 state->apply_fmt = 0; 430 } 431 432 ret = s5c73m3_isp_command(state, COMM_SENSOR_STREAMING, !!on); 433 if (ret) 434 return ret; 435 436 state->streaming = !!on; 437 438 if (!on) 439 return ret; 440 441 if (state->apply_fiv) { 442 ret = s5c73m3_set_frame_rate(state); 443 if (ret < 0) 444 v4l2_err(sd, "Error setting frame rate(%d)\n", ret); 445 } 446 447 return s5c73m3_check_status(state, REG_STATUS_ISP_COMMAND_COMPLETED); 448 } 449 450 static int s5c73m3_oif_s_stream(struct v4l2_subdev *sd, int on) 451 { 452 struct s5c73m3 *state = oif_sd_to_s5c73m3(sd); 453 int ret; 454 455 mutex_lock(&state->lock); 456 ret = __s5c73m3_s_stream(state, sd, on); 457 mutex_unlock(&state->lock); 458 459 return ret; 460 } 461 462 static int s5c73m3_system_status_wait(struct s5c73m3 *state, u32 value, 463 unsigned int delay, unsigned int steps) 464 { 465 u16 reg = 0; 466 467 while (steps-- > 0) { 468 int ret = s5c73m3_read(state, 0x30100010, ®); 469 if (ret < 0) 470 return ret; 471 if (reg == value) 472 return 0; 473 usleep_range(delay, delay + 25); 474 } 475 return -ETIMEDOUT; 476 } 477 478 static int s5c73m3_read_fw_version(struct s5c73m3 *state) 479 { 480 struct v4l2_subdev *sd = &state->sensor_sd; 481 int i, ret; 482 u16 data[2]; 483 int offset; 484 485 offset = state->isp_ready ? 0x60 : 0; 486 487 for (i = 0; i < S5C73M3_SENSOR_FW_LEN / 2; i++) { 488 ret = s5c73m3_read(state, offset + i * 2, data); 489 if (ret < 0) 490 return ret; 491 state->sensor_fw[i * 2] = (char)(*data & 0xff); 492 state->sensor_fw[i * 2 + 1] = (char)(*data >> 8); 493 } 494 state->sensor_fw[S5C73M3_SENSOR_FW_LEN] = '\0'; 495 496 497 for (i = 0; i < S5C73M3_SENSOR_TYPE_LEN / 2; i++) { 498 ret = s5c73m3_read(state, offset + 6 + i * 2, data); 499 if (ret < 0) 500 return ret; 501 state->sensor_type[i * 2] = (char)(*data & 0xff); 502 state->sensor_type[i * 2 + 1] = (char)(*data >> 8); 503 } 504 state->sensor_type[S5C73M3_SENSOR_TYPE_LEN] = '\0'; 505 506 ret = s5c73m3_read(state, offset + 0x14, data); 507 if (ret >= 0) { 508 ret = s5c73m3_read(state, offset + 0x16, data + 1); 509 if (ret >= 0) 510 state->fw_size = data[0] + (data[1] << 16); 511 } 512 513 v4l2_info(sd, "Sensor type: %s, FW version: %s\n", 514 state->sensor_type, state->sensor_fw); 515 return ret; 516 } 517 518 static int s5c73m3_fw_update_from(struct s5c73m3 *state) 519 { 520 struct v4l2_subdev *sd = &state->sensor_sd; 521 u16 status = COMM_FW_UPDATE_NOT_READY; 522 int ret; 523 int count = 0; 524 525 v4l2_warn(sd, "Updating F-ROM firmware.\n"); 526 do { 527 if (status == COMM_FW_UPDATE_NOT_READY) { 528 ret = s5c73m3_isp_command(state, COMM_FW_UPDATE, 0); 529 if (ret < 0) 530 return ret; 531 } 532 533 ret = s5c73m3_read(state, 0x00095906, &status); 534 if (ret < 0) 535 return ret; 536 switch (status) { 537 case COMM_FW_UPDATE_FAIL: 538 v4l2_warn(sd, "Updating F-ROM firmware failed.\n"); 539 return -EIO; 540 case COMM_FW_UPDATE_SUCCESS: 541 v4l2_warn(sd, "Updating F-ROM firmware finished.\n"); 542 return 0; 543 } 544 ++count; 545 msleep(20); 546 } while (count < 500); 547 548 v4l2_warn(sd, "Updating F-ROM firmware timed-out.\n"); 549 return -ETIMEDOUT; 550 } 551 552 static int s5c73m3_spi_boot(struct s5c73m3 *state, bool load_fw) 553 { 554 struct v4l2_subdev *sd = &state->sensor_sd; 555 int ret; 556 557 /* Run ARM MCU */ 558 ret = s5c73m3_write(state, 0x30000004, 0xffff); 559 if (ret < 0) 560 return ret; 561 562 usleep_range(400, 500); 563 564 /* Check booting status */ 565 ret = s5c73m3_system_status_wait(state, 0x0c, 100, 3); 566 if (ret < 0) { 567 v4l2_err(sd, "booting failed: %d\n", ret); 568 return ret; 569 } 570 571 /* P,M,S and Boot Mode */ 572 ret = s5c73m3_write(state, 0x30100014, 0x2146); 573 if (ret < 0) 574 return ret; 575 576 ret = s5c73m3_write(state, 0x30100010, 0x210c); 577 if (ret < 0) 578 return ret; 579 580 usleep_range(200, 250); 581 582 /* Check SPI status */ 583 ret = s5c73m3_system_status_wait(state, 0x210d, 100, 300); 584 if (ret < 0) 585 v4l2_err(sd, "SPI not ready: %d\n", ret); 586 587 /* Firmware download over SPI */ 588 if (load_fw) 589 s5c73m3_load_fw(sd); 590 591 /* MCU reset */ 592 ret = s5c73m3_write(state, 0x30000004, 0xfffd); 593 if (ret < 0) 594 return ret; 595 596 /* Remap */ 597 ret = s5c73m3_write(state, 0x301000a4, 0x0183); 598 if (ret < 0) 599 return ret; 600 601 /* MCU restart */ 602 ret = s5c73m3_write(state, 0x30000004, 0xffff); 603 if (ret < 0 || !load_fw) 604 return ret; 605 606 ret = s5c73m3_read_fw_version(state); 607 if (ret < 0) 608 return ret; 609 610 if (load_fw && update_fw) { 611 ret = s5c73m3_fw_update_from(state); 612 update_fw = 0; 613 } 614 615 return ret; 616 } 617 618 static int s5c73m3_set_timing_register_for_vdd(struct s5c73m3 *state) 619 { 620 static const u32 regs[][2] = { 621 { 0x30100018, 0x0618 }, 622 { 0x3010001c, 0x10c1 }, 623 { 0x30100020, 0x249e } 624 }; 625 int ret; 626 int i; 627 628 for (i = 0; i < ARRAY_SIZE(regs); i++) { 629 ret = s5c73m3_write(state, regs[i][0], regs[i][1]); 630 if (ret < 0) 631 return ret; 632 } 633 634 return 0; 635 } 636 637 static void s5c73m3_set_fw_file_version(struct s5c73m3 *state) 638 { 639 switch (state->sensor_fw[0]) { 640 case 'G': 641 case 'O': 642 state->fw_file_version[0] = 'G'; 643 break; 644 case 'S': 645 case 'Z': 646 state->fw_file_version[0] = 'Z'; 647 break; 648 } 649 650 switch (state->sensor_fw[1]) { 651 case 'C'...'F': 652 state->fw_file_version[1] = state->sensor_fw[1]; 653 break; 654 } 655 } 656 657 static int s5c73m3_get_fw_version(struct s5c73m3 *state) 658 { 659 struct v4l2_subdev *sd = &state->sensor_sd; 660 int ret; 661 662 /* Run ARM MCU */ 663 ret = s5c73m3_write(state, 0x30000004, 0xffff); 664 if (ret < 0) 665 return ret; 666 usleep_range(400, 500); 667 668 /* Check booting status */ 669 ret = s5c73m3_system_status_wait(state, 0x0c, 100, 3); 670 if (ret < 0) { 671 672 v4l2_err(sd, "%s: booting failed: %d\n", __func__, ret); 673 return ret; 674 } 675 676 /* Change I/O Driver Current in order to read from F-ROM */ 677 ret = s5c73m3_write(state, 0x30100120, 0x0820); 678 ret = s5c73m3_write(state, 0x30100124, 0x0820); 679 680 /* Offset Setting */ 681 ret = s5c73m3_write(state, 0x00010418, 0x0008); 682 683 /* P,M,S and Boot Mode */ 684 ret = s5c73m3_write(state, 0x30100014, 0x2146); 685 if (ret < 0) 686 return ret; 687 ret = s5c73m3_write(state, 0x30100010, 0x230c); 688 if (ret < 0) 689 return ret; 690 691 usleep_range(200, 250); 692 693 /* Check SPI status */ 694 ret = s5c73m3_system_status_wait(state, 0x230e, 100, 300); 695 if (ret < 0) 696 v4l2_err(sd, "SPI not ready: %d\n", ret); 697 698 /* ARM reset */ 699 ret = s5c73m3_write(state, 0x30000004, 0xfffd); 700 if (ret < 0) 701 return ret; 702 703 /* Remap */ 704 ret = s5c73m3_write(state, 0x301000a4, 0x0183); 705 if (ret < 0) 706 return ret; 707 708 s5c73m3_set_timing_register_for_vdd(state); 709 710 ret = s5c73m3_read_fw_version(state); 711 712 s5c73m3_set_fw_file_version(state); 713 714 return ret; 715 } 716 717 static int s5c73m3_rom_boot(struct s5c73m3 *state, bool load_fw) 718 { 719 static const u32 boot_regs[][2] = { 720 { 0x3100010c, 0x0044 }, 721 { 0x31000108, 0x000d }, 722 { 0x31000304, 0x0001 }, 723 { 0x00010000, 0x5800 }, 724 { 0x00010002, 0x0002 }, 725 { 0x31000000, 0x0001 }, 726 { 0x30100014, 0x1b85 }, 727 { 0x30100010, 0x230c } 728 }; 729 struct v4l2_subdev *sd = &state->sensor_sd; 730 int i, ret; 731 732 /* Run ARM MCU */ 733 ret = s5c73m3_write(state, 0x30000004, 0xffff); 734 if (ret < 0) 735 return ret; 736 usleep_range(400, 450); 737 738 /* Check booting status */ 739 ret = s5c73m3_system_status_wait(state, 0x0c, 100, 4); 740 if (ret < 0) { 741 v4l2_err(sd, "Booting failed: %d\n", ret); 742 return ret; 743 } 744 745 for (i = 0; i < ARRAY_SIZE(boot_regs); i++) { 746 ret = s5c73m3_write(state, boot_regs[i][0], boot_regs[i][1]); 747 if (ret < 0) 748 return ret; 749 } 750 msleep(200); 751 752 /* Check the binary read status */ 753 ret = s5c73m3_system_status_wait(state, 0x230e, 1000, 150); 754 if (ret < 0) { 755 v4l2_err(sd, "Binary read failed: %d\n", ret); 756 return ret; 757 } 758 759 /* ARM reset */ 760 ret = s5c73m3_write(state, 0x30000004, 0xfffd); 761 if (ret < 0) 762 return ret; 763 /* Remap */ 764 ret = s5c73m3_write(state, 0x301000a4, 0x0183); 765 if (ret < 0) 766 return ret; 767 /* MCU re-start */ 768 ret = s5c73m3_write(state, 0x30000004, 0xffff); 769 if (ret < 0) 770 return ret; 771 772 state->isp_ready = 1; 773 774 return s5c73m3_read_fw_version(state); 775 } 776 777 static int s5c73m3_isp_init(struct s5c73m3 *state) 778 { 779 int ret; 780 781 state->i2c_read_address = 0; 782 state->i2c_write_address = 0; 783 784 ret = s5c73m3_i2c_write(state->i2c_client, AHB_MSB_ADDR_PTR, 0x3310); 785 if (ret < 0) 786 return ret; 787 788 if (boot_from_rom) 789 return s5c73m3_rom_boot(state, true); 790 else 791 return s5c73m3_spi_boot(state, true); 792 } 793 794 static const struct s5c73m3_frame_size *s5c73m3_find_frame_size( 795 struct v4l2_mbus_framefmt *fmt, 796 enum s5c73m3_resolution_types idx) 797 { 798 const struct s5c73m3_frame_size *fs; 799 const struct s5c73m3_frame_size *best_fs; 800 int best_dist = INT_MAX; 801 int i; 802 803 fs = s5c73m3_resolutions[idx]; 804 best_fs = NULL; 805 for (i = 0; i < s5c73m3_resolutions_len[idx]; ++i) { 806 int dist = abs(fs->width - fmt->width) + 807 abs(fs->height - fmt->height); 808 if (dist < best_dist) { 809 best_dist = dist; 810 best_fs = fs; 811 } 812 ++fs; 813 } 814 815 return best_fs; 816 } 817 818 static void s5c73m3_oif_try_format(struct s5c73m3 *state, 819 struct v4l2_subdev_state *sd_state, 820 struct v4l2_subdev_format *fmt, 821 const struct s5c73m3_frame_size **fs) 822 { 823 struct v4l2_subdev *sd = &state->sensor_sd; 824 u32 code; 825 826 switch (fmt->pad) { 827 case OIF_ISP_PAD: 828 *fs = s5c73m3_find_frame_size(&fmt->format, RES_ISP); 829 code = S5C73M3_ISP_FMT; 830 break; 831 case OIF_JPEG_PAD: 832 *fs = s5c73m3_find_frame_size(&fmt->format, RES_JPEG); 833 code = S5C73M3_JPEG_FMT; 834 break; 835 case OIF_SOURCE_PAD: 836 default: 837 if (fmt->format.code == S5C73M3_JPEG_FMT) 838 code = S5C73M3_JPEG_FMT; 839 else 840 code = S5C73M3_ISP_FMT; 841 842 if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) 843 *fs = state->oif_pix_size[RES_ISP]; 844 else 845 *fs = s5c73m3_find_frame_size( 846 v4l2_subdev_get_try_format(sd, sd_state, 847 OIF_ISP_PAD), 848 RES_ISP); 849 break; 850 } 851 852 s5c73m3_fill_mbus_fmt(&fmt->format, *fs, code); 853 } 854 855 static void s5c73m3_try_format(struct s5c73m3 *state, 856 struct v4l2_subdev_state *sd_state, 857 struct v4l2_subdev_format *fmt, 858 const struct s5c73m3_frame_size **fs) 859 { 860 u32 code; 861 862 if (fmt->pad == S5C73M3_ISP_PAD) { 863 *fs = s5c73m3_find_frame_size(&fmt->format, RES_ISP); 864 code = S5C73M3_ISP_FMT; 865 } else { 866 *fs = s5c73m3_find_frame_size(&fmt->format, RES_JPEG); 867 code = S5C73M3_JPEG_FMT; 868 } 869 870 s5c73m3_fill_mbus_fmt(&fmt->format, *fs, code); 871 } 872 873 static int s5c73m3_oif_g_frame_interval(struct v4l2_subdev *sd, 874 struct v4l2_subdev_frame_interval *fi) 875 { 876 struct s5c73m3 *state = oif_sd_to_s5c73m3(sd); 877 878 if (fi->pad != OIF_SOURCE_PAD) 879 return -EINVAL; 880 881 mutex_lock(&state->lock); 882 fi->interval = state->fiv->interval; 883 mutex_unlock(&state->lock); 884 885 return 0; 886 } 887 888 static int __s5c73m3_set_frame_interval(struct s5c73m3 *state, 889 struct v4l2_subdev_frame_interval *fi) 890 { 891 const struct s5c73m3_frame_size *prev_size = 892 state->sensor_pix_size[RES_ISP]; 893 const struct s5c73m3_interval *fiv = &s5c73m3_intervals[0]; 894 unsigned int ret, min_err = UINT_MAX; 895 unsigned int i, fr_time; 896 897 if (fi->interval.denominator == 0) 898 return -EINVAL; 899 900 fr_time = fi->interval.numerator * 1000 / fi->interval.denominator; 901 902 for (i = 0; i < ARRAY_SIZE(s5c73m3_intervals); i++) { 903 const struct s5c73m3_interval *iv = &s5c73m3_intervals[i]; 904 905 if (prev_size->width > iv->size.width || 906 prev_size->height > iv->size.height) 907 continue; 908 909 ret = abs(iv->interval.numerator / 1000 - fr_time); 910 if (ret < min_err) { 911 fiv = iv; 912 min_err = ret; 913 } 914 } 915 state->fiv = fiv; 916 917 v4l2_dbg(1, s5c73m3_dbg, &state->sensor_sd, 918 "Changed frame interval to %u us\n", fiv->interval.numerator); 919 return 0; 920 } 921 922 static int s5c73m3_oif_s_frame_interval(struct v4l2_subdev *sd, 923 struct v4l2_subdev_frame_interval *fi) 924 { 925 struct s5c73m3 *state = oif_sd_to_s5c73m3(sd); 926 int ret; 927 928 if (fi->pad != OIF_SOURCE_PAD) 929 return -EINVAL; 930 931 v4l2_dbg(1, s5c73m3_dbg, sd, "Setting %d/%d frame interval\n", 932 fi->interval.numerator, fi->interval.denominator); 933 934 mutex_lock(&state->lock); 935 936 ret = __s5c73m3_set_frame_interval(state, fi); 937 if (!ret) { 938 if (state->streaming) 939 ret = s5c73m3_set_frame_rate(state); 940 else 941 state->apply_fiv = 1; 942 } 943 mutex_unlock(&state->lock); 944 return ret; 945 } 946 947 static int s5c73m3_oif_enum_frame_interval(struct v4l2_subdev *sd, 948 struct v4l2_subdev_state *sd_state, 949 struct v4l2_subdev_frame_interval_enum *fie) 950 { 951 struct s5c73m3 *state = oif_sd_to_s5c73m3(sd); 952 const struct s5c73m3_interval *fi; 953 int ret = 0; 954 955 if (fie->pad != OIF_SOURCE_PAD) 956 return -EINVAL; 957 if (fie->index >= ARRAY_SIZE(s5c73m3_intervals)) 958 return -EINVAL; 959 960 mutex_lock(&state->lock); 961 fi = &s5c73m3_intervals[fie->index]; 962 if (fie->width > fi->size.width || fie->height > fi->size.height) 963 ret = -EINVAL; 964 else 965 fie->interval = fi->interval; 966 mutex_unlock(&state->lock); 967 968 return ret; 969 } 970 971 static int s5c73m3_oif_get_pad_code(int pad, int index) 972 { 973 if (pad == OIF_SOURCE_PAD) { 974 if (index > 1) 975 return -EINVAL; 976 return (index == 0) ? S5C73M3_ISP_FMT : S5C73M3_JPEG_FMT; 977 } 978 979 if (index > 0) 980 return -EINVAL; 981 982 return (pad == OIF_ISP_PAD) ? S5C73M3_ISP_FMT : S5C73M3_JPEG_FMT; 983 } 984 985 static int s5c73m3_get_fmt(struct v4l2_subdev *sd, 986 struct v4l2_subdev_state *sd_state, 987 struct v4l2_subdev_format *fmt) 988 { 989 struct s5c73m3 *state = sensor_sd_to_s5c73m3(sd); 990 const struct s5c73m3_frame_size *fs; 991 u32 code; 992 993 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { 994 fmt->format = *v4l2_subdev_get_try_format(sd, sd_state, 995 fmt->pad); 996 return 0; 997 } 998 999 mutex_lock(&state->lock); 1000 1001 switch (fmt->pad) { 1002 case S5C73M3_ISP_PAD: 1003 code = S5C73M3_ISP_FMT; 1004 fs = state->sensor_pix_size[RES_ISP]; 1005 break; 1006 case S5C73M3_JPEG_PAD: 1007 code = S5C73M3_JPEG_FMT; 1008 fs = state->sensor_pix_size[RES_JPEG]; 1009 break; 1010 default: 1011 mutex_unlock(&state->lock); 1012 return -EINVAL; 1013 } 1014 s5c73m3_fill_mbus_fmt(&fmt->format, fs, code); 1015 1016 mutex_unlock(&state->lock); 1017 return 0; 1018 } 1019 1020 static int s5c73m3_oif_get_fmt(struct v4l2_subdev *sd, 1021 struct v4l2_subdev_state *sd_state, 1022 struct v4l2_subdev_format *fmt) 1023 { 1024 struct s5c73m3 *state = oif_sd_to_s5c73m3(sd); 1025 const struct s5c73m3_frame_size *fs; 1026 u32 code; 1027 1028 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { 1029 fmt->format = *v4l2_subdev_get_try_format(sd, sd_state, 1030 fmt->pad); 1031 return 0; 1032 } 1033 1034 mutex_lock(&state->lock); 1035 1036 switch (fmt->pad) { 1037 case OIF_ISP_PAD: 1038 code = S5C73M3_ISP_FMT; 1039 fs = state->oif_pix_size[RES_ISP]; 1040 break; 1041 case OIF_JPEG_PAD: 1042 code = S5C73M3_JPEG_FMT; 1043 fs = state->oif_pix_size[RES_JPEG]; 1044 break; 1045 case OIF_SOURCE_PAD: 1046 code = state->mbus_code; 1047 fs = state->oif_pix_size[RES_ISP]; 1048 break; 1049 default: 1050 mutex_unlock(&state->lock); 1051 return -EINVAL; 1052 } 1053 s5c73m3_fill_mbus_fmt(&fmt->format, fs, code); 1054 1055 mutex_unlock(&state->lock); 1056 return 0; 1057 } 1058 1059 static int s5c73m3_set_fmt(struct v4l2_subdev *sd, 1060 struct v4l2_subdev_state *sd_state, 1061 struct v4l2_subdev_format *fmt) 1062 { 1063 const struct s5c73m3_frame_size *frame_size = NULL; 1064 struct s5c73m3 *state = sensor_sd_to_s5c73m3(sd); 1065 struct v4l2_mbus_framefmt *mf; 1066 int ret = 0; 1067 1068 mutex_lock(&state->lock); 1069 1070 s5c73m3_try_format(state, sd_state, fmt, &frame_size); 1071 1072 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { 1073 mf = v4l2_subdev_get_try_format(sd, sd_state, fmt->pad); 1074 *mf = fmt->format; 1075 } else { 1076 switch (fmt->pad) { 1077 case S5C73M3_ISP_PAD: 1078 state->sensor_pix_size[RES_ISP] = frame_size; 1079 break; 1080 case S5C73M3_JPEG_PAD: 1081 state->sensor_pix_size[RES_JPEG] = frame_size; 1082 break; 1083 default: 1084 ret = -EBUSY; 1085 } 1086 1087 if (state->streaming) 1088 ret = -EBUSY; 1089 else 1090 state->apply_fmt = 1; 1091 } 1092 1093 mutex_unlock(&state->lock); 1094 1095 return ret; 1096 } 1097 1098 static int s5c73m3_oif_set_fmt(struct v4l2_subdev *sd, 1099 struct v4l2_subdev_state *sd_state, 1100 struct v4l2_subdev_format *fmt) 1101 { 1102 const struct s5c73m3_frame_size *frame_size = NULL; 1103 struct s5c73m3 *state = oif_sd_to_s5c73m3(sd); 1104 struct v4l2_mbus_framefmt *mf; 1105 int ret = 0; 1106 1107 mutex_lock(&state->lock); 1108 1109 s5c73m3_oif_try_format(state, sd_state, fmt, &frame_size); 1110 1111 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { 1112 mf = v4l2_subdev_get_try_format(sd, sd_state, fmt->pad); 1113 *mf = fmt->format; 1114 if (fmt->pad == OIF_ISP_PAD) { 1115 mf = v4l2_subdev_get_try_format(sd, sd_state, 1116 OIF_SOURCE_PAD); 1117 mf->width = fmt->format.width; 1118 mf->height = fmt->format.height; 1119 } 1120 } else { 1121 switch (fmt->pad) { 1122 case OIF_ISP_PAD: 1123 state->oif_pix_size[RES_ISP] = frame_size; 1124 break; 1125 case OIF_JPEG_PAD: 1126 state->oif_pix_size[RES_JPEG] = frame_size; 1127 break; 1128 case OIF_SOURCE_PAD: 1129 state->mbus_code = fmt->format.code; 1130 break; 1131 default: 1132 ret = -EBUSY; 1133 } 1134 1135 if (state->streaming) 1136 ret = -EBUSY; 1137 else 1138 state->apply_fmt = 1; 1139 } 1140 1141 mutex_unlock(&state->lock); 1142 1143 return ret; 1144 } 1145 1146 static int s5c73m3_oif_get_frame_desc(struct v4l2_subdev *sd, unsigned int pad, 1147 struct v4l2_mbus_frame_desc *fd) 1148 { 1149 struct s5c73m3 *state = oif_sd_to_s5c73m3(sd); 1150 int i; 1151 1152 if (pad != OIF_SOURCE_PAD || fd == NULL) 1153 return -EINVAL; 1154 1155 mutex_lock(&state->lock); 1156 fd->num_entries = 2; 1157 for (i = 0; i < fd->num_entries; i++) 1158 fd->entry[i] = state->frame_desc.entry[i]; 1159 mutex_unlock(&state->lock); 1160 1161 return 0; 1162 } 1163 1164 static int s5c73m3_oif_set_frame_desc(struct v4l2_subdev *sd, unsigned int pad, 1165 struct v4l2_mbus_frame_desc *fd) 1166 { 1167 struct s5c73m3 *state = oif_sd_to_s5c73m3(sd); 1168 struct v4l2_mbus_frame_desc *frame_desc = &state->frame_desc; 1169 int i; 1170 1171 if (pad != OIF_SOURCE_PAD || fd == NULL) 1172 return -EINVAL; 1173 1174 fd->entry[0].length = 10 * SZ_1M; 1175 fd->entry[1].length = max_t(u32, fd->entry[1].length, 1176 S5C73M3_EMBEDDED_DATA_MAXLEN); 1177 fd->num_entries = 2; 1178 1179 mutex_lock(&state->lock); 1180 for (i = 0; i < fd->num_entries; i++) 1181 frame_desc->entry[i] = fd->entry[i]; 1182 mutex_unlock(&state->lock); 1183 1184 return 0; 1185 } 1186 1187 static int s5c73m3_enum_mbus_code(struct v4l2_subdev *sd, 1188 struct v4l2_subdev_state *sd_state, 1189 struct v4l2_subdev_mbus_code_enum *code) 1190 { 1191 static const int codes[] = { 1192 [S5C73M3_ISP_PAD] = S5C73M3_ISP_FMT, 1193 [S5C73M3_JPEG_PAD] = S5C73M3_JPEG_FMT}; 1194 1195 if (code->index > 0 || code->pad >= S5C73M3_NUM_PADS) 1196 return -EINVAL; 1197 1198 code->code = codes[code->pad]; 1199 1200 return 0; 1201 } 1202 1203 static int s5c73m3_oif_enum_mbus_code(struct v4l2_subdev *sd, 1204 struct v4l2_subdev_state *sd_state, 1205 struct v4l2_subdev_mbus_code_enum *code) 1206 { 1207 int ret; 1208 1209 ret = s5c73m3_oif_get_pad_code(code->pad, code->index); 1210 if (ret < 0) 1211 return ret; 1212 1213 code->code = ret; 1214 1215 return 0; 1216 } 1217 1218 static int s5c73m3_enum_frame_size(struct v4l2_subdev *sd, 1219 struct v4l2_subdev_state *sd_state, 1220 struct v4l2_subdev_frame_size_enum *fse) 1221 { 1222 int idx; 1223 1224 if (fse->pad == S5C73M3_ISP_PAD) { 1225 if (fse->code != S5C73M3_ISP_FMT) 1226 return -EINVAL; 1227 idx = RES_ISP; 1228 } else{ 1229 if (fse->code != S5C73M3_JPEG_FMT) 1230 return -EINVAL; 1231 idx = RES_JPEG; 1232 } 1233 1234 if (fse->index >= s5c73m3_resolutions_len[idx]) 1235 return -EINVAL; 1236 1237 fse->min_width = s5c73m3_resolutions[idx][fse->index].width; 1238 fse->max_width = fse->min_width; 1239 fse->max_height = s5c73m3_resolutions[idx][fse->index].height; 1240 fse->min_height = fse->max_height; 1241 1242 return 0; 1243 } 1244 1245 static int s5c73m3_oif_enum_frame_size(struct v4l2_subdev *sd, 1246 struct v4l2_subdev_state *sd_state, 1247 struct v4l2_subdev_frame_size_enum *fse) 1248 { 1249 struct s5c73m3 *state = oif_sd_to_s5c73m3(sd); 1250 int idx; 1251 1252 if (fse->pad == OIF_SOURCE_PAD) { 1253 if (fse->index > 0) 1254 return -EINVAL; 1255 1256 switch (fse->code) { 1257 case S5C73M3_JPEG_FMT: 1258 case S5C73M3_ISP_FMT: { 1259 unsigned w, h; 1260 1261 if (fse->which == V4L2_SUBDEV_FORMAT_TRY) { 1262 struct v4l2_mbus_framefmt *mf; 1263 1264 mf = v4l2_subdev_get_try_format(sd, sd_state, 1265 OIF_ISP_PAD); 1266 1267 w = mf->width; 1268 h = mf->height; 1269 } else { 1270 const struct s5c73m3_frame_size *fs; 1271 1272 fs = state->oif_pix_size[RES_ISP]; 1273 w = fs->width; 1274 h = fs->height; 1275 } 1276 fse->max_width = fse->min_width = w; 1277 fse->max_height = fse->min_height = h; 1278 return 0; 1279 } 1280 default: 1281 return -EINVAL; 1282 } 1283 } 1284 1285 if (fse->code != s5c73m3_oif_get_pad_code(fse->pad, 0)) 1286 return -EINVAL; 1287 1288 if (fse->pad == OIF_JPEG_PAD) 1289 idx = RES_JPEG; 1290 else 1291 idx = RES_ISP; 1292 1293 if (fse->index >= s5c73m3_resolutions_len[idx]) 1294 return -EINVAL; 1295 1296 fse->min_width = s5c73m3_resolutions[idx][fse->index].width; 1297 fse->max_width = fse->min_width; 1298 fse->max_height = s5c73m3_resolutions[idx][fse->index].height; 1299 fse->min_height = fse->max_height; 1300 1301 return 0; 1302 } 1303 1304 static int s5c73m3_oif_log_status(struct v4l2_subdev *sd) 1305 { 1306 struct s5c73m3 *state = oif_sd_to_s5c73m3(sd); 1307 1308 v4l2_ctrl_handler_log_status(sd->ctrl_handler, sd->name); 1309 1310 v4l2_info(sd, "power: %d, apply_fmt: %d\n", state->power, 1311 state->apply_fmt); 1312 1313 return 0; 1314 } 1315 1316 static int s5c73m3_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) 1317 { 1318 struct v4l2_mbus_framefmt *mf; 1319 1320 mf = v4l2_subdev_get_try_format(sd, fh->state, S5C73M3_ISP_PAD); 1321 s5c73m3_fill_mbus_fmt(mf, &s5c73m3_isp_resolutions[1], 1322 S5C73M3_ISP_FMT); 1323 1324 mf = v4l2_subdev_get_try_format(sd, fh->state, S5C73M3_JPEG_PAD); 1325 s5c73m3_fill_mbus_fmt(mf, &s5c73m3_jpeg_resolutions[1], 1326 S5C73M3_JPEG_FMT); 1327 1328 return 0; 1329 } 1330 1331 static int s5c73m3_oif_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) 1332 { 1333 struct v4l2_mbus_framefmt *mf; 1334 1335 mf = v4l2_subdev_get_try_format(sd, fh->state, OIF_ISP_PAD); 1336 s5c73m3_fill_mbus_fmt(mf, &s5c73m3_isp_resolutions[1], 1337 S5C73M3_ISP_FMT); 1338 1339 mf = v4l2_subdev_get_try_format(sd, fh->state, OIF_JPEG_PAD); 1340 s5c73m3_fill_mbus_fmt(mf, &s5c73m3_jpeg_resolutions[1], 1341 S5C73M3_JPEG_FMT); 1342 1343 mf = v4l2_subdev_get_try_format(sd, fh->state, OIF_SOURCE_PAD); 1344 s5c73m3_fill_mbus_fmt(mf, &s5c73m3_isp_resolutions[1], 1345 S5C73M3_ISP_FMT); 1346 return 0; 1347 } 1348 1349 static int __s5c73m3_power_on(struct s5c73m3 *state) 1350 { 1351 int i, ret; 1352 1353 for (i = 0; i < S5C73M3_MAX_SUPPLIES; i++) { 1354 ret = regulator_enable(state->supplies[i].consumer); 1355 if (ret) 1356 goto err_reg_dis; 1357 } 1358 1359 ret = clk_set_rate(state->clock, state->mclk_frequency); 1360 if (ret < 0) 1361 goto err_reg_dis; 1362 1363 ret = clk_prepare_enable(state->clock); 1364 if (ret < 0) 1365 goto err_reg_dis; 1366 1367 v4l2_dbg(1, s5c73m3_dbg, &state->oif_sd, "clock frequency: %ld\n", 1368 clk_get_rate(state->clock)); 1369 1370 gpiod_set_value(state->stby, 0); 1371 usleep_range(100, 200); 1372 gpiod_set_value(state->reset, 0); 1373 usleep_range(50, 100); 1374 1375 return 0; 1376 1377 err_reg_dis: 1378 for (--i; i >= 0; i--) 1379 regulator_disable(state->supplies[i].consumer); 1380 return ret; 1381 } 1382 1383 static int __s5c73m3_power_off(struct s5c73m3 *state) 1384 { 1385 int i, ret; 1386 1387 gpiod_set_value(state->reset, 1); 1388 usleep_range(10, 50); 1389 gpiod_set_value(state->stby, 1); 1390 usleep_range(100, 200); 1391 1392 clk_disable_unprepare(state->clock); 1393 1394 state->streaming = 0; 1395 state->isp_ready = 0; 1396 1397 for (i = S5C73M3_MAX_SUPPLIES - 1; i >= 0; i--) { 1398 ret = regulator_disable(state->supplies[i].consumer); 1399 if (ret) 1400 goto err; 1401 } 1402 1403 return 0; 1404 err: 1405 for (++i; i < S5C73M3_MAX_SUPPLIES; i++) { 1406 int r = regulator_enable(state->supplies[i].consumer); 1407 if (r < 0) 1408 v4l2_err(&state->oif_sd, "Failed to re-enable %s: %d\n", 1409 state->supplies[i].supply, r); 1410 } 1411 1412 clk_prepare_enable(state->clock); 1413 return ret; 1414 } 1415 1416 static int s5c73m3_oif_set_power(struct v4l2_subdev *sd, int on) 1417 { 1418 struct s5c73m3 *state = oif_sd_to_s5c73m3(sd); 1419 int ret = 0; 1420 1421 mutex_lock(&state->lock); 1422 1423 if (on && !state->power) { 1424 ret = __s5c73m3_power_on(state); 1425 if (!ret) 1426 ret = s5c73m3_isp_init(state); 1427 if (!ret) { 1428 state->apply_fiv = 1; 1429 state->apply_fmt = 1; 1430 } 1431 } else if (state->power == !on) { 1432 ret = s5c73m3_set_af_softlanding(state); 1433 if (!ret) 1434 ret = __s5c73m3_power_off(state); 1435 else 1436 v4l2_err(sd, "Soft landing lens failed\n"); 1437 } 1438 if (!ret) 1439 state->power += on ? 1 : -1; 1440 1441 v4l2_dbg(1, s5c73m3_dbg, sd, "%s: power: %d\n", 1442 __func__, state->power); 1443 1444 mutex_unlock(&state->lock); 1445 return ret; 1446 } 1447 1448 static int s5c73m3_oif_registered(struct v4l2_subdev *sd) 1449 { 1450 struct s5c73m3 *state = oif_sd_to_s5c73m3(sd); 1451 int ret; 1452 1453 ret = v4l2_device_register_subdev(sd->v4l2_dev, &state->sensor_sd); 1454 if (ret) { 1455 v4l2_err(sd->v4l2_dev, "Failed to register %s\n", 1456 state->oif_sd.name); 1457 return ret; 1458 } 1459 1460 ret = media_create_pad_link(&state->sensor_sd.entity, 1461 S5C73M3_ISP_PAD, &state->oif_sd.entity, OIF_ISP_PAD, 1462 MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED); 1463 1464 ret = media_create_pad_link(&state->sensor_sd.entity, 1465 S5C73M3_JPEG_PAD, &state->oif_sd.entity, OIF_JPEG_PAD, 1466 MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED); 1467 1468 return ret; 1469 } 1470 1471 static void s5c73m3_oif_unregistered(struct v4l2_subdev *sd) 1472 { 1473 struct s5c73m3 *state = oif_sd_to_s5c73m3(sd); 1474 v4l2_device_unregister_subdev(&state->sensor_sd); 1475 } 1476 1477 static const struct v4l2_subdev_internal_ops s5c73m3_internal_ops = { 1478 .open = s5c73m3_open, 1479 }; 1480 1481 static const struct v4l2_subdev_pad_ops s5c73m3_pad_ops = { 1482 .enum_mbus_code = s5c73m3_enum_mbus_code, 1483 .enum_frame_size = s5c73m3_enum_frame_size, 1484 .get_fmt = s5c73m3_get_fmt, 1485 .set_fmt = s5c73m3_set_fmt, 1486 }; 1487 1488 static const struct v4l2_subdev_ops s5c73m3_subdev_ops = { 1489 .pad = &s5c73m3_pad_ops, 1490 }; 1491 1492 static const struct v4l2_subdev_internal_ops oif_internal_ops = { 1493 .registered = s5c73m3_oif_registered, 1494 .unregistered = s5c73m3_oif_unregistered, 1495 .open = s5c73m3_oif_open, 1496 }; 1497 1498 static const struct v4l2_subdev_pad_ops s5c73m3_oif_pad_ops = { 1499 .enum_mbus_code = s5c73m3_oif_enum_mbus_code, 1500 .enum_frame_size = s5c73m3_oif_enum_frame_size, 1501 .enum_frame_interval = s5c73m3_oif_enum_frame_interval, 1502 .get_fmt = s5c73m3_oif_get_fmt, 1503 .set_fmt = s5c73m3_oif_set_fmt, 1504 .get_frame_desc = s5c73m3_oif_get_frame_desc, 1505 .set_frame_desc = s5c73m3_oif_set_frame_desc, 1506 }; 1507 1508 static const struct v4l2_subdev_core_ops s5c73m3_oif_core_ops = { 1509 .s_power = s5c73m3_oif_set_power, 1510 .log_status = s5c73m3_oif_log_status, 1511 }; 1512 1513 static const struct v4l2_subdev_video_ops s5c73m3_oif_video_ops = { 1514 .s_stream = s5c73m3_oif_s_stream, 1515 .g_frame_interval = s5c73m3_oif_g_frame_interval, 1516 .s_frame_interval = s5c73m3_oif_s_frame_interval, 1517 }; 1518 1519 static const struct v4l2_subdev_ops oif_subdev_ops = { 1520 .core = &s5c73m3_oif_core_ops, 1521 .pad = &s5c73m3_oif_pad_ops, 1522 .video = &s5c73m3_oif_video_ops, 1523 }; 1524 1525 static int s5c73m3_get_platform_data(struct s5c73m3 *state) 1526 { 1527 struct i2c_client *c = state->i2c_client; 1528 struct device *dev = &c->dev; 1529 const struct s5c73m3_platform_data *pdata = dev->platform_data; 1530 struct device_node *node = dev->of_node; 1531 struct device_node *node_ep; 1532 struct v4l2_fwnode_endpoint ep = { .bus_type = 0 }; 1533 int ret; 1534 1535 if (!node) { 1536 if (!pdata) { 1537 dev_err(dev, "Platform data not specified\n"); 1538 return -EINVAL; 1539 } 1540 1541 state->mclk_frequency = pdata->mclk_frequency; 1542 return 0; 1543 } 1544 1545 state->clock = devm_clk_get(dev, S5C73M3_CLK_NAME); 1546 if (IS_ERR(state->clock)) 1547 return PTR_ERR(state->clock); 1548 1549 if (of_property_read_u32(node, "clock-frequency", 1550 &state->mclk_frequency)) { 1551 state->mclk_frequency = S5C73M3_DEFAULT_MCLK_FREQ; 1552 dev_info(dev, "using default %u Hz clock frequency\n", 1553 state->mclk_frequency); 1554 } 1555 1556 /* Request GPIO lines asserted */ 1557 state->stby = devm_gpiod_get(dev, "standby", GPIOD_OUT_HIGH); 1558 if (IS_ERR(state->stby)) 1559 return dev_err_probe(dev, PTR_ERR(state->stby), 1560 "failed to request gpio S5C73M3_STBY\n"); 1561 gpiod_set_consumer_name(state->stby, "S5C73M3_STBY"); 1562 state->reset = devm_gpiod_get(dev, "xshutdown", GPIOD_OUT_HIGH); 1563 if (IS_ERR(state->reset)) 1564 return dev_err_probe(dev, PTR_ERR(state->reset), 1565 "failed to request gpio S5C73M3_RST\n"); 1566 gpiod_set_consumer_name(state->reset, "S5C73M3_RST"); 1567 1568 node_ep = of_graph_get_next_endpoint(node, NULL); 1569 if (!node_ep) { 1570 dev_warn(dev, "no endpoint defined for node: %pOF\n", node); 1571 return 0; 1572 } 1573 1574 ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(node_ep), &ep); 1575 of_node_put(node_ep); 1576 if (ret) 1577 return ret; 1578 1579 if (ep.bus_type != V4L2_MBUS_CSI2_DPHY) { 1580 dev_err(dev, "unsupported bus type\n"); 1581 return -EINVAL; 1582 } 1583 /* 1584 * Number of MIPI CSI-2 data lanes is currently not configurable, 1585 * always a default value of 4 lanes is used. 1586 */ 1587 if (ep.bus.mipi_csi2.num_data_lanes != S5C73M3_MIPI_DATA_LANES) 1588 dev_info(dev, "falling back to 4 MIPI CSI-2 data lanes\n"); 1589 1590 return 0; 1591 } 1592 1593 static int s5c73m3_probe(struct i2c_client *client) 1594 { 1595 struct device *dev = &client->dev; 1596 struct v4l2_subdev *sd; 1597 struct v4l2_subdev *oif_sd; 1598 struct s5c73m3 *state; 1599 int ret, i; 1600 1601 state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL); 1602 if (!state) 1603 return -ENOMEM; 1604 1605 state->i2c_client = client; 1606 ret = s5c73m3_get_platform_data(state); 1607 if (ret < 0) 1608 return ret; 1609 1610 mutex_init(&state->lock); 1611 sd = &state->sensor_sd; 1612 oif_sd = &state->oif_sd; 1613 1614 v4l2_subdev_init(sd, &s5c73m3_subdev_ops); 1615 sd->owner = client->dev.driver->owner; 1616 v4l2_set_subdevdata(sd, state); 1617 strscpy(sd->name, "S5C73M3", sizeof(sd->name)); 1618 1619 sd->internal_ops = &s5c73m3_internal_ops; 1620 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1621 1622 state->sensor_pads[S5C73M3_JPEG_PAD].flags = MEDIA_PAD_FL_SOURCE; 1623 state->sensor_pads[S5C73M3_ISP_PAD].flags = MEDIA_PAD_FL_SOURCE; 1624 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR; 1625 1626 ret = media_entity_pads_init(&sd->entity, S5C73M3_NUM_PADS, 1627 state->sensor_pads); 1628 if (ret < 0) 1629 return ret; 1630 1631 v4l2_i2c_subdev_init(oif_sd, client, &oif_subdev_ops); 1632 /* Static name; NEVER use in new drivers! */ 1633 strscpy(oif_sd->name, "S5C73M3-OIF", sizeof(oif_sd->name)); 1634 1635 oif_sd->internal_ops = &oif_internal_ops; 1636 oif_sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1637 1638 state->oif_pads[OIF_ISP_PAD].flags = MEDIA_PAD_FL_SINK; 1639 state->oif_pads[OIF_JPEG_PAD].flags = MEDIA_PAD_FL_SINK; 1640 state->oif_pads[OIF_SOURCE_PAD].flags = MEDIA_PAD_FL_SOURCE; 1641 oif_sd->entity.function = MEDIA_ENT_F_PROC_VIDEO_SCALER; 1642 1643 ret = media_entity_pads_init(&oif_sd->entity, OIF_NUM_PADS, 1644 state->oif_pads); 1645 if (ret < 0) 1646 return ret; 1647 1648 for (i = 0; i < S5C73M3_MAX_SUPPLIES; i++) 1649 state->supplies[i].supply = s5c73m3_supply_names[i]; 1650 1651 ret = devm_regulator_bulk_get(dev, S5C73M3_MAX_SUPPLIES, 1652 state->supplies); 1653 if (ret) { 1654 dev_err(dev, "failed to get regulators\n"); 1655 goto out_err; 1656 } 1657 1658 ret = s5c73m3_init_controls(state); 1659 if (ret) 1660 goto out_err; 1661 1662 state->sensor_pix_size[RES_ISP] = &s5c73m3_isp_resolutions[1]; 1663 state->sensor_pix_size[RES_JPEG] = &s5c73m3_jpeg_resolutions[1]; 1664 state->oif_pix_size[RES_ISP] = state->sensor_pix_size[RES_ISP]; 1665 state->oif_pix_size[RES_JPEG] = state->sensor_pix_size[RES_JPEG]; 1666 1667 state->mbus_code = S5C73M3_ISP_FMT; 1668 1669 state->fiv = &s5c73m3_intervals[S5C73M3_DEFAULT_FRAME_INTERVAL]; 1670 1671 state->fw_file_version[0] = 'G'; 1672 state->fw_file_version[1] = 'C'; 1673 1674 ret = s5c73m3_register_spi_driver(state); 1675 if (ret < 0) 1676 goto out_err; 1677 1678 oif_sd->dev = dev; 1679 1680 ret = __s5c73m3_power_on(state); 1681 if (ret < 0) 1682 goto out_err1; 1683 1684 ret = s5c73m3_get_fw_version(state); 1685 __s5c73m3_power_off(state); 1686 1687 if (ret < 0) { 1688 dev_err(dev, "Device detection failed: %d\n", ret); 1689 goto out_err1; 1690 } 1691 1692 ret = v4l2_async_register_subdev(oif_sd); 1693 if (ret < 0) 1694 goto out_err1; 1695 1696 v4l2_info(sd, "%s: completed successfully\n", __func__); 1697 return 0; 1698 1699 out_err1: 1700 s5c73m3_unregister_spi_driver(state); 1701 out_err: 1702 media_entity_cleanup(&sd->entity); 1703 return ret; 1704 } 1705 1706 static void s5c73m3_remove(struct i2c_client *client) 1707 { 1708 struct v4l2_subdev *oif_sd = i2c_get_clientdata(client); 1709 struct s5c73m3 *state = oif_sd_to_s5c73m3(oif_sd); 1710 struct v4l2_subdev *sensor_sd = &state->sensor_sd; 1711 1712 v4l2_async_unregister_subdev(oif_sd); 1713 1714 v4l2_ctrl_handler_free(oif_sd->ctrl_handler); 1715 media_entity_cleanup(&oif_sd->entity); 1716 1717 v4l2_device_unregister_subdev(sensor_sd); 1718 media_entity_cleanup(&sensor_sd->entity); 1719 1720 s5c73m3_unregister_spi_driver(state); 1721 } 1722 1723 static const struct i2c_device_id s5c73m3_id[] = { 1724 { DRIVER_NAME, 0 }, 1725 { } 1726 }; 1727 MODULE_DEVICE_TABLE(i2c, s5c73m3_id); 1728 1729 #ifdef CONFIG_OF 1730 static const struct of_device_id s5c73m3_of_match[] = { 1731 { .compatible = "samsung,s5c73m3" }, 1732 { } 1733 }; 1734 MODULE_DEVICE_TABLE(of, s5c73m3_of_match); 1735 #endif 1736 1737 static struct i2c_driver s5c73m3_i2c_driver = { 1738 .driver = { 1739 .of_match_table = of_match_ptr(s5c73m3_of_match), 1740 .name = DRIVER_NAME, 1741 }, 1742 .probe_new = s5c73m3_probe, 1743 .remove = s5c73m3_remove, 1744 .id_table = s5c73m3_id, 1745 }; 1746 1747 module_i2c_driver(s5c73m3_i2c_driver); 1748 1749 MODULE_DESCRIPTION("Samsung S5C73M3 camera driver"); 1750 MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>"); 1751 MODULE_LICENSE("GPL"); 1752