1 /* 2 * Omnivision OV9650/OV9652 CMOS Image Sensor driver 3 * 4 * Copyright (C) 2013, Sylwester Nawrocki <sylvester.nawrocki@gmail.com> 5 * 6 * Register definitions and initial settings based on a driver written 7 * by Vladimir Fonov. 8 * Copyright (c) 2010, Vladimir Fonov 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 #include <linux/clk.h> 15 #include <linux/delay.h> 16 #include <linux/gpio.h> 17 #include <linux/gpio/consumer.h> 18 #include <linux/i2c.h> 19 #include <linux/kernel.h> 20 #include <linux/media.h> 21 #include <linux/module.h> 22 #include <linux/ratelimit.h> 23 #include <linux/regmap.h> 24 #include <linux/slab.h> 25 #include <linux/string.h> 26 #include <linux/videodev2.h> 27 28 #include <media/media-entity.h> 29 #include <media/v4l2-async.h> 30 #include <media/v4l2-ctrls.h> 31 #include <media/v4l2-device.h> 32 #include <media/v4l2-event.h> 33 #include <media/v4l2-image-sizes.h> 34 #include <media/v4l2-subdev.h> 35 #include <media/v4l2-mediabus.h> 36 #include <media/i2c/ov9650.h> 37 38 static int debug; 39 module_param(debug, int, 0644); 40 MODULE_PARM_DESC(debug, "Debug level (0-2)"); 41 42 #define DRIVER_NAME "OV9650" 43 44 /* 45 * OV9650/OV9652 register definitions 46 */ 47 #define REG_GAIN 0x00 /* Gain control, AGC[7:0] */ 48 #define REG_BLUE 0x01 /* AWB - Blue chanel gain */ 49 #define REG_RED 0x02 /* AWB - Red chanel gain */ 50 #define REG_VREF 0x03 /* [7:6] - AGC[9:8], [5:3]/[2:0] */ 51 #define VREF_GAIN_MASK 0xc0 /* - VREF end/start low 3 bits */ 52 #define REG_COM1 0x04 53 #define COM1_CCIR656 0x40 54 #define REG_B_AVE 0x05 55 #define REG_GB_AVE 0x06 56 #define REG_GR_AVE 0x07 57 #define REG_R_AVE 0x08 58 #define REG_COM2 0x09 59 #define REG_PID 0x0a /* Product ID MSB */ 60 #define REG_VER 0x0b /* Product ID LSB */ 61 #define REG_COM3 0x0c 62 #define COM3_SWAP 0x40 63 #define COM3_VARIOPIXEL1 0x04 64 #define REG_COM4 0x0d /* Vario Pixels */ 65 #define COM4_VARIOPIXEL2 0x80 66 #define REG_COM5 0x0e /* System clock options */ 67 #define COM5_SLAVE_MODE 0x10 68 #define COM5_SYSTEMCLOCK48MHZ 0x80 69 #define REG_COM6 0x0f /* HREF & ADBLC options */ 70 #define REG_AECH 0x10 /* Exposure value, AEC[9:2] */ 71 #define REG_CLKRC 0x11 /* Clock control */ 72 #define CLK_EXT 0x40 /* Use external clock directly */ 73 #define CLK_SCALE 0x3f /* Mask for internal clock scale */ 74 #define REG_COM7 0x12 /* SCCB reset, output format */ 75 #define COM7_RESET 0x80 76 #define COM7_FMT_MASK 0x38 77 #define COM7_FMT_VGA 0x40 78 #define COM7_FMT_CIF 0x20 79 #define COM7_FMT_QVGA 0x10 80 #define COM7_FMT_QCIF 0x08 81 #define COM7_RGB 0x04 82 #define COM7_YUV 0x00 83 #define COM7_BAYER 0x01 84 #define COM7_PBAYER 0x05 85 #define REG_COM8 0x13 /* AGC/AEC options */ 86 #define COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */ 87 #define COM8_AECSTEP 0x40 /* Unlimited AEC step size */ 88 #define COM8_BFILT 0x20 /* Band filter enable */ 89 #define COM8_AGC 0x04 /* Auto gain enable */ 90 #define COM8_AWB 0x02 /* White balance enable */ 91 #define COM8_AEC 0x01 /* Auto exposure enable */ 92 #define REG_COM9 0x14 /* Gain ceiling */ 93 #define COM9_GAIN_CEIL_MASK 0x70 /* */ 94 #define REG_COM10 0x15 /* PCLK, HREF, HSYNC signals polarity */ 95 #define COM10_HSYNC 0x40 /* HSYNC instead of HREF */ 96 #define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */ 97 #define COM10_HREF_REV 0x08 /* Reverse HREF */ 98 #define COM10_VS_LEAD 0x04 /* VSYNC on clock leading edge */ 99 #define COM10_VS_NEG 0x02 /* VSYNC negative */ 100 #define COM10_HS_NEG 0x01 /* HSYNC negative */ 101 #define REG_HSTART 0x17 /* Horiz start high bits */ 102 #define REG_HSTOP 0x18 /* Horiz stop high bits */ 103 #define REG_VSTART 0x19 /* Vert start high bits */ 104 #define REG_VSTOP 0x1a /* Vert stop high bits */ 105 #define REG_PSHFT 0x1b /* Pixel delay after HREF */ 106 #define REG_MIDH 0x1c /* Manufacturer ID MSB */ 107 #define REG_MIDL 0x1d /* Manufufacturer ID LSB */ 108 #define REG_MVFP 0x1e /* Image mirror/flip */ 109 #define MVFP_MIRROR 0x20 /* Mirror image */ 110 #define MVFP_FLIP 0x10 /* Vertical flip */ 111 #define REG_BOS 0x20 /* B channel Offset */ 112 #define REG_GBOS 0x21 /* Gb channel Offset */ 113 #define REG_GROS 0x22 /* Gr channel Offset */ 114 #define REG_ROS 0x23 /* R channel Offset */ 115 #define REG_AEW 0x24 /* AGC upper limit */ 116 #define REG_AEB 0x25 /* AGC lower limit */ 117 #define REG_VPT 0x26 /* AGC/AEC fast mode op region */ 118 #define REG_BBIAS 0x27 /* B channel output bias */ 119 #define REG_GBBIAS 0x28 /* Gb channel output bias */ 120 #define REG_GRCOM 0x29 /* Analog BLC & regulator */ 121 #define REG_EXHCH 0x2a /* Dummy pixel insert MSB */ 122 #define REG_EXHCL 0x2b /* Dummy pixel insert LSB */ 123 #define REG_RBIAS 0x2c /* R channel output bias */ 124 #define REG_ADVFL 0x2d /* LSB of dummy line insert */ 125 #define REG_ADVFH 0x2e /* MSB of dummy line insert */ 126 #define REG_YAVE 0x2f /* Y/G channel average value */ 127 #define REG_HSYST 0x30 /* HSYNC rising edge delay LSB*/ 128 #define REG_HSYEN 0x31 /* HSYNC falling edge delay LSB*/ 129 #define REG_HREF 0x32 /* HREF pieces */ 130 #define REG_CHLF 0x33 /* reserved */ 131 #define REG_ADC 0x37 /* reserved */ 132 #define REG_ACOM 0x38 /* reserved */ 133 #define REG_OFON 0x39 /* Power down register */ 134 #define OFON_PWRDN 0x08 /* Power down bit */ 135 #define REG_TSLB 0x3a /* YUVU format */ 136 #define TSLB_YUYV_MASK 0x0c /* UYVY or VYUY - see com13 */ 137 #define REG_COM11 0x3b /* Night mode, banding filter enable */ 138 #define COM11_NIGHT 0x80 /* Night mode enable */ 139 #define COM11_NMFR 0x60 /* Two bit NM frame rate */ 140 #define COM11_BANDING 0x01 /* Banding filter */ 141 #define COM11_AEC_REF_MASK 0x18 /* AEC reference area selection */ 142 #define REG_COM12 0x3c /* HREF option, UV average */ 143 #define COM12_HREF 0x80 /* HREF always */ 144 #define REG_COM13 0x3d /* Gamma selection, Color matrix en. */ 145 #define COM13_GAMMA 0x80 /* Gamma enable */ 146 #define COM13_UVSAT 0x40 /* UV saturation auto adjustment */ 147 #define COM13_UVSWAP 0x01 /* V before U - w/TSLB */ 148 #define REG_COM14 0x3e /* Edge enhancement options */ 149 #define COM14_EDGE_EN 0x02 150 #define COM14_EEF_X2 0x01 151 #define REG_EDGE 0x3f /* Edge enhancement factor */ 152 #define EDGE_FACTOR_MASK 0x0f 153 #define REG_COM15 0x40 /* Output range, RGB 555/565 */ 154 #define COM15_R10F0 0x00 /* Data range 10 to F0 */ 155 #define COM15_R01FE 0x80 /* 01 to FE */ 156 #define COM15_R00FF 0xc0 /* 00 to FF */ 157 #define COM15_RGB565 0x10 /* RGB565 output */ 158 #define COM15_RGB555 0x30 /* RGB555 output */ 159 #define COM15_SWAPRB 0x04 /* Swap R&B */ 160 #define REG_COM16 0x41 /* Color matrix coeff options */ 161 #define REG_COM17 0x42 /* Single frame out, banding filter */ 162 /* n = 1...9, 0x4f..0x57 */ 163 #define REG_MTX(__n) (0x4f + (__n) - 1) 164 #define REG_MTXS 0x58 165 /* Lens Correction Option 1...5, __n = 0...5 */ 166 #define REG_LCC(__n) (0x62 + (__n) - 1) 167 #define LCC5_LCC_ENABLE 0x01 /* LCC5, enable lens correction */ 168 #define LCC5_LCC_COLOR 0x04 169 #define REG_MANU 0x67 /* Manual U value */ 170 #define REG_MANV 0x68 /* Manual V value */ 171 #define REG_HV 0x69 /* Manual banding filter MSB */ 172 #define REG_MBD 0x6a /* Manual banding filter value */ 173 #define REG_DBLV 0x6b /* reserved */ 174 #define REG_GSP 0x6c /* Gamma curve */ 175 #define GSP_LEN 15 176 #define REG_GST 0x7c /* Gamma curve */ 177 #define GST_LEN 15 178 #define REG_COM21 0x8b 179 #define REG_COM22 0x8c /* Edge enhancement, denoising */ 180 #define COM22_WHTPCOR 0x02 /* White pixel correction enable */ 181 #define COM22_WHTPCOROPT 0x01 /* White pixel correction option */ 182 #define COM22_DENOISE 0x10 /* White pixel correction option */ 183 #define REG_COM23 0x8d /* Color bar test, color gain */ 184 #define COM23_TEST_MODE 0x10 185 #define REG_DBLC1 0x8f /* Digital BLC */ 186 #define REG_DBLC_B 0x90 /* Digital BLC B channel offset */ 187 #define REG_DBLC_R 0x91 /* Digital BLC R channel offset */ 188 #define REG_DM_LNL 0x92 /* Dummy line low 8 bits */ 189 #define REG_DM_LNH 0x93 /* Dummy line high 8 bits */ 190 #define REG_LCCFB 0x9d /* Lens Correction B channel */ 191 #define REG_LCCFR 0x9e /* Lens Correction R channel */ 192 #define REG_DBLC_GB 0x9f /* Digital BLC GB chan offset */ 193 #define REG_DBLC_GR 0xa0 /* Digital BLC GR chan offset */ 194 #define REG_AECHM 0xa1 /* Exposure value - bits AEC[15:10] */ 195 #define REG_BD50ST 0xa2 /* Banding filter value for 50Hz */ 196 #define REG_BD60ST 0xa3 /* Banding filter value for 60Hz */ 197 #define REG_NULL 0xff /* Array end token */ 198 199 #define DEF_CLKRC 0x80 200 201 #define OV965X_ID(_msb, _lsb) ((_msb) << 8 | (_lsb)) 202 #define OV9650_ID 0x9650 203 #define OV9652_ID 0x9652 204 205 struct ov965x_ctrls { 206 struct v4l2_ctrl_handler handler; 207 struct { 208 struct v4l2_ctrl *auto_exp; 209 struct v4l2_ctrl *exposure; 210 }; 211 struct { 212 struct v4l2_ctrl *auto_wb; 213 struct v4l2_ctrl *blue_balance; 214 struct v4l2_ctrl *red_balance; 215 }; 216 struct { 217 struct v4l2_ctrl *hflip; 218 struct v4l2_ctrl *vflip; 219 }; 220 struct { 221 struct v4l2_ctrl *auto_gain; 222 struct v4l2_ctrl *gain; 223 }; 224 struct v4l2_ctrl *brightness; 225 struct v4l2_ctrl *saturation; 226 struct v4l2_ctrl *sharpness; 227 struct v4l2_ctrl *light_freq; 228 u8 update; 229 }; 230 231 struct ov965x_framesize { 232 u16 width; 233 u16 height; 234 u16 max_exp_lines; 235 const u8 *regs; 236 }; 237 238 struct ov965x_interval { 239 struct v4l2_fract interval; 240 /* Maximum resolution for this interval */ 241 struct v4l2_frmsize_discrete size; 242 u8 clkrc_div; 243 }; 244 245 enum gpio_id { 246 GPIO_PWDN, 247 GPIO_RST, 248 NUM_GPIOS, 249 }; 250 251 struct ov965x { 252 struct v4l2_subdev sd; 253 struct media_pad pad; 254 enum v4l2_mbus_type bus_type; 255 struct gpio_desc *gpios[NUM_GPIOS]; 256 /* External master clock frequency */ 257 unsigned long mclk_frequency; 258 struct clk *clk; 259 260 /* Protects the struct fields below */ 261 struct mutex lock; 262 263 struct regmap *regmap; 264 265 /* Exposure row interval in us */ 266 unsigned int exp_row_interval; 267 268 unsigned short id; 269 const struct ov965x_framesize *frame_size; 270 /* YUYV sequence (pixel format) control register */ 271 u8 tslb_reg; 272 struct v4l2_mbus_framefmt format; 273 274 struct ov965x_ctrls ctrls; 275 /* Pointer to frame rate control data structure */ 276 const struct ov965x_interval *fiv; 277 278 int streaming; 279 int power; 280 281 u8 apply_frame_fmt; 282 }; 283 284 struct i2c_rv { 285 u8 addr; 286 u8 value; 287 }; 288 289 static const struct i2c_rv ov965x_init_regs[] = { 290 { REG_COM2, 0x10 }, /* Set soft sleep mode */ 291 { REG_COM5, 0x00 }, /* System clock options */ 292 { REG_COM2, 0x01 }, /* Output drive, soft sleep mode */ 293 { REG_COM10, 0x00 }, /* Slave mode, HREF vs HSYNC, signals negate */ 294 { REG_EDGE, 0xa6 }, /* Edge enhancement treshhold and factor */ 295 { REG_COM16, 0x02 }, /* Color matrix coeff double option */ 296 { REG_COM17, 0x08 }, /* Single frame out, banding filter */ 297 { 0x16, 0x06 }, 298 { REG_CHLF, 0xc0 }, /* Reserved */ 299 { 0x34, 0xbf }, 300 { 0xa8, 0x80 }, 301 { 0x96, 0x04 }, 302 { 0x8e, 0x00 }, 303 { REG_COM12, 0x77 }, /* HREF option, UV average */ 304 { 0x8b, 0x06 }, 305 { 0x35, 0x91 }, 306 { 0x94, 0x88 }, 307 { 0x95, 0x88 }, 308 { REG_COM15, 0xc1 }, /* Output range, RGB 555/565 */ 309 { REG_GRCOM, 0x2f }, /* Analog BLC & regulator */ 310 { REG_COM6, 0x43 }, /* HREF & ADBLC options */ 311 { REG_COM8, 0xe5 }, /* AGC/AEC options */ 312 { REG_COM13, 0x90 }, /* Gamma selection, colour matrix, UV delay */ 313 { REG_HV, 0x80 }, /* Manual banding filter MSB */ 314 { 0x5c, 0x96 }, /* Reserved up to 0xa5 */ 315 { 0x5d, 0x96 }, 316 { 0x5e, 0x10 }, 317 { 0x59, 0xeb }, 318 { 0x5a, 0x9c }, 319 { 0x5b, 0x55 }, 320 { 0x43, 0xf0 }, 321 { 0x44, 0x10 }, 322 { 0x45, 0x55 }, 323 { 0x46, 0x86 }, 324 { 0x47, 0x64 }, 325 { 0x48, 0x86 }, 326 { 0x5f, 0xe0 }, 327 { 0x60, 0x8c }, 328 { 0x61, 0x20 }, 329 { 0xa5, 0xd9 }, 330 { 0xa4, 0x74 }, /* reserved */ 331 { REG_COM23, 0x02 }, /* Color gain analog/_digital_ */ 332 { REG_COM8, 0xe7 }, /* Enable AEC, AWB, AEC */ 333 { REG_COM22, 0x23 }, /* Edge enhancement, denoising */ 334 { 0xa9, 0xb8 }, 335 { 0xaa, 0x92 }, 336 { 0xab, 0x0a }, 337 { REG_DBLC1, 0xdf }, /* Digital BLC */ 338 { REG_DBLC_B, 0x00 }, /* Digital BLC B chan offset */ 339 { REG_DBLC_R, 0x00 }, /* Digital BLC R chan offset */ 340 { REG_DBLC_GB, 0x00 }, /* Digital BLC GB chan offset */ 341 { REG_DBLC_GR, 0x00 }, 342 { REG_COM9, 0x3a }, /* Gain ceiling 16x */ 343 { REG_NULL, 0 } 344 }; 345 346 #define NUM_FMT_REGS 14 347 /* 348 * COM7, COM3, COM4, HSTART, HSTOP, HREF, VSTART, VSTOP, VREF, 349 * EXHCH, EXHCL, ADC, OCOM, OFON 350 */ 351 static const u8 frame_size_reg_addr[NUM_FMT_REGS] = { 352 0x12, 0x0c, 0x0d, 0x17, 0x18, 0x32, 0x19, 0x1a, 0x03, 353 0x2a, 0x2b, 0x37, 0x38, 0x39, 354 }; 355 356 static const u8 ov965x_sxga_regs[NUM_FMT_REGS] = { 357 0x00, 0x00, 0x00, 0x1e, 0xbe, 0xbf, 0x01, 0x81, 0x12, 358 0x10, 0x34, 0x81, 0x93, 0x51, 359 }; 360 361 static const u8 ov965x_vga_regs[NUM_FMT_REGS] = { 362 0x40, 0x04, 0x80, 0x26, 0xc6, 0xed, 0x01, 0x3d, 0x00, 363 0x10, 0x40, 0x91, 0x12, 0x43, 364 }; 365 366 /* Determined empirically. */ 367 static const u8 ov965x_qvga_regs[NUM_FMT_REGS] = { 368 0x10, 0x04, 0x80, 0x25, 0xc5, 0xbf, 0x00, 0x80, 0x12, 369 0x10, 0x40, 0x91, 0x12, 0x43, 370 }; 371 372 static const struct ov965x_framesize ov965x_framesizes[] = { 373 { 374 .width = SXGA_WIDTH, 375 .height = SXGA_HEIGHT, 376 .regs = ov965x_sxga_regs, 377 .max_exp_lines = 1048, 378 }, { 379 .width = VGA_WIDTH, 380 .height = VGA_HEIGHT, 381 .regs = ov965x_vga_regs, 382 .max_exp_lines = 498, 383 }, { 384 .width = QVGA_WIDTH, 385 .height = QVGA_HEIGHT, 386 .regs = ov965x_qvga_regs, 387 .max_exp_lines = 248, 388 }, 389 }; 390 391 struct ov965x_pixfmt { 392 u32 code; 393 u32 colorspace; 394 /* REG_TSLB value, only bits [3:2] may be set. */ 395 u8 tslb_reg; 396 }; 397 398 static const struct ov965x_pixfmt ov965x_formats[] = { 399 { MEDIA_BUS_FMT_YUYV8_2X8, V4L2_COLORSPACE_JPEG, 0x00}, 400 { MEDIA_BUS_FMT_YVYU8_2X8, V4L2_COLORSPACE_JPEG, 0x04}, 401 { MEDIA_BUS_FMT_UYVY8_2X8, V4L2_COLORSPACE_JPEG, 0x0c}, 402 { MEDIA_BUS_FMT_VYUY8_2X8, V4L2_COLORSPACE_JPEG, 0x08}, 403 }; 404 405 /* 406 * This table specifies possible frame resolution and interval 407 * combinations. Default CLKRC[5:0] divider values are valid 408 * only for 24 MHz external clock frequency. 409 */ 410 static struct ov965x_interval ov965x_intervals[] = { 411 {{ 100, 625 }, { SXGA_WIDTH, SXGA_HEIGHT }, 0 }, /* 6.25 fps */ 412 {{ 10, 125 }, { VGA_WIDTH, VGA_HEIGHT }, 1 }, /* 12.5 fps */ 413 {{ 10, 125 }, { QVGA_WIDTH, QVGA_HEIGHT }, 3 }, /* 12.5 fps */ 414 {{ 1, 25 }, { VGA_WIDTH, VGA_HEIGHT }, 0 }, /* 25 fps */ 415 {{ 1, 25 }, { QVGA_WIDTH, QVGA_HEIGHT }, 1 }, /* 25 fps */ 416 }; 417 418 static inline struct v4l2_subdev *ctrl_to_sd(struct v4l2_ctrl *ctrl) 419 { 420 return &container_of(ctrl->handler, struct ov965x, ctrls.handler)->sd; 421 } 422 423 static inline struct ov965x *to_ov965x(struct v4l2_subdev *sd) 424 { 425 return container_of(sd, struct ov965x, sd); 426 } 427 428 static int ov965x_read(struct ov965x *ov965x, u8 addr, u8 *val) 429 { 430 int ret; 431 unsigned int buf; 432 433 ret = regmap_read(ov965x->regmap, addr, &buf); 434 if (!ret) 435 *val = buf; 436 437 v4l2_dbg(2, debug, &ov965x->sd, "%s: 0x%02x @ 0x%02x. (%d)\n", 438 __func__, *val, addr, ret); 439 440 return ret; 441 } 442 443 static int ov965x_write(struct ov965x *ov965x, u8 addr, u8 val) 444 { 445 int ret; 446 447 ret = regmap_write(ov965x->regmap, addr, val); 448 449 v4l2_dbg(2, debug, &ov965x->sd, "%s: 0x%02x @ 0x%02X (%d)\n", 450 __func__, val, addr, ret); 451 452 return ret; 453 } 454 455 static int ov965x_write_array(struct ov965x *ov965x, 456 const struct i2c_rv *regs) 457 { 458 int i, ret = 0; 459 460 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) 461 ret = ov965x_write(ov965x, regs[i].addr, regs[i].value); 462 463 return ret; 464 } 465 466 static int ov965x_set_default_gamma_curve(struct ov965x *ov965x) 467 { 468 static const u8 gamma_curve[] = { 469 /* Values taken from OV application note. */ 470 0x40, 0x30, 0x4b, 0x60, 0x70, 0x70, 0x70, 0x70, 471 0x60, 0x60, 0x50, 0x48, 0x3a, 0x2e, 0x28, 0x22, 472 0x04, 0x07, 0x10, 0x28, 0x36, 0x44, 0x52, 0x60, 473 0x6c, 0x78, 0x8c, 0x9e, 0xbb, 0xd2, 0xe6 474 }; 475 u8 addr = REG_GSP; 476 unsigned int i; 477 478 for (i = 0; i < ARRAY_SIZE(gamma_curve); i++) { 479 int ret = ov965x_write(ov965x, addr, gamma_curve[i]); 480 481 if (ret < 0) 482 return ret; 483 addr++; 484 } 485 486 return 0; 487 }; 488 489 static int ov965x_set_color_matrix(struct ov965x *ov965x) 490 { 491 static const u8 mtx[] = { 492 /* MTX1..MTX9, MTXS */ 493 0x3a, 0x3d, 0x03, 0x12, 0x26, 0x38, 0x40, 0x40, 0x40, 0x0d 494 }; 495 u8 addr = REG_MTX(1); 496 unsigned int i; 497 498 for (i = 0; i < ARRAY_SIZE(mtx); i++) { 499 int ret = ov965x_write(ov965x, addr, mtx[i]); 500 501 if (ret < 0) 502 return ret; 503 addr++; 504 } 505 506 return 0; 507 } 508 509 static int __ov965x_set_power(struct ov965x *ov965x, int on) 510 { 511 if (on) { 512 int ret = clk_prepare_enable(ov965x->clk); 513 514 if (ret) 515 return ret; 516 517 gpiod_set_value_cansleep(ov965x->gpios[GPIO_PWDN], 0); 518 gpiod_set_value_cansleep(ov965x->gpios[GPIO_RST], 0); 519 msleep(25); 520 } else { 521 gpiod_set_value_cansleep(ov965x->gpios[GPIO_RST], 1); 522 gpiod_set_value_cansleep(ov965x->gpios[GPIO_PWDN], 1); 523 524 clk_disable_unprepare(ov965x->clk); 525 } 526 527 ov965x->streaming = 0; 528 529 return 0; 530 } 531 532 static int ov965x_s_power(struct v4l2_subdev *sd, int on) 533 { 534 struct ov965x *ov965x = to_ov965x(sd); 535 int ret = 0; 536 537 v4l2_dbg(1, debug, sd, "%s: on: %d\n", __func__, on); 538 539 mutex_lock(&ov965x->lock); 540 if (ov965x->power == !on) { 541 ret = __ov965x_set_power(ov965x, on); 542 if (!ret && on) { 543 ret = ov965x_write_array(ov965x, 544 ov965x_init_regs); 545 ov965x->apply_frame_fmt = 1; 546 ov965x->ctrls.update = 1; 547 } 548 } 549 if (!ret) 550 ov965x->power += on ? 1 : -1; 551 552 WARN_ON(ov965x->power < 0); 553 mutex_unlock(&ov965x->lock); 554 return ret; 555 } 556 557 /* 558 * V4L2 controls 559 */ 560 561 static void ov965x_update_exposure_ctrl(struct ov965x *ov965x) 562 { 563 struct v4l2_ctrl *ctrl = ov965x->ctrls.exposure; 564 unsigned long fint, trow; 565 int min, max, def; 566 u8 clkrc; 567 568 mutex_lock(&ov965x->lock); 569 if (WARN_ON(!ctrl || !ov965x->frame_size)) { 570 mutex_unlock(&ov965x->lock); 571 return; 572 } 573 clkrc = DEF_CLKRC + ov965x->fiv->clkrc_div; 574 /* Calculate internal clock frequency */ 575 fint = ov965x->mclk_frequency * ((clkrc >> 7) + 1) / 576 ((2 * ((clkrc & 0x3f) + 1))); 577 /* and the row interval (in us). */ 578 trow = (2 * 1520 * 1000000UL) / fint; 579 max = ov965x->frame_size->max_exp_lines * trow; 580 ov965x->exp_row_interval = trow; 581 mutex_unlock(&ov965x->lock); 582 583 v4l2_dbg(1, debug, &ov965x->sd, "clkrc: %#x, fi: %lu, tr: %lu, %d\n", 584 clkrc, fint, trow, max); 585 586 /* Update exposure time range to match current frame format. */ 587 min = (trow + 100) / 100; 588 max = (max - 100) / 100; 589 def = min + (max - min) / 2; 590 591 if (v4l2_ctrl_modify_range(ctrl, min, max, 1, def)) 592 v4l2_err(&ov965x->sd, "Exposure ctrl range update failed\n"); 593 } 594 595 static int ov965x_set_banding_filter(struct ov965x *ov965x, int value) 596 { 597 unsigned long mbd, light_freq; 598 int ret; 599 u8 reg; 600 601 ret = ov965x_read(ov965x, REG_COM8, ®); 602 if (!ret) { 603 if (value == V4L2_CID_POWER_LINE_FREQUENCY_DISABLED) 604 reg &= ~COM8_BFILT; 605 else 606 reg |= COM8_BFILT; 607 ret = ov965x_write(ov965x, REG_COM8, reg); 608 } 609 if (value == V4L2_CID_POWER_LINE_FREQUENCY_DISABLED) 610 return 0; 611 if (WARN_ON(!ov965x->fiv)) 612 return -EINVAL; 613 /* Set minimal exposure time for 50/60 HZ lighting */ 614 if (value == V4L2_CID_POWER_LINE_FREQUENCY_50HZ) 615 light_freq = 50; 616 else 617 light_freq = 60; 618 mbd = (1000UL * ov965x->fiv->interval.denominator * 619 ov965x->frame_size->max_exp_lines) / 620 ov965x->fiv->interval.numerator; 621 mbd = ((mbd / (light_freq * 2)) + 500) / 1000UL; 622 623 return ov965x_write(ov965x, REG_MBD, mbd); 624 } 625 626 static int ov965x_set_white_balance(struct ov965x *ov965x, int awb) 627 { 628 int ret; 629 u8 reg; 630 631 ret = ov965x_read(ov965x, REG_COM8, ®); 632 if (!ret) { 633 reg = awb ? reg | REG_COM8 : reg & ~REG_COM8; 634 ret = ov965x_write(ov965x, REG_COM8, reg); 635 } 636 if (!ret && !awb) { 637 ret = ov965x_write(ov965x, REG_BLUE, 638 ov965x->ctrls.blue_balance->val); 639 if (ret < 0) 640 return ret; 641 ret = ov965x_write(ov965x, REG_RED, 642 ov965x->ctrls.red_balance->val); 643 } 644 return ret; 645 } 646 647 #define NUM_BR_LEVELS 7 648 #define NUM_BR_REGS 3 649 650 static int ov965x_set_brightness(struct ov965x *ov965x, int val) 651 { 652 static const u8 regs[NUM_BR_LEVELS + 1][NUM_BR_REGS] = { 653 { REG_AEW, REG_AEB, REG_VPT }, 654 { 0x1c, 0x12, 0x50 }, /* -3 */ 655 { 0x3d, 0x30, 0x71 }, /* -2 */ 656 { 0x50, 0x44, 0x92 }, /* -1 */ 657 { 0x70, 0x64, 0xc3 }, /* 0 */ 658 { 0x90, 0x84, 0xd4 }, /* +1 */ 659 { 0xc4, 0xbf, 0xf9 }, /* +2 */ 660 { 0xd8, 0xd0, 0xfa }, /* +3 */ 661 }; 662 int i, ret = 0; 663 664 val += (NUM_BR_LEVELS / 2 + 1); 665 if (val > NUM_BR_LEVELS) 666 return -EINVAL; 667 668 for (i = 0; i < NUM_BR_REGS && !ret; i++) 669 ret = ov965x_write(ov965x, regs[0][i], 670 regs[val][i]); 671 return ret; 672 } 673 674 static int ov965x_set_gain(struct ov965x *ov965x, int auto_gain) 675 { 676 struct ov965x_ctrls *ctrls = &ov965x->ctrls; 677 int ret = 0; 678 u8 reg; 679 /* 680 * For manual mode we need to disable AGC first, so 681 * gain value in REG_VREF, REG_GAIN is not overwritten. 682 */ 683 if (ctrls->auto_gain->is_new) { 684 ret = ov965x_read(ov965x, REG_COM8, ®); 685 if (ret < 0) 686 return ret; 687 if (ctrls->auto_gain->val) 688 reg |= COM8_AGC; 689 else 690 reg &= ~COM8_AGC; 691 ret = ov965x_write(ov965x, REG_COM8, reg); 692 if (ret < 0) 693 return ret; 694 } 695 696 if (ctrls->gain->is_new && !auto_gain) { 697 unsigned int gain = ctrls->gain->val; 698 unsigned int rgain; 699 int m; 700 /* 701 * Convert gain control value to the sensor's gain 702 * registers (VREF[7:6], GAIN[7:0]) format. 703 */ 704 for (m = 6; m >= 0; m--) 705 if (gain >= (1 << m) * 16) 706 break; 707 rgain = (gain - ((1 << m) * 16)) / (1 << m); 708 rgain |= (((1 << m) - 1) << 4); 709 710 ret = ov965x_write(ov965x, REG_GAIN, rgain & 0xff); 711 if (ret < 0) 712 return ret; 713 ret = ov965x_read(ov965x, REG_VREF, ®); 714 if (ret < 0) 715 return ret; 716 reg &= ~VREF_GAIN_MASK; 717 reg |= (((rgain >> 8) & 0x3) << 6); 718 ret = ov965x_write(ov965x, REG_VREF, reg); 719 if (ret < 0) 720 return ret; 721 /* Return updated control's value to userspace */ 722 ctrls->gain->val = (1 << m) * (16 + (rgain & 0xf)); 723 } 724 725 return ret; 726 } 727 728 static int ov965x_set_sharpness(struct ov965x *ov965x, unsigned int value) 729 { 730 u8 com14, edge; 731 int ret; 732 733 ret = ov965x_read(ov965x, REG_COM14, &com14); 734 if (ret < 0) 735 return ret; 736 ret = ov965x_read(ov965x, REG_EDGE, &edge); 737 if (ret < 0) 738 return ret; 739 com14 = value ? com14 | COM14_EDGE_EN : com14 & ~COM14_EDGE_EN; 740 value--; 741 if (value > 0x0f) { 742 com14 |= COM14_EEF_X2; 743 value >>= 1; 744 } else { 745 com14 &= ~COM14_EEF_X2; 746 } 747 ret = ov965x_write(ov965x, REG_COM14, com14); 748 if (ret < 0) 749 return ret; 750 751 edge &= ~EDGE_FACTOR_MASK; 752 edge |= ((u8)value & 0x0f); 753 754 return ov965x_write(ov965x, REG_EDGE, edge); 755 } 756 757 static int ov965x_set_exposure(struct ov965x *ov965x, int exp) 758 { 759 struct ov965x_ctrls *ctrls = &ov965x->ctrls; 760 bool auto_exposure = (exp == V4L2_EXPOSURE_AUTO); 761 int ret; 762 u8 reg; 763 764 if (ctrls->auto_exp->is_new) { 765 ret = ov965x_read(ov965x, REG_COM8, ®); 766 if (ret < 0) 767 return ret; 768 if (auto_exposure) 769 reg |= (COM8_AEC | COM8_AGC); 770 else 771 reg &= ~(COM8_AEC | COM8_AGC); 772 ret = ov965x_write(ov965x, REG_COM8, reg); 773 if (ret < 0) 774 return ret; 775 } 776 777 if (!auto_exposure && ctrls->exposure->is_new) { 778 unsigned int exposure = (ctrls->exposure->val * 100) 779 / ov965x->exp_row_interval; 780 /* 781 * Manual exposure value 782 * [b15:b0] - AECHM (b15:b10), AECH (b9:b2), COM1 (b1:b0) 783 */ 784 ret = ov965x_write(ov965x, REG_COM1, exposure & 0x3); 785 if (!ret) 786 ret = ov965x_write(ov965x, REG_AECH, 787 (exposure >> 2) & 0xff); 788 if (!ret) 789 ret = ov965x_write(ov965x, REG_AECHM, 790 (exposure >> 10) & 0x3f); 791 /* Update the value to minimize rounding errors */ 792 ctrls->exposure->val = ((exposure * ov965x->exp_row_interval) 793 + 50) / 100; 794 if (ret < 0) 795 return ret; 796 } 797 798 v4l2_ctrl_activate(ov965x->ctrls.brightness, !exp); 799 return 0; 800 } 801 802 static int ov965x_set_flip(struct ov965x *ov965x) 803 { 804 u8 mvfp = 0; 805 806 if (ov965x->ctrls.hflip->val) 807 mvfp |= MVFP_MIRROR; 808 809 if (ov965x->ctrls.vflip->val) 810 mvfp |= MVFP_FLIP; 811 812 return ov965x_write(ov965x, REG_MVFP, mvfp); 813 } 814 815 #define NUM_SAT_LEVELS 5 816 #define NUM_SAT_REGS 6 817 818 static int ov965x_set_saturation(struct ov965x *ov965x, int val) 819 { 820 static const u8 regs[NUM_SAT_LEVELS][NUM_SAT_REGS] = { 821 /* MTX(1)...MTX(6) */ 822 { 0x1d, 0x1f, 0x02, 0x09, 0x13, 0x1c }, /* -2 */ 823 { 0x2e, 0x31, 0x02, 0x0e, 0x1e, 0x2d }, /* -1 */ 824 { 0x3a, 0x3d, 0x03, 0x12, 0x26, 0x38 }, /* 0 */ 825 { 0x46, 0x49, 0x04, 0x16, 0x2e, 0x43 }, /* +1 */ 826 { 0x57, 0x5c, 0x05, 0x1b, 0x39, 0x54 }, /* +2 */ 827 }; 828 u8 addr = REG_MTX(1); 829 int i, ret = 0; 830 831 val += (NUM_SAT_LEVELS / 2); 832 if (val >= NUM_SAT_LEVELS) 833 return -EINVAL; 834 835 for (i = 0; i < NUM_SAT_REGS && !ret; i++) 836 ret = ov965x_write(ov965x, addr + i, regs[val][i]); 837 838 return ret; 839 } 840 841 static int ov965x_set_test_pattern(struct ov965x *ov965x, int value) 842 { 843 int ret; 844 u8 reg; 845 846 ret = ov965x_read(ov965x, REG_COM23, ®); 847 if (ret < 0) 848 return ret; 849 reg = value ? reg | COM23_TEST_MODE : reg & ~COM23_TEST_MODE; 850 return ov965x_write(ov965x, REG_COM23, reg); 851 } 852 853 static int __g_volatile_ctrl(struct ov965x *ov965x, struct v4l2_ctrl *ctrl) 854 { 855 unsigned int exposure, gain, m; 856 u8 reg0, reg1, reg2; 857 int ret; 858 859 if (!ov965x->power) 860 return 0; 861 862 switch (ctrl->id) { 863 case V4L2_CID_AUTOGAIN: 864 if (!ctrl->val) 865 return 0; 866 ret = ov965x_read(ov965x, REG_GAIN, ®0); 867 if (ret < 0) 868 return ret; 869 ret = ov965x_read(ov965x, REG_VREF, ®1); 870 if (ret < 0) 871 return ret; 872 gain = ((reg1 >> 6) << 8) | reg0; 873 m = 0x01 << fls(gain >> 4); 874 ov965x->ctrls.gain->val = m * (16 + (gain & 0xf)); 875 break; 876 877 case V4L2_CID_EXPOSURE_AUTO: 878 if (ctrl->val == V4L2_EXPOSURE_MANUAL) 879 return 0; 880 ret = ov965x_read(ov965x, REG_COM1, ®0); 881 if (ret < 0) 882 return ret; 883 ret = ov965x_read(ov965x, REG_AECH, ®1); 884 if (ret < 0) 885 return ret; 886 ret = ov965x_read(ov965x, REG_AECHM, ®2); 887 if (ret < 0) 888 return ret; 889 exposure = ((reg2 & 0x3f) << 10) | (reg1 << 2) | 890 (reg0 & 0x3); 891 ov965x->ctrls.exposure->val = ((exposure * 892 ov965x->exp_row_interval) + 50) / 100; 893 break; 894 } 895 896 return 0; 897 } 898 899 static int ov965x_g_volatile_ctrl(struct v4l2_ctrl *ctrl) 900 { 901 struct v4l2_subdev *sd = ctrl_to_sd(ctrl); 902 struct ov965x *ov965x = to_ov965x(sd); 903 int ret; 904 905 v4l2_dbg(1, debug, sd, "g_ctrl: %s\n", ctrl->name); 906 907 mutex_lock(&ov965x->lock); 908 ret = __g_volatile_ctrl(ov965x, ctrl); 909 mutex_unlock(&ov965x->lock); 910 return ret; 911 } 912 913 static int ov965x_s_ctrl(struct v4l2_ctrl *ctrl) 914 { 915 struct v4l2_subdev *sd = ctrl_to_sd(ctrl); 916 struct ov965x *ov965x = to_ov965x(sd); 917 int ret = -EINVAL; 918 919 v4l2_dbg(1, debug, sd, "s_ctrl: %s, value: %d. power: %d\n", 920 ctrl->name, ctrl->val, ov965x->power); 921 922 mutex_lock(&ov965x->lock); 923 /* 924 * If the device is not powered up now postpone applying control's 925 * value to the hardware, until it is ready to accept commands. 926 */ 927 if (ov965x->power == 0) { 928 mutex_unlock(&ov965x->lock); 929 return 0; 930 } 931 932 switch (ctrl->id) { 933 case V4L2_CID_AUTO_WHITE_BALANCE: 934 ret = ov965x_set_white_balance(ov965x, ctrl->val); 935 break; 936 937 case V4L2_CID_BRIGHTNESS: 938 ret = ov965x_set_brightness(ov965x, ctrl->val); 939 break; 940 941 case V4L2_CID_EXPOSURE_AUTO: 942 ret = ov965x_set_exposure(ov965x, ctrl->val); 943 break; 944 945 case V4L2_CID_AUTOGAIN: 946 ret = ov965x_set_gain(ov965x, ctrl->val); 947 break; 948 949 case V4L2_CID_HFLIP: 950 ret = ov965x_set_flip(ov965x); 951 break; 952 953 case V4L2_CID_POWER_LINE_FREQUENCY: 954 ret = ov965x_set_banding_filter(ov965x, ctrl->val); 955 break; 956 957 case V4L2_CID_SATURATION: 958 ret = ov965x_set_saturation(ov965x, ctrl->val); 959 break; 960 961 case V4L2_CID_SHARPNESS: 962 ret = ov965x_set_sharpness(ov965x, ctrl->val); 963 break; 964 965 case V4L2_CID_TEST_PATTERN: 966 ret = ov965x_set_test_pattern(ov965x, ctrl->val); 967 break; 968 } 969 970 mutex_unlock(&ov965x->lock); 971 return ret; 972 } 973 974 static const struct v4l2_ctrl_ops ov965x_ctrl_ops = { 975 .g_volatile_ctrl = ov965x_g_volatile_ctrl, 976 .s_ctrl = ov965x_s_ctrl, 977 }; 978 979 static const char * const test_pattern_menu[] = { 980 "Disabled", 981 "Color bars", 982 }; 983 984 static int ov965x_initialize_controls(struct ov965x *ov965x) 985 { 986 const struct v4l2_ctrl_ops *ops = &ov965x_ctrl_ops; 987 struct ov965x_ctrls *ctrls = &ov965x->ctrls; 988 struct v4l2_ctrl_handler *hdl = &ctrls->handler; 989 int ret; 990 991 ret = v4l2_ctrl_handler_init(hdl, 16); 992 if (ret < 0) 993 return ret; 994 995 /* Auto/manual white balance */ 996 ctrls->auto_wb = v4l2_ctrl_new_std(hdl, ops, 997 V4L2_CID_AUTO_WHITE_BALANCE, 998 0, 1, 1, 1); 999 ctrls->blue_balance = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BLUE_BALANCE, 1000 0, 0xff, 1, 0x80); 1001 ctrls->red_balance = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_RED_BALANCE, 1002 0, 0xff, 1, 0x80); 1003 /* Auto/manual exposure */ 1004 ctrls->auto_exp = 1005 v4l2_ctrl_new_std_menu(hdl, ops, 1006 V4L2_CID_EXPOSURE_AUTO, 1007 V4L2_EXPOSURE_MANUAL, 0, 1008 V4L2_EXPOSURE_AUTO); 1009 /* Exposure time, in 100 us units. min/max is updated dynamically. */ 1010 ctrls->exposure = v4l2_ctrl_new_std(hdl, ops, 1011 V4L2_CID_EXPOSURE_ABSOLUTE, 1012 2, 1500, 1, 500); 1013 /* Auto/manual gain */ 1014 ctrls->auto_gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_AUTOGAIN, 1015 0, 1, 1, 1); 1016 ctrls->gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAIN, 1017 16, 64 * (16 + 15), 1, 64 * 16); 1018 1019 ctrls->saturation = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_SATURATION, 1020 -2, 2, 1, 0); 1021 ctrls->brightness = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS, 1022 -3, 3, 1, 0); 1023 ctrls->sharpness = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_SHARPNESS, 1024 0, 32, 1, 6); 1025 1026 ctrls->hflip = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_HFLIP, 0, 1, 1, 0); 1027 ctrls->vflip = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_VFLIP, 0, 1, 1, 0); 1028 1029 ctrls->light_freq = 1030 v4l2_ctrl_new_std_menu(hdl, ops, 1031 V4L2_CID_POWER_LINE_FREQUENCY, 1032 V4L2_CID_POWER_LINE_FREQUENCY_60HZ, ~0x7, 1033 V4L2_CID_POWER_LINE_FREQUENCY_50HZ); 1034 1035 v4l2_ctrl_new_std_menu_items(hdl, ops, V4L2_CID_TEST_PATTERN, 1036 ARRAY_SIZE(test_pattern_menu) - 1, 0, 0, 1037 test_pattern_menu); 1038 if (hdl->error) { 1039 ret = hdl->error; 1040 v4l2_ctrl_handler_free(hdl); 1041 return ret; 1042 } 1043 1044 ctrls->gain->flags |= V4L2_CTRL_FLAG_VOLATILE; 1045 ctrls->exposure->flags |= V4L2_CTRL_FLAG_VOLATILE; 1046 1047 v4l2_ctrl_auto_cluster(3, &ctrls->auto_wb, 0, false); 1048 v4l2_ctrl_auto_cluster(2, &ctrls->auto_gain, 0, true); 1049 v4l2_ctrl_auto_cluster(2, &ctrls->auto_exp, 1, true); 1050 v4l2_ctrl_cluster(2, &ctrls->hflip); 1051 1052 ov965x->sd.ctrl_handler = hdl; 1053 return 0; 1054 } 1055 1056 /* 1057 * V4L2 subdev video and pad level operations 1058 */ 1059 static void ov965x_get_default_format(struct v4l2_mbus_framefmt *mf) 1060 { 1061 mf->width = ov965x_framesizes[0].width; 1062 mf->height = ov965x_framesizes[0].height; 1063 mf->colorspace = ov965x_formats[0].colorspace; 1064 mf->code = ov965x_formats[0].code; 1065 mf->field = V4L2_FIELD_NONE; 1066 } 1067 1068 static int ov965x_enum_mbus_code(struct v4l2_subdev *sd, 1069 struct v4l2_subdev_pad_config *cfg, 1070 struct v4l2_subdev_mbus_code_enum *code) 1071 { 1072 if (code->index >= ARRAY_SIZE(ov965x_formats)) 1073 return -EINVAL; 1074 1075 code->code = ov965x_formats[code->index].code; 1076 return 0; 1077 } 1078 1079 static int ov965x_enum_frame_sizes(struct v4l2_subdev *sd, 1080 struct v4l2_subdev_pad_config *cfg, 1081 struct v4l2_subdev_frame_size_enum *fse) 1082 { 1083 int i = ARRAY_SIZE(ov965x_formats); 1084 1085 if (fse->index >= ARRAY_SIZE(ov965x_framesizes)) 1086 return -EINVAL; 1087 1088 while (--i) 1089 if (fse->code == ov965x_formats[i].code) 1090 break; 1091 1092 fse->code = ov965x_formats[i].code; 1093 1094 fse->min_width = ov965x_framesizes[fse->index].width; 1095 fse->max_width = fse->min_width; 1096 fse->max_height = ov965x_framesizes[fse->index].height; 1097 fse->min_height = fse->max_height; 1098 1099 return 0; 1100 } 1101 1102 static int ov965x_g_frame_interval(struct v4l2_subdev *sd, 1103 struct v4l2_subdev_frame_interval *fi) 1104 { 1105 struct ov965x *ov965x = to_ov965x(sd); 1106 1107 mutex_lock(&ov965x->lock); 1108 fi->interval = ov965x->fiv->interval; 1109 mutex_unlock(&ov965x->lock); 1110 1111 return 0; 1112 } 1113 1114 static int __ov965x_set_frame_interval(struct ov965x *ov965x, 1115 struct v4l2_subdev_frame_interval *fi) 1116 { 1117 struct v4l2_mbus_framefmt *mbus_fmt = &ov965x->format; 1118 const struct ov965x_interval *fiv = &ov965x_intervals[0]; 1119 u64 req_int, err, min_err = ~0ULL; 1120 unsigned int i; 1121 1122 if (fi->interval.denominator == 0) 1123 return -EINVAL; 1124 1125 req_int = (u64)fi->interval.numerator * 10000; 1126 do_div(req_int, fi->interval.denominator); 1127 1128 for (i = 0; i < ARRAY_SIZE(ov965x_intervals); i++) { 1129 const struct ov965x_interval *iv = &ov965x_intervals[i]; 1130 1131 if (mbus_fmt->width != iv->size.width || 1132 mbus_fmt->height != iv->size.height) 1133 continue; 1134 err = abs((u64)(iv->interval.numerator * 10000) / 1135 iv->interval.denominator - req_int); 1136 if (err < min_err) { 1137 fiv = iv; 1138 min_err = err; 1139 } 1140 } 1141 ov965x->fiv = fiv; 1142 1143 v4l2_dbg(1, debug, &ov965x->sd, "Changed frame interval to %u us\n", 1144 fiv->interval.numerator * 1000000 / fiv->interval.denominator); 1145 1146 return 0; 1147 } 1148 1149 static int ov965x_s_frame_interval(struct v4l2_subdev *sd, 1150 struct v4l2_subdev_frame_interval *fi) 1151 { 1152 struct ov965x *ov965x = to_ov965x(sd); 1153 int ret; 1154 1155 v4l2_dbg(1, debug, sd, "Setting %d/%d frame interval\n", 1156 fi->interval.numerator, fi->interval.denominator); 1157 1158 mutex_lock(&ov965x->lock); 1159 ret = __ov965x_set_frame_interval(ov965x, fi); 1160 ov965x->apply_frame_fmt = 1; 1161 mutex_unlock(&ov965x->lock); 1162 return ret; 1163 } 1164 1165 static int ov965x_get_fmt(struct v4l2_subdev *sd, 1166 struct v4l2_subdev_pad_config *cfg, 1167 struct v4l2_subdev_format *fmt) 1168 { 1169 struct ov965x *ov965x = to_ov965x(sd); 1170 struct v4l2_mbus_framefmt *mf; 1171 1172 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { 1173 mf = v4l2_subdev_get_try_format(sd, cfg, 0); 1174 fmt->format = *mf; 1175 return 0; 1176 } 1177 1178 mutex_lock(&ov965x->lock); 1179 fmt->format = ov965x->format; 1180 mutex_unlock(&ov965x->lock); 1181 1182 return 0; 1183 } 1184 1185 static void __ov965x_try_frame_size(struct v4l2_mbus_framefmt *mf, 1186 const struct ov965x_framesize **size) 1187 { 1188 const struct ov965x_framesize *fsize = &ov965x_framesizes[0], 1189 *match = NULL; 1190 int i = ARRAY_SIZE(ov965x_framesizes); 1191 unsigned int min_err = UINT_MAX; 1192 1193 while (i--) { 1194 int err = abs(fsize->width - mf->width) 1195 + abs(fsize->height - mf->height); 1196 if (err < min_err) { 1197 min_err = err; 1198 match = fsize; 1199 } 1200 fsize++; 1201 } 1202 if (!match) 1203 match = &ov965x_framesizes[0]; 1204 mf->width = match->width; 1205 mf->height = match->height; 1206 if (size) 1207 *size = match; 1208 } 1209 1210 static int ov965x_set_fmt(struct v4l2_subdev *sd, 1211 struct v4l2_subdev_pad_config *cfg, 1212 struct v4l2_subdev_format *fmt) 1213 { 1214 unsigned int index = ARRAY_SIZE(ov965x_formats); 1215 struct v4l2_mbus_framefmt *mf = &fmt->format; 1216 struct ov965x *ov965x = to_ov965x(sd); 1217 const struct ov965x_framesize *size = NULL; 1218 int ret = 0; 1219 1220 __ov965x_try_frame_size(mf, &size); 1221 1222 while (--index) 1223 if (ov965x_formats[index].code == mf->code) 1224 break; 1225 1226 mf->colorspace = V4L2_COLORSPACE_JPEG; 1227 mf->code = ov965x_formats[index].code; 1228 mf->field = V4L2_FIELD_NONE; 1229 1230 mutex_lock(&ov965x->lock); 1231 1232 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { 1233 if (cfg) { 1234 mf = v4l2_subdev_get_try_format(sd, cfg, fmt->pad); 1235 *mf = fmt->format; 1236 } 1237 } else { 1238 if (ov965x->streaming) { 1239 ret = -EBUSY; 1240 } else { 1241 ov965x->frame_size = size; 1242 ov965x->format = fmt->format; 1243 ov965x->tslb_reg = ov965x_formats[index].tslb_reg; 1244 ov965x->apply_frame_fmt = 1; 1245 } 1246 } 1247 1248 if (!ret && fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) { 1249 struct v4l2_subdev_frame_interval fiv = { 1250 .interval = { 0, 1 } 1251 }; 1252 /* Reset to minimum possible frame interval */ 1253 __ov965x_set_frame_interval(ov965x, &fiv); 1254 } 1255 mutex_unlock(&ov965x->lock); 1256 1257 if (!ret) 1258 ov965x_update_exposure_ctrl(ov965x); 1259 1260 return ret; 1261 } 1262 1263 static int ov965x_set_frame_size(struct ov965x *ov965x) 1264 { 1265 int i, ret = 0; 1266 1267 for (i = 0; ret == 0 && i < NUM_FMT_REGS; i++) 1268 ret = ov965x_write(ov965x, frame_size_reg_addr[i], 1269 ov965x->frame_size->regs[i]); 1270 return ret; 1271 } 1272 1273 static int __ov965x_set_params(struct ov965x *ov965x) 1274 { 1275 struct ov965x_ctrls *ctrls = &ov965x->ctrls; 1276 int ret = 0; 1277 u8 reg; 1278 1279 if (ov965x->apply_frame_fmt) { 1280 reg = DEF_CLKRC + ov965x->fiv->clkrc_div; 1281 ret = ov965x_write(ov965x, REG_CLKRC, reg); 1282 if (ret < 0) 1283 return ret; 1284 ret = ov965x_set_frame_size(ov965x); 1285 if (ret < 0) 1286 return ret; 1287 ret = ov965x_read(ov965x, REG_TSLB, ®); 1288 if (ret < 0) 1289 return ret; 1290 reg &= ~TSLB_YUYV_MASK; 1291 reg |= ov965x->tslb_reg; 1292 ret = ov965x_write(ov965x, REG_TSLB, reg); 1293 if (ret < 0) 1294 return ret; 1295 } 1296 ret = ov965x_set_default_gamma_curve(ov965x); 1297 if (ret < 0) 1298 return ret; 1299 ret = ov965x_set_color_matrix(ov965x); 1300 if (ret < 0) 1301 return ret; 1302 /* 1303 * Select manual banding filter, the filter will 1304 * be enabled further if required. 1305 */ 1306 ret = ov965x_read(ov965x, REG_COM11, ®); 1307 if (!ret) 1308 reg |= COM11_BANDING; 1309 ret = ov965x_write(ov965x, REG_COM11, reg); 1310 if (ret < 0) 1311 return ret; 1312 /* 1313 * Banding filter (REG_MBD value) needs to match selected 1314 * resolution and frame rate, so it's always updated here. 1315 */ 1316 return ov965x_set_banding_filter(ov965x, ctrls->light_freq->val); 1317 } 1318 1319 static int ov965x_s_stream(struct v4l2_subdev *sd, int on) 1320 { 1321 struct ov965x *ov965x = to_ov965x(sd); 1322 struct ov965x_ctrls *ctrls = &ov965x->ctrls; 1323 int ret = 0; 1324 1325 v4l2_dbg(1, debug, sd, "%s: on: %d\n", __func__, on); 1326 1327 mutex_lock(&ov965x->lock); 1328 if (ov965x->streaming == !on) { 1329 if (on) 1330 ret = __ov965x_set_params(ov965x); 1331 1332 if (!ret && ctrls->update) { 1333 /* 1334 * ov965x_s_ctrl callback takes the mutex 1335 * so it needs to be released here. 1336 */ 1337 mutex_unlock(&ov965x->lock); 1338 ret = v4l2_ctrl_handler_setup(&ctrls->handler); 1339 1340 mutex_lock(&ov965x->lock); 1341 if (!ret) 1342 ctrls->update = 0; 1343 } 1344 if (!ret) 1345 ret = ov965x_write(ov965x, REG_COM2, 1346 on ? 0x01 : 0x11); 1347 } 1348 if (!ret) 1349 ov965x->streaming += on ? 1 : -1; 1350 1351 WARN_ON(ov965x->streaming < 0); 1352 mutex_unlock(&ov965x->lock); 1353 1354 return ret; 1355 } 1356 1357 /* 1358 * V4L2 subdev internal operations 1359 */ 1360 static int ov965x_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) 1361 { 1362 struct v4l2_mbus_framefmt *mf = 1363 v4l2_subdev_get_try_format(sd, fh->pad, 0); 1364 1365 ov965x_get_default_format(mf); 1366 return 0; 1367 } 1368 1369 static const struct v4l2_subdev_pad_ops ov965x_pad_ops = { 1370 .enum_mbus_code = ov965x_enum_mbus_code, 1371 .enum_frame_size = ov965x_enum_frame_sizes, 1372 .get_fmt = ov965x_get_fmt, 1373 .set_fmt = ov965x_set_fmt, 1374 }; 1375 1376 static const struct v4l2_subdev_video_ops ov965x_video_ops = { 1377 .s_stream = ov965x_s_stream, 1378 .g_frame_interval = ov965x_g_frame_interval, 1379 .s_frame_interval = ov965x_s_frame_interval, 1380 1381 }; 1382 1383 static const struct v4l2_subdev_internal_ops ov965x_sd_internal_ops = { 1384 .open = ov965x_open, 1385 }; 1386 1387 static const struct v4l2_subdev_core_ops ov965x_core_ops = { 1388 .s_power = ov965x_s_power, 1389 .log_status = v4l2_ctrl_subdev_log_status, 1390 .subscribe_event = v4l2_ctrl_subdev_subscribe_event, 1391 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 1392 }; 1393 1394 static const struct v4l2_subdev_ops ov965x_subdev_ops = { 1395 .core = &ov965x_core_ops, 1396 .pad = &ov965x_pad_ops, 1397 .video = &ov965x_video_ops, 1398 }; 1399 1400 /* 1401 * Reset and power down GPIOs configuration 1402 */ 1403 static int ov965x_configure_gpios_pdata(struct ov965x *ov965x, 1404 const struct ov9650_platform_data *pdata) 1405 { 1406 int ret, i; 1407 int gpios[NUM_GPIOS]; 1408 struct device *dev = regmap_get_device(ov965x->regmap); 1409 1410 gpios[GPIO_PWDN] = pdata->gpio_pwdn; 1411 gpios[GPIO_RST] = pdata->gpio_reset; 1412 1413 for (i = 0; i < ARRAY_SIZE(ov965x->gpios); i++) { 1414 int gpio = gpios[i]; 1415 1416 if (!gpio_is_valid(gpio)) 1417 continue; 1418 ret = devm_gpio_request_one(dev, gpio, 1419 GPIOF_OUT_INIT_HIGH, "OV965X"); 1420 if (ret < 0) 1421 return ret; 1422 v4l2_dbg(1, debug, &ov965x->sd, "set gpio %d to 1\n", gpio); 1423 1424 gpio_set_value_cansleep(gpio, 1); 1425 gpio_export(gpio, 0); 1426 ov965x->gpios[i] = gpio_to_desc(gpio); 1427 } 1428 1429 return 0; 1430 } 1431 1432 static int ov965x_configure_gpios(struct ov965x *ov965x) 1433 { 1434 struct device *dev = regmap_get_device(ov965x->regmap); 1435 1436 ov965x->gpios[GPIO_PWDN] = devm_gpiod_get_optional(dev, "powerdown", 1437 GPIOD_OUT_HIGH); 1438 if (IS_ERR(ov965x->gpios[GPIO_PWDN])) { 1439 dev_info(dev, "can't get %s GPIO\n", "powerdown"); 1440 return PTR_ERR(ov965x->gpios[GPIO_PWDN]); 1441 } 1442 1443 ov965x->gpios[GPIO_RST] = devm_gpiod_get_optional(dev, "reset", 1444 GPIOD_OUT_HIGH); 1445 if (IS_ERR(ov965x->gpios[GPIO_RST])) { 1446 dev_info(dev, "can't get %s GPIO\n", "reset"); 1447 return PTR_ERR(ov965x->gpios[GPIO_RST]); 1448 } 1449 1450 return 0; 1451 } 1452 1453 static int ov965x_detect_sensor(struct v4l2_subdev *sd) 1454 { 1455 struct ov965x *ov965x = to_ov965x(sd); 1456 u8 pid, ver; 1457 int ret; 1458 1459 mutex_lock(&ov965x->lock); 1460 ret = __ov965x_set_power(ov965x, 1); 1461 if (ret) 1462 goto out; 1463 1464 msleep(25); 1465 1466 /* Check sensor revision */ 1467 ret = ov965x_read(ov965x, REG_PID, &pid); 1468 if (!ret) 1469 ret = ov965x_read(ov965x, REG_VER, &ver); 1470 1471 __ov965x_set_power(ov965x, 0); 1472 1473 if (!ret) { 1474 ov965x->id = OV965X_ID(pid, ver); 1475 if (ov965x->id == OV9650_ID || ov965x->id == OV9652_ID) { 1476 v4l2_info(sd, "Found OV%04X sensor\n", ov965x->id); 1477 } else { 1478 v4l2_err(sd, "Sensor detection failed (%04X, %d)\n", 1479 ov965x->id, ret); 1480 ret = -ENODEV; 1481 } 1482 } 1483 out: 1484 mutex_unlock(&ov965x->lock); 1485 1486 return ret; 1487 } 1488 1489 static int ov965x_probe(struct i2c_client *client, 1490 const struct i2c_device_id *id) 1491 { 1492 const struct ov9650_platform_data *pdata = client->dev.platform_data; 1493 struct v4l2_subdev *sd; 1494 struct ov965x *ov965x; 1495 int ret; 1496 static const struct regmap_config ov965x_regmap_config = { 1497 .reg_bits = 8, 1498 .val_bits = 8, 1499 .max_register = 0xab, 1500 }; 1501 1502 ov965x = devm_kzalloc(&client->dev, sizeof(*ov965x), GFP_KERNEL); 1503 if (!ov965x) 1504 return -ENOMEM; 1505 1506 ov965x->regmap = devm_regmap_init_sccb(client, &ov965x_regmap_config); 1507 if (IS_ERR(ov965x->regmap)) { 1508 dev_err(&client->dev, "Failed to allocate register map\n"); 1509 return PTR_ERR(ov965x->regmap); 1510 } 1511 1512 if (pdata) { 1513 if (pdata->mclk_frequency == 0) { 1514 dev_err(&client->dev, "MCLK frequency not specified\n"); 1515 return -EINVAL; 1516 } 1517 ov965x->mclk_frequency = pdata->mclk_frequency; 1518 1519 ret = ov965x_configure_gpios_pdata(ov965x, pdata); 1520 if (ret < 0) 1521 return ret; 1522 } else if (dev_fwnode(&client->dev)) { 1523 ov965x->clk = devm_clk_get(&client->dev, NULL); 1524 if (IS_ERR(ov965x->clk)) 1525 return PTR_ERR(ov965x->clk); 1526 ov965x->mclk_frequency = clk_get_rate(ov965x->clk); 1527 1528 ret = ov965x_configure_gpios(ov965x); 1529 if (ret < 0) 1530 return ret; 1531 } else { 1532 dev_err(&client->dev, 1533 "Neither platform data nor device property specified\n"); 1534 1535 return -EINVAL; 1536 } 1537 1538 mutex_init(&ov965x->lock); 1539 1540 sd = &ov965x->sd; 1541 v4l2_i2c_subdev_init(sd, client, &ov965x_subdev_ops); 1542 strscpy(sd->name, DRIVER_NAME, sizeof(sd->name)); 1543 1544 sd->internal_ops = &ov965x_sd_internal_ops; 1545 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | 1546 V4L2_SUBDEV_FL_HAS_EVENTS; 1547 1548 ov965x->pad.flags = MEDIA_PAD_FL_SOURCE; 1549 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR; 1550 ret = media_entity_pads_init(&sd->entity, 1, &ov965x->pad); 1551 if (ret < 0) 1552 goto err_mutex; 1553 1554 ret = ov965x_initialize_controls(ov965x); 1555 if (ret < 0) 1556 goto err_me; 1557 1558 ov965x_get_default_format(&ov965x->format); 1559 ov965x->frame_size = &ov965x_framesizes[0]; 1560 ov965x->fiv = &ov965x_intervals[0]; 1561 1562 ret = ov965x_detect_sensor(sd); 1563 if (ret < 0) 1564 goto err_ctrls; 1565 1566 /* Update exposure time min/max to match frame format */ 1567 ov965x_update_exposure_ctrl(ov965x); 1568 1569 ret = v4l2_async_register_subdev(sd); 1570 if (ret < 0) 1571 goto err_ctrls; 1572 1573 return 0; 1574 err_ctrls: 1575 v4l2_ctrl_handler_free(sd->ctrl_handler); 1576 err_me: 1577 media_entity_cleanup(&sd->entity); 1578 err_mutex: 1579 mutex_destroy(&ov965x->lock); 1580 return ret; 1581 } 1582 1583 static int ov965x_remove(struct i2c_client *client) 1584 { 1585 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1586 struct ov965x *ov965x = to_ov965x(sd); 1587 1588 v4l2_async_unregister_subdev(sd); 1589 v4l2_ctrl_handler_free(sd->ctrl_handler); 1590 media_entity_cleanup(&sd->entity); 1591 mutex_destroy(&ov965x->lock); 1592 1593 return 0; 1594 } 1595 1596 static const struct i2c_device_id ov965x_id[] = { 1597 { "OV9650", 0 }, 1598 { "OV9652", 0 }, 1599 { /* sentinel */ } 1600 }; 1601 MODULE_DEVICE_TABLE(i2c, ov965x_id); 1602 1603 #if IS_ENABLED(CONFIG_OF) 1604 static const struct of_device_id ov965x_of_match[] = { 1605 { .compatible = "ovti,ov9650", }, 1606 { .compatible = "ovti,ov9652", }, 1607 { /* sentinel */ } 1608 }; 1609 MODULE_DEVICE_TABLE(of, ov965x_of_match); 1610 #endif 1611 1612 static struct i2c_driver ov965x_i2c_driver = { 1613 .driver = { 1614 .name = DRIVER_NAME, 1615 .of_match_table = of_match_ptr(ov965x_of_match), 1616 }, 1617 .probe = ov965x_probe, 1618 .remove = ov965x_remove, 1619 .id_table = ov965x_id, 1620 }; 1621 1622 module_i2c_driver(ov965x_i2c_driver); 1623 1624 MODULE_AUTHOR("Sylwester Nawrocki <sylvester.nawrocki@gmail.com>"); 1625 MODULE_DESCRIPTION("OV9650/OV9652 CMOS Image Sensor driver"); 1626 MODULE_LICENSE("GPL"); 1627