1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * OmniVision ov9282 Camera Sensor Driver 4 * 5 * Copyright (C) 2021 Intel Corporation 6 */ 7 #include <linux/unaligned.h> 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/i2c.h> 12 #include <linux/math.h> 13 #include <linux/module.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/regmap.h> 16 #include <linux/regulator/consumer.h> 17 18 #include <media/v4l2-cci.h> 19 #include <media/v4l2-ctrls.h> 20 #include <media/v4l2-event.h> 21 #include <media/v4l2-fwnode.h> 22 #include <media/v4l2-subdev.h> 23 24 /* Streaming Mode */ 25 #define OV9282_REG_MODE_SELECT CCI_REG8(0x0100) 26 #define OV9282_MODE_STANDBY 0x00 27 #define OV9282_MODE_STREAMING 0x01 28 29 #define OV9282_REG_PLL_CTRL_0D CCI_REG8(0x030d) 30 #define OV9282_PLL_CTRL_0D_RAW8 0x60 31 #define OV9282_PLL_CTRL_0D_RAW10 0x50 32 33 #define OV9282_REG_TIMING_HTS CCI_REG16(0x380c) 34 #define OV9282_TIMING_HTS_MAX 0x7fff 35 36 /* Lines per frame */ 37 #define OV9282_REG_LPFR CCI_REG16(0x380e) 38 39 /* Chip ID */ 40 #define OV9282_REG_ID CCI_REG16(0x300a) 41 #define OV9282_ID 0x9281 42 43 /* Output enable registers */ 44 #define OV9282_REG_OUTPUT_ENABLE4 CCI_REG8(0x3004) 45 #define OV9282_OUTPUT_ENABLE4_GPIO2 BIT(1) 46 #define OV9282_OUTPUT_ENABLE4_D9 BIT(0) 47 48 #define OV9282_REG_OUTPUT_ENABLE5 CCI_REG8(0x3005) 49 #define OV9282_OUTPUT_ENABLE5_D8 BIT(7) 50 #define OV9282_OUTPUT_ENABLE5_D7 BIT(6) 51 #define OV9282_OUTPUT_ENABLE5_D6 BIT(5) 52 #define OV9282_OUTPUT_ENABLE5_D5 BIT(4) 53 #define OV9282_OUTPUT_ENABLE5_D4 BIT(3) 54 #define OV9282_OUTPUT_ENABLE5_D3 BIT(2) 55 #define OV9282_OUTPUT_ENABLE5_D2 BIT(1) 56 #define OV9282_OUTPUT_ENABLE5_D1 BIT(0) 57 58 #define OV9282_REG_OUTPUT_ENABLE6 CCI_REG8(0x3006) 59 #define OV9282_OUTPUT_ENABLE6_D0 BIT(7) 60 #define OV9282_OUTPUT_ENABLE6_PCLK BIT(6) 61 #define OV9282_OUTPUT_ENABLE6_HREF BIT(5) 62 #define OV9282_OUTPUT_ENABLE6_STROBE BIT(3) 63 #define OV9282_OUTPUT_ENABLE6_ILPWM BIT(2) 64 #define OV9282_OUTPUT_ENABLE6_VSYNC BIT(1) 65 66 /* Exposure control */ 67 #define OV9282_REG_EXPOSURE CCI_REG24(0x3500) 68 #define OV9282_EXPOSURE_MIN 1 69 #define OV9282_EXPOSURE_OFFSET 25 70 #define OV9282_EXPOSURE_STEP 1 71 #define OV9282_EXPOSURE_DEFAULT 0x0282 72 73 /* AEC/AGC manual */ 74 #define OV9282_REG_AEC_MANUAL CCI_REG8(0x3503) 75 #define OV9282_DIGFRAC_GAIN_DELAY BIT(6) 76 #define OV9282_GAIN_CHANGE_DELAY BIT(5) 77 #define OV9282_GAIN_DELAY BIT(4) 78 #define OV9282_GAIN_PREC16_EN BIT(3) 79 #define OV9282_GAIN_MANUAL_AS_SENSGAIN BIT(2) 80 #define OV9282_AEC_MANUAL_DEFAULT 0x00 81 82 /* Analog gain control */ 83 #define OV9282_REG_AGAIN CCI_REG8(0x3509) 84 #define OV9282_AGAIN_MIN 0x10 85 #define OV9282_AGAIN_MAX 0xff 86 #define OV9282_AGAIN_STEP 1 87 #define OV9282_AGAIN_DEFAULT 0x10 88 89 /* Group hold register */ 90 #define OV9282_REG_HOLD CCI_REG8(0x3308) 91 92 #define OV9282_REG_ANA_CORE_2 CCI_REG8(0x3662) 93 #define OV9282_ANA_CORE2_RAW8 0x07 94 #define OV9282_ANA_CORE2_RAW10 0x05 95 96 #define OV9282_REG_TIMING_FORMAT_1 CCI_REG8(0x3820) 97 #define OV9282_REG_TIMING_FORMAT_2 CCI_REG8(0x3821) 98 #define OV9282_FLIP_BIT BIT(2) 99 100 #define OV9282_REG_MIPI_CTRL00 CCI_REG8(0x4800) 101 #define OV9282_GATED_CLOCK BIT(5) 102 103 /* Flash/Strobe control registers */ 104 #define OV9282_REG_STROBE_FRAME_SPAN CCI_REG32(0x3925) 105 #define OV9282_STROBE_FRAME_SPAN_DEFAULT 0x0000001a 106 107 /* Input clock rate */ 108 #define OV9282_INCLK_RATE 24000000 109 110 /* CSI2 HW configuration */ 111 #define OV9282_LINK_FREQ 400000000 112 #define OV9282_NUM_DATA_LANES 2 113 114 /* Pixel rate */ 115 #define OV9282_PIXEL_RATE_10BIT (OV9282_LINK_FREQ * 2 * \ 116 OV9282_NUM_DATA_LANES / 10) 117 #define OV9282_PIXEL_RATE_8BIT (OV9282_LINK_FREQ * 2 * \ 118 OV9282_NUM_DATA_LANES / 8) 119 120 /* 121 * OV9282 native and active pixel array size. 122 * 8 dummy rows/columns on each edge of a 1280x800 active array 123 */ 124 #define OV9282_NATIVE_WIDTH 1296U 125 #define OV9282_NATIVE_HEIGHT 816U 126 #define OV9282_PIXEL_ARRAY_LEFT 8U 127 #define OV9282_PIXEL_ARRAY_TOP 8U 128 #define OV9282_PIXEL_ARRAY_WIDTH 1280U 129 #define OV9282_PIXEL_ARRAY_HEIGHT 800U 130 131 #define OV9282_REG_MIN 0x00 132 #define OV9282_REG_MAX 0xfffff 133 134 #define OV9282_STROBE_SPAN_FACTOR 192 135 136 static const char * const ov9282_supply_names[] = { 137 "avdd", /* Analog power */ 138 "dovdd", /* Digital I/O power */ 139 "dvdd", /* Digital core power */ 140 }; 141 142 #define OV9282_NUM_SUPPLIES ARRAY_SIZE(ov9282_supply_names) 143 144 /** 145 * struct ov9282_reg_list - ov9282 sensor register list 146 * @num_of_regs: Number of registers in the list 147 * @regs: Pointer to register list 148 */ 149 struct ov9282_reg_list { 150 u32 num_of_regs; 151 const struct cci_reg_sequence *regs; 152 }; 153 154 /** 155 * struct ov9282_mode - ov9282 sensor mode structure 156 * @width: Frame width 157 * @height: Frame height 158 * @hblank_min: Minimum horizontal blanking in lines for non-continuous[0] and 159 * continuous[1] clock modes 160 * @vblank: Vertical blanking in lines 161 * @vblank_min: Minimum vertical blanking in lines 162 * @vblank_max: Maximum vertical blanking in lines 163 * @link_freq_idx: Link frequency index 164 * @crop: on-sensor cropping for this mode 165 * @reg_list: Register list for sensor mode 166 */ 167 struct ov9282_mode { 168 u32 width; 169 u32 height; 170 u32 hblank_min[2]; 171 u32 vblank; 172 u32 vblank_min; 173 u32 vblank_max; 174 u32 link_freq_idx; 175 struct v4l2_rect crop; 176 struct ov9282_reg_list reg_list; 177 }; 178 179 /** 180 * struct ov9282 - ov9282 sensor device structure 181 * @dev: Pointer to generic device 182 * @sd: V4L2 sub-device 183 * @regmap: Regmap for sensor register access 184 * @pad: Media pad. Only one pad supported 185 * @reset_gpio: Sensor reset gpio 186 * @inclk: Sensor input clock 187 * @supplies: Regulator supplies for the sensor 188 * @ctrl_handler: V4L2 control handler 189 * @link_freq_ctrl: Pointer to link frequency control 190 * @hblank_ctrl: Pointer to horizontal blanking control 191 * @vblank_ctrl: Pointer to vertical blanking control 192 * @exp_ctrl: Pointer to exposure control 193 * @again_ctrl: Pointer to analog gain control 194 * @pixel_rate: Pointer to pixel rate control 195 * @flash_duration: Pointer to flash duration control 196 * @vblank: Vertical blanking in lines 197 * @noncontinuous_clock: Selection of CSI2 noncontinuous clock mode 198 * @cur_mode: Pointer to current selected sensor mode 199 * @code: Mbus code currently selected 200 * @mutex: Mutex for serializing sensor controls 201 */ 202 struct ov9282 { 203 struct device *dev; 204 struct v4l2_subdev sd; 205 struct regmap *regmap; 206 struct media_pad pad; 207 struct gpio_desc *reset_gpio; 208 struct clk *inclk; 209 struct regulator_bulk_data supplies[OV9282_NUM_SUPPLIES]; 210 struct v4l2_ctrl_handler ctrl_handler; 211 struct v4l2_ctrl *link_freq_ctrl; 212 struct v4l2_ctrl *hblank_ctrl; 213 struct v4l2_ctrl *vblank_ctrl; 214 struct { 215 struct v4l2_ctrl *exp_ctrl; 216 struct v4l2_ctrl *again_ctrl; 217 }; 218 struct v4l2_ctrl *pixel_rate; 219 struct v4l2_ctrl *flash_duration; 220 u32 vblank; 221 bool noncontinuous_clock; 222 const struct ov9282_mode *cur_mode; 223 u32 code; 224 }; 225 226 static const s64 link_freq[] = { 227 OV9282_LINK_FREQ, 228 }; 229 230 /* 231 * Common registers 232 * 233 * Note: Do NOT include a software reset (0x0103, 0x01) in any of these 234 * register arrays as some settings are written as part of ov9282_power_on, 235 * and the reset will clear them. 236 */ 237 static const struct cci_reg_sequence common_regs[] = { 238 {CCI_REG8(0x0302), 0x32}, 239 {CCI_REG8(0x030e), 0x02}, 240 {CCI_REG8(0x3001), 0x00}, 241 {OV9282_REG_OUTPUT_ENABLE4, 0x00}, 242 {OV9282_REG_OUTPUT_ENABLE5, 0x00}, 243 {OV9282_REG_OUTPUT_ENABLE6, OV9282_OUTPUT_ENABLE6_ILPWM}, 244 {CCI_REG8(0x3011), 0x0a}, 245 {CCI_REG8(0x3013), 0x18}, 246 {CCI_REG8(0x301c), 0xf0}, 247 {CCI_REG8(0x3022), 0x01}, 248 {CCI_REG8(0x3030), 0x10}, 249 {CCI_REG8(0x3039), 0x32}, 250 {CCI_REG8(0x303a), 0x00}, 251 {OV9282_REG_AEC_MANUAL, OV9282_GAIN_PREC16_EN}, 252 {CCI_REG8(0x3505), 0x8c}, 253 {CCI_REG8(0x3507), 0x03}, 254 {CCI_REG8(0x3508), 0x00}, 255 {CCI_REG8(0x3610), 0x80}, 256 {CCI_REG8(0x3611), 0xa0}, 257 {CCI_REG8(0x3620), 0x6e}, 258 {CCI_REG8(0x3632), 0x56}, 259 {CCI_REG8(0x3633), 0x78}, 260 {CCI_REG8(0x3666), 0x00}, 261 {CCI_REG8(0x366f), 0x5a}, 262 {CCI_REG8(0x3680), 0x84}, 263 {CCI_REG8(0x3712), 0x80}, 264 {CCI_REG8(0x372d), 0x22}, 265 {CCI_REG8(0x3731), 0x80}, 266 {CCI_REG8(0x3732), 0x30}, 267 {CCI_REG8(0x377d), 0x22}, 268 {CCI_REG8(0x3788), 0x02}, 269 {CCI_REG8(0x3789), 0xa4}, 270 {CCI_REG8(0x378a), 0x00}, 271 {CCI_REG8(0x378b), 0x4a}, 272 {CCI_REG8(0x3799), 0x20}, 273 {CCI_REG8(0x3881), 0x42}, 274 {CCI_REG8(0x38a8), 0x02}, 275 {CCI_REG8(0x38a9), 0x80}, 276 {CCI_REG8(0x38b1), 0x00}, 277 {CCI_REG8(0x38c4), 0x00}, 278 {CCI_REG8(0x38c5), 0xc0}, 279 {CCI_REG8(0x38c6), 0x04}, 280 {CCI_REG8(0x38c7), 0x80}, 281 {CCI_REG8(0x3920), 0xff}, 282 {CCI_REG8(0x4010), 0x40}, 283 {CCI_REG8(0x4043), 0x40}, 284 {CCI_REG8(0x4307), 0x30}, 285 {CCI_REG8(0x4317), 0x00}, 286 {CCI_REG8(0x4501), 0x00}, 287 {CCI_REG8(0x450a), 0x08}, 288 {CCI_REG8(0x4601), 0x04}, 289 {CCI_REG8(0x470f), 0x00}, 290 {CCI_REG8(0x4f07), 0x00}, 291 {CCI_REG8(0x5000), 0x9f}, 292 {CCI_REG8(0x5001), 0x00}, 293 {CCI_REG8(0x5e00), 0x00}, 294 {CCI_REG8(0x5d00), 0x07}, 295 {CCI_REG8(0x5d01), 0x00}, 296 {CCI_REG8(0x0101), 0x01}, 297 {CCI_REG8(0x1000), 0x03}, 298 {CCI_REG8(0x5a08), 0x84}, 299 }; 300 301 #define MODE_1280_800 0 302 #define MODE_1280_720 1 303 #define MODE_640_400 2 304 305 #define DEFAULT_MODE MODE_1280_720 306 307 /* Sensor mode registers */ 308 static const struct cci_reg_sequence mode_1280x800_regs[] = { 309 {CCI_REG8(0x3778), 0x00}, 310 {CCI_REG8(0x3800), 0x00}, 311 {CCI_REG8(0x3801), 0x00}, 312 {CCI_REG8(0x3802), 0x00}, 313 {CCI_REG8(0x3803), 0x00}, 314 {CCI_REG8(0x3804), 0x05}, 315 {CCI_REG8(0x3805), 0x0f}, 316 {CCI_REG8(0x3806), 0x03}, 317 {CCI_REG8(0x3807), 0x2f}, 318 {CCI_REG8(0x3808), 0x05}, 319 {CCI_REG8(0x3809), 0x00}, 320 {CCI_REG8(0x380a), 0x03}, 321 {CCI_REG8(0x380b), 0x20}, 322 {CCI_REG8(0x3810), 0x00}, 323 {CCI_REG8(0x3811), 0x08}, 324 {CCI_REG8(0x3812), 0x00}, 325 {CCI_REG8(0x3813), 0x08}, 326 {CCI_REG8(0x3814), 0x11}, 327 {CCI_REG8(0x3815), 0x11}, 328 {OV9282_REG_TIMING_FORMAT_1, 0x40}, 329 {OV9282_REG_TIMING_FORMAT_2, 0x00}, 330 {CCI_REG8(0x4003), 0x40}, 331 {CCI_REG8(0x4008), 0x04}, 332 {CCI_REG8(0x4009), 0x0b}, 333 {CCI_REG8(0x400c), 0x00}, 334 {CCI_REG8(0x400d), 0x07}, 335 {CCI_REG8(0x4507), 0x00}, 336 {CCI_REG8(0x4509), 0x00}, 337 }; 338 339 static const struct cci_reg_sequence mode_1280x720_regs[] = { 340 {CCI_REG8(0x3778), 0x00}, 341 {CCI_REG8(0x3800), 0x00}, 342 {CCI_REG8(0x3801), 0x00}, 343 {CCI_REG8(0x3802), 0x00}, 344 {CCI_REG8(0x3803), 0x00}, 345 {CCI_REG8(0x3804), 0x05}, 346 {CCI_REG8(0x3805), 0x0f}, 347 {CCI_REG8(0x3806), 0x02}, 348 {CCI_REG8(0x3807), 0xdf}, 349 {CCI_REG8(0x3808), 0x05}, 350 {CCI_REG8(0x3809), 0x00}, 351 {CCI_REG8(0x380a), 0x02}, 352 {CCI_REG8(0x380b), 0xd0}, 353 {CCI_REG8(0x3810), 0x00}, 354 {CCI_REG8(0x3811), 0x08}, 355 {CCI_REG8(0x3812), 0x00}, 356 {CCI_REG8(0x3813), 0x08}, 357 {CCI_REG8(0x3814), 0x11}, 358 {CCI_REG8(0x3815), 0x11}, 359 {OV9282_REG_TIMING_FORMAT_1, 0x3c}, 360 {OV9282_REG_TIMING_FORMAT_2, 0x84}, 361 {CCI_REG8(0x4003), 0x40}, 362 {CCI_REG8(0x4008), 0x02}, 363 {CCI_REG8(0x4009), 0x05}, 364 {CCI_REG8(0x400c), 0x00}, 365 {CCI_REG8(0x400d), 0x03}, 366 {CCI_REG8(0x4507), 0x00}, 367 {CCI_REG8(0x4509), 0x80}, 368 }; 369 370 static const struct cci_reg_sequence mode_640x400_regs[] = { 371 {CCI_REG8(0x3778), 0x10}, 372 {CCI_REG8(0x3800), 0x00}, 373 {CCI_REG8(0x3801), 0x00}, 374 {CCI_REG8(0x3802), 0x00}, 375 {CCI_REG8(0x3803), 0x00}, 376 {CCI_REG8(0x3804), 0x05}, 377 {CCI_REG8(0x3805), 0x0f}, 378 {CCI_REG8(0x3806), 0x03}, 379 {CCI_REG8(0x3807), 0x2f}, 380 {CCI_REG8(0x3808), 0x02}, 381 {CCI_REG8(0x3809), 0x80}, 382 {CCI_REG8(0x380a), 0x01}, 383 {CCI_REG8(0x380b), 0x90}, 384 {CCI_REG8(0x3810), 0x00}, 385 {CCI_REG8(0x3811), 0x04}, 386 {CCI_REG8(0x3812), 0x00}, 387 {CCI_REG8(0x3813), 0x04}, 388 {CCI_REG8(0x3814), 0x31}, 389 {CCI_REG8(0x3815), 0x22}, 390 {OV9282_REG_TIMING_FORMAT_1, 0x60}, 391 {OV9282_REG_TIMING_FORMAT_2, 0x01}, 392 {CCI_REG8(0x4008), 0x02}, 393 {CCI_REG8(0x4009), 0x05}, 394 {CCI_REG8(0x400c), 0x00}, 395 {CCI_REG8(0x400d), 0x03}, 396 {CCI_REG8(0x4507), 0x03}, 397 {CCI_REG8(0x4509), 0x80}, 398 }; 399 400 /* Supported sensor mode configurations */ 401 static const struct ov9282_mode supported_modes[] = { 402 [MODE_1280_800] = { 403 .width = 1280, 404 .height = 800, 405 .hblank_min = { 250, 176 }, 406 .vblank = 1022, 407 .vblank_min = 110, 408 .vblank_max = 51540, 409 .link_freq_idx = 0, 410 .crop = { 411 .left = OV9282_PIXEL_ARRAY_LEFT, 412 .top = OV9282_PIXEL_ARRAY_TOP, 413 .width = 1280, 414 .height = 800 415 }, 416 .reg_list = { 417 .num_of_regs = ARRAY_SIZE(mode_1280x800_regs), 418 .regs = mode_1280x800_regs, 419 }, 420 }, 421 [MODE_1280_720] = { 422 .width = 1280, 423 .height = 720, 424 .hblank_min = { 250, 176 }, 425 .vblank = 1022, 426 .vblank_min = 41, 427 .vblank_max = 51540, 428 .link_freq_idx = 0, 429 .crop = { 430 /* 431 * Note that this mode takes the top 720 lines from the 432 * 800 of the sensor. It does not take a middle crop. 433 */ 434 .left = OV9282_PIXEL_ARRAY_LEFT, 435 .top = OV9282_PIXEL_ARRAY_TOP, 436 .width = 1280, 437 .height = 720 438 }, 439 .reg_list = { 440 .num_of_regs = ARRAY_SIZE(mode_1280x720_regs), 441 .regs = mode_1280x720_regs, 442 }, 443 }, 444 [MODE_640_400] = { 445 .width = 640, 446 .height = 400, 447 .hblank_min = { 890, 816 }, 448 .vblank = 1022, 449 .vblank_min = 22, 450 .vblank_max = 51540, 451 .link_freq_idx = 0, 452 .crop = { 453 .left = OV9282_PIXEL_ARRAY_LEFT, 454 .top = OV9282_PIXEL_ARRAY_TOP, 455 .width = 1280, 456 .height = 800 457 }, 458 .reg_list = { 459 .num_of_regs = ARRAY_SIZE(mode_640x400_regs), 460 .regs = mode_640x400_regs, 461 }, 462 }, 463 }; 464 465 /** 466 * to_ov9282() - ov9282 V4L2 sub-device to ov9282 device. 467 * @subdev: pointer to ov9282 V4L2 sub-device 468 * 469 * Return: pointer to ov9282 device 470 */ 471 static inline struct ov9282 *to_ov9282(struct v4l2_subdev *subdev) 472 { 473 return container_of(subdev, struct ov9282, sd); 474 } 475 476 /** 477 * ov9282_update_controls() - Update control ranges based on streaming mode 478 * @ov9282: pointer to ov9282 device 479 * @mode: pointer to ov9282_mode sensor mode 480 * @fmt: pointer to the requested mode 481 * 482 * Return: 0 if successful, error code otherwise. 483 */ 484 static int ov9282_update_controls(struct ov9282 *ov9282, 485 const struct ov9282_mode *mode, 486 const struct v4l2_subdev_format *fmt) 487 { 488 u32 hblank_min; 489 s64 pixel_rate; 490 int ret; 491 492 ret = __v4l2_ctrl_s_ctrl(ov9282->link_freq_ctrl, mode->link_freq_idx); 493 if (ret) 494 return ret; 495 496 pixel_rate = (fmt->format.code == MEDIA_BUS_FMT_Y10_1X10) ? 497 OV9282_PIXEL_RATE_10BIT : OV9282_PIXEL_RATE_8BIT; 498 ret = __v4l2_ctrl_modify_range(ov9282->pixel_rate, pixel_rate, 499 pixel_rate, 1, pixel_rate); 500 if (ret) 501 return ret; 502 503 hblank_min = mode->hblank_min[ov9282->noncontinuous_clock ? 0 : 1]; 504 ret = __v4l2_ctrl_modify_range(ov9282->hblank_ctrl, hblank_min, 505 OV9282_TIMING_HTS_MAX - mode->width, 1, 506 hblank_min); 507 if (ret) 508 return ret; 509 510 return __v4l2_ctrl_modify_range(ov9282->vblank_ctrl, mode->vblank_min, 511 mode->vblank_max, 1, mode->vblank); 512 } 513 514 static u32 ov9282_exposure_to_us(struct ov9282 *ov9282, u32 exposure) 515 { 516 /* calculate exposure time in µs */ 517 u32 frame_width = ov9282->cur_mode->width + ov9282->hblank_ctrl->val; 518 u32 trow_us = frame_width / (ov9282->pixel_rate->val / 1000000UL); 519 520 return exposure * trow_us; 521 } 522 523 /** 524 * ov9282_update_exp_gain() - Set updated exposure and gain 525 * @ov9282: pointer to ov9282 device 526 * @exposure: updated exposure value 527 * @gain: updated analog gain value 528 * 529 * Return: 0 if successful, error code otherwise. 530 */ 531 static int ov9282_update_exp_gain(struct ov9282 *ov9282, u32 exposure, u32 gain) 532 { 533 u32 exposure_us = ov9282_exposure_to_us(ov9282, exposure); 534 int ret, ret_hold; 535 536 dev_dbg(ov9282->dev, "Set exp %u (~%u us), analog gain %u", 537 exposure, exposure_us, gain); 538 539 ret = cci_write(ov9282->regmap, OV9282_REG_HOLD, 0x01, NULL); 540 if (ret) 541 return ret; 542 543 ret = cci_write(ov9282->regmap, OV9282_REG_EXPOSURE, exposure << 4, NULL); 544 if (ret) 545 goto error_release_group_hold; 546 547 ret = cci_write(ov9282->regmap, OV9282_REG_AGAIN, gain, NULL); 548 if (ret) 549 goto error_release_group_hold; 550 551 ret = __v4l2_ctrl_modify_range(ov9282->flash_duration, 552 0, exposure_us, 1, 553 OV9282_STROBE_FRAME_SPAN_DEFAULT); 554 555 error_release_group_hold: 556 ret_hold = cci_write(ov9282->regmap, OV9282_REG_HOLD, 0, NULL); 557 558 return ret ? ret : ret_hold; 559 } 560 561 static u32 ov9282_us_to_flash_duration(struct ov9282 *ov9282, u32 value) 562 { 563 /* 564 * Calculate "strobe_frame_span" increments from a given value (µs). 565 * This is quite tricky as "The step width of shift and span is 566 * programmable under system clock domain.", but it's not documented 567 * how to program this step width (at least in the datasheet available 568 * to the author at time of writing). 569 * The formula below is interpolated from different modes/framerates 570 * and should work quite well for most settings. 571 */ 572 u32 frame_width = ov9282->cur_mode->width + ov9282->hblank_ctrl->val; 573 574 return value * OV9282_STROBE_SPAN_FACTOR / frame_width; 575 } 576 577 static u32 ov9282_flash_duration_to_us(struct ov9282 *ov9282, u32 value) 578 { 579 /* 580 * Calculate back to microseconds from "strobe_frame_span" increments. 581 * As the calculation in ov9282_us_to_flash_duration uses an integer 582 * divison round up here. 583 */ 584 u32 frame_width = ov9282->cur_mode->width + ov9282->hblank_ctrl->val; 585 586 return DIV_ROUND_UP(value * frame_width, OV9282_STROBE_SPAN_FACTOR); 587 } 588 589 /** 590 * ov9282_set_ctrl() - Set subdevice control 591 * @ctrl: pointer to v4l2_ctrl structure 592 * 593 * Supported controls: 594 * - V4L2_CID_VBLANK 595 * - cluster controls: 596 * - V4L2_CID_ANALOGUE_GAIN 597 * - V4L2_CID_EXPOSURE 598 * 599 * Return: 0 if successful, error code otherwise. 600 */ 601 static int ov9282_set_ctrl(struct v4l2_ctrl *ctrl) 602 { 603 struct ov9282 *ov9282 = 604 container_of(ctrl->handler, struct ov9282, ctrl_handler); 605 u32 analog_gain; 606 u32 exposure; 607 u32 lpfr; 608 int ret; 609 610 switch (ctrl->id) { 611 case V4L2_CID_VBLANK: 612 ov9282->vblank = ov9282->vblank_ctrl->val; 613 614 dev_dbg(ov9282->dev, "Received vblank %u, new lpfr %u", 615 ov9282->vblank, 616 ov9282->vblank + ov9282->cur_mode->height); 617 618 ret = __v4l2_ctrl_modify_range(ov9282->exp_ctrl, 619 OV9282_EXPOSURE_MIN, 620 ov9282->vblank + 621 ov9282->cur_mode->height - 622 OV9282_EXPOSURE_OFFSET, 623 1, OV9282_EXPOSURE_DEFAULT); 624 break; 625 } 626 627 /* Set controls only if sensor is in power on state */ 628 if (!pm_runtime_get_if_in_use(ov9282->dev)) 629 return 0; 630 631 switch (ctrl->id) { 632 case V4L2_CID_EXPOSURE: 633 exposure = ctrl->val; 634 analog_gain = ov9282->again_ctrl->val; 635 636 dev_dbg(ov9282->dev, "Received exp %u, analog gain %u", 637 exposure, analog_gain); 638 639 ret = ov9282_update_exp_gain(ov9282, exposure, analog_gain); 640 break; 641 case V4L2_CID_VBLANK: 642 lpfr = ov9282->vblank + ov9282->cur_mode->height; 643 ret = cci_write(ov9282->regmap, OV9282_REG_LPFR, lpfr, NULL); 644 break; 645 case V4L2_CID_HFLIP: 646 ret = cci_update_bits(ov9282->regmap, OV9282_REG_TIMING_FORMAT_2, 647 OV9282_FLIP_BIT, ctrl->val ? OV9282_FLIP_BIT : 0, NULL); 648 break; 649 case V4L2_CID_VFLIP: 650 ret = cci_update_bits(ov9282->regmap, OV9282_REG_TIMING_FORMAT_1, 651 OV9282_FLIP_BIT, ctrl->val ? OV9282_FLIP_BIT : 0, NULL); 652 break; 653 case V4L2_CID_HBLANK: 654 ret = cci_write(ov9282->regmap, OV9282_REG_TIMING_HTS, 655 (ctrl->val + ov9282->cur_mode->width) >> 1, NULL); 656 break; 657 case V4L2_CID_FLASH_STROBE_OE: 658 ret = cci_update_bits(ov9282->regmap, OV9282_REG_OUTPUT_ENABLE6, 659 OV9282_OUTPUT_ENABLE6_STROBE, 660 ctrl->val ? OV9282_OUTPUT_ENABLE6_STROBE : 0, NULL); 661 break; 662 case V4L2_CID_FLASH_DURATION: 663 ret = cci_write(ov9282->regmap, OV9282_REG_STROBE_FRAME_SPAN, ctrl->val, NULL); 664 break; 665 default: 666 dev_err(ov9282->dev, "Invalid control %d", ctrl->id); 667 ret = -EINVAL; 668 } 669 670 pm_runtime_put(ov9282->dev); 671 672 return ret; 673 } 674 675 static int ov9282_try_ctrl(struct v4l2_ctrl *ctrl) 676 { 677 struct ov9282 *ov9282 = 678 container_of_const(ctrl->handler, struct ov9282, ctrl_handler); 679 680 if (ctrl->id == V4L2_CID_FLASH_DURATION) { 681 u32 us = ctrl->val; 682 u32 fd = ov9282_us_to_flash_duration(ov9282, us); 683 684 /* get nearest strobe_duration value */ 685 u32 us0 = ov9282_flash_duration_to_us(ov9282, fd); 686 u32 us1 = ov9282_flash_duration_to_us(ov9282, fd + 1); 687 688 if (abs(us1 - us) < abs(us - us0)) 689 ctrl->val = us1; 690 else 691 ctrl->val = us0; 692 693 if (us != ctrl->val) 694 dev_dbg(ov9282->dev, "using next valid strobe_duration %u instead of %u\n", 695 ctrl->val, us); 696 } 697 698 return 0; 699 } 700 701 /* V4l2 subdevice control ops*/ 702 static const struct v4l2_ctrl_ops ov9282_ctrl_ops = { 703 .s_ctrl = ov9282_set_ctrl, 704 .try_ctrl = ov9282_try_ctrl, 705 }; 706 707 /** 708 * ov9282_enum_mbus_code() - Enumerate V4L2 sub-device mbus codes 709 * @sd: pointer to ov9282 V4L2 sub-device structure 710 * @sd_state: V4L2 sub-device configuration 711 * @code: V4L2 sub-device code enumeration need to be filled 712 * 713 * Return: 0 if successful, error code otherwise. 714 */ 715 static int ov9282_enum_mbus_code(struct v4l2_subdev *sd, 716 struct v4l2_subdev_state *sd_state, 717 struct v4l2_subdev_mbus_code_enum *code) 718 { 719 switch (code->index) { 720 case 0: 721 code->code = MEDIA_BUS_FMT_Y10_1X10; 722 break; 723 case 1: 724 code->code = MEDIA_BUS_FMT_Y8_1X8; 725 break; 726 default: 727 return -EINVAL; 728 } 729 730 return 0; 731 } 732 733 /** 734 * ov9282_enum_frame_size() - Enumerate V4L2 sub-device frame sizes 735 * @sd: pointer to ov9282 V4L2 sub-device structure 736 * @sd_state: V4L2 sub-device configuration 737 * @fsize: V4L2 sub-device size enumeration need to be filled 738 * 739 * Return: 0 if successful, error code otherwise. 740 */ 741 static int ov9282_enum_frame_size(struct v4l2_subdev *sd, 742 struct v4l2_subdev_state *sd_state, 743 struct v4l2_subdev_frame_size_enum *fsize) 744 { 745 if (fsize->index >= ARRAY_SIZE(supported_modes)) 746 return -EINVAL; 747 748 if (fsize->code != MEDIA_BUS_FMT_Y10_1X10 && 749 fsize->code != MEDIA_BUS_FMT_Y8_1X8) 750 return -EINVAL; 751 752 fsize->min_width = supported_modes[fsize->index].width; 753 fsize->max_width = fsize->min_width; 754 fsize->min_height = supported_modes[fsize->index].height; 755 fsize->max_height = fsize->min_height; 756 757 return 0; 758 } 759 760 /** 761 * ov9282_fill_pad_format() - Fill subdevice pad format 762 * from selected sensor mode 763 * @ov9282: pointer to ov9282 device 764 * @mode: pointer to ov9282_mode sensor mode 765 * @code: mbus code to be stored 766 * @fmt: V4L2 sub-device format need to be filled 767 */ 768 static void ov9282_fill_pad_format(struct ov9282 *ov9282, 769 const struct ov9282_mode *mode, 770 u32 code, 771 struct v4l2_subdev_format *fmt) 772 { 773 fmt->format.width = mode->width; 774 fmt->format.height = mode->height; 775 fmt->format.code = code; 776 fmt->format.field = V4L2_FIELD_NONE; 777 fmt->format.colorspace = V4L2_COLORSPACE_RAW; 778 fmt->format.ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; 779 fmt->format.quantization = V4L2_QUANTIZATION_DEFAULT; 780 fmt->format.xfer_func = V4L2_XFER_FUNC_NONE; 781 } 782 783 /** 784 * ov9282_get_pad_format() - Get subdevice pad format 785 * @sd: pointer to ov9282 V4L2 sub-device structure 786 * @sd_state: V4L2 sub-device configuration 787 * @fmt: V4L2 sub-device format need to be set 788 * 789 * Return: 0 if successful, error code otherwise. 790 */ 791 static int ov9282_get_pad_format(struct v4l2_subdev *sd, 792 struct v4l2_subdev_state *sd_state, 793 struct v4l2_subdev_format *fmt) 794 { 795 struct ov9282 *ov9282 = to_ov9282(sd); 796 797 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { 798 struct v4l2_mbus_framefmt *framefmt; 799 800 framefmt = v4l2_subdev_state_get_format(sd_state, fmt->pad); 801 fmt->format = *framefmt; 802 } else { 803 ov9282_fill_pad_format(ov9282, ov9282->cur_mode, ov9282->code, 804 fmt); 805 } 806 807 return 0; 808 } 809 810 /** 811 * ov9282_set_pad_format() - Set subdevice pad format 812 * @sd: pointer to ov9282 V4L2 sub-device structure 813 * @sd_state: V4L2 sub-device configuration 814 * @fmt: V4L2 sub-device format need to be set 815 * 816 * Return: 0 if successful, error code otherwise. 817 */ 818 static int ov9282_set_pad_format(struct v4l2_subdev *sd, 819 struct v4l2_subdev_state *sd_state, 820 struct v4l2_subdev_format *fmt) 821 { 822 struct ov9282 *ov9282 = to_ov9282(sd); 823 const struct ov9282_mode *mode; 824 u32 code; 825 int ret = 0; 826 827 mode = v4l2_find_nearest_size(supported_modes, 828 ARRAY_SIZE(supported_modes), 829 width, height, 830 fmt->format.width, 831 fmt->format.height); 832 if (fmt->format.code == MEDIA_BUS_FMT_Y8_1X8) 833 code = MEDIA_BUS_FMT_Y8_1X8; 834 else 835 code = MEDIA_BUS_FMT_Y10_1X10; 836 837 ov9282_fill_pad_format(ov9282, mode, code, fmt); 838 839 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { 840 struct v4l2_mbus_framefmt *framefmt; 841 842 framefmt = v4l2_subdev_state_get_format(sd_state, fmt->pad); 843 *framefmt = fmt->format; 844 } else { 845 ret = ov9282_update_controls(ov9282, mode, fmt); 846 if (!ret) { 847 ov9282->cur_mode = mode; 848 ov9282->code = code; 849 } 850 } 851 852 return ret; 853 } 854 855 /** 856 * ov9282_init_state() - Initialize sub-device state 857 * @sd: pointer to ov9282 V4L2 sub-device structure 858 * @sd_state: V4L2 sub-device configuration 859 * 860 * Return: 0 if successful, error code otherwise. 861 */ 862 static int ov9282_init_state(struct v4l2_subdev *sd, 863 struct v4l2_subdev_state *sd_state) 864 { 865 struct ov9282 *ov9282 = to_ov9282(sd); 866 struct v4l2_subdev_format fmt = { 0 }; 867 868 fmt.which = sd_state ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE; 869 ov9282_fill_pad_format(ov9282, &supported_modes[DEFAULT_MODE], 870 ov9282->code, &fmt); 871 872 return ov9282_set_pad_format(sd, sd_state, &fmt); 873 } 874 875 static const struct v4l2_rect * 876 __ov9282_get_pad_crop(struct ov9282 *ov9282, 877 struct v4l2_subdev_state *sd_state, 878 unsigned int pad, enum v4l2_subdev_format_whence which) 879 { 880 switch (which) { 881 case V4L2_SUBDEV_FORMAT_TRY: 882 return v4l2_subdev_state_get_crop(sd_state, pad); 883 case V4L2_SUBDEV_FORMAT_ACTIVE: 884 return &ov9282->cur_mode->crop; 885 } 886 887 return NULL; 888 } 889 890 static int ov9282_get_selection(struct v4l2_subdev *sd, 891 struct v4l2_subdev_state *sd_state, 892 struct v4l2_subdev_selection *sel) 893 { 894 switch (sel->target) { 895 case V4L2_SEL_TGT_CROP: { 896 struct ov9282 *ov9282 = to_ov9282(sd); 897 898 sel->r = *__ov9282_get_pad_crop(ov9282, sd_state, sel->pad, 899 sel->which); 900 901 return 0; 902 } 903 904 case V4L2_SEL_TGT_NATIVE_SIZE: 905 sel->r.top = 0; 906 sel->r.left = 0; 907 sel->r.width = OV9282_NATIVE_WIDTH; 908 sel->r.height = OV9282_NATIVE_HEIGHT; 909 910 return 0; 911 912 case V4L2_SEL_TGT_CROP_DEFAULT: 913 case V4L2_SEL_TGT_CROP_BOUNDS: 914 sel->r.top = OV9282_PIXEL_ARRAY_TOP; 915 sel->r.left = OV9282_PIXEL_ARRAY_LEFT; 916 sel->r.width = OV9282_PIXEL_ARRAY_WIDTH; 917 sel->r.height = OV9282_PIXEL_ARRAY_HEIGHT; 918 919 return 0; 920 } 921 922 return -EINVAL; 923 } 924 925 static int ov9282_enable_streams(struct v4l2_subdev *sd, 926 struct v4l2_subdev_state *state, u32 pad, 927 u64 streams_mask) 928 { 929 const struct cci_reg_sequence bitdepth_regs[2][2] = { 930 { 931 {OV9282_REG_PLL_CTRL_0D, OV9282_PLL_CTRL_0D_RAW10}, 932 {OV9282_REG_ANA_CORE_2, OV9282_ANA_CORE2_RAW10}, 933 }, { 934 {OV9282_REG_PLL_CTRL_0D, OV9282_PLL_CTRL_0D_RAW8}, 935 {OV9282_REG_ANA_CORE_2, OV9282_ANA_CORE2_RAW8}, 936 } 937 }; 938 struct ov9282 *ov9282 = to_ov9282(sd); 939 const struct ov9282_reg_list *reg_list; 940 int bitdepth_index; 941 int ret; 942 943 ret = pm_runtime_resume_and_get(ov9282->dev); 944 if (ret) 945 return ret; 946 947 /* Write common registers */ 948 ret = cci_multi_reg_write(ov9282->regmap, common_regs, 949 ARRAY_SIZE(common_regs), NULL); 950 if (ret) { 951 dev_err(ov9282->dev, "fail to write common registers"); 952 goto err_pm_put; 953 } 954 955 bitdepth_index = ov9282->code == MEDIA_BUS_FMT_Y10_1X10 ? 0 : 1; 956 ret = cci_multi_reg_write(ov9282->regmap, 957 bitdepth_regs[bitdepth_index], 2, NULL); 958 if (ret) { 959 dev_err(ov9282->dev, "fail to write bitdepth regs"); 960 goto err_pm_put; 961 } 962 963 /* Write sensor mode registers */ 964 reg_list = &ov9282->cur_mode->reg_list; 965 ret = cci_multi_reg_write(ov9282->regmap, reg_list->regs, 966 reg_list->num_of_regs, NULL); 967 if (ret) { 968 dev_err(ov9282->dev, "fail to write initial registers"); 969 goto err_pm_put; 970 } 971 972 /* Setup handler will write actual exposure and gain */ 973 ret = __v4l2_ctrl_handler_setup(ov9282->sd.ctrl_handler); 974 if (ret) { 975 dev_err(ov9282->dev, "fail to setup handler"); 976 goto err_pm_put; 977 } 978 979 /* Start streaming */ 980 ret = cci_write(ov9282->regmap, OV9282_REG_MODE_SELECT, 981 OV9282_MODE_STREAMING, NULL); 982 if (ret) { 983 dev_err(ov9282->dev, "fail to start streaming"); 984 goto err_pm_put; 985 } 986 987 return 0; 988 989 err_pm_put: 990 pm_runtime_put(ov9282->dev); 991 992 return ret; 993 } 994 995 static int ov9282_disable_streams(struct v4l2_subdev *sd, 996 struct v4l2_subdev_state *state, u32 pad, 997 u64 streams_mask) 998 { 999 struct ov9282 *ov9282 = to_ov9282(sd); 1000 int ret; 1001 1002 ret = cci_write(ov9282->regmap, OV9282_REG_MODE_SELECT, 1003 OV9282_MODE_STANDBY, NULL); 1004 1005 pm_runtime_put(ov9282->dev); 1006 1007 return ret; 1008 } 1009 1010 /** 1011 * ov9282_detect() - Detect ov9282 sensor 1012 * @ov9282: pointer to ov9282 device 1013 * 1014 * Return: 0 if successful, -EIO if sensor id does not match 1015 */ 1016 static int ov9282_detect(struct ov9282 *ov9282) 1017 { 1018 int ret; 1019 u64 val; 1020 1021 ret = cci_read(ov9282->regmap, OV9282_REG_ID, &val, NULL); 1022 if (ret) 1023 return ret; 1024 1025 if (val != OV9282_ID) { 1026 dev_err(ov9282->dev, "chip id mismatch: %x!=%llx", 1027 OV9282_ID, val); 1028 return -ENXIO; 1029 } 1030 1031 return 0; 1032 } 1033 1034 static int ov9282_configure_regulators(struct ov9282 *ov9282) 1035 { 1036 unsigned int i; 1037 1038 for (i = 0; i < OV9282_NUM_SUPPLIES; i++) 1039 ov9282->supplies[i].supply = ov9282_supply_names[i]; 1040 1041 return devm_regulator_bulk_get(ov9282->dev, 1042 OV9282_NUM_SUPPLIES, 1043 ov9282->supplies); 1044 } 1045 1046 /** 1047 * ov9282_parse_hw_config() - Parse HW configuration and check if supported 1048 * @ov9282: pointer to ov9282 device 1049 * 1050 * Return: 0 if successful, error code otherwise. 1051 */ 1052 static int ov9282_parse_hw_config(struct ov9282 *ov9282) 1053 { 1054 struct fwnode_handle *fwnode = dev_fwnode(ov9282->dev); 1055 struct v4l2_fwnode_endpoint bus_cfg = { 1056 .bus_type = V4L2_MBUS_CSI2_DPHY 1057 }; 1058 struct fwnode_handle *ep; 1059 unsigned long rate; 1060 unsigned int i; 1061 int ret; 1062 1063 if (!fwnode) 1064 return -ENXIO; 1065 1066 /* Request optional reset pin */ 1067 ov9282->reset_gpio = devm_gpiod_get_optional(ov9282->dev, "reset", 1068 GPIOD_OUT_LOW); 1069 if (IS_ERR(ov9282->reset_gpio)) { 1070 dev_err(ov9282->dev, "failed to get reset gpio %pe", 1071 ov9282->reset_gpio); 1072 return PTR_ERR(ov9282->reset_gpio); 1073 } 1074 1075 /* Get sensor input clock */ 1076 ov9282->inclk = devm_v4l2_sensor_clk_get(ov9282->dev, NULL); 1077 if (IS_ERR(ov9282->inclk)) 1078 return dev_err_probe(ov9282->dev, PTR_ERR(ov9282->inclk), 1079 "could not get inclk\n"); 1080 1081 ret = ov9282_configure_regulators(ov9282); 1082 if (ret) 1083 return dev_err_probe(ov9282->dev, ret, 1084 "Failed to get power regulators\n"); 1085 1086 rate = clk_get_rate(ov9282->inclk); 1087 if (rate != OV9282_INCLK_RATE) { 1088 dev_err(ov9282->dev, "inclk frequency mismatch"); 1089 return -EINVAL; 1090 } 1091 1092 ep = fwnode_graph_get_next_endpoint(fwnode, NULL); 1093 if (!ep) 1094 return -ENXIO; 1095 1096 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg); 1097 fwnode_handle_put(ep); 1098 if (ret) 1099 return ret; 1100 1101 ov9282->noncontinuous_clock = 1102 bus_cfg.bus.mipi_csi2.flags & V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK; 1103 1104 if (bus_cfg.bus.mipi_csi2.num_data_lanes != OV9282_NUM_DATA_LANES) { 1105 dev_err(ov9282->dev, 1106 "number of CSI2 data lanes %d is not supported", 1107 bus_cfg.bus.mipi_csi2.num_data_lanes); 1108 ret = -EINVAL; 1109 goto done_endpoint_free; 1110 } 1111 1112 if (!bus_cfg.nr_of_link_frequencies) { 1113 dev_err(ov9282->dev, "no link frequencies defined"); 1114 ret = -EINVAL; 1115 goto done_endpoint_free; 1116 } 1117 1118 for (i = 0; i < bus_cfg.nr_of_link_frequencies; i++) 1119 if (bus_cfg.link_frequencies[i] == OV9282_LINK_FREQ) 1120 goto done_endpoint_free; 1121 1122 ret = -EINVAL; 1123 1124 done_endpoint_free: 1125 v4l2_fwnode_endpoint_free(&bus_cfg); 1126 1127 return ret; 1128 } 1129 1130 /* V4l2 subdevice ops */ 1131 static const struct v4l2_subdev_core_ops ov9282_core_ops = { 1132 .subscribe_event = v4l2_ctrl_subdev_subscribe_event, 1133 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 1134 }; 1135 1136 static const struct v4l2_subdev_video_ops ov9282_video_ops = { 1137 .s_stream = v4l2_subdev_s_stream_helper, 1138 }; 1139 1140 static const struct v4l2_subdev_pad_ops ov9282_pad_ops = { 1141 .enum_mbus_code = ov9282_enum_mbus_code, 1142 .enum_frame_size = ov9282_enum_frame_size, 1143 .get_fmt = ov9282_get_pad_format, 1144 .set_fmt = ov9282_set_pad_format, 1145 .get_selection = ov9282_get_selection, 1146 .enable_streams = ov9282_enable_streams, 1147 .disable_streams = ov9282_disable_streams, 1148 }; 1149 1150 static const struct v4l2_subdev_ops ov9282_subdev_ops = { 1151 .core = &ov9282_core_ops, 1152 .video = &ov9282_video_ops, 1153 .pad = &ov9282_pad_ops, 1154 }; 1155 1156 static const struct v4l2_subdev_internal_ops ov9282_internal_ops = { 1157 .init_state = ov9282_init_state, 1158 }; 1159 1160 /** 1161 * ov9282_power_on() - Sensor power on sequence 1162 * @dev: pointer to i2c device 1163 * 1164 * Return: 0 if successful, error code otherwise. 1165 */ 1166 static int ov9282_power_on(struct device *dev) 1167 { 1168 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1169 struct ov9282 *ov9282 = to_ov9282(sd); 1170 int ret; 1171 1172 ret = regulator_bulk_enable(OV9282_NUM_SUPPLIES, ov9282->supplies); 1173 if (ret < 0) { 1174 dev_err(dev, "Failed to enable regulators\n"); 1175 return ret; 1176 } 1177 1178 usleep_range(400, 600); 1179 1180 gpiod_set_value_cansleep(ov9282->reset_gpio, 1); 1181 1182 ret = clk_prepare_enable(ov9282->inclk); 1183 if (ret) { 1184 dev_err(ov9282->dev, "fail to enable inclk"); 1185 goto error_reset; 1186 } 1187 1188 usleep_range(400, 600); 1189 1190 ret = cci_write(ov9282->regmap, OV9282_REG_MIPI_CTRL00, 1191 ov9282->noncontinuous_clock ? OV9282_GATED_CLOCK : 0, NULL); 1192 if (ret) { 1193 dev_err(ov9282->dev, "fail to write MIPI_CTRL00"); 1194 goto error_clk; 1195 } 1196 1197 return 0; 1198 1199 error_clk: 1200 clk_disable_unprepare(ov9282->inclk); 1201 error_reset: 1202 gpiod_set_value_cansleep(ov9282->reset_gpio, 0); 1203 1204 regulator_bulk_disable(OV9282_NUM_SUPPLIES, ov9282->supplies); 1205 1206 return ret; 1207 } 1208 1209 /** 1210 * ov9282_power_off() - Sensor power off sequence 1211 * @dev: pointer to i2c device 1212 * 1213 * Return: 0 if successful, error code otherwise. 1214 */ 1215 static int ov9282_power_off(struct device *dev) 1216 { 1217 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1218 struct ov9282 *ov9282 = to_ov9282(sd); 1219 1220 gpiod_set_value_cansleep(ov9282->reset_gpio, 0); 1221 1222 clk_disable_unprepare(ov9282->inclk); 1223 1224 regulator_bulk_disable(OV9282_NUM_SUPPLIES, ov9282->supplies); 1225 1226 return 0; 1227 } 1228 1229 /** 1230 * ov9282_init_controls() - Initialize sensor subdevice controls 1231 * @ov9282: pointer to ov9282 device 1232 * 1233 * Return: 0 if successful, error code otherwise. 1234 */ 1235 static int ov9282_init_controls(struct ov9282 *ov9282) 1236 { 1237 struct v4l2_ctrl_handler *ctrl_hdlr = &ov9282->ctrl_handler; 1238 const struct ov9282_mode *mode = ov9282->cur_mode; 1239 struct v4l2_fwnode_device_properties props; 1240 u32 hblank_min; 1241 u32 exposure_us; 1242 u32 lpfr; 1243 int ret; 1244 1245 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 12); 1246 if (ret) 1247 return ret; 1248 1249 /* Initialize exposure and gain */ 1250 lpfr = mode->vblank + mode->height; 1251 ov9282->exp_ctrl = v4l2_ctrl_new_std(ctrl_hdlr, 1252 &ov9282_ctrl_ops, 1253 V4L2_CID_EXPOSURE, 1254 OV9282_EXPOSURE_MIN, 1255 lpfr - OV9282_EXPOSURE_OFFSET, 1256 OV9282_EXPOSURE_STEP, 1257 OV9282_EXPOSURE_DEFAULT); 1258 1259 ov9282->again_ctrl = v4l2_ctrl_new_std(ctrl_hdlr, 1260 &ov9282_ctrl_ops, 1261 V4L2_CID_ANALOGUE_GAIN, 1262 OV9282_AGAIN_MIN, 1263 OV9282_AGAIN_MAX, 1264 OV9282_AGAIN_STEP, 1265 OV9282_AGAIN_DEFAULT); 1266 1267 v4l2_ctrl_cluster(2, &ov9282->exp_ctrl); 1268 1269 ov9282->vblank_ctrl = v4l2_ctrl_new_std(ctrl_hdlr, 1270 &ov9282_ctrl_ops, 1271 V4L2_CID_VBLANK, 1272 mode->vblank_min, 1273 mode->vblank_max, 1274 1, mode->vblank); 1275 1276 v4l2_ctrl_new_std(ctrl_hdlr, &ov9282_ctrl_ops, V4L2_CID_VFLIP, 1277 0, 1, 1, 1); 1278 1279 v4l2_ctrl_new_std(ctrl_hdlr, &ov9282_ctrl_ops, V4L2_CID_HFLIP, 1280 0, 1, 1, 1); 1281 1282 /* Read only controls */ 1283 ov9282->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov9282_ctrl_ops, 1284 V4L2_CID_PIXEL_RATE, 1285 OV9282_PIXEL_RATE_10BIT, 1286 OV9282_PIXEL_RATE_10BIT, 1, 1287 OV9282_PIXEL_RATE_10BIT); 1288 1289 ov9282->link_freq_ctrl = v4l2_ctrl_new_int_menu(ctrl_hdlr, 1290 &ov9282_ctrl_ops, 1291 V4L2_CID_LINK_FREQ, 1292 ARRAY_SIZE(link_freq) - 1293 1, 1294 mode->link_freq_idx, 1295 link_freq); 1296 if (ov9282->link_freq_ctrl) 1297 ov9282->link_freq_ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY; 1298 1299 hblank_min = mode->hblank_min[ov9282->noncontinuous_clock ? 0 : 1]; 1300 ov9282->hblank_ctrl = v4l2_ctrl_new_std(ctrl_hdlr, 1301 &ov9282_ctrl_ops, 1302 V4L2_CID_HBLANK, 1303 hblank_min, 1304 OV9282_TIMING_HTS_MAX - mode->width, 1305 1, hblank_min); 1306 1307 /* Flash/Strobe controls */ 1308 v4l2_ctrl_new_std(ctrl_hdlr, &ov9282_ctrl_ops, 1309 V4L2_CID_FLASH_STROBE_OE, 0, 1, 1, 0); 1310 1311 exposure_us = ov9282_exposure_to_us(ov9282, OV9282_EXPOSURE_DEFAULT); 1312 ov9282->flash_duration = 1313 v4l2_ctrl_new_std(ctrl_hdlr, &ov9282_ctrl_ops, 1314 V4L2_CID_FLASH_DURATION, 0, exposure_us, 1, 1315 OV9282_STROBE_FRAME_SPAN_DEFAULT); 1316 1317 ret = v4l2_fwnode_device_parse(ov9282->dev, &props); 1318 if (!ret) { 1319 /* Failure sets ctrl_hdlr->error, which we check afterwards anyway */ 1320 v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &ov9282_ctrl_ops, 1321 &props); 1322 } 1323 1324 if (ctrl_hdlr->error || ret) { 1325 dev_err(ov9282->dev, "control init failed: %d", 1326 ctrl_hdlr->error); 1327 v4l2_ctrl_handler_free(ctrl_hdlr); 1328 return ctrl_hdlr->error; 1329 } 1330 1331 ov9282->sd.ctrl_handler = ctrl_hdlr; 1332 1333 return 0; 1334 } 1335 1336 /** 1337 * ov9282_probe() - I2C client device binding 1338 * @client: pointer to i2c client device 1339 * 1340 * Return: 0 if successful, error code otherwise. 1341 */ 1342 static int ov9282_probe(struct i2c_client *client) 1343 { 1344 struct ov9282 *ov9282; 1345 int ret; 1346 1347 ov9282 = devm_kzalloc(&client->dev, sizeof(*ov9282), GFP_KERNEL); 1348 if (!ov9282) 1349 return -ENOMEM; 1350 1351 ov9282->dev = &client->dev; 1352 1353 /* Initialize subdev */ 1354 v4l2_i2c_subdev_init(&ov9282->sd, client, &ov9282_subdev_ops); 1355 ov9282->sd.internal_ops = &ov9282_internal_ops; 1356 v4l2_i2c_subdev_set_name(&ov9282->sd, client, 1357 device_get_match_data(ov9282->dev), NULL); 1358 1359 ret = ov9282_parse_hw_config(ov9282); 1360 if (ret) { 1361 dev_err(ov9282->dev, "HW configuration is not supported"); 1362 return ret; 1363 } 1364 1365 ov9282->regmap = devm_cci_regmap_init_i2c(client, 16); 1366 if (IS_ERR(ov9282->regmap)) 1367 return dev_err_probe(ov9282->dev, PTR_ERR(ov9282->regmap), 1368 "Failed to init CCI\n"); 1369 1370 ret = ov9282_power_on(ov9282->dev); 1371 if (ret) 1372 return dev_err_probe(ov9282->dev, ret, 1373 "failed to power-on the sensor"); 1374 1375 /* Check module identity */ 1376 ret = ov9282_detect(ov9282); 1377 if (ret) { 1378 dev_err(ov9282->dev, "failed to find sensor: %d", ret); 1379 goto error_power_off; 1380 } 1381 1382 /* Set default mode to first mode */ 1383 ov9282->cur_mode = &supported_modes[DEFAULT_MODE]; 1384 ov9282->code = MEDIA_BUS_FMT_Y10_1X10; 1385 ov9282->vblank = ov9282->cur_mode->vblank; 1386 1387 ret = ov9282_init_controls(ov9282); 1388 if (ret) { 1389 dev_err(ov9282->dev, "failed to init controls: %d", ret); 1390 goto error_power_off; 1391 } 1392 1393 /* Initialize subdev */ 1394 ov9282->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | 1395 V4L2_SUBDEV_FL_HAS_EVENTS; 1396 ov9282->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1397 1398 /* Initialize source pad */ 1399 ov9282->pad.flags = MEDIA_PAD_FL_SOURCE; 1400 ret = media_entity_pads_init(&ov9282->sd.entity, 1, &ov9282->pad); 1401 if (ret) { 1402 dev_err(ov9282->dev, "failed to init entity pads: %d", ret); 1403 goto error_handler_free; 1404 } 1405 1406 ov9282->sd.state_lock = ov9282->ctrl_handler.lock; 1407 ret = v4l2_subdev_init_finalize(&ov9282->sd); 1408 if (ret < 0) { 1409 dev_err_probe(ov9282->dev, ret, "failed to init subdev\n"); 1410 goto error_media_entity; 1411 } 1412 1413 pm_runtime_set_active(ov9282->dev); 1414 pm_runtime_enable(ov9282->dev); 1415 1416 ret = v4l2_async_register_subdev_sensor(&ov9282->sd); 1417 if (ret < 0) 1418 goto v4l2_subdev_cleanup; 1419 1420 pm_runtime_idle(ov9282->dev); 1421 1422 return 0; 1423 1424 v4l2_subdev_cleanup: 1425 v4l2_subdev_cleanup(&ov9282->sd); 1426 pm_runtime_disable(ov9282->dev); 1427 pm_runtime_set_suspended(ov9282->dev); 1428 error_media_entity: 1429 media_entity_cleanup(&ov9282->sd.entity); 1430 error_handler_free: 1431 v4l2_ctrl_handler_free(ov9282->sd.ctrl_handler); 1432 error_power_off: 1433 ov9282_power_off(ov9282->dev); 1434 1435 return ret; 1436 } 1437 1438 /** 1439 * ov9282_remove() - I2C client device unbinding 1440 * @client: pointer to I2C client device 1441 * 1442 * Return: 0 if successful, error code otherwise. 1443 */ 1444 static void ov9282_remove(struct i2c_client *client) 1445 { 1446 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1447 1448 v4l2_async_unregister_subdev(sd); 1449 v4l2_subdev_cleanup(sd); 1450 media_entity_cleanup(&sd->entity); 1451 v4l2_ctrl_handler_free(sd->ctrl_handler); 1452 1453 pm_runtime_disable(&client->dev); 1454 if (!pm_runtime_status_suspended(&client->dev)) 1455 ov9282_power_off(&client->dev); 1456 pm_runtime_set_suspended(&client->dev); 1457 } 1458 1459 static const struct dev_pm_ops ov9282_pm_ops = { 1460 SET_RUNTIME_PM_OPS(ov9282_power_off, ov9282_power_on, NULL) 1461 }; 1462 1463 static const struct of_device_id ov9282_of_match[] = { 1464 { .compatible = "ovti,ov9281", .data = "ov9281" }, 1465 { .compatible = "ovti,ov9282", .data = "ov9282" }, 1466 { } 1467 }; 1468 1469 MODULE_DEVICE_TABLE(of, ov9282_of_match); 1470 1471 static struct i2c_driver ov9282_driver = { 1472 .probe = ov9282_probe, 1473 .remove = ov9282_remove, 1474 .driver = { 1475 .name = "ov9282", 1476 .pm = &ov9282_pm_ops, 1477 .of_match_table = ov9282_of_match, 1478 }, 1479 }; 1480 1481 module_i2c_driver(ov9282_driver); 1482 1483 MODULE_DESCRIPTION("OmniVision ov9282 sensor driver"); 1484 MODULE_LICENSE("GPL"); 1485