1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * OmniVision ov9282 Camera Sensor Driver 4 * 5 * Copyright (C) 2021 Intel Corporation 6 */ 7 #include <linux/unaligned.h> 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/i2c.h> 12 #include <linux/math.h> 13 #include <linux/module.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/regmap.h> 16 #include <linux/regulator/consumer.h> 17 18 #include <media/v4l2-cci.h> 19 #include <media/v4l2-ctrls.h> 20 #include <media/v4l2-event.h> 21 #include <media/v4l2-fwnode.h> 22 #include <media/v4l2-subdev.h> 23 24 /* Streaming Mode */ 25 #define OV9282_REG_MODE_SELECT CCI_REG8(0x0100) 26 #define OV9282_MODE_STANDBY 0x00 27 #define OV9282_MODE_STREAMING 0x01 28 29 #define OV9282_REG_PLL_CTRL_0D CCI_REG8(0x030d) 30 #define OV9282_PLL_CTRL_0D_RAW8 0x60 31 #define OV9282_PLL_CTRL_0D_RAW10 0x50 32 33 #define OV9282_REG_TIMING_HTS CCI_REG16(0x380c) 34 #define OV9282_TIMING_HTS_MAX 0x7fff 35 36 /* Lines per frame */ 37 #define OV9282_REG_LPFR CCI_REG16(0x380e) 38 39 /* Chip ID */ 40 #define OV9282_REG_ID CCI_REG16(0x300a) 41 #define OV9282_ID 0x9281 42 43 /* Output enable registers */ 44 #define OV9282_REG_OUTPUT_ENABLE4 CCI_REG8(0x3004) 45 #define OV9282_OUTPUT_ENABLE4_GPIO2 BIT(1) 46 #define OV9282_OUTPUT_ENABLE4_D9 BIT(0) 47 48 #define OV9282_REG_OUTPUT_ENABLE5 CCI_REG8(0x3005) 49 #define OV9282_OUTPUT_ENABLE5_D8 BIT(7) 50 #define OV9282_OUTPUT_ENABLE5_D7 BIT(6) 51 #define OV9282_OUTPUT_ENABLE5_D6 BIT(5) 52 #define OV9282_OUTPUT_ENABLE5_D5 BIT(4) 53 #define OV9282_OUTPUT_ENABLE5_D4 BIT(3) 54 #define OV9282_OUTPUT_ENABLE5_D3 BIT(2) 55 #define OV9282_OUTPUT_ENABLE5_D2 BIT(1) 56 #define OV9282_OUTPUT_ENABLE5_D1 BIT(0) 57 58 #define OV9282_REG_OUTPUT_ENABLE6 CCI_REG8(0x3006) 59 #define OV9282_OUTPUT_ENABLE6_D0 BIT(7) 60 #define OV9282_OUTPUT_ENABLE6_PCLK BIT(6) 61 #define OV9282_OUTPUT_ENABLE6_HREF BIT(5) 62 #define OV9282_OUTPUT_ENABLE6_STROBE BIT(3) 63 #define OV9282_OUTPUT_ENABLE6_ILPWM BIT(2) 64 #define OV9282_OUTPUT_ENABLE6_VSYNC BIT(1) 65 66 /* Exposure control */ 67 #define OV9282_REG_EXPOSURE CCI_REG24(0x3500) 68 #define OV9282_EXPOSURE_MIN 1 69 #define OV9282_EXPOSURE_OFFSET 25 70 #define OV9282_EXPOSURE_STEP 1 71 #define OV9282_EXPOSURE_DEFAULT 0x0282 72 73 /* AEC/AGC manual */ 74 #define OV9282_REG_AEC_MANUAL CCI_REG8(0x3503) 75 #define OV9282_DIGFRAC_GAIN_DELAY BIT(6) 76 #define OV9282_GAIN_CHANGE_DELAY BIT(5) 77 #define OV9282_GAIN_DELAY BIT(4) 78 #define OV9282_GAIN_PREC16_EN BIT(3) 79 #define OV9282_GAIN_MANUAL_AS_SENSGAIN BIT(2) 80 #define OV9282_AEC_MANUAL_DEFAULT 0x00 81 82 /* Analog gain control */ 83 #define OV9282_REG_AGAIN CCI_REG8(0x3509) 84 #define OV9282_AGAIN_MIN 0x10 85 #define OV9282_AGAIN_MAX 0xff 86 #define OV9282_AGAIN_STEP 1 87 #define OV9282_AGAIN_DEFAULT 0x10 88 89 /* Group hold register */ 90 #define OV9282_REG_HOLD CCI_REG8(0x3308) 91 92 #define OV9282_REG_ANA_CORE_2 CCI_REG8(0x3662) 93 #define OV9282_ANA_CORE2_RAW8 0x07 94 #define OV9282_ANA_CORE2_RAW10 0x05 95 96 #define OV9282_REG_TIMING_FORMAT_1 CCI_REG8(0x3820) 97 #define OV9282_REG_TIMING_FORMAT_2 CCI_REG8(0x3821) 98 #define OV9282_FLIP_BIT BIT(2) 99 100 #define OV9282_REG_MIPI_CTRL00 CCI_REG8(0x4800) 101 #define OV9282_GATED_CLOCK BIT(5) 102 103 /* Flash/Strobe control registers */ 104 #define OV9282_REG_STROBE_FRAME_SPAN CCI_REG32(0x3925) 105 #define OV9282_STROBE_FRAME_SPAN_DEFAULT 0x0000001a 106 107 /* Input clock rate */ 108 #define OV9282_INCLK_RATE 24000000 109 110 /* CSI2 HW configuration */ 111 #define OV9282_LINK_FREQ 400000000 112 #define OV9282_NUM_DATA_LANES 2 113 114 /* Pixel rate */ 115 #define OV9282_PIXEL_RATE_10BIT (OV9282_LINK_FREQ * 2 * \ 116 OV9282_NUM_DATA_LANES / 10) 117 #define OV9282_PIXEL_RATE_8BIT (OV9282_LINK_FREQ * 2 * \ 118 OV9282_NUM_DATA_LANES / 8) 119 120 /* 121 * OV9282 native and active pixel array size. 122 * 8 dummy rows/columns on each edge of a 1280x800 active array 123 */ 124 #define OV9282_NATIVE_WIDTH 1296U 125 #define OV9282_NATIVE_HEIGHT 816U 126 #define OV9282_PIXEL_ARRAY_LEFT 8U 127 #define OV9282_PIXEL_ARRAY_TOP 8U 128 #define OV9282_PIXEL_ARRAY_WIDTH 1280U 129 #define OV9282_PIXEL_ARRAY_HEIGHT 800U 130 131 #define OV9282_REG_MIN 0x00 132 #define OV9282_REG_MAX 0xfffff 133 134 #define OV9282_STROBE_SPAN_FACTOR 192 135 136 static const char * const ov9282_supply_names[] = { 137 "avdd", /* Analog power */ 138 "dovdd", /* Digital I/O power */ 139 "dvdd", /* Digital core power */ 140 }; 141 142 #define OV9282_NUM_SUPPLIES ARRAY_SIZE(ov9282_supply_names) 143 144 /** 145 * struct ov9282_reg_list - ov9282 sensor register list 146 * @num_of_regs: Number of registers in the list 147 * @regs: Pointer to register list 148 */ 149 struct ov9282_reg_list { 150 u32 num_of_regs; 151 const struct cci_reg_sequence *regs; 152 }; 153 154 /** 155 * struct ov9282_mode - ov9282 sensor mode structure 156 * @width: Frame width 157 * @height: Frame height 158 * @hblank_min: Minimum horizontal blanking in lines for non-continuous[0] and 159 * continuous[1] clock modes 160 * @vblank: Vertical blanking in lines 161 * @vblank_min: Minimum vertical blanking in lines 162 * @vblank_max: Maximum vertical blanking in lines 163 * @link_freq_idx: Link frequency index 164 * @crop: on-sensor cropping for this mode 165 * @reg_list: Register list for sensor mode 166 */ 167 struct ov9282_mode { 168 u32 width; 169 u32 height; 170 u32 hblank_min[2]; 171 u32 vblank; 172 u32 vblank_min; 173 u32 vblank_max; 174 u32 link_freq_idx; 175 struct v4l2_rect crop; 176 struct ov9282_reg_list reg_list; 177 }; 178 179 /** 180 * struct ov9282 - ov9282 sensor device structure 181 * @dev: Pointer to generic device 182 * @sd: V4L2 sub-device 183 * @regmap: Regmap for sensor register access 184 * @pad: Media pad. Only one pad supported 185 * @reset_gpio: Sensor reset gpio 186 * @inclk: Sensor input clock 187 * @supplies: Regulator supplies for the sensor 188 * @ctrl_handler: V4L2 control handler 189 * @link_freq_ctrl: Pointer to link frequency control 190 * @hblank_ctrl: Pointer to horizontal blanking control 191 * @vblank_ctrl: Pointer to vertical blanking control 192 * @exp_ctrl: Pointer to exposure control 193 * @again_ctrl: Pointer to analog gain control 194 * @pixel_rate: Pointer to pixel rate control 195 * @flash_duration: Pointer to flash duration control 196 * @vblank: Vertical blanking in lines 197 * @noncontinuous_clock: Selection of CSI2 noncontinuous clock mode 198 * @cur_mode: Pointer to current selected sensor mode 199 * @code: Mbus code currently selected 200 */ 201 struct ov9282 { 202 struct device *dev; 203 struct v4l2_subdev sd; 204 struct regmap *regmap; 205 struct media_pad pad; 206 struct gpio_desc *reset_gpio; 207 struct clk *inclk; 208 struct regulator_bulk_data supplies[OV9282_NUM_SUPPLIES]; 209 struct v4l2_ctrl_handler ctrl_handler; 210 struct v4l2_ctrl *link_freq_ctrl; 211 struct v4l2_ctrl *hblank_ctrl; 212 struct v4l2_ctrl *vblank_ctrl; 213 struct { 214 struct v4l2_ctrl *exp_ctrl; 215 struct v4l2_ctrl *again_ctrl; 216 }; 217 struct v4l2_ctrl *pixel_rate; 218 struct v4l2_ctrl *flash_duration; 219 u32 vblank; 220 bool noncontinuous_clock; 221 const struct ov9282_mode *cur_mode; 222 u32 code; 223 }; 224 225 static const s64 link_freq[] = { 226 OV9282_LINK_FREQ, 227 }; 228 229 /* 230 * Common registers 231 * 232 * Note: Do NOT include a software reset (0x0103, 0x01) in any of these 233 * register arrays as some settings are written as part of ov9282_power_on, 234 * and the reset will clear them. 235 */ 236 static const struct cci_reg_sequence common_regs[] = { 237 {CCI_REG8(0x0302), 0x32}, 238 {CCI_REG8(0x030e), 0x02}, 239 {CCI_REG8(0x3001), 0x00}, 240 {OV9282_REG_OUTPUT_ENABLE4, 0x00}, 241 {OV9282_REG_OUTPUT_ENABLE5, 0x00}, 242 {OV9282_REG_OUTPUT_ENABLE6, OV9282_OUTPUT_ENABLE6_ILPWM}, 243 {CCI_REG8(0x3011), 0x0a}, 244 {CCI_REG8(0x3013), 0x18}, 245 {CCI_REG8(0x301c), 0xf0}, 246 {CCI_REG8(0x3022), 0x01}, 247 {CCI_REG8(0x3030), 0x10}, 248 {CCI_REG8(0x3039), 0x32}, 249 {CCI_REG8(0x303a), 0x00}, 250 {OV9282_REG_AEC_MANUAL, OV9282_GAIN_PREC16_EN}, 251 {CCI_REG8(0x3505), 0x8c}, 252 {CCI_REG8(0x3507), 0x03}, 253 {CCI_REG8(0x3508), 0x00}, 254 {CCI_REG8(0x3610), 0x80}, 255 {CCI_REG8(0x3611), 0xa0}, 256 {CCI_REG8(0x3620), 0x6e}, 257 {CCI_REG8(0x3632), 0x56}, 258 {CCI_REG8(0x3633), 0x78}, 259 {CCI_REG8(0x3666), 0x00}, 260 {CCI_REG8(0x366f), 0x5a}, 261 {CCI_REG8(0x3680), 0x84}, 262 {CCI_REG8(0x3712), 0x80}, 263 {CCI_REG8(0x372d), 0x22}, 264 {CCI_REG8(0x3731), 0x80}, 265 {CCI_REG8(0x3732), 0x30}, 266 {CCI_REG8(0x377d), 0x22}, 267 {CCI_REG8(0x3788), 0x02}, 268 {CCI_REG8(0x3789), 0xa4}, 269 {CCI_REG8(0x378a), 0x00}, 270 {CCI_REG8(0x378b), 0x4a}, 271 {CCI_REG8(0x3799), 0x20}, 272 {CCI_REG8(0x3881), 0x42}, 273 {CCI_REG8(0x38a8), 0x02}, 274 {CCI_REG8(0x38a9), 0x80}, 275 {CCI_REG8(0x38b1), 0x00}, 276 {CCI_REG8(0x38c4), 0x00}, 277 {CCI_REG8(0x38c5), 0xc0}, 278 {CCI_REG8(0x38c6), 0x04}, 279 {CCI_REG8(0x38c7), 0x80}, 280 {CCI_REG8(0x3920), 0xff}, 281 {CCI_REG8(0x4010), 0x40}, 282 {CCI_REG8(0x4043), 0x40}, 283 {CCI_REG8(0x4307), 0x30}, 284 {CCI_REG8(0x4317), 0x00}, 285 {CCI_REG8(0x4501), 0x00}, 286 {CCI_REG8(0x450a), 0x08}, 287 {CCI_REG8(0x4601), 0x04}, 288 {CCI_REG8(0x470f), 0x00}, 289 {CCI_REG8(0x4f07), 0x00}, 290 {CCI_REG8(0x5000), 0x9f}, 291 {CCI_REG8(0x5001), 0x00}, 292 {CCI_REG8(0x5e00), 0x00}, 293 {CCI_REG8(0x5d00), 0x07}, 294 {CCI_REG8(0x5d01), 0x00}, 295 {CCI_REG8(0x0101), 0x01}, 296 {CCI_REG8(0x1000), 0x03}, 297 {CCI_REG8(0x5a08), 0x84}, 298 }; 299 300 #define MODE_1280_800 0 301 #define MODE_1280_720 1 302 #define MODE_640_400 2 303 304 #define DEFAULT_MODE MODE_1280_720 305 306 /* Sensor mode registers */ 307 static const struct cci_reg_sequence mode_1280x800_regs[] = { 308 {CCI_REG8(0x3778), 0x00}, 309 {CCI_REG8(0x3800), 0x00}, 310 {CCI_REG8(0x3801), 0x00}, 311 {CCI_REG8(0x3802), 0x00}, 312 {CCI_REG8(0x3803), 0x00}, 313 {CCI_REG8(0x3804), 0x05}, 314 {CCI_REG8(0x3805), 0x0f}, 315 {CCI_REG8(0x3806), 0x03}, 316 {CCI_REG8(0x3807), 0x2f}, 317 {CCI_REG8(0x3808), 0x05}, 318 {CCI_REG8(0x3809), 0x00}, 319 {CCI_REG8(0x380a), 0x03}, 320 {CCI_REG8(0x380b), 0x20}, 321 {CCI_REG8(0x3810), 0x00}, 322 {CCI_REG8(0x3811), 0x08}, 323 {CCI_REG8(0x3812), 0x00}, 324 {CCI_REG8(0x3813), 0x08}, 325 {CCI_REG8(0x3814), 0x11}, 326 {CCI_REG8(0x3815), 0x11}, 327 {OV9282_REG_TIMING_FORMAT_1, 0x40}, 328 {OV9282_REG_TIMING_FORMAT_2, 0x00}, 329 {CCI_REG8(0x4003), 0x40}, 330 {CCI_REG8(0x4008), 0x04}, 331 {CCI_REG8(0x4009), 0x0b}, 332 {CCI_REG8(0x400c), 0x00}, 333 {CCI_REG8(0x400d), 0x07}, 334 {CCI_REG8(0x4507), 0x00}, 335 {CCI_REG8(0x4509), 0x00}, 336 }; 337 338 static const struct cci_reg_sequence mode_1280x720_regs[] = { 339 {CCI_REG8(0x3778), 0x00}, 340 {CCI_REG8(0x3800), 0x00}, 341 {CCI_REG8(0x3801), 0x00}, 342 {CCI_REG8(0x3802), 0x00}, 343 {CCI_REG8(0x3803), 0x00}, 344 {CCI_REG8(0x3804), 0x05}, 345 {CCI_REG8(0x3805), 0x0f}, 346 {CCI_REG8(0x3806), 0x02}, 347 {CCI_REG8(0x3807), 0xdf}, 348 {CCI_REG8(0x3808), 0x05}, 349 {CCI_REG8(0x3809), 0x00}, 350 {CCI_REG8(0x380a), 0x02}, 351 {CCI_REG8(0x380b), 0xd0}, 352 {CCI_REG8(0x3810), 0x00}, 353 {CCI_REG8(0x3811), 0x08}, 354 {CCI_REG8(0x3812), 0x00}, 355 {CCI_REG8(0x3813), 0x08}, 356 {CCI_REG8(0x3814), 0x11}, 357 {CCI_REG8(0x3815), 0x11}, 358 {OV9282_REG_TIMING_FORMAT_1, 0x3c}, 359 {OV9282_REG_TIMING_FORMAT_2, 0x84}, 360 {CCI_REG8(0x4003), 0x40}, 361 {CCI_REG8(0x4008), 0x02}, 362 {CCI_REG8(0x4009), 0x05}, 363 {CCI_REG8(0x400c), 0x00}, 364 {CCI_REG8(0x400d), 0x03}, 365 {CCI_REG8(0x4507), 0x00}, 366 {CCI_REG8(0x4509), 0x80}, 367 }; 368 369 static const struct cci_reg_sequence mode_640x400_regs[] = { 370 {CCI_REG8(0x3778), 0x10}, 371 {CCI_REG8(0x3800), 0x00}, 372 {CCI_REG8(0x3801), 0x00}, 373 {CCI_REG8(0x3802), 0x00}, 374 {CCI_REG8(0x3803), 0x00}, 375 {CCI_REG8(0x3804), 0x05}, 376 {CCI_REG8(0x3805), 0x0f}, 377 {CCI_REG8(0x3806), 0x03}, 378 {CCI_REG8(0x3807), 0x2f}, 379 {CCI_REG8(0x3808), 0x02}, 380 {CCI_REG8(0x3809), 0x80}, 381 {CCI_REG8(0x380a), 0x01}, 382 {CCI_REG8(0x380b), 0x90}, 383 {CCI_REG8(0x3810), 0x00}, 384 {CCI_REG8(0x3811), 0x04}, 385 {CCI_REG8(0x3812), 0x00}, 386 {CCI_REG8(0x3813), 0x04}, 387 {CCI_REG8(0x3814), 0x31}, 388 {CCI_REG8(0x3815), 0x22}, 389 {OV9282_REG_TIMING_FORMAT_1, 0x60}, 390 {OV9282_REG_TIMING_FORMAT_2, 0x01}, 391 {CCI_REG8(0x4008), 0x02}, 392 {CCI_REG8(0x4009), 0x05}, 393 {CCI_REG8(0x400c), 0x00}, 394 {CCI_REG8(0x400d), 0x03}, 395 {CCI_REG8(0x4507), 0x03}, 396 {CCI_REG8(0x4509), 0x80}, 397 }; 398 399 /* Supported sensor mode configurations */ 400 static const struct ov9282_mode supported_modes[] = { 401 [MODE_1280_800] = { 402 .width = 1280, 403 .height = 800, 404 .hblank_min = { 250, 176 }, 405 .vblank = 1022, 406 .vblank_min = 110, 407 .vblank_max = 51540, 408 .link_freq_idx = 0, 409 .crop = { 410 .left = OV9282_PIXEL_ARRAY_LEFT, 411 .top = OV9282_PIXEL_ARRAY_TOP, 412 .width = 1280, 413 .height = 800 414 }, 415 .reg_list = { 416 .num_of_regs = ARRAY_SIZE(mode_1280x800_regs), 417 .regs = mode_1280x800_regs, 418 }, 419 }, 420 [MODE_1280_720] = { 421 .width = 1280, 422 .height = 720, 423 .hblank_min = { 250, 176 }, 424 .vblank = 1022, 425 .vblank_min = 41, 426 .vblank_max = 51540, 427 .link_freq_idx = 0, 428 .crop = { 429 /* 430 * Note that this mode takes the top 720 lines from the 431 * 800 of the sensor. It does not take a middle crop. 432 */ 433 .left = OV9282_PIXEL_ARRAY_LEFT, 434 .top = OV9282_PIXEL_ARRAY_TOP, 435 .width = 1280, 436 .height = 720 437 }, 438 .reg_list = { 439 .num_of_regs = ARRAY_SIZE(mode_1280x720_regs), 440 .regs = mode_1280x720_regs, 441 }, 442 }, 443 [MODE_640_400] = { 444 .width = 640, 445 .height = 400, 446 .hblank_min = { 890, 816 }, 447 .vblank = 1022, 448 .vblank_min = 22, 449 .vblank_max = 51540, 450 .link_freq_idx = 0, 451 .crop = { 452 .left = OV9282_PIXEL_ARRAY_LEFT, 453 .top = OV9282_PIXEL_ARRAY_TOP, 454 .width = 1280, 455 .height = 800 456 }, 457 .reg_list = { 458 .num_of_regs = ARRAY_SIZE(mode_640x400_regs), 459 .regs = mode_640x400_regs, 460 }, 461 }, 462 }; 463 464 /** 465 * to_ov9282() - ov9282 V4L2 sub-device to ov9282 device. 466 * @subdev: pointer to ov9282 V4L2 sub-device 467 * 468 * Return: pointer to ov9282 device 469 */ 470 static inline struct ov9282 *to_ov9282(struct v4l2_subdev *subdev) 471 { 472 return container_of(subdev, struct ov9282, sd); 473 } 474 475 /** 476 * ov9282_update_controls() - Update control ranges based on streaming mode 477 * @ov9282: pointer to ov9282 device 478 * @mode: pointer to ov9282_mode sensor mode 479 * @fmt: pointer to the requested mode 480 * 481 * Return: 0 if successful, error code otherwise. 482 */ 483 static int ov9282_update_controls(struct ov9282 *ov9282, 484 const struct ov9282_mode *mode, 485 const struct v4l2_subdev_format *fmt) 486 { 487 u32 hblank_min; 488 s64 pixel_rate; 489 int ret; 490 491 ret = __v4l2_ctrl_s_ctrl(ov9282->link_freq_ctrl, mode->link_freq_idx); 492 if (ret) 493 return ret; 494 495 pixel_rate = (fmt->format.code == MEDIA_BUS_FMT_Y10_1X10) ? 496 OV9282_PIXEL_RATE_10BIT : OV9282_PIXEL_RATE_8BIT; 497 ret = __v4l2_ctrl_modify_range(ov9282->pixel_rate, pixel_rate, 498 pixel_rate, 1, pixel_rate); 499 if (ret) 500 return ret; 501 502 hblank_min = mode->hblank_min[ov9282->noncontinuous_clock ? 0 : 1]; 503 ret = __v4l2_ctrl_modify_range(ov9282->hblank_ctrl, hblank_min, 504 OV9282_TIMING_HTS_MAX - mode->width, 1, 505 hblank_min); 506 if (ret) 507 return ret; 508 509 return __v4l2_ctrl_modify_range(ov9282->vblank_ctrl, mode->vblank_min, 510 mode->vblank_max, 1, mode->vblank); 511 } 512 513 static u32 ov9282_exposure_to_us(struct ov9282 *ov9282, u32 exposure) 514 { 515 /* calculate exposure time in µs */ 516 u32 frame_width = ov9282->cur_mode->width + ov9282->hblank_ctrl->val; 517 u32 trow_us = frame_width / (ov9282->pixel_rate->val / 1000000UL); 518 519 return exposure * trow_us; 520 } 521 522 /** 523 * ov9282_update_exp_gain() - Set updated exposure and gain 524 * @ov9282: pointer to ov9282 device 525 * @exposure: updated exposure value 526 * @gain: updated analog gain value 527 * 528 * Return: 0 if successful, error code otherwise. 529 */ 530 static int ov9282_update_exp_gain(struct ov9282 *ov9282, u32 exposure, u32 gain) 531 { 532 u32 exposure_us = ov9282_exposure_to_us(ov9282, exposure); 533 int ret, ret_hold; 534 535 dev_dbg(ov9282->dev, "Set exp %u (~%u us), analog gain %u", 536 exposure, exposure_us, gain); 537 538 ret = cci_write(ov9282->regmap, OV9282_REG_HOLD, 0x01, NULL); 539 if (ret) 540 return ret; 541 542 ret = cci_write(ov9282->regmap, OV9282_REG_EXPOSURE, exposure << 4, NULL); 543 if (ret) 544 goto error_release_group_hold; 545 546 ret = cci_write(ov9282->regmap, OV9282_REG_AGAIN, gain, NULL); 547 if (ret) 548 goto error_release_group_hold; 549 550 ret = __v4l2_ctrl_modify_range(ov9282->flash_duration, 551 0, exposure_us, 1, 552 OV9282_STROBE_FRAME_SPAN_DEFAULT); 553 554 error_release_group_hold: 555 ret_hold = cci_write(ov9282->regmap, OV9282_REG_HOLD, 0, NULL); 556 557 return ret ? ret : ret_hold; 558 } 559 560 static u32 ov9282_us_to_flash_duration(struct ov9282 *ov9282, u32 value) 561 { 562 /* 563 * Calculate "strobe_frame_span" increments from a given value (µs). 564 * This is quite tricky as "The step width of shift and span is 565 * programmable under system clock domain.", but it's not documented 566 * how to program this step width (at least in the datasheet available 567 * to the author at time of writing). 568 * The formula below is interpolated from different modes/framerates 569 * and should work quite well for most settings. 570 */ 571 u32 frame_width = ov9282->cur_mode->width + ov9282->hblank_ctrl->val; 572 573 return value * OV9282_STROBE_SPAN_FACTOR / frame_width; 574 } 575 576 static u32 ov9282_flash_duration_to_us(struct ov9282 *ov9282, u32 value) 577 { 578 /* 579 * Calculate back to microseconds from "strobe_frame_span" increments. 580 * As the calculation in ov9282_us_to_flash_duration uses an integer 581 * divison round up here. 582 */ 583 u32 frame_width = ov9282->cur_mode->width + ov9282->hblank_ctrl->val; 584 585 return DIV_ROUND_UP(value * frame_width, OV9282_STROBE_SPAN_FACTOR); 586 } 587 588 static int ov9282_set_ctrl(struct v4l2_ctrl *ctrl) 589 { 590 struct ov9282 *ov9282 = 591 container_of(ctrl->handler, struct ov9282, ctrl_handler); 592 u32 analog_gain; 593 u32 exposure; 594 u32 lpfr; 595 int ret; 596 597 switch (ctrl->id) { 598 case V4L2_CID_VBLANK: 599 ov9282->vblank = ov9282->vblank_ctrl->val; 600 601 dev_dbg(ov9282->dev, "Received vblank %u, new lpfr %u", 602 ov9282->vblank, 603 ov9282->vblank + ov9282->cur_mode->height); 604 605 ret = __v4l2_ctrl_modify_range(ov9282->exp_ctrl, 606 OV9282_EXPOSURE_MIN, 607 ov9282->vblank + 608 ov9282->cur_mode->height - 609 OV9282_EXPOSURE_OFFSET, 610 1, OV9282_EXPOSURE_DEFAULT); 611 break; 612 } 613 614 /* Set controls only if sensor is in power on state */ 615 if (!pm_runtime_get_if_in_use(ov9282->dev)) 616 return 0; 617 618 switch (ctrl->id) { 619 case V4L2_CID_EXPOSURE: 620 exposure = ctrl->val; 621 analog_gain = ov9282->again_ctrl->val; 622 623 dev_dbg(ov9282->dev, "Received exp %u, analog gain %u", 624 exposure, analog_gain); 625 626 ret = ov9282_update_exp_gain(ov9282, exposure, analog_gain); 627 break; 628 case V4L2_CID_VBLANK: 629 lpfr = ov9282->vblank + ov9282->cur_mode->height; 630 ret = cci_write(ov9282->regmap, OV9282_REG_LPFR, lpfr, NULL); 631 break; 632 case V4L2_CID_HFLIP: 633 ret = cci_update_bits(ov9282->regmap, OV9282_REG_TIMING_FORMAT_2, 634 OV9282_FLIP_BIT, ctrl->val ? OV9282_FLIP_BIT : 0, NULL); 635 break; 636 case V4L2_CID_VFLIP: 637 ret = cci_update_bits(ov9282->regmap, OV9282_REG_TIMING_FORMAT_1, 638 OV9282_FLIP_BIT, ctrl->val ? OV9282_FLIP_BIT : 0, NULL); 639 break; 640 case V4L2_CID_HBLANK: 641 ret = cci_write(ov9282->regmap, OV9282_REG_TIMING_HTS, 642 (ctrl->val + ov9282->cur_mode->width) >> 1, NULL); 643 break; 644 case V4L2_CID_FLASH_STROBE_OE: 645 ret = cci_update_bits(ov9282->regmap, OV9282_REG_OUTPUT_ENABLE6, 646 OV9282_OUTPUT_ENABLE6_STROBE, 647 ctrl->val ? OV9282_OUTPUT_ENABLE6_STROBE : 0, NULL); 648 break; 649 case V4L2_CID_FLASH_DURATION: 650 ret = cci_write(ov9282->regmap, OV9282_REG_STROBE_FRAME_SPAN, 651 ov9282_us_to_flash_duration(ov9282, ctrl->val), NULL); 652 break; 653 default: 654 dev_err(ov9282->dev, "Invalid control %d", ctrl->id); 655 ret = -EINVAL; 656 } 657 658 pm_runtime_put(ov9282->dev); 659 660 return ret; 661 } 662 663 static int ov9282_try_ctrl(struct v4l2_ctrl *ctrl) 664 { 665 struct ov9282 *ov9282 = 666 container_of_const(ctrl->handler, struct ov9282, ctrl_handler); 667 668 if (ctrl->id == V4L2_CID_FLASH_DURATION) { 669 u32 us = ctrl->val; 670 u32 fd = ov9282_us_to_flash_duration(ov9282, us); 671 672 /* get nearest strobe_duration value */ 673 u32 us0 = ov9282_flash_duration_to_us(ov9282, fd); 674 u32 us1 = ov9282_flash_duration_to_us(ov9282, fd + 1); 675 676 if (abs(us1 - us) < abs(us - us0)) 677 ctrl->val = us1; 678 else 679 ctrl->val = us0; 680 681 if (us != ctrl->val) 682 dev_dbg(ov9282->dev, "using next valid strobe_duration %u instead of %u\n", 683 ctrl->val, us); 684 } 685 686 return 0; 687 } 688 689 /* V4l2 subdevice control ops*/ 690 static const struct v4l2_ctrl_ops ov9282_ctrl_ops = { 691 .s_ctrl = ov9282_set_ctrl, 692 .try_ctrl = ov9282_try_ctrl, 693 }; 694 695 static int ov9282_enum_mbus_code(struct v4l2_subdev *sd, 696 struct v4l2_subdev_state *sd_state, 697 struct v4l2_subdev_mbus_code_enum *code) 698 { 699 switch (code->index) { 700 case 0: 701 code->code = MEDIA_BUS_FMT_Y10_1X10; 702 break; 703 case 1: 704 code->code = MEDIA_BUS_FMT_Y8_1X8; 705 break; 706 default: 707 return -EINVAL; 708 } 709 710 return 0; 711 } 712 713 /** 714 * ov9282_enum_frame_size() - Enumerate V4L2 sub-device frame sizes 715 * @sd: pointer to ov9282 V4L2 sub-device structure 716 * @sd_state: V4L2 sub-device configuration 717 * @fsize: V4L2 sub-device size enumeration need to be filled 718 * 719 * Return: 0 if successful, error code otherwise. 720 */ 721 static int ov9282_enum_frame_size(struct v4l2_subdev *sd, 722 struct v4l2_subdev_state *sd_state, 723 struct v4l2_subdev_frame_size_enum *fsize) 724 { 725 if (fsize->index >= ARRAY_SIZE(supported_modes)) 726 return -EINVAL; 727 728 if (fsize->code != MEDIA_BUS_FMT_Y10_1X10 && 729 fsize->code != MEDIA_BUS_FMT_Y8_1X8) 730 return -EINVAL; 731 732 fsize->min_width = supported_modes[fsize->index].width; 733 fsize->max_width = fsize->min_width; 734 fsize->min_height = supported_modes[fsize->index].height; 735 fsize->max_height = fsize->min_height; 736 737 return 0; 738 } 739 740 /** 741 * ov9282_fill_pad_format() - Fill subdevice pad format 742 * from selected sensor mode 743 * @ov9282: pointer to ov9282 device 744 * @mode: pointer to ov9282_mode sensor mode 745 * @code: mbus code to be stored 746 * @fmt: V4L2 sub-device format need to be filled 747 */ 748 static void ov9282_fill_pad_format(struct ov9282 *ov9282, 749 const struct ov9282_mode *mode, 750 u32 code, 751 struct v4l2_subdev_format *fmt) 752 { 753 fmt->format.width = mode->width; 754 fmt->format.height = mode->height; 755 fmt->format.code = code; 756 fmt->format.field = V4L2_FIELD_NONE; 757 fmt->format.colorspace = V4L2_COLORSPACE_RAW; 758 fmt->format.ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; 759 fmt->format.quantization = V4L2_QUANTIZATION_DEFAULT; 760 fmt->format.xfer_func = V4L2_XFER_FUNC_NONE; 761 } 762 763 static int ov9282_get_pad_format(struct v4l2_subdev *sd, 764 struct v4l2_subdev_state *sd_state, 765 struct v4l2_subdev_format *fmt) 766 { 767 struct ov9282 *ov9282 = to_ov9282(sd); 768 769 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { 770 struct v4l2_mbus_framefmt *framefmt; 771 772 framefmt = v4l2_subdev_state_get_format(sd_state, fmt->pad); 773 fmt->format = *framefmt; 774 } else { 775 ov9282_fill_pad_format(ov9282, ov9282->cur_mode, ov9282->code, 776 fmt); 777 } 778 779 return 0; 780 } 781 782 static int ov9282_set_pad_format(struct v4l2_subdev *sd, 783 struct v4l2_subdev_state *sd_state, 784 struct v4l2_subdev_format *fmt) 785 { 786 struct ov9282 *ov9282 = to_ov9282(sd); 787 const struct ov9282_mode *mode; 788 u32 code; 789 int ret = 0; 790 791 mode = v4l2_find_nearest_size(supported_modes, 792 ARRAY_SIZE(supported_modes), 793 width, height, 794 fmt->format.width, 795 fmt->format.height); 796 if (fmt->format.code == MEDIA_BUS_FMT_Y8_1X8) 797 code = MEDIA_BUS_FMT_Y8_1X8; 798 else 799 code = MEDIA_BUS_FMT_Y10_1X10; 800 801 ov9282_fill_pad_format(ov9282, mode, code, fmt); 802 803 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { 804 struct v4l2_mbus_framefmt *framefmt; 805 806 framefmt = v4l2_subdev_state_get_format(sd_state, fmt->pad); 807 *framefmt = fmt->format; 808 } else { 809 ret = ov9282_update_controls(ov9282, mode, fmt); 810 if (!ret) { 811 ov9282->cur_mode = mode; 812 ov9282->code = code; 813 } 814 } 815 816 return ret; 817 } 818 819 static int ov9282_init_state(struct v4l2_subdev *sd, 820 struct v4l2_subdev_state *sd_state) 821 { 822 struct ov9282 *ov9282 = to_ov9282(sd); 823 struct v4l2_subdev_format fmt = { 0 }; 824 825 fmt.which = sd_state ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE; 826 ov9282_fill_pad_format(ov9282, &supported_modes[DEFAULT_MODE], 827 ov9282->code, &fmt); 828 829 return ov9282_set_pad_format(sd, sd_state, &fmt); 830 } 831 832 static const struct v4l2_rect * 833 __ov9282_get_pad_crop(struct ov9282 *ov9282, 834 struct v4l2_subdev_state *sd_state, 835 unsigned int pad, enum v4l2_subdev_format_whence which) 836 { 837 switch (which) { 838 case V4L2_SUBDEV_FORMAT_TRY: 839 return v4l2_subdev_state_get_crop(sd_state, pad); 840 case V4L2_SUBDEV_FORMAT_ACTIVE: 841 return &ov9282->cur_mode->crop; 842 } 843 844 return NULL; 845 } 846 847 static int ov9282_get_selection(struct v4l2_subdev *sd, 848 struct v4l2_subdev_state *sd_state, 849 struct v4l2_subdev_selection *sel) 850 { 851 switch (sel->target) { 852 case V4L2_SEL_TGT_CROP: { 853 struct ov9282 *ov9282 = to_ov9282(sd); 854 855 sel->r = *__ov9282_get_pad_crop(ov9282, sd_state, sel->pad, 856 sel->which); 857 858 return 0; 859 } 860 861 case V4L2_SEL_TGT_NATIVE_SIZE: 862 sel->r.top = 0; 863 sel->r.left = 0; 864 sel->r.width = OV9282_NATIVE_WIDTH; 865 sel->r.height = OV9282_NATIVE_HEIGHT; 866 867 return 0; 868 869 case V4L2_SEL_TGT_CROP_DEFAULT: 870 case V4L2_SEL_TGT_CROP_BOUNDS: 871 sel->r.top = OV9282_PIXEL_ARRAY_TOP; 872 sel->r.left = OV9282_PIXEL_ARRAY_LEFT; 873 sel->r.width = OV9282_PIXEL_ARRAY_WIDTH; 874 sel->r.height = OV9282_PIXEL_ARRAY_HEIGHT; 875 876 return 0; 877 } 878 879 return -EINVAL; 880 } 881 882 static int ov9282_enable_streams(struct v4l2_subdev *sd, 883 struct v4l2_subdev_state *state, u32 pad, 884 u64 streams_mask) 885 { 886 const struct cci_reg_sequence bitdepth_regs[2][2] = { 887 { 888 {OV9282_REG_PLL_CTRL_0D, OV9282_PLL_CTRL_0D_RAW10}, 889 {OV9282_REG_ANA_CORE_2, OV9282_ANA_CORE2_RAW10}, 890 }, { 891 {OV9282_REG_PLL_CTRL_0D, OV9282_PLL_CTRL_0D_RAW8}, 892 {OV9282_REG_ANA_CORE_2, OV9282_ANA_CORE2_RAW8}, 893 } 894 }; 895 struct ov9282 *ov9282 = to_ov9282(sd); 896 const struct ov9282_reg_list *reg_list; 897 int bitdepth_index; 898 int ret; 899 900 ret = pm_runtime_resume_and_get(ov9282->dev); 901 if (ret) 902 return ret; 903 904 /* Write common registers */ 905 ret = cci_multi_reg_write(ov9282->regmap, common_regs, 906 ARRAY_SIZE(common_regs), NULL); 907 if (ret) { 908 dev_err(ov9282->dev, "fail to write common registers"); 909 goto err_pm_put; 910 } 911 912 bitdepth_index = ov9282->code == MEDIA_BUS_FMT_Y10_1X10 ? 0 : 1; 913 ret = cci_multi_reg_write(ov9282->regmap, 914 bitdepth_regs[bitdepth_index], 2, NULL); 915 if (ret) { 916 dev_err(ov9282->dev, "fail to write bitdepth regs"); 917 goto err_pm_put; 918 } 919 920 /* Write sensor mode registers */ 921 reg_list = &ov9282->cur_mode->reg_list; 922 ret = cci_multi_reg_write(ov9282->regmap, reg_list->regs, 923 reg_list->num_of_regs, NULL); 924 if (ret) { 925 dev_err(ov9282->dev, "fail to write initial registers"); 926 goto err_pm_put; 927 } 928 929 /* Setup handler will write actual exposure and gain */ 930 ret = __v4l2_ctrl_handler_setup(ov9282->sd.ctrl_handler); 931 if (ret) { 932 dev_err(ov9282->dev, "fail to setup handler"); 933 goto err_pm_put; 934 } 935 936 /* Start streaming */ 937 ret = cci_write(ov9282->regmap, OV9282_REG_MODE_SELECT, 938 OV9282_MODE_STREAMING, NULL); 939 if (ret) { 940 dev_err(ov9282->dev, "fail to start streaming"); 941 goto err_pm_put; 942 } 943 944 return 0; 945 946 err_pm_put: 947 pm_runtime_put(ov9282->dev); 948 949 return ret; 950 } 951 952 static int ov9282_disable_streams(struct v4l2_subdev *sd, 953 struct v4l2_subdev_state *state, u32 pad, 954 u64 streams_mask) 955 { 956 struct ov9282 *ov9282 = to_ov9282(sd); 957 int ret; 958 959 ret = cci_write(ov9282->regmap, OV9282_REG_MODE_SELECT, 960 OV9282_MODE_STANDBY, NULL); 961 962 pm_runtime_put(ov9282->dev); 963 964 return ret; 965 } 966 967 /** 968 * ov9282_detect() - Detect ov9282 sensor 969 * @ov9282: pointer to ov9282 device 970 * 971 * Return: 0 if successful, -EIO if sensor id does not match 972 */ 973 static int ov9282_detect(struct ov9282 *ov9282) 974 { 975 int ret; 976 u64 val; 977 978 ret = cci_read(ov9282->regmap, OV9282_REG_ID, &val, NULL); 979 if (ret) 980 return ret; 981 982 if (val != OV9282_ID) { 983 dev_err(ov9282->dev, "chip id mismatch: %x!=%llx", 984 OV9282_ID, val); 985 return -ENXIO; 986 } 987 988 return 0; 989 } 990 991 static int ov9282_configure_regulators(struct ov9282 *ov9282) 992 { 993 unsigned int i; 994 995 for (i = 0; i < OV9282_NUM_SUPPLIES; i++) 996 ov9282->supplies[i].supply = ov9282_supply_names[i]; 997 998 return devm_regulator_bulk_get(ov9282->dev, 999 OV9282_NUM_SUPPLIES, 1000 ov9282->supplies); 1001 } 1002 1003 /** 1004 * ov9282_parse_hw_config() - Parse HW configuration and check if supported 1005 * @ov9282: pointer to ov9282 device 1006 * 1007 * Return: 0 if successful, error code otherwise. 1008 */ 1009 static int ov9282_parse_hw_config(struct ov9282 *ov9282) 1010 { 1011 struct fwnode_handle *fwnode = dev_fwnode(ov9282->dev); 1012 struct v4l2_fwnode_endpoint bus_cfg = { 1013 .bus_type = V4L2_MBUS_CSI2_DPHY 1014 }; 1015 struct fwnode_handle *ep; 1016 unsigned long rate; 1017 unsigned int i; 1018 int ret; 1019 1020 if (!fwnode) 1021 return -ENXIO; 1022 1023 /* Request optional reset pin */ 1024 ov9282->reset_gpio = devm_gpiod_get_optional(ov9282->dev, "reset", 1025 GPIOD_OUT_LOW); 1026 if (IS_ERR(ov9282->reset_gpio)) { 1027 dev_err(ov9282->dev, "failed to get reset gpio %pe", 1028 ov9282->reset_gpio); 1029 return PTR_ERR(ov9282->reset_gpio); 1030 } 1031 1032 /* Get sensor input clock */ 1033 ov9282->inclk = devm_v4l2_sensor_clk_get(ov9282->dev, NULL); 1034 if (IS_ERR(ov9282->inclk)) 1035 return dev_err_probe(ov9282->dev, PTR_ERR(ov9282->inclk), 1036 "could not get inclk\n"); 1037 1038 ret = ov9282_configure_regulators(ov9282); 1039 if (ret) 1040 return dev_err_probe(ov9282->dev, ret, 1041 "Failed to get power regulators\n"); 1042 1043 rate = clk_get_rate(ov9282->inclk); 1044 if (rate != OV9282_INCLK_RATE) { 1045 dev_err(ov9282->dev, "inclk frequency mismatch"); 1046 return -EINVAL; 1047 } 1048 1049 ep = fwnode_graph_get_next_endpoint(fwnode, NULL); 1050 if (!ep) 1051 return -ENXIO; 1052 1053 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg); 1054 fwnode_handle_put(ep); 1055 if (ret) 1056 return ret; 1057 1058 ov9282->noncontinuous_clock = 1059 bus_cfg.bus.mipi_csi2.flags & V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK; 1060 1061 if (bus_cfg.bus.mipi_csi2.num_data_lanes != OV9282_NUM_DATA_LANES) { 1062 dev_err(ov9282->dev, 1063 "number of CSI2 data lanes %d is not supported", 1064 bus_cfg.bus.mipi_csi2.num_data_lanes); 1065 ret = -EINVAL; 1066 goto done_endpoint_free; 1067 } 1068 1069 if (!bus_cfg.nr_of_link_frequencies) { 1070 dev_err(ov9282->dev, "no link frequencies defined"); 1071 ret = -EINVAL; 1072 goto done_endpoint_free; 1073 } 1074 1075 for (i = 0; i < bus_cfg.nr_of_link_frequencies; i++) 1076 if (bus_cfg.link_frequencies[i] == OV9282_LINK_FREQ) 1077 goto done_endpoint_free; 1078 1079 ret = -EINVAL; 1080 1081 done_endpoint_free: 1082 v4l2_fwnode_endpoint_free(&bus_cfg); 1083 1084 return ret; 1085 } 1086 1087 /* V4l2 subdevice ops */ 1088 static const struct v4l2_subdev_core_ops ov9282_core_ops = { 1089 .subscribe_event = v4l2_ctrl_subdev_subscribe_event, 1090 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 1091 }; 1092 1093 static const struct v4l2_subdev_video_ops ov9282_video_ops = { 1094 .s_stream = v4l2_subdev_s_stream_helper, 1095 }; 1096 1097 static const struct v4l2_subdev_pad_ops ov9282_pad_ops = { 1098 .enum_mbus_code = ov9282_enum_mbus_code, 1099 .enum_frame_size = ov9282_enum_frame_size, 1100 .get_fmt = ov9282_get_pad_format, 1101 .set_fmt = ov9282_set_pad_format, 1102 .get_selection = ov9282_get_selection, 1103 .enable_streams = ov9282_enable_streams, 1104 .disable_streams = ov9282_disable_streams, 1105 }; 1106 1107 static const struct v4l2_subdev_ops ov9282_subdev_ops = { 1108 .core = &ov9282_core_ops, 1109 .video = &ov9282_video_ops, 1110 .pad = &ov9282_pad_ops, 1111 }; 1112 1113 static const struct v4l2_subdev_internal_ops ov9282_internal_ops = { 1114 .init_state = ov9282_init_state, 1115 }; 1116 1117 static int ov9282_power_on(struct device *dev) 1118 { 1119 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1120 struct ov9282 *ov9282 = to_ov9282(sd); 1121 int ret; 1122 1123 ret = regulator_bulk_enable(OV9282_NUM_SUPPLIES, ov9282->supplies); 1124 if (ret < 0) { 1125 dev_err(dev, "Failed to enable regulators\n"); 1126 return ret; 1127 } 1128 1129 usleep_range(400, 600); 1130 1131 gpiod_set_value_cansleep(ov9282->reset_gpio, 1); 1132 1133 ret = clk_prepare_enable(ov9282->inclk); 1134 if (ret) { 1135 dev_err(ov9282->dev, "fail to enable inclk"); 1136 goto error_reset; 1137 } 1138 1139 usleep_range(400, 600); 1140 1141 ret = cci_write(ov9282->regmap, OV9282_REG_MIPI_CTRL00, 1142 ov9282->noncontinuous_clock ? OV9282_GATED_CLOCK : 0, NULL); 1143 if (ret) { 1144 dev_err(ov9282->dev, "fail to write MIPI_CTRL00"); 1145 goto error_clk; 1146 } 1147 1148 return 0; 1149 1150 error_clk: 1151 clk_disable_unprepare(ov9282->inclk); 1152 error_reset: 1153 gpiod_set_value_cansleep(ov9282->reset_gpio, 0); 1154 1155 regulator_bulk_disable(OV9282_NUM_SUPPLIES, ov9282->supplies); 1156 1157 return ret; 1158 } 1159 1160 static int ov9282_power_off(struct device *dev) 1161 { 1162 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1163 struct ov9282 *ov9282 = to_ov9282(sd); 1164 1165 gpiod_set_value_cansleep(ov9282->reset_gpio, 0); 1166 1167 clk_disable_unprepare(ov9282->inclk); 1168 1169 regulator_bulk_disable(OV9282_NUM_SUPPLIES, ov9282->supplies); 1170 1171 return 0; 1172 } 1173 1174 /** 1175 * ov9282_init_controls() - Initialize sensor subdevice controls 1176 * @ov9282: pointer to ov9282 device 1177 * 1178 * Return: 0 if successful, error code otherwise. 1179 */ 1180 static int ov9282_init_controls(struct ov9282 *ov9282) 1181 { 1182 struct v4l2_ctrl_handler *ctrl_hdlr = &ov9282->ctrl_handler; 1183 const struct ov9282_mode *mode = ov9282->cur_mode; 1184 struct v4l2_fwnode_device_properties props; 1185 u32 hblank_min; 1186 u32 exposure_us; 1187 u32 lpfr; 1188 int ret; 1189 1190 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 12); 1191 if (ret) 1192 return ret; 1193 1194 /* Initialize exposure and gain */ 1195 lpfr = mode->vblank + mode->height; 1196 ov9282->exp_ctrl = v4l2_ctrl_new_std(ctrl_hdlr, 1197 &ov9282_ctrl_ops, 1198 V4L2_CID_EXPOSURE, 1199 OV9282_EXPOSURE_MIN, 1200 lpfr - OV9282_EXPOSURE_OFFSET, 1201 OV9282_EXPOSURE_STEP, 1202 OV9282_EXPOSURE_DEFAULT); 1203 1204 ov9282->again_ctrl = v4l2_ctrl_new_std(ctrl_hdlr, 1205 &ov9282_ctrl_ops, 1206 V4L2_CID_ANALOGUE_GAIN, 1207 OV9282_AGAIN_MIN, 1208 OV9282_AGAIN_MAX, 1209 OV9282_AGAIN_STEP, 1210 OV9282_AGAIN_DEFAULT); 1211 1212 v4l2_ctrl_cluster(2, &ov9282->exp_ctrl); 1213 1214 ov9282->vblank_ctrl = v4l2_ctrl_new_std(ctrl_hdlr, 1215 &ov9282_ctrl_ops, 1216 V4L2_CID_VBLANK, 1217 mode->vblank_min, 1218 mode->vblank_max, 1219 1, mode->vblank); 1220 1221 v4l2_ctrl_new_std(ctrl_hdlr, &ov9282_ctrl_ops, V4L2_CID_VFLIP, 1222 0, 1, 1, 1); 1223 1224 v4l2_ctrl_new_std(ctrl_hdlr, &ov9282_ctrl_ops, V4L2_CID_HFLIP, 1225 0, 1, 1, 1); 1226 1227 /* Read only controls */ 1228 ov9282->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov9282_ctrl_ops, 1229 V4L2_CID_PIXEL_RATE, 1230 OV9282_PIXEL_RATE_10BIT, 1231 OV9282_PIXEL_RATE_10BIT, 1, 1232 OV9282_PIXEL_RATE_10BIT); 1233 1234 ov9282->link_freq_ctrl = v4l2_ctrl_new_int_menu(ctrl_hdlr, 1235 &ov9282_ctrl_ops, 1236 V4L2_CID_LINK_FREQ, 1237 ARRAY_SIZE(link_freq) - 1238 1, 1239 mode->link_freq_idx, 1240 link_freq); 1241 if (ov9282->link_freq_ctrl) 1242 ov9282->link_freq_ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY; 1243 1244 hblank_min = mode->hblank_min[ov9282->noncontinuous_clock ? 0 : 1]; 1245 ov9282->hblank_ctrl = v4l2_ctrl_new_std(ctrl_hdlr, 1246 &ov9282_ctrl_ops, 1247 V4L2_CID_HBLANK, 1248 hblank_min, 1249 OV9282_TIMING_HTS_MAX - mode->width, 1250 1, hblank_min); 1251 1252 /* Flash/Strobe controls */ 1253 v4l2_ctrl_new_std(ctrl_hdlr, &ov9282_ctrl_ops, 1254 V4L2_CID_FLASH_STROBE_OE, 0, 1, 1, 0); 1255 1256 exposure_us = ov9282_exposure_to_us(ov9282, OV9282_EXPOSURE_DEFAULT); 1257 ov9282->flash_duration = 1258 v4l2_ctrl_new_std(ctrl_hdlr, &ov9282_ctrl_ops, 1259 V4L2_CID_FLASH_DURATION, 0, exposure_us, 1, 1260 OV9282_STROBE_FRAME_SPAN_DEFAULT); 1261 1262 ret = v4l2_fwnode_device_parse(ov9282->dev, &props); 1263 if (!ret) { 1264 /* Failure sets ctrl_hdlr->error, which we check afterwards anyway */ 1265 v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &ov9282_ctrl_ops, 1266 &props); 1267 } 1268 1269 if (ctrl_hdlr->error || ret) { 1270 dev_err(ov9282->dev, "control init failed: %d", 1271 ctrl_hdlr->error); 1272 v4l2_ctrl_handler_free(ctrl_hdlr); 1273 return ctrl_hdlr->error; 1274 } 1275 1276 ov9282->sd.ctrl_handler = ctrl_hdlr; 1277 1278 return 0; 1279 } 1280 1281 static int ov9282_probe(struct i2c_client *client) 1282 { 1283 struct ov9282 *ov9282; 1284 int ret; 1285 1286 ov9282 = devm_kzalloc(&client->dev, sizeof(*ov9282), GFP_KERNEL); 1287 if (!ov9282) 1288 return -ENOMEM; 1289 1290 ov9282->dev = &client->dev; 1291 1292 /* Initialize subdev */ 1293 v4l2_i2c_subdev_init(&ov9282->sd, client, &ov9282_subdev_ops); 1294 ov9282->sd.internal_ops = &ov9282_internal_ops; 1295 v4l2_i2c_subdev_set_name(&ov9282->sd, client, 1296 device_get_match_data(ov9282->dev), NULL); 1297 1298 ret = ov9282_parse_hw_config(ov9282); 1299 if (ret) { 1300 dev_err(ov9282->dev, "HW configuration is not supported"); 1301 return ret; 1302 } 1303 1304 ov9282->regmap = devm_cci_regmap_init_i2c(client, 16); 1305 if (IS_ERR(ov9282->regmap)) 1306 return dev_err_probe(ov9282->dev, PTR_ERR(ov9282->regmap), 1307 "Failed to init CCI\n"); 1308 1309 ret = ov9282_power_on(ov9282->dev); 1310 if (ret) 1311 return dev_err_probe(ov9282->dev, ret, 1312 "failed to power-on the sensor"); 1313 1314 /* Check module identity */ 1315 ret = ov9282_detect(ov9282); 1316 if (ret) { 1317 dev_err(ov9282->dev, "failed to find sensor: %d", ret); 1318 goto error_power_off; 1319 } 1320 1321 /* Set default mode to first mode */ 1322 ov9282->cur_mode = &supported_modes[DEFAULT_MODE]; 1323 ov9282->code = MEDIA_BUS_FMT_Y10_1X10; 1324 ov9282->vblank = ov9282->cur_mode->vblank; 1325 1326 ret = ov9282_init_controls(ov9282); 1327 if (ret) { 1328 dev_err(ov9282->dev, "failed to init controls: %d", ret); 1329 goto error_power_off; 1330 } 1331 1332 /* Initialize subdev */ 1333 ov9282->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | 1334 V4L2_SUBDEV_FL_HAS_EVENTS; 1335 ov9282->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1336 1337 /* Initialize source pad */ 1338 ov9282->pad.flags = MEDIA_PAD_FL_SOURCE; 1339 ret = media_entity_pads_init(&ov9282->sd.entity, 1, &ov9282->pad); 1340 if (ret) { 1341 dev_err(ov9282->dev, "failed to init entity pads: %d", ret); 1342 goto error_handler_free; 1343 } 1344 1345 ov9282->sd.state_lock = ov9282->ctrl_handler.lock; 1346 ret = v4l2_subdev_init_finalize(&ov9282->sd); 1347 if (ret < 0) { 1348 dev_err_probe(ov9282->dev, ret, "failed to init subdev\n"); 1349 goto error_media_entity; 1350 } 1351 1352 pm_runtime_set_active(ov9282->dev); 1353 pm_runtime_enable(ov9282->dev); 1354 1355 ret = v4l2_async_register_subdev_sensor(&ov9282->sd); 1356 if (ret < 0) 1357 goto v4l2_subdev_cleanup; 1358 1359 pm_runtime_idle(ov9282->dev); 1360 1361 return 0; 1362 1363 v4l2_subdev_cleanup: 1364 v4l2_subdev_cleanup(&ov9282->sd); 1365 pm_runtime_disable(ov9282->dev); 1366 pm_runtime_set_suspended(ov9282->dev); 1367 error_media_entity: 1368 media_entity_cleanup(&ov9282->sd.entity); 1369 error_handler_free: 1370 v4l2_ctrl_handler_free(ov9282->sd.ctrl_handler); 1371 error_power_off: 1372 ov9282_power_off(ov9282->dev); 1373 1374 return ret; 1375 } 1376 1377 static void ov9282_remove(struct i2c_client *client) 1378 { 1379 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1380 1381 v4l2_async_unregister_subdev(sd); 1382 v4l2_subdev_cleanup(sd); 1383 media_entity_cleanup(&sd->entity); 1384 v4l2_ctrl_handler_free(sd->ctrl_handler); 1385 1386 pm_runtime_disable(&client->dev); 1387 if (!pm_runtime_status_suspended(&client->dev)) 1388 ov9282_power_off(&client->dev); 1389 pm_runtime_set_suspended(&client->dev); 1390 } 1391 1392 static const struct dev_pm_ops ov9282_pm_ops = { 1393 SET_RUNTIME_PM_OPS(ov9282_power_off, ov9282_power_on, NULL) 1394 }; 1395 1396 static const struct of_device_id ov9282_of_match[] = { 1397 { .compatible = "ovti,ov9281", .data = "ov9281" }, 1398 { .compatible = "ovti,ov9282", .data = "ov9282" }, 1399 { } 1400 }; 1401 1402 MODULE_DEVICE_TABLE(of, ov9282_of_match); 1403 1404 static struct i2c_driver ov9282_driver = { 1405 .probe = ov9282_probe, 1406 .remove = ov9282_remove, 1407 .driver = { 1408 .name = "ov9282", 1409 .pm = &ov9282_pm_ops, 1410 .of_match_table = ov9282_of_match, 1411 }, 1412 }; 1413 1414 module_i2c_driver(ov9282_driver); 1415 1416 MODULE_DESCRIPTION("OmniVision ov9282 sensor driver"); 1417 MODULE_LICENSE("GPL"); 1418