1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2017 Microchip Corporation. 3 4 #include <linux/clk.h> 5 #include <linux/delay.h> 6 #include <linux/gpio/consumer.h> 7 #include <linux/i2c.h> 8 #include <linux/module.h> 9 #include <linux/pm_runtime.h> 10 #include <linux/regmap.h> 11 #include <media/v4l2-ctrls.h> 12 #include <media/v4l2-event.h> 13 #include <media/v4l2-image-sizes.h> 14 #include <media/v4l2-subdev.h> 15 16 #define REG_OUTSIZE_LSB 0x34 17 18 /* OV7740 register tables */ 19 #define REG_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */ 20 #define REG_BGAIN 0x01 /* blue gain */ 21 #define REG_RGAIN 0x02 /* red gain */ 22 #define REG_GGAIN 0x03 /* green gain */ 23 #define REG_REG04 0x04 /* analog setting, don't change*/ 24 #define REG_BAVG 0x05 /* b channel average */ 25 #define REG_GAVG 0x06 /* g channel average */ 26 #define REG_RAVG 0x07 /* r channel average */ 27 28 #define REG_REG0C 0x0C /* filp enable */ 29 #define REG0C_IMG_FLIP 0x80 30 #define REG0C_IMG_MIRROR 0x40 31 32 #define REG_REG0E 0x0E /* blc line */ 33 #define REG_HAEC 0x0F /* auto exposure cntrl */ 34 #define REG_AEC 0x10 /* auto exposure cntrl */ 35 36 #define REG_CLK 0x11 /* Clock control */ 37 #define REG_REG55 0x55 /* Clock PLL DIV/PreDiv */ 38 39 #define REG_REG12 0x12 40 41 #define REG_REG13 0x13 /* auto/manual AGC, AEC, Write Balance*/ 42 #define REG13_AEC_EN 0x01 43 #define REG13_AGC_EN 0x04 44 45 #define REG_REG14 0x14 46 #define REG_CTRL15 0x15 47 #define REG15_GAIN_MSB 0x03 48 49 #define REG_REG16 0x16 50 51 #define REG_MIDH 0x1C /* manufacture id byte */ 52 #define REG_MIDL 0x1D /* manufacture id byre */ 53 #define REG_PIDH 0x0A /* Product ID MSB */ 54 #define REG_PIDL 0x0B /* Product ID LSB */ 55 56 #define REG_84 0x84 /* lots of stuff */ 57 #define REG_REG38 0x38 /* sub-addr */ 58 59 #define REG_AHSTART 0x17 /* Horiz start high bits */ 60 #define REG_AHSIZE 0x18 61 #define REG_AVSTART 0x19 /* Vert start high bits */ 62 #define REG_AVSIZE 0x1A 63 #define REG_PSHFT 0x1b /* Pixel delay after HREF */ 64 65 #define REG_HOUTSIZE 0x31 66 #define REG_VOUTSIZE 0x32 67 #define REG_HVSIZEOFF 0x33 68 #define REG_REG34 0x34 /* DSP output size H/V LSB*/ 69 70 #define REG_ISP_CTRL00 0x80 71 #define ISPCTRL00_AWB_EN 0x10 72 #define ISPCTRL00_AWB_GAIN_EN 0x04 73 74 #define REG_YGAIN 0xE2 /* ygain for contrast control */ 75 76 #define REG_YBRIGHT 0xE3 77 #define REG_SGNSET 0xE4 78 #define SGNSET_YBRIGHT_MASK 0x08 79 80 #define REG_USAT 0xDD 81 #define REG_VSAT 0xDE 82 83 84 struct ov7740 { 85 struct v4l2_subdev subdev; 86 #if defined(CONFIG_MEDIA_CONTROLLER) 87 struct media_pad pad; 88 #endif 89 struct v4l2_mbus_framefmt format; 90 const struct ov7740_pixfmt *fmt; /* Current format */ 91 const struct ov7740_framesize *frmsize; 92 struct regmap *regmap; 93 struct clk *xvclk; 94 struct v4l2_ctrl_handler ctrl_handler; 95 struct { 96 /* gain cluster */ 97 struct v4l2_ctrl *auto_gain; 98 struct v4l2_ctrl *gain; 99 }; 100 struct { 101 struct v4l2_ctrl *auto_wb; 102 struct v4l2_ctrl *blue_balance; 103 struct v4l2_ctrl *red_balance; 104 }; 105 struct { 106 struct v4l2_ctrl *hflip; 107 struct v4l2_ctrl *vflip; 108 }; 109 struct { 110 /* exposure cluster */ 111 struct v4l2_ctrl *auto_exposure; 112 struct v4l2_ctrl *exposure; 113 }; 114 struct { 115 /* saturation/hue cluster */ 116 struct v4l2_ctrl *saturation; 117 struct v4l2_ctrl *hue; 118 }; 119 struct v4l2_ctrl *brightness; 120 struct v4l2_ctrl *contrast; 121 122 struct mutex mutex; /* To serialize asynchronus callbacks */ 123 bool streaming; /* Streaming on/off */ 124 125 struct gpio_desc *resetb_gpio; 126 struct gpio_desc *pwdn_gpio; 127 }; 128 129 struct ov7740_pixfmt { 130 u32 mbus_code; 131 enum v4l2_colorspace colorspace; 132 const struct reg_sequence *regs; 133 u32 reg_num; 134 }; 135 136 struct ov7740_framesize { 137 u16 width; 138 u16 height; 139 const struct reg_sequence *regs; 140 u32 reg_num; 141 }; 142 143 static const struct reg_sequence ov7740_vga[] = { 144 {0x55, 0x40}, 145 {0x11, 0x02}, 146 147 {0xd5, 0x10}, 148 {0x0c, 0x12}, 149 {0x0d, 0x34}, 150 {0x17, 0x25}, 151 {0x18, 0xa0}, 152 {0x19, 0x03}, 153 {0x1a, 0xf0}, 154 {0x1b, 0x89}, 155 {0x22, 0x03}, 156 {0x29, 0x18}, 157 {0x2b, 0xf8}, 158 {0x2c, 0x01}, 159 {REG_HOUTSIZE, 0xa0}, 160 {REG_VOUTSIZE, 0xf0}, 161 {0x33, 0xc4}, 162 {REG_OUTSIZE_LSB, 0x0}, 163 {0x35, 0x05}, 164 {0x04, 0x60}, 165 {0x27, 0x80}, 166 {0x3d, 0x0f}, 167 {0x3e, 0x80}, 168 {0x3f, 0x40}, 169 {0x40, 0x7f}, 170 {0x41, 0x6a}, 171 {0x42, 0x29}, 172 {0x44, 0x22}, 173 {0x45, 0x41}, 174 {0x47, 0x02}, 175 {0x49, 0x64}, 176 {0x4a, 0xa1}, 177 {0x4b, 0x40}, 178 {0x4c, 0x1a}, 179 {0x4d, 0x50}, 180 {0x4e, 0x13}, 181 {0x64, 0x00}, 182 {0x67, 0x88}, 183 {0x68, 0x1a}, 184 185 {0x14, 0x28}, 186 {0x24, 0x3c}, 187 {0x25, 0x30}, 188 {0x26, 0x72}, 189 {0x50, 0x97}, 190 {0x51, 0x1f}, 191 {0x52, 0x00}, 192 {0x53, 0x00}, 193 {0x20, 0x00}, 194 {0x21, 0xcf}, 195 {0x50, 0x4b}, 196 {0x38, 0x14}, 197 {0xe9, 0x00}, 198 {0x56, 0x55}, 199 {0x57, 0xff}, 200 {0x58, 0xff}, 201 {0x59, 0xff}, 202 {0x5f, 0x04}, 203 {0xec, 0x00}, 204 {0x13, 0xff}, 205 206 {0x81, 0x3f}, 207 {0x82, 0x32}, 208 {0x38, 0x11}, 209 {0x84, 0x70}, 210 {0x85, 0x00}, 211 {0x86, 0x03}, 212 {0x87, 0x01}, 213 {0x88, 0x05}, 214 {0x89, 0x30}, 215 {0x8d, 0x30}, 216 {0x8f, 0x85}, 217 {0x93, 0x30}, 218 {0x95, 0x85}, 219 {0x99, 0x30}, 220 {0x9b, 0x85}, 221 222 {0x9c, 0x08}, 223 {0x9d, 0x12}, 224 {0x9e, 0x23}, 225 {0x9f, 0x45}, 226 {0xa0, 0x55}, 227 {0xa1, 0x64}, 228 {0xa2, 0x72}, 229 {0xa3, 0x7f}, 230 {0xa4, 0x8b}, 231 {0xa5, 0x95}, 232 {0xa6, 0xa7}, 233 {0xa7, 0xb5}, 234 {0xa8, 0xcb}, 235 {0xa9, 0xdd}, 236 {0xaa, 0xec}, 237 {0xab, 0x1a}, 238 239 {0xce, 0x78}, 240 {0xcf, 0x6e}, 241 {0xd0, 0x0a}, 242 {0xd1, 0x0c}, 243 {0xd2, 0x84}, 244 {0xd3, 0x90}, 245 {0xd4, 0x1e}, 246 247 {0x5a, 0x24}, 248 {0x5b, 0x1f}, 249 {0x5c, 0x88}, 250 {0x5d, 0x60}, 251 252 {0xac, 0x6e}, 253 {0xbe, 0xff}, 254 {0xbf, 0x00}, 255 256 {0x0f, 0x1d}, 257 {0x0f, 0x1f}, 258 }; 259 260 static const struct ov7740_framesize ov7740_framesizes[] = { 261 { 262 .width = VGA_WIDTH, 263 .height = VGA_HEIGHT, 264 .regs = ov7740_vga, 265 .reg_num = ARRAY_SIZE(ov7740_vga), 266 }, 267 }; 268 269 #ifdef CONFIG_VIDEO_ADV_DEBUG 270 static int ov7740_get_register(struct v4l2_subdev *sd, 271 struct v4l2_dbg_register *reg) 272 { 273 struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev); 274 struct regmap *regmap = ov7740->regmap; 275 unsigned int val = 0; 276 int ret; 277 278 ret = regmap_read(regmap, reg->reg & 0xff, &val); 279 reg->val = val; 280 reg->size = 1; 281 282 return ret; 283 } 284 285 static int ov7740_set_register(struct v4l2_subdev *sd, 286 const struct v4l2_dbg_register *reg) 287 { 288 struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev); 289 struct regmap *regmap = ov7740->regmap; 290 291 regmap_write(regmap, reg->reg & 0xff, reg->val & 0xff); 292 293 return 0; 294 } 295 #endif 296 297 static int ov7740_set_power(struct ov7740 *ov7740, int on) 298 { 299 int ret; 300 301 if (on) { 302 ret = clk_prepare_enable(ov7740->xvclk); 303 if (ret) 304 return ret; 305 306 if (ov7740->pwdn_gpio) 307 gpiod_direction_output(ov7740->pwdn_gpio, 0); 308 309 if (ov7740->resetb_gpio) { 310 gpiod_set_value(ov7740->resetb_gpio, 1); 311 usleep_range(500, 1000); 312 gpiod_set_value(ov7740->resetb_gpio, 0); 313 usleep_range(3000, 5000); 314 } 315 } else { 316 clk_disable_unprepare(ov7740->xvclk); 317 318 if (ov7740->pwdn_gpio) 319 gpiod_direction_output(ov7740->pwdn_gpio, 0); 320 } 321 322 return 0; 323 } 324 325 static const struct v4l2_subdev_core_ops ov7740_subdev_core_ops = { 326 .log_status = v4l2_ctrl_subdev_log_status, 327 #ifdef CONFIG_VIDEO_ADV_DEBUG 328 .g_register = ov7740_get_register, 329 .s_register = ov7740_set_register, 330 #endif 331 .subscribe_event = v4l2_ctrl_subdev_subscribe_event, 332 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 333 }; 334 335 static int ov7740_set_white_balance(struct ov7740 *ov7740, int awb) 336 { 337 struct regmap *regmap = ov7740->regmap; 338 unsigned int value; 339 int ret; 340 341 ret = regmap_read(regmap, REG_ISP_CTRL00, &value); 342 if (!ret) { 343 if (awb) 344 value |= (ISPCTRL00_AWB_EN | ISPCTRL00_AWB_GAIN_EN); 345 else 346 value &= ~(ISPCTRL00_AWB_EN | ISPCTRL00_AWB_GAIN_EN); 347 ret = regmap_write(regmap, REG_ISP_CTRL00, value); 348 if (ret) 349 return ret; 350 } 351 352 if (!awb) { 353 ret = regmap_write(regmap, REG_BGAIN, 354 ov7740->blue_balance->val); 355 if (ret) 356 return ret; 357 358 ret = regmap_write(regmap, REG_RGAIN, ov7740->red_balance->val); 359 if (ret) 360 return ret; 361 } 362 363 return 0; 364 } 365 366 static int ov7740_set_saturation(struct regmap *regmap, int value) 367 { 368 int ret; 369 370 ret = regmap_write(regmap, REG_USAT, (unsigned char)value); 371 if (ret) 372 return ret; 373 374 return regmap_write(regmap, REG_VSAT, (unsigned char)value); 375 } 376 377 static int ov7740_set_gain(struct regmap *regmap, int value) 378 { 379 int ret; 380 381 ret = regmap_write(regmap, REG_GAIN, value & 0xff); 382 if (ret) 383 return ret; 384 385 ret = regmap_update_bits(regmap, REG_CTRL15, 386 REG15_GAIN_MSB, (value >> 8) & 0x3); 387 if (!ret) 388 ret = regmap_update_bits(regmap, REG_REG13, REG13_AGC_EN, 0); 389 390 return ret; 391 } 392 393 static int ov7740_set_autogain(struct regmap *regmap, int value) 394 { 395 unsigned int reg; 396 int ret; 397 398 ret = regmap_read(regmap, REG_REG13, ®); 399 if (ret) 400 return ret; 401 if (value) 402 reg |= REG13_AGC_EN; 403 else 404 reg &= ~REG13_AGC_EN; 405 return regmap_write(regmap, REG_REG13, reg); 406 } 407 408 static int ov7740_set_brightness(struct regmap *regmap, int value) 409 { 410 /* Turn off AEC/AGC */ 411 regmap_update_bits(regmap, REG_REG13, REG13_AEC_EN, 0); 412 regmap_update_bits(regmap, REG_REG13, REG13_AGC_EN, 0); 413 414 if (value >= 0) { 415 regmap_write(regmap, REG_YBRIGHT, (unsigned char)value); 416 regmap_update_bits(regmap, REG_SGNSET, SGNSET_YBRIGHT_MASK, 0); 417 } else{ 418 regmap_write(regmap, REG_YBRIGHT, (unsigned char)(-value)); 419 regmap_update_bits(regmap, REG_SGNSET, SGNSET_YBRIGHT_MASK, 1); 420 } 421 422 return 0; 423 } 424 425 static int ov7740_set_contrast(struct regmap *regmap, int value) 426 { 427 return regmap_write(regmap, REG_YGAIN, (unsigned char)value); 428 } 429 430 static int ov7740_get_gain(struct ov7740 *ov7740, struct v4l2_ctrl *ctrl) 431 { 432 struct regmap *regmap = ov7740->regmap; 433 unsigned int value0, value1; 434 int ret; 435 436 if (!ctrl->val) 437 return 0; 438 439 ret = regmap_read(regmap, REG_GAIN, &value0); 440 if (ret) 441 return ret; 442 ret = regmap_read(regmap, REG_CTRL15, &value1); 443 if (ret) 444 return ret; 445 446 ov7740->gain->val = (value1 << 8) | (value0 & 0xff); 447 448 return 0; 449 } 450 451 static int ov7740_get_exp(struct ov7740 *ov7740, struct v4l2_ctrl *ctrl) 452 { 453 struct regmap *regmap = ov7740->regmap; 454 unsigned int value0, value1; 455 int ret; 456 457 if (ctrl->val == V4L2_EXPOSURE_MANUAL) 458 return 0; 459 460 ret = regmap_read(regmap, REG_AEC, &value0); 461 if (ret) 462 return ret; 463 ret = regmap_read(regmap, REG_HAEC, &value1); 464 if (ret) 465 return ret; 466 467 ov7740->exposure->val = (value1 << 8) | (value0 & 0xff); 468 469 return 0; 470 } 471 472 static int ov7740_set_exp(struct regmap *regmap, int value) 473 { 474 int ret; 475 476 /* Turn off AEC/AGC */ 477 ret = regmap_update_bits(regmap, REG_REG13, 478 REG13_AEC_EN | REG13_AGC_EN, 0); 479 if (ret) 480 return ret; 481 482 ret = regmap_write(regmap, REG_AEC, (unsigned char)value); 483 if (ret) 484 return ret; 485 486 return regmap_write(regmap, REG_HAEC, (unsigned char)(value >> 8)); 487 } 488 489 static int ov7740_set_autoexp(struct regmap *regmap, 490 enum v4l2_exposure_auto_type value) 491 { 492 unsigned int reg; 493 int ret; 494 495 ret = regmap_read(regmap, REG_REG13, ®); 496 if (!ret) { 497 if (value == V4L2_EXPOSURE_AUTO) 498 reg |= (REG13_AEC_EN | REG13_AGC_EN); 499 else 500 reg &= ~(REG13_AEC_EN | REG13_AGC_EN); 501 ret = regmap_write(regmap, REG_REG13, reg); 502 } 503 504 return ret; 505 } 506 507 508 static int ov7740_get_volatile_ctrl(struct v4l2_ctrl *ctrl) 509 { 510 struct ov7740 *ov7740 = container_of(ctrl->handler, 511 struct ov7740, ctrl_handler); 512 int ret; 513 514 switch (ctrl->id) { 515 case V4L2_CID_AUTOGAIN: 516 ret = ov7740_get_gain(ov7740, ctrl); 517 break; 518 case V4L2_CID_EXPOSURE_AUTO: 519 ret = ov7740_get_exp(ov7740, ctrl); 520 break; 521 default: 522 ret = -EINVAL; 523 break; 524 } 525 return ret; 526 } 527 528 static int ov7740_set_ctrl(struct v4l2_ctrl *ctrl) 529 { 530 struct ov7740 *ov7740 = container_of(ctrl->handler, 531 struct ov7740, ctrl_handler); 532 struct i2c_client *client = v4l2_get_subdevdata(&ov7740->subdev); 533 struct regmap *regmap = ov7740->regmap; 534 int ret; 535 u8 val = 0; 536 537 if (!pm_runtime_get_if_in_use(&client->dev)) 538 return 0; 539 540 switch (ctrl->id) { 541 case V4L2_CID_AUTO_WHITE_BALANCE: 542 ret = ov7740_set_white_balance(ov7740, ctrl->val); 543 break; 544 case V4L2_CID_SATURATION: 545 ret = ov7740_set_saturation(regmap, ctrl->val); 546 break; 547 case V4L2_CID_BRIGHTNESS: 548 ret = ov7740_set_brightness(regmap, ctrl->val); 549 break; 550 case V4L2_CID_CONTRAST: 551 ret = ov7740_set_contrast(regmap, ctrl->val); 552 break; 553 case V4L2_CID_VFLIP: 554 ret = regmap_update_bits(regmap, REG_REG0C, 555 REG0C_IMG_FLIP, val); 556 break; 557 case V4L2_CID_HFLIP: 558 val = ctrl->val ? REG0C_IMG_MIRROR : 0x00; 559 ret = regmap_update_bits(regmap, REG_REG0C, 560 REG0C_IMG_MIRROR, val); 561 break; 562 case V4L2_CID_AUTOGAIN: 563 if (!ctrl->val) 564 return ov7740_set_gain(regmap, ov7740->gain->val); 565 566 ret = ov7740_set_autogain(regmap, ctrl->val); 567 break; 568 569 case V4L2_CID_EXPOSURE_AUTO: 570 if (ctrl->val == V4L2_EXPOSURE_MANUAL) 571 return ov7740_set_exp(regmap, ov7740->exposure->val); 572 573 ret = ov7740_set_autoexp(regmap, ctrl->val); 574 break; 575 default: 576 ret = -EINVAL; 577 break; 578 } 579 580 pm_runtime_put(&client->dev); 581 582 return ret; 583 } 584 585 static const struct v4l2_ctrl_ops ov7740_ctrl_ops = { 586 .g_volatile_ctrl = ov7740_get_volatile_ctrl, 587 .s_ctrl = ov7740_set_ctrl, 588 }; 589 590 static int ov7740_start_streaming(struct ov7740 *ov7740) 591 { 592 int ret; 593 594 if (ov7740->fmt) { 595 ret = regmap_multi_reg_write(ov7740->regmap, 596 ov7740->fmt->regs, 597 ov7740->fmt->reg_num); 598 if (ret) 599 return ret; 600 } 601 602 if (ov7740->frmsize) { 603 ret = regmap_multi_reg_write(ov7740->regmap, 604 ov7740->frmsize->regs, 605 ov7740->frmsize->reg_num); 606 if (ret) 607 return ret; 608 } 609 610 return __v4l2_ctrl_handler_setup(ov7740->subdev.ctrl_handler); 611 } 612 613 static int ov7740_set_stream(struct v4l2_subdev *sd, int enable) 614 { 615 struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev); 616 struct i2c_client *client = v4l2_get_subdevdata(sd); 617 int ret = 0; 618 619 mutex_lock(&ov7740->mutex); 620 if (ov7740->streaming == enable) { 621 mutex_unlock(&ov7740->mutex); 622 return 0; 623 } 624 625 if (enable) { 626 ret = pm_runtime_get_sync(&client->dev); 627 if (ret < 0) { 628 pm_runtime_put_noidle(&client->dev); 629 goto err_unlock; 630 } 631 632 ret = ov7740_start_streaming(ov7740); 633 if (ret) 634 goto err_rpm_put; 635 } else { 636 pm_runtime_put(&client->dev); 637 } 638 639 ov7740->streaming = enable; 640 641 mutex_unlock(&ov7740->mutex); 642 return ret; 643 644 err_rpm_put: 645 pm_runtime_put(&client->dev); 646 err_unlock: 647 mutex_unlock(&ov7740->mutex); 648 return ret; 649 } 650 651 static int ov7740_g_frame_interval(struct v4l2_subdev *sd, 652 struct v4l2_subdev_frame_interval *ival) 653 { 654 struct v4l2_fract *tpf = &ival->interval; 655 656 657 tpf->numerator = 1; 658 tpf->denominator = 60; 659 660 return 0; 661 } 662 663 static int ov7740_s_frame_interval(struct v4l2_subdev *sd, 664 struct v4l2_subdev_frame_interval *ival) 665 { 666 struct v4l2_fract *tpf = &ival->interval; 667 668 669 tpf->numerator = 1; 670 tpf->denominator = 60; 671 672 return 0; 673 } 674 675 static const struct v4l2_subdev_video_ops ov7740_subdev_video_ops = { 676 .s_stream = ov7740_set_stream, 677 .s_frame_interval = ov7740_s_frame_interval, 678 .g_frame_interval = ov7740_g_frame_interval, 679 }; 680 681 static const struct reg_sequence ov7740_format_yuyv[] = { 682 {0x12, 0x00}, 683 {0x36, 0x3f}, 684 {0x80, 0x7f}, 685 {0x83, 0x01}, 686 }; 687 688 static const struct reg_sequence ov7740_format_bggr8[] = { 689 {0x36, 0x2f}, 690 {0x80, 0x01}, 691 {0x83, 0x04}, 692 }; 693 694 static const struct ov7740_pixfmt ov7740_formats[] = { 695 { 696 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8, 697 .colorspace = V4L2_COLORSPACE_SRGB, 698 .regs = ov7740_format_yuyv, 699 .reg_num = ARRAY_SIZE(ov7740_format_yuyv), 700 }, 701 { 702 .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8, 703 .colorspace = V4L2_COLORSPACE_SRGB, 704 .regs = ov7740_format_bggr8, 705 .reg_num = ARRAY_SIZE(ov7740_format_bggr8), 706 } 707 }; 708 #define N_OV7740_FMTS ARRAY_SIZE(ov7740_formats) 709 710 static int ov7740_enum_mbus_code(struct v4l2_subdev *sd, 711 struct v4l2_subdev_pad_config *cfg, 712 struct v4l2_subdev_mbus_code_enum *code) 713 { 714 if (code->pad || code->index >= N_OV7740_FMTS) 715 return -EINVAL; 716 717 code->code = ov7740_formats[code->index].mbus_code; 718 719 return 0; 720 } 721 722 static int ov7740_enum_frame_interval(struct v4l2_subdev *sd, 723 struct v4l2_subdev_pad_config *cfg, 724 struct v4l2_subdev_frame_interval_enum *fie) 725 { 726 if (fie->pad) 727 return -EINVAL; 728 729 if (fie->index >= 1) 730 return -EINVAL; 731 732 if ((fie->width != VGA_WIDTH) || (fie->height != VGA_HEIGHT)) 733 return -EINVAL; 734 735 fie->interval.numerator = 1; 736 fie->interval.denominator = 60; 737 738 return 0; 739 } 740 741 static int ov7740_enum_frame_size(struct v4l2_subdev *sd, 742 struct v4l2_subdev_pad_config *cfg, 743 struct v4l2_subdev_frame_size_enum *fse) 744 { 745 if (fse->pad) 746 return -EINVAL; 747 748 if (fse->index > 0) 749 return -EINVAL; 750 751 fse->min_width = fse->max_width = VGA_WIDTH; 752 fse->min_height = fse->max_height = VGA_HEIGHT; 753 754 return 0; 755 } 756 757 static int ov7740_try_fmt_internal(struct v4l2_subdev *sd, 758 struct v4l2_mbus_framefmt *fmt, 759 const struct ov7740_pixfmt **ret_fmt, 760 const struct ov7740_framesize **ret_frmsize) 761 { 762 struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev); 763 const struct ov7740_framesize *fsize = &ov7740_framesizes[0]; 764 int index, i; 765 766 for (index = 0; index < N_OV7740_FMTS; index++) { 767 if (ov7740_formats[index].mbus_code == fmt->code) 768 break; 769 } 770 if (index >= N_OV7740_FMTS) { 771 /* default to first format */ 772 index = 0; 773 fmt->code = ov7740_formats[0].mbus_code; 774 } 775 if (ret_fmt != NULL) 776 *ret_fmt = ov7740_formats + index; 777 778 for (i = 0; i < ARRAY_SIZE(ov7740_framesizes); i++) { 779 if ((fsize->width >= fmt->width) && 780 (fsize->height >= fmt->height)) { 781 fmt->width = fsize->width; 782 fmt->height = fsize->height; 783 break; 784 } 785 786 fsize++; 787 } 788 789 if (ret_frmsize != NULL) 790 *ret_frmsize = fsize; 791 792 fmt->field = V4L2_FIELD_NONE; 793 fmt->colorspace = ov7740_formats[index].colorspace; 794 795 ov7740->format = *fmt; 796 797 return 0; 798 } 799 800 static int ov7740_set_fmt(struct v4l2_subdev *sd, 801 struct v4l2_subdev_pad_config *cfg, 802 struct v4l2_subdev_format *format) 803 { 804 struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev); 805 const struct ov7740_pixfmt *ovfmt; 806 const struct ov7740_framesize *fsize; 807 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 808 struct v4l2_mbus_framefmt *mbus_fmt; 809 #endif 810 int ret; 811 812 mutex_lock(&ov7740->mutex); 813 if (format->pad) { 814 ret = -EINVAL; 815 goto error; 816 } 817 818 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 819 ret = ov7740_try_fmt_internal(sd, &format->format, NULL, NULL); 820 if (ret) 821 goto error; 822 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 823 mbus_fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad); 824 *mbus_fmt = format->format; 825 826 mutex_unlock(&ov7740->mutex); 827 return 0; 828 #else 829 ret = -ENOTTY; 830 goto error; 831 #endif 832 } 833 834 ret = ov7740_try_fmt_internal(sd, &format->format, &ovfmt, &fsize); 835 if (ret) 836 goto error; 837 838 ov7740->fmt = ovfmt; 839 ov7740->frmsize = fsize; 840 841 mutex_unlock(&ov7740->mutex); 842 return 0; 843 844 error: 845 mutex_unlock(&ov7740->mutex); 846 return ret; 847 } 848 849 static int ov7740_get_fmt(struct v4l2_subdev *sd, 850 struct v4l2_subdev_pad_config *cfg, 851 struct v4l2_subdev_format *format) 852 { 853 struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev); 854 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 855 struct v4l2_mbus_framefmt *mbus_fmt; 856 #endif 857 int ret = 0; 858 859 mutex_lock(&ov7740->mutex); 860 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 861 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 862 mbus_fmt = v4l2_subdev_get_try_format(sd, cfg, 0); 863 format->format = *mbus_fmt; 864 ret = 0; 865 #else 866 ret = -ENOTTY; 867 #endif 868 } else { 869 format->format = ov7740->format; 870 } 871 mutex_unlock(&ov7740->mutex); 872 873 return ret; 874 } 875 876 static const struct v4l2_subdev_pad_ops ov7740_subdev_pad_ops = { 877 .enum_frame_interval = ov7740_enum_frame_interval, 878 .enum_frame_size = ov7740_enum_frame_size, 879 .enum_mbus_code = ov7740_enum_mbus_code, 880 .get_fmt = ov7740_get_fmt, 881 .set_fmt = ov7740_set_fmt, 882 }; 883 884 static const struct v4l2_subdev_ops ov7740_subdev_ops = { 885 .core = &ov7740_subdev_core_ops, 886 .video = &ov7740_subdev_video_ops, 887 .pad = &ov7740_subdev_pad_ops, 888 }; 889 890 static void ov7740_get_default_format(struct v4l2_subdev *sd, 891 struct v4l2_mbus_framefmt *format) 892 { 893 struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev); 894 895 format->width = ov7740->frmsize->width; 896 format->height = ov7740->frmsize->height; 897 format->colorspace = ov7740->fmt->colorspace; 898 format->code = ov7740->fmt->mbus_code; 899 format->field = V4L2_FIELD_NONE; 900 } 901 902 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 903 static int ov7740_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) 904 { 905 struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev); 906 struct v4l2_mbus_framefmt *format = 907 v4l2_subdev_get_try_format(sd, fh->pad, 0); 908 909 mutex_lock(&ov7740->mutex); 910 ov7740_get_default_format(sd, format); 911 mutex_unlock(&ov7740->mutex); 912 913 return 0; 914 } 915 916 static const struct v4l2_subdev_internal_ops ov7740_subdev_internal_ops = { 917 .open = ov7740_open, 918 }; 919 #endif 920 921 static int ov7740_probe_dt(struct i2c_client *client, 922 struct ov7740 *ov7740) 923 { 924 ov7740->resetb_gpio = devm_gpiod_get_optional(&client->dev, "reset", 925 GPIOD_OUT_HIGH); 926 if (IS_ERR(ov7740->resetb_gpio)) { 927 dev_info(&client->dev, "can't get %s GPIO\n", "reset"); 928 return PTR_ERR(ov7740->resetb_gpio); 929 } 930 931 ov7740->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "powerdown", 932 GPIOD_OUT_LOW); 933 if (IS_ERR(ov7740->pwdn_gpio)) { 934 dev_info(&client->dev, "can't get %s GPIO\n", "powerdown"); 935 return PTR_ERR(ov7740->pwdn_gpio); 936 } 937 938 return 0; 939 } 940 941 static int ov7740_detect(struct ov7740 *ov7740) 942 { 943 struct regmap *regmap = ov7740->regmap; 944 unsigned int midh, midl, pidh, pidl; 945 int ret; 946 947 ret = regmap_read(regmap, REG_MIDH, &midh); 948 if (ret) 949 return ret; 950 if (midh != 0x7f) 951 return -ENODEV; 952 953 ret = regmap_read(regmap, REG_MIDL, &midl); 954 if (ret) 955 return ret; 956 if (midl != 0xa2) 957 return -ENODEV; 958 959 ret = regmap_read(regmap, REG_PIDH, &pidh); 960 if (ret) 961 return ret; 962 if (pidh != 0x77) 963 return -ENODEV; 964 965 ret = regmap_read(regmap, REG_PIDL, &pidl); 966 if (ret) 967 return ret; 968 if ((pidl != 0x40) && (pidl != 0x41) && (pidl != 0x42)) 969 return -ENODEV; 970 971 return 0; 972 } 973 974 static int ov7740_init_controls(struct ov7740 *ov7740) 975 { 976 struct i2c_client *client = v4l2_get_subdevdata(&ov7740->subdev); 977 struct v4l2_ctrl_handler *ctrl_hdlr = &ov7740->ctrl_handler; 978 int ret; 979 980 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 12); 981 if (ret < 0) 982 return ret; 983 984 ctrl_hdlr->lock = &ov7740->mutex; 985 ov7740->auto_wb = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops, 986 V4L2_CID_AUTO_WHITE_BALANCE, 987 0, 1, 1, 1); 988 ov7740->blue_balance = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops, 989 V4L2_CID_BLUE_BALANCE, 990 0, 0xff, 1, 0x80); 991 ov7740->red_balance = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops, 992 V4L2_CID_RED_BALANCE, 993 0, 0xff, 1, 0x80); 994 995 ov7740->brightness = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops, 996 V4L2_CID_BRIGHTNESS, 997 -255, 255, 1, 0); 998 ov7740->contrast = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops, 999 V4L2_CID_CONTRAST, 1000 0, 127, 1, 0x20); 1001 ov7740->saturation = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops, 1002 V4L2_CID_SATURATION, 0, 256, 1, 0x80); 1003 ov7740->hflip = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops, 1004 V4L2_CID_HFLIP, 0, 1, 1, 0); 1005 ov7740->vflip = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops, 1006 V4L2_CID_VFLIP, 0, 1, 1, 0); 1007 1008 ov7740->gain = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops, 1009 V4L2_CID_GAIN, 0, 1023, 1, 500); 1010 if (ov7740->gain) 1011 ov7740->gain->flags |= V4L2_CTRL_FLAG_VOLATILE; 1012 1013 ov7740->auto_gain = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops, 1014 V4L2_CID_AUTOGAIN, 0, 1, 1, 1); 1015 1016 ov7740->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops, 1017 V4L2_CID_EXPOSURE, 0, 65535, 1, 500); 1018 1019 ov7740->auto_exposure = v4l2_ctrl_new_std_menu(ctrl_hdlr, 1020 &ov7740_ctrl_ops, 1021 V4L2_CID_EXPOSURE_AUTO, 1022 V4L2_EXPOSURE_MANUAL, 0, 1023 V4L2_EXPOSURE_AUTO); 1024 1025 v4l2_ctrl_auto_cluster(3, &ov7740->auto_wb, 0, false); 1026 v4l2_ctrl_auto_cluster(2, &ov7740->auto_gain, 0, true); 1027 v4l2_ctrl_auto_cluster(2, &ov7740->auto_exposure, 1028 V4L2_EXPOSURE_MANUAL, true); 1029 v4l2_ctrl_cluster(2, &ov7740->hflip); 1030 1031 if (ctrl_hdlr->error) { 1032 ret = ctrl_hdlr->error; 1033 dev_err(&client->dev, "controls initialisation failed (%d)\n", 1034 ret); 1035 goto error; 1036 } 1037 1038 ret = v4l2_ctrl_handler_setup(ctrl_hdlr); 1039 if (ret) { 1040 dev_err(&client->dev, "%s control init failed (%d)\n", 1041 __func__, ret); 1042 goto error; 1043 } 1044 1045 ov7740->subdev.ctrl_handler = ctrl_hdlr; 1046 return 0; 1047 1048 error: 1049 v4l2_ctrl_handler_free(ctrl_hdlr); 1050 mutex_destroy(&ov7740->mutex); 1051 return ret; 1052 } 1053 1054 static void ov7740_free_controls(struct ov7740 *ov7740) 1055 { 1056 v4l2_ctrl_handler_free(ov7740->subdev.ctrl_handler); 1057 mutex_destroy(&ov7740->mutex); 1058 } 1059 1060 #define OV7740_MAX_REGISTER 0xff 1061 static const struct regmap_config ov7740_regmap_config = { 1062 .reg_bits = 8, 1063 .val_bits = 8, 1064 .max_register = OV7740_MAX_REGISTER, 1065 }; 1066 1067 static int ov7740_probe(struct i2c_client *client, 1068 const struct i2c_device_id *id) 1069 { 1070 struct ov7740 *ov7740; 1071 struct v4l2_subdev *sd; 1072 int ret; 1073 1074 if (!i2c_check_functionality(client->adapter, 1075 I2C_FUNC_SMBUS_BYTE_DATA)) { 1076 dev_err(&client->dev, 1077 "OV7740: I2C-Adapter doesn't support SMBUS\n"); 1078 return -EIO; 1079 } 1080 1081 ov7740 = devm_kzalloc(&client->dev, sizeof(*ov7740), GFP_KERNEL); 1082 if (!ov7740) 1083 return -ENOMEM; 1084 1085 ov7740->xvclk = devm_clk_get(&client->dev, "xvclk"); 1086 if (IS_ERR(ov7740->xvclk)) { 1087 ret = PTR_ERR(ov7740->xvclk); 1088 dev_err(&client->dev, 1089 "OV7740: fail to get xvclk: %d\n", ret); 1090 return ret; 1091 } 1092 1093 ret = ov7740_probe_dt(client, ov7740); 1094 if (ret) 1095 return ret; 1096 1097 ov7740->regmap = devm_regmap_init_i2c(client, &ov7740_regmap_config); 1098 if (IS_ERR(ov7740->regmap)) { 1099 ret = PTR_ERR(ov7740->regmap); 1100 dev_err(&client->dev, "Failed to allocate register map: %d\n", 1101 ret); 1102 return ret; 1103 } 1104 1105 sd = &ov7740->subdev; 1106 client->flags |= I2C_CLIENT_SCCB; 1107 v4l2_i2c_subdev_init(sd, client, &ov7740_subdev_ops); 1108 1109 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1110 sd->internal_ops = &ov7740_subdev_internal_ops; 1111 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; 1112 #endif 1113 1114 #if defined(CONFIG_MEDIA_CONTROLLER) 1115 ov7740->pad.flags = MEDIA_PAD_FL_SOURCE; 1116 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR; 1117 ret = media_entity_pads_init(&sd->entity, 1, &ov7740->pad); 1118 if (ret) 1119 return ret; 1120 #endif 1121 1122 ret = ov7740_set_power(ov7740, 1); 1123 if (ret) 1124 return ret; 1125 1126 pm_runtime_set_active(&client->dev); 1127 pm_runtime_enable(&client->dev); 1128 1129 ret = ov7740_detect(ov7740); 1130 if (ret) 1131 goto error_detect; 1132 1133 mutex_init(&ov7740->mutex); 1134 1135 ret = ov7740_init_controls(ov7740); 1136 if (ret) 1137 goto error_init_controls; 1138 1139 v4l_info(client, "chip found @ 0x%02x (%s)\n", 1140 client->addr << 1, client->adapter->name); 1141 1142 ov7740->fmt = &ov7740_formats[0]; 1143 ov7740->frmsize = &ov7740_framesizes[0]; 1144 1145 ov7740_get_default_format(sd, &ov7740->format); 1146 1147 ret = v4l2_async_register_subdev(sd); 1148 if (ret) 1149 goto error_async_register; 1150 1151 pm_runtime_idle(&client->dev); 1152 1153 return 0; 1154 1155 error_async_register: 1156 v4l2_ctrl_handler_free(ov7740->subdev.ctrl_handler); 1157 error_init_controls: 1158 ov7740_free_controls(ov7740); 1159 error_detect: 1160 pm_runtime_disable(&client->dev); 1161 pm_runtime_set_suspended(&client->dev); 1162 ov7740_set_power(ov7740, 0); 1163 media_entity_cleanup(&ov7740->subdev.entity); 1164 1165 return ret; 1166 } 1167 1168 static int ov7740_remove(struct i2c_client *client) 1169 { 1170 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1171 struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev); 1172 1173 mutex_destroy(&ov7740->mutex); 1174 v4l2_ctrl_handler_free(ov7740->subdev.ctrl_handler); 1175 media_entity_cleanup(&ov7740->subdev.entity); 1176 v4l2_async_unregister_subdev(sd); 1177 ov7740_free_controls(ov7740); 1178 1179 pm_runtime_get_sync(&client->dev); 1180 pm_runtime_disable(&client->dev); 1181 pm_runtime_set_suspended(&client->dev); 1182 pm_runtime_put_noidle(&client->dev); 1183 1184 ov7740_set_power(ov7740, 0); 1185 return 0; 1186 } 1187 1188 static int __maybe_unused ov7740_runtime_suspend(struct device *dev) 1189 { 1190 struct i2c_client *client = to_i2c_client(dev); 1191 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1192 struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev); 1193 1194 ov7740_set_power(ov7740, 0); 1195 1196 return 0; 1197 } 1198 1199 static int __maybe_unused ov7740_runtime_resume(struct device *dev) 1200 { 1201 struct i2c_client *client = to_i2c_client(dev); 1202 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1203 struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev); 1204 1205 return ov7740_set_power(ov7740, 1); 1206 } 1207 1208 static const struct i2c_device_id ov7740_id[] = { 1209 { "ov7740", 0 }, 1210 { /* sentinel */ } 1211 }; 1212 MODULE_DEVICE_TABLE(i2c, ov7740_id); 1213 1214 static const struct dev_pm_ops ov7740_pm_ops = { 1215 SET_RUNTIME_PM_OPS(ov7740_runtime_suspend, ov7740_runtime_resume, NULL) 1216 }; 1217 1218 static const struct of_device_id ov7740_of_match[] = { 1219 {.compatible = "ovti,ov7740", }, 1220 { /* sentinel */ }, 1221 }; 1222 MODULE_DEVICE_TABLE(of, ov7740_of_match); 1223 1224 static struct i2c_driver ov7740_i2c_driver = { 1225 .driver = { 1226 .name = "ov7740", 1227 .pm = &ov7740_pm_ops, 1228 .of_match_table = of_match_ptr(ov7740_of_match), 1229 }, 1230 .probe = ov7740_probe, 1231 .remove = ov7740_remove, 1232 .id_table = ov7740_id, 1233 }; 1234 module_i2c_driver(ov7740_i2c_driver); 1235 1236 MODULE_DESCRIPTION("The V4L2 driver for Omnivision 7740 sensor"); 1237 MODULE_AUTHOR("Songjun Wu <songjun.wu@atmel.com>"); 1238 MODULE_LICENSE("GPL v2"); 1239