1d30bb512STodor Tomov // SPDX-License-Identifier: GPL-2.0 2d30bb512STodor Tomov /* 3d30bb512STodor Tomov * Driver for the OV7251 camera sensor. 4d30bb512STodor Tomov * 5d30bb512STodor Tomov * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. 6d30bb512STodor Tomov * Copyright (c) 2017-2018, Linaro Ltd. 7d30bb512STodor Tomov */ 8d30bb512STodor Tomov 9d30bb512STodor Tomov #include <linux/bitops.h> 10d30bb512STodor Tomov #include <linux/clk.h> 11d30bb512STodor Tomov #include <linux/delay.h> 12d30bb512STodor Tomov #include <linux/device.h> 13d30bb512STodor Tomov #include <linux/gpio/consumer.h> 14d30bb512STodor Tomov #include <linux/i2c.h> 15d30bb512STodor Tomov #include <linux/init.h> 16d30bb512STodor Tomov #include <linux/module.h> 176766cff6SDaniel Scally #include <linux/mod_devicetable.h> 18d30bb512STodor Tomov #include <linux/regulator/consumer.h> 19d30bb512STodor Tomov #include <linux/slab.h> 20d30bb512STodor Tomov #include <linux/types.h> 21d30bb512STodor Tomov #include <media/v4l2-ctrls.h> 22d30bb512STodor Tomov #include <media/v4l2-fwnode.h> 23d30bb512STodor Tomov #include <media/v4l2-subdev.h> 24d30bb512STodor Tomov 25d30bb512STodor Tomov #define OV7251_SC_MODE_SELECT 0x0100 26d30bb512STodor Tomov #define OV7251_SC_MODE_SELECT_SW_STANDBY 0x0 27d30bb512STodor Tomov #define OV7251_SC_MODE_SELECT_STREAMING 0x1 28d30bb512STodor Tomov 29d30bb512STodor Tomov #define OV7251_CHIP_ID_HIGH 0x300a 30d30bb512STodor Tomov #define OV7251_CHIP_ID_HIGH_BYTE 0x77 31d30bb512STodor Tomov #define OV7251_CHIP_ID_LOW 0x300b 32d30bb512STodor Tomov #define OV7251_CHIP_ID_LOW_BYTE 0x50 33d30bb512STodor Tomov #define OV7251_SC_GP_IO_IN1 0x3029 34d30bb512STodor Tomov #define OV7251_AEC_EXPO_0 0x3500 35d30bb512STodor Tomov #define OV7251_AEC_EXPO_1 0x3501 36d30bb512STodor Tomov #define OV7251_AEC_EXPO_2 0x3502 37d30bb512STodor Tomov #define OV7251_AEC_AGC_ADJ_0 0x350a 38d30bb512STodor Tomov #define OV7251_AEC_AGC_ADJ_1 0x350b 39d30bb512STodor Tomov #define OV7251_TIMING_FORMAT1 0x3820 40d30bb512STodor Tomov #define OV7251_TIMING_FORMAT1_VFLIP BIT(2) 41d30bb512STodor Tomov #define OV7251_TIMING_FORMAT2 0x3821 42d30bb512STodor Tomov #define OV7251_TIMING_FORMAT2_MIRROR BIT(2) 43d30bb512STodor Tomov #define OV7251_PRE_ISP_00 0x5e00 44d30bb512STodor Tomov #define OV7251_PRE_ISP_00_TEST_PATTERN BIT(7) 45*df057b0dSDaniel Scally #define OV7251_PLL1_PRE_DIV_REG 0x30b4 46*df057b0dSDaniel Scally #define OV7251_PLL1_MULT_REG 0x30b3 47*df057b0dSDaniel Scally #define OV7251_PLL1_DIVIDER_REG 0x30b1 48*df057b0dSDaniel Scally #define OV7251_PLL1_PIX_DIV_REG 0x30b0 49*df057b0dSDaniel Scally #define OV7251_PLL1_MIPI_DIV_REG 0x30b5 50*df057b0dSDaniel Scally #define OV7251_PLL2_PRE_DIV_REG 0x3098 51*df057b0dSDaniel Scally #define OV7251_PLL2_MULT_REG 0x3099 52*df057b0dSDaniel Scally #define OV7251_PLL2_DIVIDER_REG 0x309d 53*df057b0dSDaniel Scally #define OV7251_PLL2_SYS_DIV_REG 0x309a 54*df057b0dSDaniel Scally #define OV7251_PLL2_ADC_DIV_REG 0x309b 55d30bb512STodor Tomov 56d30bb512STodor Tomov struct reg_value { 57d30bb512STodor Tomov u16 reg; 58d30bb512STodor Tomov u8 val; 59d30bb512STodor Tomov }; 60d30bb512STodor Tomov 61d30bb512STodor Tomov struct ov7251_mode_info { 62d30bb512STodor Tomov u32 width; 63d30bb512STodor Tomov u32 height; 64d30bb512STodor Tomov const struct reg_value *data; 65d30bb512STodor Tomov u32 data_size; 66d30bb512STodor Tomov u32 pixel_clock; 67d30bb512STodor Tomov u32 link_freq; 68d30bb512STodor Tomov u16 exposure_max; 69d30bb512STodor Tomov u16 exposure_def; 70d30bb512STodor Tomov struct v4l2_fract timeperframe; 71d30bb512STodor Tomov }; 72d30bb512STodor Tomov 73*df057b0dSDaniel Scally struct ov7251_pll1_cfg { 74*df057b0dSDaniel Scally unsigned int pre_div; 75*df057b0dSDaniel Scally unsigned int mult; 76*df057b0dSDaniel Scally unsigned int div; 77*df057b0dSDaniel Scally unsigned int pix_div; 78*df057b0dSDaniel Scally unsigned int mipi_div; 79*df057b0dSDaniel Scally }; 80*df057b0dSDaniel Scally 81*df057b0dSDaniel Scally struct ov7251_pll2_cfg { 82*df057b0dSDaniel Scally unsigned int pre_div; 83*df057b0dSDaniel Scally unsigned int mult; 84*df057b0dSDaniel Scally unsigned int div; 85*df057b0dSDaniel Scally unsigned int sys_div; 86*df057b0dSDaniel Scally unsigned int adc_div; 87*df057b0dSDaniel Scally }; 88*df057b0dSDaniel Scally 89*df057b0dSDaniel Scally /* 90*df057b0dSDaniel Scally * Rubbish ordering, but only PLL1 needs to have a separate configuration per 91*df057b0dSDaniel Scally * link frequency and the array member needs to be last. 92*df057b0dSDaniel Scally */ 93*df057b0dSDaniel Scally struct ov7251_pll_cfgs { 94*df057b0dSDaniel Scally const struct ov7251_pll2_cfg *pll2; 95*df057b0dSDaniel Scally const struct ov7251_pll1_cfg *pll1[]; 96*df057b0dSDaniel Scally }; 97*df057b0dSDaniel Scally 98*df057b0dSDaniel Scally enum xclk_rate { 99*df057b0dSDaniel Scally OV7251_24_MHZ, 100*df057b0dSDaniel Scally OV7251_NUM_SUPPORTED_RATES 101*df057b0dSDaniel Scally }; 102*df057b0dSDaniel Scally 103cc125aaaSDaniel Scally enum supported_link_freqs { 104cc125aaaSDaniel Scally OV7251_LINK_FREQ_240_MHZ, 105cc125aaaSDaniel Scally OV7251_NUM_SUPPORTED_LINK_FREQS 106cc125aaaSDaniel Scally }; 107cc125aaaSDaniel Scally 108d30bb512STodor Tomov struct ov7251 { 109d30bb512STodor Tomov struct i2c_client *i2c_client; 110d30bb512STodor Tomov struct device *dev; 111d30bb512STodor Tomov struct v4l2_subdev sd; 112d30bb512STodor Tomov struct media_pad pad; 113d30bb512STodor Tomov struct v4l2_fwnode_endpoint ep; 114d30bb512STodor Tomov struct v4l2_mbus_framefmt fmt; 115d30bb512STodor Tomov struct v4l2_rect crop; 116d30bb512STodor Tomov struct clk *xclk; 117d30bb512STodor Tomov u32 xclk_freq; 118d30bb512STodor Tomov 119d30bb512STodor Tomov struct regulator *io_regulator; 120d30bb512STodor Tomov struct regulator *core_regulator; 121d30bb512STodor Tomov struct regulator *analog_regulator; 122d30bb512STodor Tomov 123*df057b0dSDaniel Scally const struct ov7251_pll_cfgs *pll_cfgs; 124cc125aaaSDaniel Scally enum supported_link_freqs link_freq_idx; 125d30bb512STodor Tomov const struct ov7251_mode_info *current_mode; 126d30bb512STodor Tomov 127d30bb512STodor Tomov struct v4l2_ctrl_handler ctrls; 128d30bb512STodor Tomov struct v4l2_ctrl *pixel_clock; 129d30bb512STodor Tomov struct v4l2_ctrl *link_freq; 130d30bb512STodor Tomov struct v4l2_ctrl *exposure; 131d30bb512STodor Tomov struct v4l2_ctrl *gain; 132d30bb512STodor Tomov 133d30bb512STodor Tomov /* Cached register values */ 134d30bb512STodor Tomov u8 aec_pk_manual; 135d30bb512STodor Tomov u8 pre_isp_00; 136d30bb512STodor Tomov u8 timing_format1; 137d30bb512STodor Tomov u8 timing_format2; 138d30bb512STodor Tomov 139d30bb512STodor Tomov struct mutex lock; /* lock to protect power state, ctrls and mode */ 140d30bb512STodor Tomov bool power_on; 141d30bb512STodor Tomov 142d30bb512STodor Tomov struct gpio_desc *enable_gpio; 143d30bb512STodor Tomov }; 144d30bb512STodor Tomov 145d30bb512STodor Tomov static inline struct ov7251 *to_ov7251(struct v4l2_subdev *sd) 146d30bb512STodor Tomov { 147d30bb512STodor Tomov return container_of(sd, struct ov7251, sd); 148d30bb512STodor Tomov } 149d30bb512STodor Tomov 150*df057b0dSDaniel Scally static const struct ov7251_pll1_cfg ov7251_pll1_cfg_24_mhz_240_mhz = { 151*df057b0dSDaniel Scally .pre_div = 0x03, 152*df057b0dSDaniel Scally .mult = 0x64, 153*df057b0dSDaniel Scally .div = 0x01, 154*df057b0dSDaniel Scally .pix_div = 0x0a, 155*df057b0dSDaniel Scally .mipi_div = 0x05, 156*df057b0dSDaniel Scally }; 157*df057b0dSDaniel Scally 158*df057b0dSDaniel Scally static const struct ov7251_pll2_cfg ov7251_pll2_cfg_24_mhz = { 159*df057b0dSDaniel Scally .pre_div = 0x04, 160*df057b0dSDaniel Scally .mult = 0x28, 161*df057b0dSDaniel Scally .div = 0x00, 162*df057b0dSDaniel Scally .sys_div = 0x05, 163*df057b0dSDaniel Scally .adc_div = 0x04, 164*df057b0dSDaniel Scally }; 165*df057b0dSDaniel Scally 166*df057b0dSDaniel Scally static const struct ov7251_pll_cfgs ov7251_pll_cfgs_24_mhz = { 167*df057b0dSDaniel Scally .pll2 = &ov7251_pll2_cfg_24_mhz, 168*df057b0dSDaniel Scally .pll1 = { 169*df057b0dSDaniel Scally [OV7251_LINK_FREQ_240_MHZ] = &ov7251_pll1_cfg_24_mhz_240_mhz, 170*df057b0dSDaniel Scally }, 171*df057b0dSDaniel Scally }; 172*df057b0dSDaniel Scally 173*df057b0dSDaniel Scally static const struct ov7251_pll_cfgs *ov7251_pll_cfgs[] = { 174*df057b0dSDaniel Scally [OV7251_24_MHZ] = &ov7251_pll_cfgs_24_mhz, 175*df057b0dSDaniel Scally }; 176*df057b0dSDaniel Scally 177d30bb512STodor Tomov static const struct reg_value ov7251_global_init_setting[] = { 178d30bb512STodor Tomov { 0x0103, 0x01 }, 179d30bb512STodor Tomov { 0x303b, 0x02 }, 180d30bb512STodor Tomov }; 181d30bb512STodor Tomov 182d30bb512STodor Tomov static const struct reg_value ov7251_setting_vga_30fps[] = { 183d30bb512STodor Tomov { 0x3005, 0x00 }, 184d30bb512STodor Tomov { 0x3012, 0xc0 }, 185d30bb512STodor Tomov { 0x3013, 0xd2 }, 186d30bb512STodor Tomov { 0x3014, 0x04 }, 187d30bb512STodor Tomov { 0x3016, 0xf0 }, 188d30bb512STodor Tomov { 0x3017, 0xf0 }, 189d30bb512STodor Tomov { 0x3018, 0xf0 }, 190d30bb512STodor Tomov { 0x301a, 0xf0 }, 191d30bb512STodor Tomov { 0x301b, 0xf0 }, 192d30bb512STodor Tomov { 0x301c, 0xf0 }, 193d30bb512STodor Tomov { 0x3023, 0x05 }, 194d30bb512STodor Tomov { 0x3037, 0xf0 }, 195d30bb512STodor Tomov { 0x3106, 0xda }, 196d30bb512STodor Tomov { 0x3503, 0x07 }, 197d30bb512STodor Tomov { 0x3509, 0x10 }, 198d30bb512STodor Tomov { 0x3600, 0x1c }, 199d30bb512STodor Tomov { 0x3602, 0x62 }, 200d30bb512STodor Tomov { 0x3620, 0xb7 }, 201d30bb512STodor Tomov { 0x3622, 0x04 }, 202d30bb512STodor Tomov { 0x3626, 0x21 }, 203d30bb512STodor Tomov { 0x3627, 0x30 }, 204d30bb512STodor Tomov { 0x3630, 0x44 }, 205d30bb512STodor Tomov { 0x3631, 0x35 }, 206d30bb512STodor Tomov { 0x3634, 0x60 }, 207d30bb512STodor Tomov { 0x3636, 0x00 }, 208d30bb512STodor Tomov { 0x3662, 0x01 }, 209d30bb512STodor Tomov { 0x3663, 0x70 }, 210d30bb512STodor Tomov { 0x3664, 0x50 }, 211d30bb512STodor Tomov { 0x3666, 0x0a }, 212d30bb512STodor Tomov { 0x3669, 0x1a }, 213d30bb512STodor Tomov { 0x366a, 0x00 }, 214d30bb512STodor Tomov { 0x366b, 0x50 }, 215d30bb512STodor Tomov { 0x3673, 0x01 }, 216d30bb512STodor Tomov { 0x3674, 0xff }, 217d30bb512STodor Tomov { 0x3675, 0x03 }, 218d30bb512STodor Tomov { 0x3705, 0xc1 }, 219d30bb512STodor Tomov { 0x3709, 0x40 }, 220d30bb512STodor Tomov { 0x373c, 0x08 }, 221d30bb512STodor Tomov { 0x3742, 0x00 }, 222d30bb512STodor Tomov { 0x3757, 0xb3 }, 223d30bb512STodor Tomov { 0x3788, 0x00 }, 224d30bb512STodor Tomov { 0x37a8, 0x01 }, 225d30bb512STodor Tomov { 0x37a9, 0xc0 }, 226d30bb512STodor Tomov { 0x3800, 0x00 }, 227d30bb512STodor Tomov { 0x3801, 0x04 }, 228d30bb512STodor Tomov { 0x3802, 0x00 }, 229d30bb512STodor Tomov { 0x3803, 0x04 }, 230d30bb512STodor Tomov { 0x3804, 0x02 }, 231d30bb512STodor Tomov { 0x3805, 0x8b }, 232d30bb512STodor Tomov { 0x3806, 0x01 }, 233d30bb512STodor Tomov { 0x3807, 0xeb }, 234d30bb512STodor Tomov { 0x3808, 0x02 }, /* width high */ 235d30bb512STodor Tomov { 0x3809, 0x80 }, /* width low */ 236d30bb512STodor Tomov { 0x380a, 0x01 }, /* height high */ 237d30bb512STodor Tomov { 0x380b, 0xe0 }, /* height low */ 238d30bb512STodor Tomov { 0x380c, 0x03 }, /* total horiz timing high */ 239d30bb512STodor Tomov { 0x380d, 0xa0 }, /* total horiz timing low */ 240d30bb512STodor Tomov { 0x380e, 0x06 }, /* total vertical timing high */ 241d30bb512STodor Tomov { 0x380f, 0xbc }, /* total vertical timing low */ 242d30bb512STodor Tomov { 0x3810, 0x00 }, 243d30bb512STodor Tomov { 0x3811, 0x04 }, 244d30bb512STodor Tomov { 0x3812, 0x00 }, 245d30bb512STodor Tomov { 0x3813, 0x05 }, 246d30bb512STodor Tomov { 0x3814, 0x11 }, 247d30bb512STodor Tomov { 0x3815, 0x11 }, 248d30bb512STodor Tomov { 0x3820, 0x40 }, 249d30bb512STodor Tomov { 0x3821, 0x00 }, 250d30bb512STodor Tomov { 0x382f, 0x0e }, 251d30bb512STodor Tomov { 0x3832, 0x00 }, 252d30bb512STodor Tomov { 0x3833, 0x05 }, 253d30bb512STodor Tomov { 0x3834, 0x00 }, 254d30bb512STodor Tomov { 0x3835, 0x0c }, 255d30bb512STodor Tomov { 0x3837, 0x00 }, 256d30bb512STodor Tomov { 0x3b80, 0x00 }, 257d30bb512STodor Tomov { 0x3b81, 0xa5 }, 258d30bb512STodor Tomov { 0x3b82, 0x10 }, 259d30bb512STodor Tomov { 0x3b83, 0x00 }, 260d30bb512STodor Tomov { 0x3b84, 0x08 }, 261d30bb512STodor Tomov { 0x3b85, 0x00 }, 262d30bb512STodor Tomov { 0x3b86, 0x01 }, 263d30bb512STodor Tomov { 0x3b87, 0x00 }, 264d30bb512STodor Tomov { 0x3b88, 0x00 }, 265d30bb512STodor Tomov { 0x3b89, 0x00 }, 266d30bb512STodor Tomov { 0x3b8a, 0x00 }, 267d30bb512STodor Tomov { 0x3b8b, 0x05 }, 268d30bb512STodor Tomov { 0x3b8c, 0x00 }, 269d30bb512STodor Tomov { 0x3b8d, 0x00 }, 270d30bb512STodor Tomov { 0x3b8e, 0x00 }, 271d30bb512STodor Tomov { 0x3b8f, 0x1a }, 272d30bb512STodor Tomov { 0x3b94, 0x05 }, 273d30bb512STodor Tomov { 0x3b95, 0xf2 }, 274d30bb512STodor Tomov { 0x3b96, 0x40 }, 275d30bb512STodor Tomov { 0x3c00, 0x89 }, 276d30bb512STodor Tomov { 0x3c01, 0x63 }, 277d30bb512STodor Tomov { 0x3c02, 0x01 }, 278d30bb512STodor Tomov { 0x3c03, 0x00 }, 279d30bb512STodor Tomov { 0x3c04, 0x00 }, 280d30bb512STodor Tomov { 0x3c05, 0x03 }, 281d30bb512STodor Tomov { 0x3c06, 0x00 }, 282d30bb512STodor Tomov { 0x3c07, 0x06 }, 283d30bb512STodor Tomov { 0x3c0c, 0x01 }, 284d30bb512STodor Tomov { 0x3c0d, 0xd0 }, 285d30bb512STodor Tomov { 0x3c0e, 0x02 }, 286d30bb512STodor Tomov { 0x3c0f, 0x0a }, 287d30bb512STodor Tomov { 0x4001, 0x42 }, 288d30bb512STodor Tomov { 0x4004, 0x04 }, 289d30bb512STodor Tomov { 0x4005, 0x00 }, 290d30bb512STodor Tomov { 0x404e, 0x01 }, 291d30bb512STodor Tomov { 0x4300, 0xff }, 292d30bb512STodor Tomov { 0x4301, 0x00 }, 293d30bb512STodor Tomov { 0x4315, 0x00 }, 294d30bb512STodor Tomov { 0x4501, 0x48 }, 295d30bb512STodor Tomov { 0x4600, 0x00 }, 296d30bb512STodor Tomov { 0x4601, 0x4e }, 297d30bb512STodor Tomov { 0x4801, 0x0f }, 298d30bb512STodor Tomov { 0x4806, 0x0f }, 299d30bb512STodor Tomov { 0x4819, 0xaa }, 300d30bb512STodor Tomov { 0x4823, 0x3e }, 301d30bb512STodor Tomov { 0x4837, 0x19 }, 302d30bb512STodor Tomov { 0x4a0d, 0x00 }, 303d30bb512STodor Tomov { 0x4a47, 0x7f }, 304d30bb512STodor Tomov { 0x4a49, 0xf0 }, 305d30bb512STodor Tomov { 0x4a4b, 0x30 }, 306d30bb512STodor Tomov { 0x5000, 0x85 }, 307d30bb512STodor Tomov { 0x5001, 0x80 }, 308d30bb512STodor Tomov }; 309d30bb512STodor Tomov 310d30bb512STodor Tomov static const struct reg_value ov7251_setting_vga_60fps[] = { 311d30bb512STodor Tomov { 0x3005, 0x00 }, 312d30bb512STodor Tomov { 0x3012, 0xc0 }, 313d30bb512STodor Tomov { 0x3013, 0xd2 }, 314d30bb512STodor Tomov { 0x3014, 0x04 }, 315d30bb512STodor Tomov { 0x3016, 0x10 }, 316d30bb512STodor Tomov { 0x3017, 0x00 }, 317d30bb512STodor Tomov { 0x3018, 0x00 }, 318d30bb512STodor Tomov { 0x301a, 0x00 }, 319d30bb512STodor Tomov { 0x301b, 0x00 }, 320d30bb512STodor Tomov { 0x301c, 0x00 }, 321d30bb512STodor Tomov { 0x3023, 0x05 }, 322d30bb512STodor Tomov { 0x3037, 0xf0 }, 323d30bb512STodor Tomov { 0x3106, 0xda }, 324d30bb512STodor Tomov { 0x3503, 0x07 }, 325d30bb512STodor Tomov { 0x3509, 0x10 }, 326d30bb512STodor Tomov { 0x3600, 0x1c }, 327d30bb512STodor Tomov { 0x3602, 0x62 }, 328d30bb512STodor Tomov { 0x3620, 0xb7 }, 329d30bb512STodor Tomov { 0x3622, 0x04 }, 330d30bb512STodor Tomov { 0x3626, 0x21 }, 331d30bb512STodor Tomov { 0x3627, 0x30 }, 332d30bb512STodor Tomov { 0x3630, 0x44 }, 333d30bb512STodor Tomov { 0x3631, 0x35 }, 334d30bb512STodor Tomov { 0x3634, 0x60 }, 335d30bb512STodor Tomov { 0x3636, 0x00 }, 336d30bb512STodor Tomov { 0x3662, 0x01 }, 337d30bb512STodor Tomov { 0x3663, 0x70 }, 338d30bb512STodor Tomov { 0x3664, 0x50 }, 339d30bb512STodor Tomov { 0x3666, 0x0a }, 340d30bb512STodor Tomov { 0x3669, 0x1a }, 341d30bb512STodor Tomov { 0x366a, 0x00 }, 342d30bb512STodor Tomov { 0x366b, 0x50 }, 343d30bb512STodor Tomov { 0x3673, 0x01 }, 344d30bb512STodor Tomov { 0x3674, 0xff }, 345d30bb512STodor Tomov { 0x3675, 0x03 }, 346d30bb512STodor Tomov { 0x3705, 0xc1 }, 347d30bb512STodor Tomov { 0x3709, 0x40 }, 348d30bb512STodor Tomov { 0x373c, 0x08 }, 349d30bb512STodor Tomov { 0x3742, 0x00 }, 350d30bb512STodor Tomov { 0x3757, 0xb3 }, 351d30bb512STodor Tomov { 0x3788, 0x00 }, 352d30bb512STodor Tomov { 0x37a8, 0x01 }, 353d30bb512STodor Tomov { 0x37a9, 0xc0 }, 354d30bb512STodor Tomov { 0x3800, 0x00 }, 355d30bb512STodor Tomov { 0x3801, 0x04 }, 356d30bb512STodor Tomov { 0x3802, 0x00 }, 357d30bb512STodor Tomov { 0x3803, 0x04 }, 358d30bb512STodor Tomov { 0x3804, 0x02 }, 359d30bb512STodor Tomov { 0x3805, 0x8b }, 360d30bb512STodor Tomov { 0x3806, 0x01 }, 361d30bb512STodor Tomov { 0x3807, 0xeb }, 362d30bb512STodor Tomov { 0x3808, 0x02 }, /* width high */ 363d30bb512STodor Tomov { 0x3809, 0x80 }, /* width low */ 364d30bb512STodor Tomov { 0x380a, 0x01 }, /* height high */ 365d30bb512STodor Tomov { 0x380b, 0xe0 }, /* height low */ 366d30bb512STodor Tomov { 0x380c, 0x03 }, /* total horiz timing high */ 367d30bb512STodor Tomov { 0x380d, 0xa0 }, /* total horiz timing low */ 368d30bb512STodor Tomov { 0x380e, 0x03 }, /* total vertical timing high */ 369d30bb512STodor Tomov { 0x380f, 0x5c }, /* total vertical timing low */ 370d30bb512STodor Tomov { 0x3810, 0x00 }, 371d30bb512STodor Tomov { 0x3811, 0x04 }, 372d30bb512STodor Tomov { 0x3812, 0x00 }, 373d30bb512STodor Tomov { 0x3813, 0x05 }, 374d30bb512STodor Tomov { 0x3814, 0x11 }, 375d30bb512STodor Tomov { 0x3815, 0x11 }, 376d30bb512STodor Tomov { 0x3820, 0x40 }, 377d30bb512STodor Tomov { 0x3821, 0x00 }, 378d30bb512STodor Tomov { 0x382f, 0x0e }, 379d30bb512STodor Tomov { 0x3832, 0x00 }, 380d30bb512STodor Tomov { 0x3833, 0x05 }, 381d30bb512STodor Tomov { 0x3834, 0x00 }, 382d30bb512STodor Tomov { 0x3835, 0x0c }, 383d30bb512STodor Tomov { 0x3837, 0x00 }, 384d30bb512STodor Tomov { 0x3b80, 0x00 }, 385d30bb512STodor Tomov { 0x3b81, 0xa5 }, 386d30bb512STodor Tomov { 0x3b82, 0x10 }, 387d30bb512STodor Tomov { 0x3b83, 0x00 }, 388d30bb512STodor Tomov { 0x3b84, 0x08 }, 389d30bb512STodor Tomov { 0x3b85, 0x00 }, 390d30bb512STodor Tomov { 0x3b86, 0x01 }, 391d30bb512STodor Tomov { 0x3b87, 0x00 }, 392d30bb512STodor Tomov { 0x3b88, 0x00 }, 393d30bb512STodor Tomov { 0x3b89, 0x00 }, 394d30bb512STodor Tomov { 0x3b8a, 0x00 }, 395d30bb512STodor Tomov { 0x3b8b, 0x05 }, 396d30bb512STodor Tomov { 0x3b8c, 0x00 }, 397d30bb512STodor Tomov { 0x3b8d, 0x00 }, 398d30bb512STodor Tomov { 0x3b8e, 0x00 }, 399d30bb512STodor Tomov { 0x3b8f, 0x1a }, 400d30bb512STodor Tomov { 0x3b94, 0x05 }, 401d30bb512STodor Tomov { 0x3b95, 0xf2 }, 402d30bb512STodor Tomov { 0x3b96, 0x40 }, 403d30bb512STodor Tomov { 0x3c00, 0x89 }, 404d30bb512STodor Tomov { 0x3c01, 0x63 }, 405d30bb512STodor Tomov { 0x3c02, 0x01 }, 406d30bb512STodor Tomov { 0x3c03, 0x00 }, 407d30bb512STodor Tomov { 0x3c04, 0x00 }, 408d30bb512STodor Tomov { 0x3c05, 0x03 }, 409d30bb512STodor Tomov { 0x3c06, 0x00 }, 410d30bb512STodor Tomov { 0x3c07, 0x06 }, 411d30bb512STodor Tomov { 0x3c0c, 0x01 }, 412d30bb512STodor Tomov { 0x3c0d, 0xd0 }, 413d30bb512STodor Tomov { 0x3c0e, 0x02 }, 414d30bb512STodor Tomov { 0x3c0f, 0x0a }, 415d30bb512STodor Tomov { 0x4001, 0x42 }, 416d30bb512STodor Tomov { 0x4004, 0x04 }, 417d30bb512STodor Tomov { 0x4005, 0x00 }, 418d30bb512STodor Tomov { 0x404e, 0x01 }, 419d30bb512STodor Tomov { 0x4300, 0xff }, 420d30bb512STodor Tomov { 0x4301, 0x00 }, 421d30bb512STodor Tomov { 0x4315, 0x00 }, 422d30bb512STodor Tomov { 0x4501, 0x48 }, 423d30bb512STodor Tomov { 0x4600, 0x00 }, 424d30bb512STodor Tomov { 0x4601, 0x4e }, 425d30bb512STodor Tomov { 0x4801, 0x0f }, 426d30bb512STodor Tomov { 0x4806, 0x0f }, 427d30bb512STodor Tomov { 0x4819, 0xaa }, 428d30bb512STodor Tomov { 0x4823, 0x3e }, 429d30bb512STodor Tomov { 0x4837, 0x19 }, 430d30bb512STodor Tomov { 0x4a0d, 0x00 }, 431d30bb512STodor Tomov { 0x4a47, 0x7f }, 432d30bb512STodor Tomov { 0x4a49, 0xf0 }, 433d30bb512STodor Tomov { 0x4a4b, 0x30 }, 434d30bb512STodor Tomov { 0x5000, 0x85 }, 435d30bb512STodor Tomov { 0x5001, 0x80 }, 436d30bb512STodor Tomov }; 437d30bb512STodor Tomov 438d30bb512STodor Tomov static const struct reg_value ov7251_setting_vga_90fps[] = { 439d30bb512STodor Tomov { 0x3005, 0x00 }, 440d30bb512STodor Tomov { 0x3012, 0xc0 }, 441d30bb512STodor Tomov { 0x3013, 0xd2 }, 442d30bb512STodor Tomov { 0x3014, 0x04 }, 443d30bb512STodor Tomov { 0x3016, 0x10 }, 444d30bb512STodor Tomov { 0x3017, 0x00 }, 445d30bb512STodor Tomov { 0x3018, 0x00 }, 446d30bb512STodor Tomov { 0x301a, 0x00 }, 447d30bb512STodor Tomov { 0x301b, 0x00 }, 448d30bb512STodor Tomov { 0x301c, 0x00 }, 449d30bb512STodor Tomov { 0x3023, 0x05 }, 450d30bb512STodor Tomov { 0x3037, 0xf0 }, 451d30bb512STodor Tomov { 0x3106, 0xda }, 452d30bb512STodor Tomov { 0x3503, 0x07 }, 453d30bb512STodor Tomov { 0x3509, 0x10 }, 454d30bb512STodor Tomov { 0x3600, 0x1c }, 455d30bb512STodor Tomov { 0x3602, 0x62 }, 456d30bb512STodor Tomov { 0x3620, 0xb7 }, 457d30bb512STodor Tomov { 0x3622, 0x04 }, 458d30bb512STodor Tomov { 0x3626, 0x21 }, 459d30bb512STodor Tomov { 0x3627, 0x30 }, 460d30bb512STodor Tomov { 0x3630, 0x44 }, 461d30bb512STodor Tomov { 0x3631, 0x35 }, 462d30bb512STodor Tomov { 0x3634, 0x60 }, 463d30bb512STodor Tomov { 0x3636, 0x00 }, 464d30bb512STodor Tomov { 0x3662, 0x01 }, 465d30bb512STodor Tomov { 0x3663, 0x70 }, 466d30bb512STodor Tomov { 0x3664, 0x50 }, 467d30bb512STodor Tomov { 0x3666, 0x0a }, 468d30bb512STodor Tomov { 0x3669, 0x1a }, 469d30bb512STodor Tomov { 0x366a, 0x00 }, 470d30bb512STodor Tomov { 0x366b, 0x50 }, 471d30bb512STodor Tomov { 0x3673, 0x01 }, 472d30bb512STodor Tomov { 0x3674, 0xff }, 473d30bb512STodor Tomov { 0x3675, 0x03 }, 474d30bb512STodor Tomov { 0x3705, 0xc1 }, 475d30bb512STodor Tomov { 0x3709, 0x40 }, 476d30bb512STodor Tomov { 0x373c, 0x08 }, 477d30bb512STodor Tomov { 0x3742, 0x00 }, 478d30bb512STodor Tomov { 0x3757, 0xb3 }, 479d30bb512STodor Tomov { 0x3788, 0x00 }, 480d30bb512STodor Tomov { 0x37a8, 0x01 }, 481d30bb512STodor Tomov { 0x37a9, 0xc0 }, 482d30bb512STodor Tomov { 0x3800, 0x00 }, 483d30bb512STodor Tomov { 0x3801, 0x04 }, 484d30bb512STodor Tomov { 0x3802, 0x00 }, 485d30bb512STodor Tomov { 0x3803, 0x04 }, 486d30bb512STodor Tomov { 0x3804, 0x02 }, 487d30bb512STodor Tomov { 0x3805, 0x8b }, 488d30bb512STodor Tomov { 0x3806, 0x01 }, 489d30bb512STodor Tomov { 0x3807, 0xeb }, 490d30bb512STodor Tomov { 0x3808, 0x02 }, /* width high */ 491d30bb512STodor Tomov { 0x3809, 0x80 }, /* width low */ 492d30bb512STodor Tomov { 0x380a, 0x01 }, /* height high */ 493d30bb512STodor Tomov { 0x380b, 0xe0 }, /* height low */ 494d30bb512STodor Tomov { 0x380c, 0x03 }, /* total horiz timing high */ 495d30bb512STodor Tomov { 0x380d, 0xa0 }, /* total horiz timing low */ 496d30bb512STodor Tomov { 0x380e, 0x02 }, /* total vertical timing high */ 497d30bb512STodor Tomov { 0x380f, 0x3c }, /* total vertical timing low */ 498d30bb512STodor Tomov { 0x3810, 0x00 }, 499d30bb512STodor Tomov { 0x3811, 0x04 }, 500d30bb512STodor Tomov { 0x3812, 0x00 }, 501d30bb512STodor Tomov { 0x3813, 0x05 }, 502d30bb512STodor Tomov { 0x3814, 0x11 }, 503d30bb512STodor Tomov { 0x3815, 0x11 }, 504d30bb512STodor Tomov { 0x3820, 0x40 }, 505d30bb512STodor Tomov { 0x3821, 0x00 }, 506d30bb512STodor Tomov { 0x382f, 0x0e }, 507d30bb512STodor Tomov { 0x3832, 0x00 }, 508d30bb512STodor Tomov { 0x3833, 0x05 }, 509d30bb512STodor Tomov { 0x3834, 0x00 }, 510d30bb512STodor Tomov { 0x3835, 0x0c }, 511d30bb512STodor Tomov { 0x3837, 0x00 }, 512d30bb512STodor Tomov { 0x3b80, 0x00 }, 513d30bb512STodor Tomov { 0x3b81, 0xa5 }, 514d30bb512STodor Tomov { 0x3b82, 0x10 }, 515d30bb512STodor Tomov { 0x3b83, 0x00 }, 516d30bb512STodor Tomov { 0x3b84, 0x08 }, 517d30bb512STodor Tomov { 0x3b85, 0x00 }, 518d30bb512STodor Tomov { 0x3b86, 0x01 }, 519d30bb512STodor Tomov { 0x3b87, 0x00 }, 520d30bb512STodor Tomov { 0x3b88, 0x00 }, 521d30bb512STodor Tomov { 0x3b89, 0x00 }, 522d30bb512STodor Tomov { 0x3b8a, 0x00 }, 523d30bb512STodor Tomov { 0x3b8b, 0x05 }, 524d30bb512STodor Tomov { 0x3b8c, 0x00 }, 525d30bb512STodor Tomov { 0x3b8d, 0x00 }, 526d30bb512STodor Tomov { 0x3b8e, 0x00 }, 527d30bb512STodor Tomov { 0x3b8f, 0x1a }, 528d30bb512STodor Tomov { 0x3b94, 0x05 }, 529d30bb512STodor Tomov { 0x3b95, 0xf2 }, 530d30bb512STodor Tomov { 0x3b96, 0x40 }, 531d30bb512STodor Tomov { 0x3c00, 0x89 }, 532d30bb512STodor Tomov { 0x3c01, 0x63 }, 533d30bb512STodor Tomov { 0x3c02, 0x01 }, 534d30bb512STodor Tomov { 0x3c03, 0x00 }, 535d30bb512STodor Tomov { 0x3c04, 0x00 }, 536d30bb512STodor Tomov { 0x3c05, 0x03 }, 537d30bb512STodor Tomov { 0x3c06, 0x00 }, 538d30bb512STodor Tomov { 0x3c07, 0x06 }, 539d30bb512STodor Tomov { 0x3c0c, 0x01 }, 540d30bb512STodor Tomov { 0x3c0d, 0xd0 }, 541d30bb512STodor Tomov { 0x3c0e, 0x02 }, 542d30bb512STodor Tomov { 0x3c0f, 0x0a }, 543d30bb512STodor Tomov { 0x4001, 0x42 }, 544d30bb512STodor Tomov { 0x4004, 0x04 }, 545d30bb512STodor Tomov { 0x4005, 0x00 }, 546d30bb512STodor Tomov { 0x404e, 0x01 }, 547d30bb512STodor Tomov { 0x4300, 0xff }, 548d30bb512STodor Tomov { 0x4301, 0x00 }, 549d30bb512STodor Tomov { 0x4315, 0x00 }, 550d30bb512STodor Tomov { 0x4501, 0x48 }, 551d30bb512STodor Tomov { 0x4600, 0x00 }, 552d30bb512STodor Tomov { 0x4601, 0x4e }, 553d30bb512STodor Tomov { 0x4801, 0x0f }, 554d30bb512STodor Tomov { 0x4806, 0x0f }, 555d30bb512STodor Tomov { 0x4819, 0xaa }, 556d30bb512STodor Tomov { 0x4823, 0x3e }, 557d30bb512STodor Tomov { 0x4837, 0x19 }, 558d30bb512STodor Tomov { 0x4a0d, 0x00 }, 559d30bb512STodor Tomov { 0x4a47, 0x7f }, 560d30bb512STodor Tomov { 0x4a49, 0xf0 }, 561d30bb512STodor Tomov { 0x4a4b, 0x30 }, 562d30bb512STodor Tomov { 0x5000, 0x85 }, 563d30bb512STodor Tomov { 0x5001, 0x80 }, 564d30bb512STodor Tomov }; 565d30bb512STodor Tomov 566*df057b0dSDaniel Scally static const unsigned long supported_xclk_rates[] = { 567*df057b0dSDaniel Scally [OV7251_24_MHZ] = 24000000, 568*df057b0dSDaniel Scally }; 569*df057b0dSDaniel Scally 570d30bb512STodor Tomov static const s64 link_freq[] = { 5711757b44eSDaniel Scally [OV7251_LINK_FREQ_240_MHZ] = 240000000, 5721757b44eSDaniel Scally }; 5731757b44eSDaniel Scally 5741757b44eSDaniel Scally static const s64 pixel_rates[] = { 5751757b44eSDaniel Scally [OV7251_LINK_FREQ_240_MHZ] = 48000000, 576d30bb512STodor Tomov }; 577d30bb512STodor Tomov 578d30bb512STodor Tomov static const struct ov7251_mode_info ov7251_mode_info_data[] = { 579d30bb512STodor Tomov { 580d30bb512STodor Tomov .width = 640, 581d30bb512STodor Tomov .height = 480, 582d30bb512STodor Tomov .data = ov7251_setting_vga_30fps, 583d30bb512STodor Tomov .data_size = ARRAY_SIZE(ov7251_setting_vga_30fps), 584d30bb512STodor Tomov .exposure_max = 1704, 585d30bb512STodor Tomov .exposure_def = 504, 586d30bb512STodor Tomov .timeperframe = { 587d30bb512STodor Tomov .numerator = 100, 588d30bb512STodor Tomov .denominator = 3000 589d30bb512STodor Tomov } 590d30bb512STodor Tomov }, 591d30bb512STodor Tomov { 592d30bb512STodor Tomov .width = 640, 593d30bb512STodor Tomov .height = 480, 594d30bb512STodor Tomov .data = ov7251_setting_vga_60fps, 595d30bb512STodor Tomov .data_size = ARRAY_SIZE(ov7251_setting_vga_60fps), 596d30bb512STodor Tomov .exposure_max = 840, 597d30bb512STodor Tomov .exposure_def = 504, 598d30bb512STodor Tomov .timeperframe = { 599d30bb512STodor Tomov .numerator = 100, 600d30bb512STodor Tomov .denominator = 6014 601d30bb512STodor Tomov } 602d30bb512STodor Tomov }, 603d30bb512STodor Tomov { 604d30bb512STodor Tomov .width = 640, 605d30bb512STodor Tomov .height = 480, 606d30bb512STodor Tomov .data = ov7251_setting_vga_90fps, 607d30bb512STodor Tomov .data_size = ARRAY_SIZE(ov7251_setting_vga_90fps), 608d30bb512STodor Tomov .exposure_max = 552, 609d30bb512STodor Tomov .exposure_def = 504, 610d30bb512STodor Tomov .timeperframe = { 611d30bb512STodor Tomov .numerator = 100, 612d30bb512STodor Tomov .denominator = 9043 613d30bb512STodor Tomov } 614d30bb512STodor Tomov }, 615d30bb512STodor Tomov }; 616d30bb512STodor Tomov 617d30bb512STodor Tomov static int ov7251_regulators_enable(struct ov7251 *ov7251) 618d30bb512STodor Tomov { 619d30bb512STodor Tomov int ret; 620d30bb512STodor Tomov 621d30bb512STodor Tomov /* OV7251 power up sequence requires core regulator 622d30bb512STodor Tomov * to be enabled not earlier than io regulator 623d30bb512STodor Tomov */ 624d30bb512STodor Tomov 625d30bb512STodor Tomov ret = regulator_enable(ov7251->io_regulator); 626d30bb512STodor Tomov if (ret < 0) { 627d30bb512STodor Tomov dev_err(ov7251->dev, "set io voltage failed\n"); 628d30bb512STodor Tomov return ret; 629d30bb512STodor Tomov } 630d30bb512STodor Tomov 631d30bb512STodor Tomov ret = regulator_enable(ov7251->analog_regulator); 632d30bb512STodor Tomov if (ret) { 633d30bb512STodor Tomov dev_err(ov7251->dev, "set analog voltage failed\n"); 634d30bb512STodor Tomov goto err_disable_io; 635d30bb512STodor Tomov } 636d30bb512STodor Tomov 637d30bb512STodor Tomov ret = regulator_enable(ov7251->core_regulator); 638d30bb512STodor Tomov if (ret) { 639d30bb512STodor Tomov dev_err(ov7251->dev, "set core voltage failed\n"); 640d30bb512STodor Tomov goto err_disable_analog; 641d30bb512STodor Tomov } 642d30bb512STodor Tomov 643d30bb512STodor Tomov return 0; 644d30bb512STodor Tomov 645d30bb512STodor Tomov err_disable_analog: 646d30bb512STodor Tomov regulator_disable(ov7251->analog_regulator); 647d30bb512STodor Tomov 648d30bb512STodor Tomov err_disable_io: 649d30bb512STodor Tomov regulator_disable(ov7251->io_regulator); 650d30bb512STodor Tomov 651d30bb512STodor Tomov return ret; 652d30bb512STodor Tomov } 653d30bb512STodor Tomov 654d30bb512STodor Tomov static void ov7251_regulators_disable(struct ov7251 *ov7251) 655d30bb512STodor Tomov { 656d30bb512STodor Tomov int ret; 657d30bb512STodor Tomov 658d30bb512STodor Tomov ret = regulator_disable(ov7251->core_regulator); 659d30bb512STodor Tomov if (ret < 0) 660d30bb512STodor Tomov dev_err(ov7251->dev, "core regulator disable failed\n"); 661d30bb512STodor Tomov 662d30bb512STodor Tomov ret = regulator_disable(ov7251->analog_regulator); 663d30bb512STodor Tomov if (ret < 0) 664d30bb512STodor Tomov dev_err(ov7251->dev, "analog regulator disable failed\n"); 665d30bb512STodor Tomov 666d30bb512STodor Tomov ret = regulator_disable(ov7251->io_regulator); 667d30bb512STodor Tomov if (ret < 0) 668d30bb512STodor Tomov dev_err(ov7251->dev, "io regulator disable failed\n"); 669d30bb512STodor Tomov } 670d30bb512STodor Tomov 671d30bb512STodor Tomov static int ov7251_write_reg(struct ov7251 *ov7251, u16 reg, u8 val) 672d30bb512STodor Tomov { 673d30bb512STodor Tomov u8 regbuf[3]; 674d30bb512STodor Tomov int ret; 675d30bb512STodor Tomov 676d30bb512STodor Tomov regbuf[0] = reg >> 8; 677d30bb512STodor Tomov regbuf[1] = reg & 0xff; 678d30bb512STodor Tomov regbuf[2] = val; 679d30bb512STodor Tomov 680d30bb512STodor Tomov ret = i2c_master_send(ov7251->i2c_client, regbuf, 3); 681d30bb512STodor Tomov if (ret < 0) { 682d30bb512STodor Tomov dev_err(ov7251->dev, "%s: write reg error %d: reg=%x, val=%x\n", 683d30bb512STodor Tomov __func__, ret, reg, val); 684d30bb512STodor Tomov return ret; 685d30bb512STodor Tomov } 686d30bb512STodor Tomov 687d30bb512STodor Tomov return 0; 688d30bb512STodor Tomov } 689d30bb512STodor Tomov 690d30bb512STodor Tomov static int ov7251_write_seq_regs(struct ov7251 *ov7251, u16 reg, u8 *val, 691d30bb512STodor Tomov u8 num) 692d30bb512STodor Tomov { 693d30bb512STodor Tomov u8 regbuf[5]; 694d30bb512STodor Tomov u8 nregbuf = sizeof(reg) + num * sizeof(*val); 695d30bb512STodor Tomov int ret = 0; 696d30bb512STodor Tomov 697d30bb512STodor Tomov if (nregbuf > sizeof(regbuf)) 698d30bb512STodor Tomov return -EINVAL; 699d30bb512STodor Tomov 700d30bb512STodor Tomov regbuf[0] = reg >> 8; 701d30bb512STodor Tomov regbuf[1] = reg & 0xff; 702d30bb512STodor Tomov 703d30bb512STodor Tomov memcpy(regbuf + 2, val, num); 704d30bb512STodor Tomov 705d30bb512STodor Tomov ret = i2c_master_send(ov7251->i2c_client, regbuf, nregbuf); 706d30bb512STodor Tomov if (ret < 0) { 707d30bb512STodor Tomov dev_err(ov7251->dev, 708d30bb512STodor Tomov "%s: write seq regs error %d: first reg=%x\n", 709d30bb512STodor Tomov __func__, ret, reg); 710d30bb512STodor Tomov return ret; 711d30bb512STodor Tomov } 712d30bb512STodor Tomov 713d30bb512STodor Tomov return 0; 714d30bb512STodor Tomov } 715d30bb512STodor Tomov 716d30bb512STodor Tomov static int ov7251_read_reg(struct ov7251 *ov7251, u16 reg, u8 *val) 717d30bb512STodor Tomov { 718d30bb512STodor Tomov u8 regbuf[2]; 719d30bb512STodor Tomov int ret; 720d30bb512STodor Tomov 721d30bb512STodor Tomov regbuf[0] = reg >> 8; 722d30bb512STodor Tomov regbuf[1] = reg & 0xff; 723d30bb512STodor Tomov 724d30bb512STodor Tomov ret = i2c_master_send(ov7251->i2c_client, regbuf, 2); 725d30bb512STodor Tomov if (ret < 0) { 726d30bb512STodor Tomov dev_err(ov7251->dev, "%s: write reg error %d: reg=%x\n", 727d30bb512STodor Tomov __func__, ret, reg); 728d30bb512STodor Tomov return ret; 729d30bb512STodor Tomov } 730d30bb512STodor Tomov 731d30bb512STodor Tomov ret = i2c_master_recv(ov7251->i2c_client, val, 1); 732d30bb512STodor Tomov if (ret < 0) { 733d30bb512STodor Tomov dev_err(ov7251->dev, "%s: read reg error %d: reg=%x\n", 734d30bb512STodor Tomov __func__, ret, reg); 735d30bb512STodor Tomov return ret; 736d30bb512STodor Tomov } 737d30bb512STodor Tomov 738d30bb512STodor Tomov return 0; 739d30bb512STodor Tomov } 740d30bb512STodor Tomov 741*df057b0dSDaniel Scally static int ov7251_pll_configure(struct ov7251 *ov7251) 742*df057b0dSDaniel Scally { 743*df057b0dSDaniel Scally const struct ov7251_pll_cfgs *configs; 744*df057b0dSDaniel Scally int ret; 745*df057b0dSDaniel Scally 746*df057b0dSDaniel Scally configs = ov7251->pll_cfgs; 747*df057b0dSDaniel Scally 748*df057b0dSDaniel Scally ret = ov7251_write_reg(ov7251, OV7251_PLL1_PRE_DIV_REG, 749*df057b0dSDaniel Scally configs->pll1[ov7251->link_freq_idx]->pre_div); 750*df057b0dSDaniel Scally if (ret < 0) 751*df057b0dSDaniel Scally return ret; 752*df057b0dSDaniel Scally 753*df057b0dSDaniel Scally ret = ov7251_write_reg(ov7251, OV7251_PLL1_MULT_REG, 754*df057b0dSDaniel Scally configs->pll1[ov7251->link_freq_idx]->mult); 755*df057b0dSDaniel Scally if (ret < 0) 756*df057b0dSDaniel Scally return ret; 757*df057b0dSDaniel Scally ret = ov7251_write_reg(ov7251, OV7251_PLL1_DIVIDER_REG, 758*df057b0dSDaniel Scally configs->pll1[ov7251->link_freq_idx]->div); 759*df057b0dSDaniel Scally if (ret < 0) 760*df057b0dSDaniel Scally return ret; 761*df057b0dSDaniel Scally 762*df057b0dSDaniel Scally ret = ov7251_write_reg(ov7251, OV7251_PLL1_PIX_DIV_REG, 763*df057b0dSDaniel Scally configs->pll1[ov7251->link_freq_idx]->pix_div); 764*df057b0dSDaniel Scally if (ret < 0) 765*df057b0dSDaniel Scally return ret; 766*df057b0dSDaniel Scally 767*df057b0dSDaniel Scally ret = ov7251_write_reg(ov7251, OV7251_PLL1_MIPI_DIV_REG, 768*df057b0dSDaniel Scally configs->pll1[ov7251->link_freq_idx]->mipi_div); 769*df057b0dSDaniel Scally if (ret < 0) 770*df057b0dSDaniel Scally return ret; 771*df057b0dSDaniel Scally 772*df057b0dSDaniel Scally ret = ov7251_write_reg(ov7251, OV7251_PLL2_PRE_DIV_REG, 773*df057b0dSDaniel Scally configs->pll2->pre_div); 774*df057b0dSDaniel Scally if (ret < 0) 775*df057b0dSDaniel Scally return ret; 776*df057b0dSDaniel Scally 777*df057b0dSDaniel Scally ret = ov7251_write_reg(ov7251, OV7251_PLL2_MULT_REG, 778*df057b0dSDaniel Scally configs->pll2->mult); 779*df057b0dSDaniel Scally if (ret < 0) 780*df057b0dSDaniel Scally return ret; 781*df057b0dSDaniel Scally 782*df057b0dSDaniel Scally ret = ov7251_write_reg(ov7251, OV7251_PLL2_DIVIDER_REG, 783*df057b0dSDaniel Scally configs->pll2->div); 784*df057b0dSDaniel Scally if (ret < 0) 785*df057b0dSDaniel Scally return ret; 786*df057b0dSDaniel Scally 787*df057b0dSDaniel Scally ret = ov7251_write_reg(ov7251, OV7251_PLL2_SYS_DIV_REG, 788*df057b0dSDaniel Scally configs->pll2->sys_div); 789*df057b0dSDaniel Scally if (ret < 0) 790*df057b0dSDaniel Scally return ret; 791*df057b0dSDaniel Scally 792*df057b0dSDaniel Scally ret = ov7251_write_reg(ov7251, OV7251_PLL2_ADC_DIV_REG, 793*df057b0dSDaniel Scally configs->pll2->adc_div); 794*df057b0dSDaniel Scally 795*df057b0dSDaniel Scally return ret; 796*df057b0dSDaniel Scally } 797*df057b0dSDaniel Scally 798d30bb512STodor Tomov static int ov7251_set_exposure(struct ov7251 *ov7251, s32 exposure) 799d30bb512STodor Tomov { 800d30bb512STodor Tomov u16 reg; 801d30bb512STodor Tomov u8 val[3]; 802d30bb512STodor Tomov 803d30bb512STodor Tomov reg = OV7251_AEC_EXPO_0; 804d30bb512STodor Tomov val[0] = (exposure & 0xf000) >> 12; /* goes to OV7251_AEC_EXPO_0 */ 805d30bb512STodor Tomov val[1] = (exposure & 0x0ff0) >> 4; /* goes to OV7251_AEC_EXPO_1 */ 806d30bb512STodor Tomov val[2] = (exposure & 0x000f) << 4; /* goes to OV7251_AEC_EXPO_2 */ 807d30bb512STodor Tomov 808d30bb512STodor Tomov return ov7251_write_seq_regs(ov7251, reg, val, 3); 809d30bb512STodor Tomov } 810d30bb512STodor Tomov 811d30bb512STodor Tomov static int ov7251_set_gain(struct ov7251 *ov7251, s32 gain) 812d30bb512STodor Tomov { 813d30bb512STodor Tomov u16 reg; 814d30bb512STodor Tomov u8 val[2]; 815d30bb512STodor Tomov 816d30bb512STodor Tomov reg = OV7251_AEC_AGC_ADJ_0; 817d30bb512STodor Tomov val[0] = (gain & 0x0300) >> 8; /* goes to OV7251_AEC_AGC_ADJ_0 */ 818d30bb512STodor Tomov val[1] = gain & 0xff; /* goes to OV7251_AEC_AGC_ADJ_1 */ 819d30bb512STodor Tomov 820d30bb512STodor Tomov return ov7251_write_seq_regs(ov7251, reg, val, 2); 821d30bb512STodor Tomov } 822d30bb512STodor Tomov 823d30bb512STodor Tomov static int ov7251_set_register_array(struct ov7251 *ov7251, 824d30bb512STodor Tomov const struct reg_value *settings, 825d30bb512STodor Tomov unsigned int num_settings) 826d30bb512STodor Tomov { 827d30bb512STodor Tomov unsigned int i; 828d30bb512STodor Tomov int ret; 829d30bb512STodor Tomov 830d30bb512STodor Tomov for (i = 0; i < num_settings; ++i, ++settings) { 831d30bb512STodor Tomov ret = ov7251_write_reg(ov7251, settings->reg, settings->val); 832d30bb512STodor Tomov if (ret < 0) 833d30bb512STodor Tomov return ret; 834d30bb512STodor Tomov } 835d30bb512STodor Tomov 836d30bb512STodor Tomov return 0; 837d30bb512STodor Tomov } 838d30bb512STodor Tomov 839d30bb512STodor Tomov static int ov7251_set_power_on(struct ov7251 *ov7251) 840d30bb512STodor Tomov { 841d30bb512STodor Tomov int ret; 842d30bb512STodor Tomov u32 wait_us; 843d30bb512STodor Tomov 844d30bb512STodor Tomov ret = ov7251_regulators_enable(ov7251); 845d30bb512STodor Tomov if (ret < 0) 846d30bb512STodor Tomov return ret; 847d30bb512STodor Tomov 848d30bb512STodor Tomov ret = clk_prepare_enable(ov7251->xclk); 849d30bb512STodor Tomov if (ret < 0) { 850d30bb512STodor Tomov dev_err(ov7251->dev, "clk prepare enable failed\n"); 851d30bb512STodor Tomov ov7251_regulators_disable(ov7251); 852d30bb512STodor Tomov return ret; 853d30bb512STodor Tomov } 854d30bb512STodor Tomov 855d30bb512STodor Tomov gpiod_set_value_cansleep(ov7251->enable_gpio, 1); 856d30bb512STodor Tomov 857d30bb512STodor Tomov /* wait at least 65536 external clock cycles */ 858d30bb512STodor Tomov wait_us = DIV_ROUND_UP(65536 * 1000, 859d30bb512STodor Tomov DIV_ROUND_UP(ov7251->xclk_freq, 1000)); 860d30bb512STodor Tomov usleep_range(wait_us, wait_us + 1000); 861d30bb512STodor Tomov 862d30bb512STodor Tomov return 0; 863d30bb512STodor Tomov } 864d30bb512STodor Tomov 865d30bb512STodor Tomov static void ov7251_set_power_off(struct ov7251 *ov7251) 866d30bb512STodor Tomov { 867d30bb512STodor Tomov clk_disable_unprepare(ov7251->xclk); 868d30bb512STodor Tomov gpiod_set_value_cansleep(ov7251->enable_gpio, 0); 869d30bb512STodor Tomov ov7251_regulators_disable(ov7251); 870d30bb512STodor Tomov } 871d30bb512STodor Tomov 872d30bb512STodor Tomov static int ov7251_s_power(struct v4l2_subdev *sd, int on) 873d30bb512STodor Tomov { 874d30bb512STodor Tomov struct ov7251 *ov7251 = to_ov7251(sd); 875d30bb512STodor Tomov int ret = 0; 876d30bb512STodor Tomov 877d30bb512STodor Tomov mutex_lock(&ov7251->lock); 878d30bb512STodor Tomov 879d30bb512STodor Tomov /* If the power state is not modified - no work to do. */ 880d30bb512STodor Tomov if (ov7251->power_on == !!on) 881d30bb512STodor Tomov goto exit; 882d30bb512STodor Tomov 883d30bb512STodor Tomov if (on) { 884d30bb512STodor Tomov ret = ov7251_set_power_on(ov7251); 885d30bb512STodor Tomov if (ret < 0) 886d30bb512STodor Tomov goto exit; 887d30bb512STodor Tomov 888d30bb512STodor Tomov ret = ov7251_set_register_array(ov7251, 889d30bb512STodor Tomov ov7251_global_init_setting, 890d30bb512STodor Tomov ARRAY_SIZE(ov7251_global_init_setting)); 891d30bb512STodor Tomov if (ret < 0) { 892d30bb512STodor Tomov dev_err(ov7251->dev, "could not set init registers\n"); 893d30bb512STodor Tomov ov7251_set_power_off(ov7251); 894d30bb512STodor Tomov goto exit; 895d30bb512STodor Tomov } 896d30bb512STodor Tomov 897d30bb512STodor Tomov ov7251->power_on = true; 898d30bb512STodor Tomov } else { 899d30bb512STodor Tomov ov7251_set_power_off(ov7251); 900d30bb512STodor Tomov ov7251->power_on = false; 901d30bb512STodor Tomov } 902d30bb512STodor Tomov 903d30bb512STodor Tomov exit: 904d30bb512STodor Tomov mutex_unlock(&ov7251->lock); 905d30bb512STodor Tomov 906d30bb512STodor Tomov return ret; 907d30bb512STodor Tomov } 908d30bb512STodor Tomov 909d30bb512STodor Tomov static int ov7251_set_hflip(struct ov7251 *ov7251, s32 value) 910d30bb512STodor Tomov { 911d30bb512STodor Tomov u8 val = ov7251->timing_format2; 912d30bb512STodor Tomov int ret; 913d30bb512STodor Tomov 914d30bb512STodor Tomov if (value) 915d30bb512STodor Tomov val |= OV7251_TIMING_FORMAT2_MIRROR; 916d30bb512STodor Tomov else 917d30bb512STodor Tomov val &= ~OV7251_TIMING_FORMAT2_MIRROR; 918d30bb512STodor Tomov 919d30bb512STodor Tomov ret = ov7251_write_reg(ov7251, OV7251_TIMING_FORMAT2, val); 920d30bb512STodor Tomov if (!ret) 921d30bb512STodor Tomov ov7251->timing_format2 = val; 922d30bb512STodor Tomov 923d30bb512STodor Tomov return ret; 924d30bb512STodor Tomov } 925d30bb512STodor Tomov 926d30bb512STodor Tomov static int ov7251_set_vflip(struct ov7251 *ov7251, s32 value) 927d30bb512STodor Tomov { 928d30bb512STodor Tomov u8 val = ov7251->timing_format1; 929d30bb512STodor Tomov int ret; 930d30bb512STodor Tomov 931d30bb512STodor Tomov if (value) 932d30bb512STodor Tomov val |= OV7251_TIMING_FORMAT1_VFLIP; 933d30bb512STodor Tomov else 934d30bb512STodor Tomov val &= ~OV7251_TIMING_FORMAT1_VFLIP; 935d30bb512STodor Tomov 936d30bb512STodor Tomov ret = ov7251_write_reg(ov7251, OV7251_TIMING_FORMAT1, val); 937d30bb512STodor Tomov if (!ret) 938d30bb512STodor Tomov ov7251->timing_format1 = val; 939d30bb512STodor Tomov 940d30bb512STodor Tomov return ret; 941d30bb512STodor Tomov } 942d30bb512STodor Tomov 943d30bb512STodor Tomov static int ov7251_set_test_pattern(struct ov7251 *ov7251, s32 value) 944d30bb512STodor Tomov { 945d30bb512STodor Tomov u8 val = ov7251->pre_isp_00; 946d30bb512STodor Tomov int ret; 947d30bb512STodor Tomov 948d30bb512STodor Tomov if (value) 949d30bb512STodor Tomov val |= OV7251_PRE_ISP_00_TEST_PATTERN; 950d30bb512STodor Tomov else 951d30bb512STodor Tomov val &= ~OV7251_PRE_ISP_00_TEST_PATTERN; 952d30bb512STodor Tomov 953d30bb512STodor Tomov ret = ov7251_write_reg(ov7251, OV7251_PRE_ISP_00, val); 954d30bb512STodor Tomov if (!ret) 955d30bb512STodor Tomov ov7251->pre_isp_00 = val; 956d30bb512STodor Tomov 957d30bb512STodor Tomov return ret; 958d30bb512STodor Tomov } 959d30bb512STodor Tomov 960d30bb512STodor Tomov static const char * const ov7251_test_pattern_menu[] = { 961d30bb512STodor Tomov "Disabled", 962d30bb512STodor Tomov "Vertical Pattern Bars", 963d30bb512STodor Tomov }; 964d30bb512STodor Tomov 965d30bb512STodor Tomov static int ov7251_s_ctrl(struct v4l2_ctrl *ctrl) 966d30bb512STodor Tomov { 967d30bb512STodor Tomov struct ov7251 *ov7251 = container_of(ctrl->handler, 968d30bb512STodor Tomov struct ov7251, ctrls); 969d30bb512STodor Tomov int ret; 970d30bb512STodor Tomov 971d30bb512STodor Tomov /* v4l2_ctrl_lock() locks our mutex */ 972d30bb512STodor Tomov 973d30bb512STodor Tomov if (!ov7251->power_on) 974d30bb512STodor Tomov return 0; 975d30bb512STodor Tomov 976d30bb512STodor Tomov switch (ctrl->id) { 977d30bb512STodor Tomov case V4L2_CID_EXPOSURE: 978d30bb512STodor Tomov ret = ov7251_set_exposure(ov7251, ctrl->val); 979d30bb512STodor Tomov break; 980d30bb512STodor Tomov case V4L2_CID_GAIN: 981d30bb512STodor Tomov ret = ov7251_set_gain(ov7251, ctrl->val); 982d30bb512STodor Tomov break; 983d30bb512STodor Tomov case V4L2_CID_TEST_PATTERN: 984d30bb512STodor Tomov ret = ov7251_set_test_pattern(ov7251, ctrl->val); 985d30bb512STodor Tomov break; 986d30bb512STodor Tomov case V4L2_CID_HFLIP: 987d30bb512STodor Tomov ret = ov7251_set_hflip(ov7251, ctrl->val); 988d30bb512STodor Tomov break; 989d30bb512STodor Tomov case V4L2_CID_VFLIP: 990d30bb512STodor Tomov ret = ov7251_set_vflip(ov7251, ctrl->val); 991d30bb512STodor Tomov break; 992d30bb512STodor Tomov default: 993d30bb512STodor Tomov ret = -EINVAL; 994d30bb512STodor Tomov break; 995d30bb512STodor Tomov } 996d30bb512STodor Tomov 997d30bb512STodor Tomov return ret; 998d30bb512STodor Tomov } 999d30bb512STodor Tomov 1000d30bb512STodor Tomov static const struct v4l2_ctrl_ops ov7251_ctrl_ops = { 1001d30bb512STodor Tomov .s_ctrl = ov7251_s_ctrl, 1002d30bb512STodor Tomov }; 1003d30bb512STodor Tomov 1004d30bb512STodor Tomov static int ov7251_enum_mbus_code(struct v4l2_subdev *sd, 10050d346d2aSTomi Valkeinen struct v4l2_subdev_state *sd_state, 1006d30bb512STodor Tomov struct v4l2_subdev_mbus_code_enum *code) 1007d30bb512STodor Tomov { 1008d30bb512STodor Tomov if (code->index > 0) 1009d30bb512STodor Tomov return -EINVAL; 1010d30bb512STodor Tomov 1011d30bb512STodor Tomov code->code = MEDIA_BUS_FMT_Y10_1X10; 1012d30bb512STodor Tomov 1013d30bb512STodor Tomov return 0; 1014d30bb512STodor Tomov } 1015d30bb512STodor Tomov 1016d30bb512STodor Tomov static int ov7251_enum_frame_size(struct v4l2_subdev *subdev, 10170d346d2aSTomi Valkeinen struct v4l2_subdev_state *sd_state, 1018d30bb512STodor Tomov struct v4l2_subdev_frame_size_enum *fse) 1019d30bb512STodor Tomov { 1020d30bb512STodor Tomov if (fse->code != MEDIA_BUS_FMT_Y10_1X10) 1021d30bb512STodor Tomov return -EINVAL; 1022d30bb512STodor Tomov 1023d30bb512STodor Tomov if (fse->index >= ARRAY_SIZE(ov7251_mode_info_data)) 1024d30bb512STodor Tomov return -EINVAL; 1025d30bb512STodor Tomov 1026d30bb512STodor Tomov fse->min_width = ov7251_mode_info_data[fse->index].width; 1027d30bb512STodor Tomov fse->max_width = ov7251_mode_info_data[fse->index].width; 1028d30bb512STodor Tomov fse->min_height = ov7251_mode_info_data[fse->index].height; 1029d30bb512STodor Tomov fse->max_height = ov7251_mode_info_data[fse->index].height; 1030d30bb512STodor Tomov 1031d30bb512STodor Tomov return 0; 1032d30bb512STodor Tomov } 1033d30bb512STodor Tomov 1034d30bb512STodor Tomov static int ov7251_enum_frame_ival(struct v4l2_subdev *subdev, 10350d346d2aSTomi Valkeinen struct v4l2_subdev_state *sd_state, 1036d30bb512STodor Tomov struct v4l2_subdev_frame_interval_enum *fie) 1037d30bb512STodor Tomov { 1038d30bb512STodor Tomov unsigned int index = fie->index; 1039d30bb512STodor Tomov unsigned int i; 1040d30bb512STodor Tomov 1041d30bb512STodor Tomov for (i = 0; i < ARRAY_SIZE(ov7251_mode_info_data); i++) { 1042d30bb512STodor Tomov if (fie->width != ov7251_mode_info_data[i].width || 1043d30bb512STodor Tomov fie->height != ov7251_mode_info_data[i].height) 1044d30bb512STodor Tomov continue; 1045d30bb512STodor Tomov 1046d30bb512STodor Tomov if (index-- == 0) { 1047d30bb512STodor Tomov fie->interval = ov7251_mode_info_data[i].timeperframe; 1048d30bb512STodor Tomov return 0; 1049d30bb512STodor Tomov } 1050d30bb512STodor Tomov } 1051d30bb512STodor Tomov 1052d30bb512STodor Tomov return -EINVAL; 1053d30bb512STodor Tomov } 1054d30bb512STodor Tomov 1055d30bb512STodor Tomov static struct v4l2_mbus_framefmt * 1056d30bb512STodor Tomov __ov7251_get_pad_format(struct ov7251 *ov7251, 10570d346d2aSTomi Valkeinen struct v4l2_subdev_state *sd_state, 1058d30bb512STodor Tomov unsigned int pad, 1059d30bb512STodor Tomov enum v4l2_subdev_format_whence which) 1060d30bb512STodor Tomov { 1061d30bb512STodor Tomov switch (which) { 1062d30bb512STodor Tomov case V4L2_SUBDEV_FORMAT_TRY: 10630d346d2aSTomi Valkeinen return v4l2_subdev_get_try_format(&ov7251->sd, sd_state, pad); 1064d30bb512STodor Tomov case V4L2_SUBDEV_FORMAT_ACTIVE: 1065d30bb512STodor Tomov return &ov7251->fmt; 1066d30bb512STodor Tomov default: 1067d30bb512STodor Tomov return NULL; 1068d30bb512STodor Tomov } 1069d30bb512STodor Tomov } 1070d30bb512STodor Tomov 1071d30bb512STodor Tomov static int ov7251_get_format(struct v4l2_subdev *sd, 10720d346d2aSTomi Valkeinen struct v4l2_subdev_state *sd_state, 1073d30bb512STodor Tomov struct v4l2_subdev_format *format) 1074d30bb512STodor Tomov { 1075d30bb512STodor Tomov struct ov7251 *ov7251 = to_ov7251(sd); 1076d30bb512STodor Tomov 1077d30bb512STodor Tomov mutex_lock(&ov7251->lock); 10780d346d2aSTomi Valkeinen format->format = *__ov7251_get_pad_format(ov7251, sd_state, 10790d346d2aSTomi Valkeinen format->pad, 1080d30bb512STodor Tomov format->which); 1081d30bb512STodor Tomov mutex_unlock(&ov7251->lock); 1082d30bb512STodor Tomov 1083d30bb512STodor Tomov return 0; 1084d30bb512STodor Tomov } 1085d30bb512STodor Tomov 1086d30bb512STodor Tomov static struct v4l2_rect * 10870d346d2aSTomi Valkeinen __ov7251_get_pad_crop(struct ov7251 *ov7251, 10880d346d2aSTomi Valkeinen struct v4l2_subdev_state *sd_state, 1089d30bb512STodor Tomov unsigned int pad, enum v4l2_subdev_format_whence which) 1090d30bb512STodor Tomov { 1091d30bb512STodor Tomov switch (which) { 1092d30bb512STodor Tomov case V4L2_SUBDEV_FORMAT_TRY: 10930d346d2aSTomi Valkeinen return v4l2_subdev_get_try_crop(&ov7251->sd, sd_state, pad); 1094d30bb512STodor Tomov case V4L2_SUBDEV_FORMAT_ACTIVE: 1095d30bb512STodor Tomov return &ov7251->crop; 1096d30bb512STodor Tomov default: 1097d30bb512STodor Tomov return NULL; 1098d30bb512STodor Tomov } 1099d30bb512STodor Tomov } 1100d30bb512STodor Tomov 1101d30bb512STodor Tomov static inline u32 avg_fps(const struct v4l2_fract *t) 1102d30bb512STodor Tomov { 1103d30bb512STodor Tomov return (t->denominator + (t->numerator >> 1)) / t->numerator; 1104d30bb512STodor Tomov } 1105d30bb512STodor Tomov 1106d30bb512STodor Tomov static const struct ov7251_mode_info * 1107d30bb512STodor Tomov ov7251_find_mode_by_ival(struct ov7251 *ov7251, struct v4l2_fract *timeperframe) 1108d30bb512STodor Tomov { 1109d30bb512STodor Tomov const struct ov7251_mode_info *mode = ov7251->current_mode; 1110d30bb512STodor Tomov unsigned int fps_req = avg_fps(timeperframe); 1111d30bb512STodor Tomov unsigned int max_dist_match = (unsigned int) -1; 1112d30bb512STodor Tomov unsigned int i, n = 0; 1113d30bb512STodor Tomov 1114d30bb512STodor Tomov for (i = 0; i < ARRAY_SIZE(ov7251_mode_info_data); i++) { 1115d30bb512STodor Tomov unsigned int dist; 1116d30bb512STodor Tomov unsigned int fps_tmp; 1117d30bb512STodor Tomov 1118d30bb512STodor Tomov if (mode->width != ov7251_mode_info_data[i].width || 1119d30bb512STodor Tomov mode->height != ov7251_mode_info_data[i].height) 1120d30bb512STodor Tomov continue; 1121d30bb512STodor Tomov 1122d30bb512STodor Tomov fps_tmp = avg_fps(&ov7251_mode_info_data[i].timeperframe); 1123d30bb512STodor Tomov 1124d30bb512STodor Tomov dist = abs(fps_req - fps_tmp); 1125d30bb512STodor Tomov 1126d30bb512STodor Tomov if (dist < max_dist_match) { 1127d30bb512STodor Tomov n = i; 1128d30bb512STodor Tomov max_dist_match = dist; 1129d30bb512STodor Tomov } 1130d30bb512STodor Tomov } 1131d30bb512STodor Tomov 1132d30bb512STodor Tomov return &ov7251_mode_info_data[n]; 1133d30bb512STodor Tomov } 1134d30bb512STodor Tomov 1135d30bb512STodor Tomov static int ov7251_set_format(struct v4l2_subdev *sd, 11360d346d2aSTomi Valkeinen struct v4l2_subdev_state *sd_state, 1137d30bb512STodor Tomov struct v4l2_subdev_format *format) 1138d30bb512STodor Tomov { 1139d30bb512STodor Tomov struct ov7251 *ov7251 = to_ov7251(sd); 1140d30bb512STodor Tomov struct v4l2_mbus_framefmt *__format; 1141d30bb512STodor Tomov struct v4l2_rect *__crop; 1142d30bb512STodor Tomov const struct ov7251_mode_info *new_mode; 1143d30bb512STodor Tomov int ret = 0; 1144d30bb512STodor Tomov 1145d30bb512STodor Tomov mutex_lock(&ov7251->lock); 1146d30bb512STodor Tomov 11470d346d2aSTomi Valkeinen __crop = __ov7251_get_pad_crop(ov7251, sd_state, format->pad, 11480d346d2aSTomi Valkeinen format->which); 1149d30bb512STodor Tomov 1150d30bb512STodor Tomov new_mode = v4l2_find_nearest_size(ov7251_mode_info_data, 1151d30bb512STodor Tomov ARRAY_SIZE(ov7251_mode_info_data), 1152d30bb512STodor Tomov width, height, 1153d30bb512STodor Tomov format->format.width, format->format.height); 1154d30bb512STodor Tomov 1155d30bb512STodor Tomov __crop->width = new_mode->width; 1156d30bb512STodor Tomov __crop->height = new_mode->height; 1157d30bb512STodor Tomov 1158d30bb512STodor Tomov if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) { 1159d30bb512STodor Tomov ret = __v4l2_ctrl_modify_range(ov7251->exposure, 1160d30bb512STodor Tomov 1, new_mode->exposure_max, 1161d30bb512STodor Tomov 1, new_mode->exposure_def); 1162d30bb512STodor Tomov if (ret < 0) 1163d30bb512STodor Tomov goto exit; 1164d30bb512STodor Tomov 1165d30bb512STodor Tomov ret = __v4l2_ctrl_s_ctrl(ov7251->exposure, 1166d30bb512STodor Tomov new_mode->exposure_def); 1167d30bb512STodor Tomov if (ret < 0) 1168d30bb512STodor Tomov goto exit; 1169d30bb512STodor Tomov 1170d30bb512STodor Tomov ret = __v4l2_ctrl_s_ctrl(ov7251->gain, 16); 1171d30bb512STodor Tomov if (ret < 0) 1172d30bb512STodor Tomov goto exit; 1173d30bb512STodor Tomov 1174d30bb512STodor Tomov ov7251->current_mode = new_mode; 1175d30bb512STodor Tomov } 1176d30bb512STodor Tomov 11770d346d2aSTomi Valkeinen __format = __ov7251_get_pad_format(ov7251, sd_state, format->pad, 1178d30bb512STodor Tomov format->which); 1179d30bb512STodor Tomov __format->width = __crop->width; 1180d30bb512STodor Tomov __format->height = __crop->height; 1181d30bb512STodor Tomov __format->code = MEDIA_BUS_FMT_Y10_1X10; 1182d30bb512STodor Tomov __format->field = V4L2_FIELD_NONE; 1183d30bb512STodor Tomov __format->colorspace = V4L2_COLORSPACE_SRGB; 1184d30bb512STodor Tomov __format->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(__format->colorspace); 1185d30bb512STodor Tomov __format->quantization = V4L2_MAP_QUANTIZATION_DEFAULT(true, 1186d30bb512STodor Tomov __format->colorspace, __format->ycbcr_enc); 1187d30bb512STodor Tomov __format->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(__format->colorspace); 1188d30bb512STodor Tomov 1189d30bb512STodor Tomov format->format = *__format; 1190d30bb512STodor Tomov 1191d30bb512STodor Tomov exit: 1192d30bb512STodor Tomov mutex_unlock(&ov7251->lock); 1193d30bb512STodor Tomov 1194d30bb512STodor Tomov return ret; 1195d30bb512STodor Tomov } 1196d30bb512STodor Tomov 1197d30bb512STodor Tomov static int ov7251_entity_init_cfg(struct v4l2_subdev *subdev, 11980d346d2aSTomi Valkeinen struct v4l2_subdev_state *sd_state) 1199d30bb512STodor Tomov { 1200d30bb512STodor Tomov struct v4l2_subdev_format fmt = { 12010d346d2aSTomi Valkeinen .which = sd_state ? V4L2_SUBDEV_FORMAT_TRY 1202d30bb512STodor Tomov : V4L2_SUBDEV_FORMAT_ACTIVE, 1203d30bb512STodor Tomov .format = { 1204d30bb512STodor Tomov .width = 640, 1205d30bb512STodor Tomov .height = 480 1206d30bb512STodor Tomov } 1207d30bb512STodor Tomov }; 1208d30bb512STodor Tomov 12090d346d2aSTomi Valkeinen ov7251_set_format(subdev, sd_state, &fmt); 1210d30bb512STodor Tomov 1211d30bb512STodor Tomov return 0; 1212d30bb512STodor Tomov } 1213d30bb512STodor Tomov 1214d30bb512STodor Tomov static int ov7251_get_selection(struct v4l2_subdev *sd, 12150d346d2aSTomi Valkeinen struct v4l2_subdev_state *sd_state, 1216d30bb512STodor Tomov struct v4l2_subdev_selection *sel) 1217d30bb512STodor Tomov { 1218d30bb512STodor Tomov struct ov7251 *ov7251 = to_ov7251(sd); 1219d30bb512STodor Tomov 1220d30bb512STodor Tomov if (sel->target != V4L2_SEL_TGT_CROP) 1221d30bb512STodor Tomov return -EINVAL; 1222d30bb512STodor Tomov 1223d30bb512STodor Tomov mutex_lock(&ov7251->lock); 12240d346d2aSTomi Valkeinen sel->r = *__ov7251_get_pad_crop(ov7251, sd_state, sel->pad, 1225d30bb512STodor Tomov sel->which); 1226d30bb512STodor Tomov mutex_unlock(&ov7251->lock); 1227d30bb512STodor Tomov 1228d30bb512STodor Tomov return 0; 1229d30bb512STodor Tomov } 1230d30bb512STodor Tomov 1231d30bb512STodor Tomov static int ov7251_s_stream(struct v4l2_subdev *subdev, int enable) 1232d30bb512STodor Tomov { 1233d30bb512STodor Tomov struct ov7251 *ov7251 = to_ov7251(subdev); 1234d30bb512STodor Tomov int ret; 1235d30bb512STodor Tomov 1236d30bb512STodor Tomov mutex_lock(&ov7251->lock); 1237d30bb512STodor Tomov 1238d30bb512STodor Tomov if (enable) { 1239*df057b0dSDaniel Scally ret = ov7251_pll_configure(ov7251); 1240*df057b0dSDaniel Scally if (ret) 1241*df057b0dSDaniel Scally return dev_err_probe(ov7251->dev, ret, 1242*df057b0dSDaniel Scally "error configuring PLLs\n"); 1243*df057b0dSDaniel Scally 1244d30bb512STodor Tomov ret = ov7251_set_register_array(ov7251, 1245d30bb512STodor Tomov ov7251->current_mode->data, 1246d30bb512STodor Tomov ov7251->current_mode->data_size); 1247d30bb512STodor Tomov if (ret < 0) { 1248d30bb512STodor Tomov dev_err(ov7251->dev, "could not set mode %dx%d\n", 1249d30bb512STodor Tomov ov7251->current_mode->width, 1250d30bb512STodor Tomov ov7251->current_mode->height); 1251d30bb512STodor Tomov goto exit; 1252d30bb512STodor Tomov } 1253d30bb512STodor Tomov ret = __v4l2_ctrl_handler_setup(&ov7251->ctrls); 1254d30bb512STodor Tomov if (ret < 0) { 1255d30bb512STodor Tomov dev_err(ov7251->dev, "could not sync v4l2 controls\n"); 1256d30bb512STodor Tomov goto exit; 1257d30bb512STodor Tomov } 1258d30bb512STodor Tomov ret = ov7251_write_reg(ov7251, OV7251_SC_MODE_SELECT, 1259d30bb512STodor Tomov OV7251_SC_MODE_SELECT_STREAMING); 1260d30bb512STodor Tomov } else { 1261d30bb512STodor Tomov ret = ov7251_write_reg(ov7251, OV7251_SC_MODE_SELECT, 1262d30bb512STodor Tomov OV7251_SC_MODE_SELECT_SW_STANDBY); 1263d30bb512STodor Tomov } 1264d30bb512STodor Tomov 1265d30bb512STodor Tomov exit: 1266d30bb512STodor Tomov mutex_unlock(&ov7251->lock); 1267d30bb512STodor Tomov 1268d30bb512STodor Tomov return ret; 1269d30bb512STodor Tomov } 1270d30bb512STodor Tomov 1271d30bb512STodor Tomov static int ov7251_get_frame_interval(struct v4l2_subdev *subdev, 1272d30bb512STodor Tomov struct v4l2_subdev_frame_interval *fi) 1273d30bb512STodor Tomov { 1274d30bb512STodor Tomov struct ov7251 *ov7251 = to_ov7251(subdev); 1275d30bb512STodor Tomov 1276d30bb512STodor Tomov mutex_lock(&ov7251->lock); 1277d30bb512STodor Tomov fi->interval = ov7251->current_mode->timeperframe; 1278d30bb512STodor Tomov mutex_unlock(&ov7251->lock); 1279d30bb512STodor Tomov 1280d30bb512STodor Tomov return 0; 1281d30bb512STodor Tomov } 1282d30bb512STodor Tomov 1283d30bb512STodor Tomov static int ov7251_set_frame_interval(struct v4l2_subdev *subdev, 1284d30bb512STodor Tomov struct v4l2_subdev_frame_interval *fi) 1285d30bb512STodor Tomov { 1286d30bb512STodor Tomov struct ov7251 *ov7251 = to_ov7251(subdev); 1287d30bb512STodor Tomov const struct ov7251_mode_info *new_mode; 1288d30bb512STodor Tomov int ret = 0; 1289d30bb512STodor Tomov 1290d30bb512STodor Tomov mutex_lock(&ov7251->lock); 1291d30bb512STodor Tomov new_mode = ov7251_find_mode_by_ival(ov7251, &fi->interval); 1292d30bb512STodor Tomov 1293d30bb512STodor Tomov if (new_mode != ov7251->current_mode) { 1294d30bb512STodor Tomov ret = __v4l2_ctrl_modify_range(ov7251->exposure, 1295d30bb512STodor Tomov 1, new_mode->exposure_max, 1296d30bb512STodor Tomov 1, new_mode->exposure_def); 1297d30bb512STodor Tomov if (ret < 0) 1298d30bb512STodor Tomov goto exit; 1299d30bb512STodor Tomov 1300d30bb512STodor Tomov ret = __v4l2_ctrl_s_ctrl(ov7251->exposure, 1301d30bb512STodor Tomov new_mode->exposure_def); 1302d30bb512STodor Tomov if (ret < 0) 1303d30bb512STodor Tomov goto exit; 1304d30bb512STodor Tomov 1305d30bb512STodor Tomov ret = __v4l2_ctrl_s_ctrl(ov7251->gain, 16); 1306d30bb512STodor Tomov if (ret < 0) 1307d30bb512STodor Tomov goto exit; 1308d30bb512STodor Tomov 1309d30bb512STodor Tomov ov7251->current_mode = new_mode; 1310d30bb512STodor Tomov } 1311d30bb512STodor Tomov 1312d30bb512STodor Tomov fi->interval = ov7251->current_mode->timeperframe; 1313d30bb512STodor Tomov 1314d30bb512STodor Tomov exit: 1315d30bb512STodor Tomov mutex_unlock(&ov7251->lock); 1316d30bb512STodor Tomov 1317d30bb512STodor Tomov return ret; 1318d30bb512STodor Tomov } 1319d30bb512STodor Tomov 1320d30bb512STodor Tomov static const struct v4l2_subdev_core_ops ov7251_core_ops = { 1321d30bb512STodor Tomov .s_power = ov7251_s_power, 1322d30bb512STodor Tomov }; 1323d30bb512STodor Tomov 1324d30bb512STodor Tomov static const struct v4l2_subdev_video_ops ov7251_video_ops = { 1325d30bb512STodor Tomov .s_stream = ov7251_s_stream, 1326d30bb512STodor Tomov .g_frame_interval = ov7251_get_frame_interval, 1327d30bb512STodor Tomov .s_frame_interval = ov7251_set_frame_interval, 1328d30bb512STodor Tomov }; 1329d30bb512STodor Tomov 1330d30bb512STodor Tomov static const struct v4l2_subdev_pad_ops ov7251_subdev_pad_ops = { 1331d30bb512STodor Tomov .init_cfg = ov7251_entity_init_cfg, 1332d30bb512STodor Tomov .enum_mbus_code = ov7251_enum_mbus_code, 1333d30bb512STodor Tomov .enum_frame_size = ov7251_enum_frame_size, 1334d30bb512STodor Tomov .enum_frame_interval = ov7251_enum_frame_ival, 1335d30bb512STodor Tomov .get_fmt = ov7251_get_format, 1336d30bb512STodor Tomov .set_fmt = ov7251_set_format, 1337d30bb512STodor Tomov .get_selection = ov7251_get_selection, 1338d30bb512STodor Tomov }; 1339d30bb512STodor Tomov 1340d30bb512STodor Tomov static const struct v4l2_subdev_ops ov7251_subdev_ops = { 1341d30bb512STodor Tomov .core = &ov7251_core_ops, 1342d30bb512STodor Tomov .video = &ov7251_video_ops, 1343d30bb512STodor Tomov .pad = &ov7251_subdev_pad_ops, 1344d30bb512STodor Tomov }; 1345d30bb512STodor Tomov 1346cc125aaaSDaniel Scally static int ov7251_check_hwcfg(struct ov7251 *ov7251) 1347cc125aaaSDaniel Scally { 1348cc125aaaSDaniel Scally struct fwnode_handle *fwnode = dev_fwnode(ov7251->dev); 1349cc125aaaSDaniel Scally struct v4l2_fwnode_endpoint bus_cfg = { 1350cc125aaaSDaniel Scally .bus_type = V4L2_MBUS_CSI2_DPHY, 1351cc125aaaSDaniel Scally }; 1352cc125aaaSDaniel Scally struct fwnode_handle *endpoint; 1353cc125aaaSDaniel Scally unsigned int i, j; 1354cc125aaaSDaniel Scally int ret; 1355cc125aaaSDaniel Scally 1356cc125aaaSDaniel Scally endpoint = fwnode_graph_get_next_endpoint(fwnode, NULL); 1357cc125aaaSDaniel Scally if (!endpoint) 1358cc125aaaSDaniel Scally return -EPROBE_DEFER; /* could be provided by cio2-bridge */ 1359cc125aaaSDaniel Scally 1360cc125aaaSDaniel Scally ret = v4l2_fwnode_endpoint_alloc_parse(endpoint, &bus_cfg); 1361cc125aaaSDaniel Scally fwnode_handle_put(endpoint); 1362cc125aaaSDaniel Scally if (ret) 1363cc125aaaSDaniel Scally return dev_err_probe(ov7251->dev, ret, 1364cc125aaaSDaniel Scally "parsing endpoint node failed\n"); 1365cc125aaaSDaniel Scally 1366cc125aaaSDaniel Scally if (!bus_cfg.nr_of_link_frequencies) { 1367cc125aaaSDaniel Scally ret = dev_err_probe(ov7251->dev, -EINVAL, 1368cc125aaaSDaniel Scally "no link frequencies defined\n"); 1369cc125aaaSDaniel Scally goto out_free_bus_cfg; 1370cc125aaaSDaniel Scally } 1371cc125aaaSDaniel Scally 1372cc125aaaSDaniel Scally for (i = 0; i < bus_cfg.nr_of_link_frequencies; i++) { 1373cc125aaaSDaniel Scally for (j = 0; j < ARRAY_SIZE(link_freq); j++) 1374cc125aaaSDaniel Scally if (bus_cfg.link_frequencies[i] == link_freq[j]) 1375cc125aaaSDaniel Scally break; 1376cc125aaaSDaniel Scally 1377cc125aaaSDaniel Scally if (j < ARRAY_SIZE(link_freq)) 1378cc125aaaSDaniel Scally break; 1379cc125aaaSDaniel Scally } 1380cc125aaaSDaniel Scally 1381cc125aaaSDaniel Scally if (i == bus_cfg.nr_of_link_frequencies) { 1382cc125aaaSDaniel Scally ret = dev_err_probe(ov7251->dev, -EINVAL, 1383cc125aaaSDaniel Scally "no supported link freq found\n"); 1384cc125aaaSDaniel Scally goto out_free_bus_cfg; 1385cc125aaaSDaniel Scally } 1386cc125aaaSDaniel Scally 1387cc125aaaSDaniel Scally ov7251->link_freq_idx = i; 1388cc125aaaSDaniel Scally 1389cc125aaaSDaniel Scally out_free_bus_cfg: 1390cc125aaaSDaniel Scally v4l2_fwnode_endpoint_free(&bus_cfg); 1391cc125aaaSDaniel Scally 1392cc125aaaSDaniel Scally return ret; 1393cc125aaaSDaniel Scally } 1394cc125aaaSDaniel Scally 1395d30bb512STodor Tomov static int ov7251_probe(struct i2c_client *client) 1396d30bb512STodor Tomov { 1397d30bb512STodor Tomov struct device *dev = &client->dev; 1398d30bb512STodor Tomov struct ov7251 *ov7251; 1399d30bb512STodor Tomov u8 chip_id_high, chip_id_low, chip_rev; 14001757b44eSDaniel Scally s64 pixel_rate; 1401d30bb512STodor Tomov int ret; 1402*df057b0dSDaniel Scally int i; 1403d30bb512STodor Tomov 1404d30bb512STodor Tomov ov7251 = devm_kzalloc(dev, sizeof(struct ov7251), GFP_KERNEL); 1405d30bb512STodor Tomov if (!ov7251) 1406d30bb512STodor Tomov return -ENOMEM; 1407d30bb512STodor Tomov 1408d30bb512STodor Tomov ov7251->i2c_client = client; 1409d30bb512STodor Tomov ov7251->dev = dev; 1410d30bb512STodor Tomov 1411cc125aaaSDaniel Scally ret = ov7251_check_hwcfg(ov7251); 1412cc125aaaSDaniel Scally if (ret) 1413d30bb512STodor Tomov return ret; 1414d30bb512STodor Tomov 1415d30bb512STodor Tomov /* get system clock (xclk) */ 1416d30bb512STodor Tomov ov7251->xclk = devm_clk_get(dev, "xclk"); 1417d30bb512STodor Tomov if (IS_ERR(ov7251->xclk)) { 1418d30bb512STodor Tomov dev_err(dev, "could not get xclk"); 1419d30bb512STodor Tomov return PTR_ERR(ov7251->xclk); 1420d30bb512STodor Tomov } 1421d30bb512STodor Tomov 1422d30bb512STodor Tomov ret = fwnode_property_read_u32(dev_fwnode(dev), "clock-frequency", 1423d30bb512STodor Tomov &ov7251->xclk_freq); 1424d30bb512STodor Tomov if (ret) { 1425d30bb512STodor Tomov dev_err(dev, "could not get xclk frequency\n"); 1426d30bb512STodor Tomov return ret; 1427d30bb512STodor Tomov } 1428d30bb512STodor Tomov 1429d30bb512STodor Tomov /* external clock must be 24MHz, allow 1% tolerance */ 1430d30bb512STodor Tomov if (ov7251->xclk_freq < 23760000 || ov7251->xclk_freq > 24240000) { 1431d30bb512STodor Tomov dev_err(dev, "external clock frequency %u is not supported\n", 1432d30bb512STodor Tomov ov7251->xclk_freq); 1433d30bb512STodor Tomov return -EINVAL; 1434d30bb512STodor Tomov } 1435d30bb512STodor Tomov 1436d30bb512STodor Tomov ret = clk_set_rate(ov7251->xclk, ov7251->xclk_freq); 1437d30bb512STodor Tomov if (ret) { 1438d30bb512STodor Tomov dev_err(dev, "could not set xclk frequency\n"); 1439d30bb512STodor Tomov return ret; 1440d30bb512STodor Tomov } 1441*df057b0dSDaniel Scally for (i = 0; i < ARRAY_SIZE(supported_xclk_rates); i++) 1442*df057b0dSDaniel Scally if (ov7251->xclk_freq == supported_xclk_rates[i]) 1443*df057b0dSDaniel Scally break; 1444*df057b0dSDaniel Scally 1445*df057b0dSDaniel Scally if (i == ARRAY_SIZE(supported_xclk_rates)) 1446*df057b0dSDaniel Scally return dev_err_probe(dev, -EINVAL, 1447*df057b0dSDaniel Scally "clock rate %u Hz is unsupported\n", 1448*df057b0dSDaniel Scally ov7251->xclk_freq); 1449*df057b0dSDaniel Scally 1450*df057b0dSDaniel Scally ov7251->pll_cfgs = ov7251_pll_cfgs[i]; 1451d30bb512STodor Tomov 1452d30bb512STodor Tomov ov7251->io_regulator = devm_regulator_get(dev, "vdddo"); 1453d30bb512STodor Tomov if (IS_ERR(ov7251->io_regulator)) { 1454d30bb512STodor Tomov dev_err(dev, "cannot get io regulator\n"); 1455d30bb512STodor Tomov return PTR_ERR(ov7251->io_regulator); 1456d30bb512STodor Tomov } 1457d30bb512STodor Tomov 1458d30bb512STodor Tomov ov7251->core_regulator = devm_regulator_get(dev, "vddd"); 1459d30bb512STodor Tomov if (IS_ERR(ov7251->core_regulator)) { 1460d30bb512STodor Tomov dev_err(dev, "cannot get core regulator\n"); 1461d30bb512STodor Tomov return PTR_ERR(ov7251->core_regulator); 1462d30bb512STodor Tomov } 1463d30bb512STodor Tomov 1464d30bb512STodor Tomov ov7251->analog_regulator = devm_regulator_get(dev, "vdda"); 1465d30bb512STodor Tomov if (IS_ERR(ov7251->analog_regulator)) { 1466d30bb512STodor Tomov dev_err(dev, "cannot get analog regulator\n"); 1467d30bb512STodor Tomov return PTR_ERR(ov7251->analog_regulator); 1468d30bb512STodor Tomov } 1469d30bb512STodor Tomov 1470d30bb512STodor Tomov ov7251->enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_HIGH); 1471d30bb512STodor Tomov if (IS_ERR(ov7251->enable_gpio)) { 1472d30bb512STodor Tomov dev_err(dev, "cannot get enable gpio\n"); 1473d30bb512STodor Tomov return PTR_ERR(ov7251->enable_gpio); 1474d30bb512STodor Tomov } 1475d30bb512STodor Tomov 1476d30bb512STodor Tomov mutex_init(&ov7251->lock); 1477d30bb512STodor Tomov 1478d30bb512STodor Tomov v4l2_ctrl_handler_init(&ov7251->ctrls, 7); 1479d30bb512STodor Tomov ov7251->ctrls.lock = &ov7251->lock; 1480d30bb512STodor Tomov 1481d30bb512STodor Tomov v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops, 1482d30bb512STodor Tomov V4L2_CID_HFLIP, 0, 1, 1, 0); 1483d30bb512STodor Tomov v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops, 1484d30bb512STodor Tomov V4L2_CID_VFLIP, 0, 1, 1, 0); 1485d30bb512STodor Tomov ov7251->exposure = v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops, 1486d30bb512STodor Tomov V4L2_CID_EXPOSURE, 1, 32, 1, 32); 1487d30bb512STodor Tomov ov7251->gain = v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops, 1488d30bb512STodor Tomov V4L2_CID_GAIN, 16, 1023, 1, 16); 1489d30bb512STodor Tomov v4l2_ctrl_new_std_menu_items(&ov7251->ctrls, &ov7251_ctrl_ops, 1490d30bb512STodor Tomov V4L2_CID_TEST_PATTERN, 1491d30bb512STodor Tomov ARRAY_SIZE(ov7251_test_pattern_menu) - 1, 1492d30bb512STodor Tomov 0, 0, ov7251_test_pattern_menu); 14931757b44eSDaniel Scally 14941757b44eSDaniel Scally pixel_rate = pixel_rates[ov7251->link_freq_idx]; 1495d30bb512STodor Tomov ov7251->pixel_clock = v4l2_ctrl_new_std(&ov7251->ctrls, 1496d30bb512STodor Tomov &ov7251_ctrl_ops, 1497d30bb512STodor Tomov V4L2_CID_PIXEL_RATE, 14981757b44eSDaniel Scally pixel_rate, INT_MAX, 14991757b44eSDaniel Scally pixel_rate, pixel_rate); 1500d30bb512STodor Tomov ov7251->link_freq = v4l2_ctrl_new_int_menu(&ov7251->ctrls, 1501d30bb512STodor Tomov &ov7251_ctrl_ops, 1502d30bb512STodor Tomov V4L2_CID_LINK_FREQ, 1503d30bb512STodor Tomov ARRAY_SIZE(link_freq) - 1, 15041757b44eSDaniel Scally ov7251->link_freq_idx, 15051757b44eSDaniel Scally link_freq); 1506d30bb512STodor Tomov if (ov7251->link_freq) 1507d30bb512STodor Tomov ov7251->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; 15081757b44eSDaniel Scally if (ov7251->pixel_clock) 15091757b44eSDaniel Scally ov7251->pixel_clock->flags |= V4L2_CTRL_FLAG_READ_ONLY; 1510d30bb512STodor Tomov 1511d30bb512STodor Tomov ov7251->sd.ctrl_handler = &ov7251->ctrls; 1512d30bb512STodor Tomov 1513d30bb512STodor Tomov if (ov7251->ctrls.error) { 1514d30bb512STodor Tomov dev_err(dev, "%s: control initialization error %d\n", 1515d30bb512STodor Tomov __func__, ov7251->ctrls.error); 1516d30bb512STodor Tomov ret = ov7251->ctrls.error; 1517d30bb512STodor Tomov goto free_ctrl; 1518d30bb512STodor Tomov } 1519d30bb512STodor Tomov 1520d30bb512STodor Tomov v4l2_i2c_subdev_init(&ov7251->sd, client, &ov7251_subdev_ops); 1521d30bb512STodor Tomov ov7251->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1522d30bb512STodor Tomov ov7251->pad.flags = MEDIA_PAD_FL_SOURCE; 1523d30bb512STodor Tomov ov7251->sd.dev = &client->dev; 1524d30bb512STodor Tomov ov7251->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1525d30bb512STodor Tomov 1526d30bb512STodor Tomov ret = media_entity_pads_init(&ov7251->sd.entity, 1, &ov7251->pad); 1527d30bb512STodor Tomov if (ret < 0) { 1528d30bb512STodor Tomov dev_err(dev, "could not register media entity\n"); 1529d30bb512STodor Tomov goto free_ctrl; 1530d30bb512STodor Tomov } 1531d30bb512STodor Tomov 1532d30bb512STodor Tomov ret = ov7251_s_power(&ov7251->sd, true); 1533d30bb512STodor Tomov if (ret < 0) { 1534d30bb512STodor Tomov dev_err(dev, "could not power up OV7251\n"); 1535d30bb512STodor Tomov goto free_entity; 1536d30bb512STodor Tomov } 1537d30bb512STodor Tomov 1538d30bb512STodor Tomov ret = ov7251_read_reg(ov7251, OV7251_CHIP_ID_HIGH, &chip_id_high); 1539d30bb512STodor Tomov if (ret < 0 || chip_id_high != OV7251_CHIP_ID_HIGH_BYTE) { 1540d30bb512STodor Tomov dev_err(dev, "could not read ID high\n"); 1541d30bb512STodor Tomov ret = -ENODEV; 1542d30bb512STodor Tomov goto power_down; 1543d30bb512STodor Tomov } 1544d30bb512STodor Tomov ret = ov7251_read_reg(ov7251, OV7251_CHIP_ID_LOW, &chip_id_low); 1545d30bb512STodor Tomov if (ret < 0 || chip_id_low != OV7251_CHIP_ID_LOW_BYTE) { 1546d30bb512STodor Tomov dev_err(dev, "could not read ID low\n"); 1547d30bb512STodor Tomov ret = -ENODEV; 1548d30bb512STodor Tomov goto power_down; 1549d30bb512STodor Tomov } 1550d30bb512STodor Tomov 1551d30bb512STodor Tomov ret = ov7251_read_reg(ov7251, OV7251_SC_GP_IO_IN1, &chip_rev); 1552d30bb512STodor Tomov if (ret < 0) { 1553d30bb512STodor Tomov dev_err(dev, "could not read revision\n"); 1554d30bb512STodor Tomov ret = -ENODEV; 1555d30bb512STodor Tomov goto power_down; 1556d30bb512STodor Tomov } 1557d30bb512STodor Tomov chip_rev >>= 4; 1558d30bb512STodor Tomov 1559d30bb512STodor Tomov dev_info(dev, "OV7251 revision %x (%s) detected at address 0x%02x\n", 1560d30bb512STodor Tomov chip_rev, 1561d30bb512STodor Tomov chip_rev == 0x4 ? "1A / 1B" : 1562d30bb512STodor Tomov chip_rev == 0x5 ? "1C / 1D" : 1563d30bb512STodor Tomov chip_rev == 0x6 ? "1E" : 1564d30bb512STodor Tomov chip_rev == 0x7 ? "1F" : "unknown", 1565d30bb512STodor Tomov client->addr); 1566d30bb512STodor Tomov 1567d30bb512STodor Tomov ret = ov7251_read_reg(ov7251, OV7251_PRE_ISP_00, 1568d30bb512STodor Tomov &ov7251->pre_isp_00); 1569d30bb512STodor Tomov if (ret < 0) { 1570d30bb512STodor Tomov dev_err(dev, "could not read test pattern value\n"); 1571d30bb512STodor Tomov ret = -ENODEV; 1572d30bb512STodor Tomov goto power_down; 1573d30bb512STodor Tomov } 1574d30bb512STodor Tomov 1575d30bb512STodor Tomov ret = ov7251_read_reg(ov7251, OV7251_TIMING_FORMAT1, 1576d30bb512STodor Tomov &ov7251->timing_format1); 1577d30bb512STodor Tomov if (ret < 0) { 1578d30bb512STodor Tomov dev_err(dev, "could not read vflip value\n"); 1579d30bb512STodor Tomov ret = -ENODEV; 1580d30bb512STodor Tomov goto power_down; 1581d30bb512STodor Tomov } 1582d30bb512STodor Tomov 1583d30bb512STodor Tomov ret = ov7251_read_reg(ov7251, OV7251_TIMING_FORMAT2, 1584d30bb512STodor Tomov &ov7251->timing_format2); 1585d30bb512STodor Tomov if (ret < 0) { 1586d30bb512STodor Tomov dev_err(dev, "could not read hflip value\n"); 1587d30bb512STodor Tomov ret = -ENODEV; 1588d30bb512STodor Tomov goto power_down; 1589d30bb512STodor Tomov } 1590d30bb512STodor Tomov 1591d30bb512STodor Tomov ov7251_s_power(&ov7251->sd, false); 1592d30bb512STodor Tomov 1593d30bb512STodor Tomov ret = v4l2_async_register_subdev(&ov7251->sd); 1594d30bb512STodor Tomov if (ret < 0) { 1595d30bb512STodor Tomov dev_err(dev, "could not register v4l2 device\n"); 1596d30bb512STodor Tomov goto free_entity; 1597d30bb512STodor Tomov } 1598d30bb512STodor Tomov 1599d30bb512STodor Tomov ov7251_entity_init_cfg(&ov7251->sd, NULL); 1600d30bb512STodor Tomov 1601d30bb512STodor Tomov return 0; 1602d30bb512STodor Tomov 1603d30bb512STodor Tomov power_down: 1604d30bb512STodor Tomov ov7251_s_power(&ov7251->sd, false); 1605d30bb512STodor Tomov free_entity: 1606d30bb512STodor Tomov media_entity_cleanup(&ov7251->sd.entity); 1607d30bb512STodor Tomov free_ctrl: 1608d30bb512STodor Tomov v4l2_ctrl_handler_free(&ov7251->ctrls); 1609d30bb512STodor Tomov mutex_destroy(&ov7251->lock); 1610d30bb512STodor Tomov 1611d30bb512STodor Tomov return ret; 1612d30bb512STodor Tomov } 1613d30bb512STodor Tomov 1614d30bb512STodor Tomov static int ov7251_remove(struct i2c_client *client) 1615d30bb512STodor Tomov { 1616d30bb512STodor Tomov struct v4l2_subdev *sd = i2c_get_clientdata(client); 1617d30bb512STodor Tomov struct ov7251 *ov7251 = to_ov7251(sd); 1618d30bb512STodor Tomov 1619d30bb512STodor Tomov v4l2_async_unregister_subdev(&ov7251->sd); 1620d30bb512STodor Tomov media_entity_cleanup(&ov7251->sd.entity); 1621d30bb512STodor Tomov v4l2_ctrl_handler_free(&ov7251->ctrls); 1622d30bb512STodor Tomov mutex_destroy(&ov7251->lock); 1623d30bb512STodor Tomov 1624d30bb512STodor Tomov return 0; 1625d30bb512STodor Tomov } 1626d30bb512STodor Tomov 1627d30bb512STodor Tomov static const struct of_device_id ov7251_of_match[] = { 1628d30bb512STodor Tomov { .compatible = "ovti,ov7251" }, 1629d30bb512STodor Tomov { /* sentinel */ } 1630d30bb512STodor Tomov }; 1631d30bb512STodor Tomov MODULE_DEVICE_TABLE(of, ov7251_of_match); 1632d30bb512STodor Tomov 16336766cff6SDaniel Scally static const struct acpi_device_id ov7251_acpi_match[] = { 16346766cff6SDaniel Scally { "INT347E" }, 16356766cff6SDaniel Scally { } 16366766cff6SDaniel Scally }; 16376766cff6SDaniel Scally MODULE_DEVICE_TABLE(acpi, ov7251_acpi_match); 16386766cff6SDaniel Scally 1639d30bb512STodor Tomov static struct i2c_driver ov7251_i2c_driver = { 1640d30bb512STodor Tomov .driver = { 1641d30bb512STodor Tomov .of_match_table = ov7251_of_match, 16426766cff6SDaniel Scally .acpi_match_table = ov7251_acpi_match, 1643d30bb512STodor Tomov .name = "ov7251", 1644d30bb512STodor Tomov }, 1645d30bb512STodor Tomov .probe_new = ov7251_probe, 1646d30bb512STodor Tomov .remove = ov7251_remove, 1647d30bb512STodor Tomov }; 1648d30bb512STodor Tomov 1649d30bb512STodor Tomov module_i2c_driver(ov7251_i2c_driver); 1650d30bb512STodor Tomov 1651d30bb512STodor Tomov MODULE_DESCRIPTION("Omnivision OV7251 Camera Driver"); 1652d30bb512STodor Tomov MODULE_AUTHOR("Todor Tomov <todor.tomov@linaro.org>"); 1653d30bb512STodor Tomov MODULE_LICENSE("GPL v2"); 1654