xref: /linux/drivers/media/i2c/ov7251.c (revision 06d07429858317ded2db7986113a9e0129cd599b)
1d30bb512STodor Tomov // SPDX-License-Identifier: GPL-2.0
2d30bb512STodor Tomov /*
3d30bb512STodor Tomov  * Driver for the OV7251 camera sensor.
4d30bb512STodor Tomov  *
5d30bb512STodor Tomov  * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
6d30bb512STodor Tomov  * Copyright (c) 2017-2018, Linaro Ltd.
7d30bb512STodor Tomov  */
8d30bb512STodor Tomov 
9d30bb512STodor Tomov #include <linux/bitops.h>
10d30bb512STodor Tomov #include <linux/clk.h>
11d30bb512STodor Tomov #include <linux/delay.h>
12d30bb512STodor Tomov #include <linux/device.h>
13d30bb512STodor Tomov #include <linux/gpio/consumer.h>
14d30bb512STodor Tomov #include <linux/i2c.h>
15d30bb512STodor Tomov #include <linux/init.h>
16d30bb512STodor Tomov #include <linux/module.h>
176766cff6SDaniel Scally #include <linux/mod_devicetable.h>
18207f4162SDaniel Scally #include <linux/pm_runtime.h>
19d30bb512STodor Tomov #include <linux/regulator/consumer.h>
20d30bb512STodor Tomov #include <linux/slab.h>
21d30bb512STodor Tomov #include <linux/types.h>
22d30bb512STodor Tomov #include <media/v4l2-ctrls.h>
23d30bb512STodor Tomov #include <media/v4l2-fwnode.h>
24d30bb512STodor Tomov #include <media/v4l2-subdev.h>
25d30bb512STodor Tomov 
26d30bb512STodor Tomov #define OV7251_SC_MODE_SELECT		0x0100
27d30bb512STodor Tomov #define OV7251_SC_MODE_SELECT_SW_STANDBY	0x0
28d30bb512STodor Tomov #define OV7251_SC_MODE_SELECT_STREAMING		0x1
29d30bb512STodor Tomov 
30d30bb512STodor Tomov #define OV7251_CHIP_ID_HIGH		0x300a
31d30bb512STodor Tomov #define OV7251_CHIP_ID_HIGH_BYTE	0x77
32d30bb512STodor Tomov #define OV7251_CHIP_ID_LOW		0x300b
33d30bb512STodor Tomov #define OV7251_CHIP_ID_LOW_BYTE		0x50
34d30bb512STodor Tomov #define OV7251_SC_GP_IO_IN1		0x3029
35d30bb512STodor Tomov #define OV7251_AEC_EXPO_0		0x3500
36d30bb512STodor Tomov #define OV7251_AEC_EXPO_1		0x3501
37d30bb512STodor Tomov #define OV7251_AEC_EXPO_2		0x3502
38d30bb512STodor Tomov #define OV7251_AEC_AGC_ADJ_0		0x350a
39d30bb512STodor Tomov #define OV7251_AEC_AGC_ADJ_1		0x350b
40d30bb512STodor Tomov #define OV7251_TIMING_FORMAT1		0x3820
41d30bb512STodor Tomov #define OV7251_TIMING_FORMAT1_VFLIP	BIT(2)
42d30bb512STodor Tomov #define OV7251_TIMING_FORMAT2		0x3821
43d30bb512STodor Tomov #define OV7251_TIMING_FORMAT2_MIRROR	BIT(2)
44d30bb512STodor Tomov #define OV7251_PRE_ISP_00		0x5e00
45d30bb512STodor Tomov #define OV7251_PRE_ISP_00_TEST_PATTERN	BIT(7)
46df057b0dSDaniel Scally #define OV7251_PLL1_PRE_DIV_REG		0x30b4
47df057b0dSDaniel Scally #define OV7251_PLL1_MULT_REG		0x30b3
48df057b0dSDaniel Scally #define OV7251_PLL1_DIVIDER_REG		0x30b1
49df057b0dSDaniel Scally #define OV7251_PLL1_PIX_DIV_REG		0x30b0
50df057b0dSDaniel Scally #define OV7251_PLL1_MIPI_DIV_REG	0x30b5
51df057b0dSDaniel Scally #define OV7251_PLL2_PRE_DIV_REG		0x3098
52df057b0dSDaniel Scally #define OV7251_PLL2_MULT_REG		0x3099
53df057b0dSDaniel Scally #define OV7251_PLL2_DIVIDER_REG		0x309d
54df057b0dSDaniel Scally #define OV7251_PLL2_SYS_DIV_REG		0x309a
55df057b0dSDaniel Scally #define OV7251_PLL2_ADC_DIV_REG		0x309b
56d30bb512STodor Tomov 
5777ec83cdSDaniel Scally #define OV7251_NATIVE_WIDTH		656
5877ec83cdSDaniel Scally #define OV7251_NATIVE_HEIGHT		496
5977ec83cdSDaniel Scally #define OV7251_ACTIVE_START_LEFT	4
6077ec83cdSDaniel Scally #define OV7251_ACTIVE_START_TOP		4
6177ec83cdSDaniel Scally #define OV7251_ACTIVE_WIDTH		648
6277ec83cdSDaniel Scally #define OV7251_ACTIVE_HEIGHT		488
6377ec83cdSDaniel Scally 
6426066ae6SDaniel Scally #define OV7251_FIXED_PPL		928
651b598f41SDaniel Scally #define OV7251_TIMING_VTS_REG		0x380e
661b598f41SDaniel Scally #define OV7251_TIMING_MIN_VTS		1
671b598f41SDaniel Scally #define OV7251_TIMING_MAX_VTS		0xffff
681b598f41SDaniel Scally #define OV7251_INTEGRATION_MARGIN	20
6926066ae6SDaniel Scally 
70d30bb512STodor Tomov struct reg_value {
71d30bb512STodor Tomov 	u16 reg;
72d30bb512STodor Tomov 	u8 val;
73d30bb512STodor Tomov };
74d30bb512STodor Tomov 
75d30bb512STodor Tomov struct ov7251_mode_info {
76d30bb512STodor Tomov 	u32 width;
77d30bb512STodor Tomov 	u32 height;
781b598f41SDaniel Scally 	u32 vts;
79d30bb512STodor Tomov 	const struct reg_value *data;
80d30bb512STodor Tomov 	u32 data_size;
81d30bb512STodor Tomov 	u32 pixel_clock;
82d30bb512STodor Tomov 	u32 link_freq;
83d30bb512STodor Tomov 	u16 exposure_max;
84d30bb512STodor Tomov 	u16 exposure_def;
85d30bb512STodor Tomov 	struct v4l2_fract timeperframe;
86d30bb512STodor Tomov };
87d30bb512STodor Tomov 
88df057b0dSDaniel Scally struct ov7251_pll1_cfg {
89df057b0dSDaniel Scally 	unsigned int pre_div;
90df057b0dSDaniel Scally 	unsigned int mult;
91df057b0dSDaniel Scally 	unsigned int div;
92df057b0dSDaniel Scally 	unsigned int pix_div;
93df057b0dSDaniel Scally 	unsigned int mipi_div;
94df057b0dSDaniel Scally };
95df057b0dSDaniel Scally 
96df057b0dSDaniel Scally struct ov7251_pll2_cfg {
97df057b0dSDaniel Scally 	unsigned int pre_div;
98df057b0dSDaniel Scally 	unsigned int mult;
99df057b0dSDaniel Scally 	unsigned int div;
100df057b0dSDaniel Scally 	unsigned int sys_div;
101df057b0dSDaniel Scally 	unsigned int adc_div;
102df057b0dSDaniel Scally };
103df057b0dSDaniel Scally 
104df057b0dSDaniel Scally /*
105df057b0dSDaniel Scally  * Rubbish ordering, but only PLL1 needs to have a separate configuration per
106df057b0dSDaniel Scally  * link frequency and the array member needs to be last.
107df057b0dSDaniel Scally  */
108df057b0dSDaniel Scally struct ov7251_pll_cfgs {
109df057b0dSDaniel Scally 	const struct ov7251_pll2_cfg *pll2;
110df057b0dSDaniel Scally 	const struct ov7251_pll1_cfg *pll1[];
111df057b0dSDaniel Scally };
112df057b0dSDaniel Scally 
113df057b0dSDaniel Scally enum xclk_rate {
114ed9566ceSDaniel Scally 	OV7251_19_2_MHZ,
115df057b0dSDaniel Scally 	OV7251_24_MHZ,
116df057b0dSDaniel Scally 	OV7251_NUM_SUPPORTED_RATES
117df057b0dSDaniel Scally };
118df057b0dSDaniel Scally 
119cc125aaaSDaniel Scally enum supported_link_freqs {
120cc125aaaSDaniel Scally 	OV7251_LINK_FREQ_240_MHZ,
121ed9566ceSDaniel Scally 	OV7251_LINK_FREQ_319_2_MHZ,
122cc125aaaSDaniel Scally 	OV7251_NUM_SUPPORTED_LINK_FREQS
123cc125aaaSDaniel Scally };
124cc125aaaSDaniel Scally 
125d30bb512STodor Tomov struct ov7251 {
126d30bb512STodor Tomov 	struct i2c_client *i2c_client;
127d30bb512STodor Tomov 	struct device *dev;
128d30bb512STodor Tomov 	struct v4l2_subdev sd;
129d30bb512STodor Tomov 	struct media_pad pad;
130d30bb512STodor Tomov 	struct v4l2_fwnode_endpoint ep;
131d30bb512STodor Tomov 	struct v4l2_mbus_framefmt fmt;
132d30bb512STodor Tomov 	struct v4l2_rect crop;
133d30bb512STodor Tomov 	struct clk *xclk;
134d30bb512STodor Tomov 	u32 xclk_freq;
135d30bb512STodor Tomov 
136d30bb512STodor Tomov 	struct regulator *io_regulator;
137d30bb512STodor Tomov 	struct regulator *core_regulator;
138d30bb512STodor Tomov 	struct regulator *analog_regulator;
139d30bb512STodor Tomov 
140df057b0dSDaniel Scally 	const struct ov7251_pll_cfgs *pll_cfgs;
141cc125aaaSDaniel Scally 	enum supported_link_freqs link_freq_idx;
142d30bb512STodor Tomov 	const struct ov7251_mode_info *current_mode;
143d30bb512STodor Tomov 
144d30bb512STodor Tomov 	struct v4l2_ctrl_handler ctrls;
145d30bb512STodor Tomov 	struct v4l2_ctrl *pixel_clock;
146d30bb512STodor Tomov 	struct v4l2_ctrl *link_freq;
147d30bb512STodor Tomov 	struct v4l2_ctrl *exposure;
148d30bb512STodor Tomov 	struct v4l2_ctrl *gain;
14926066ae6SDaniel Scally 	struct v4l2_ctrl *hblank;
1501b598f41SDaniel Scally 	struct v4l2_ctrl *vblank;
151d30bb512STodor Tomov 
152d30bb512STodor Tomov 	/* Cached register values */
153d30bb512STodor Tomov 	u8 aec_pk_manual;
154d30bb512STodor Tomov 	u8 pre_isp_00;
155d30bb512STodor Tomov 	u8 timing_format1;
156d30bb512STodor Tomov 	u8 timing_format2;
157d30bb512STodor Tomov 
158d30bb512STodor Tomov 	struct mutex lock; /* lock to protect power state, ctrls and mode */
159d30bb512STodor Tomov 	bool power_on;
160d30bb512STodor Tomov 
161d30bb512STodor Tomov 	struct gpio_desc *enable_gpio;
162d30bb512STodor Tomov };
163d30bb512STodor Tomov 
to_ov7251(struct v4l2_subdev * sd)164d30bb512STodor Tomov static inline struct ov7251 *to_ov7251(struct v4l2_subdev *sd)
165d30bb512STodor Tomov {
166d30bb512STodor Tomov 	return container_of(sd, struct ov7251, sd);
167d30bb512STodor Tomov }
168d30bb512STodor Tomov 
169ed9566ceSDaniel Scally static const struct ov7251_pll1_cfg ov7251_pll1_cfg_19_2_mhz_240_mhz = {
170ed9566ceSDaniel Scally 	.pre_div = 0x03,
171ed9566ceSDaniel Scally 	.mult = 0x4b,
172ed9566ceSDaniel Scally 	.div = 0x01,
173ed9566ceSDaniel Scally 	.pix_div = 0x0a,
174ed9566ceSDaniel Scally 	.mipi_div = 0x05,
175ed9566ceSDaniel Scally };
176ed9566ceSDaniel Scally 
177ed9566ceSDaniel Scally static const struct ov7251_pll1_cfg ov7251_pll1_cfg_19_2_mhz_319_2_mhz = {
178ed9566ceSDaniel Scally 	.pre_div = 0x01,
179ed9566ceSDaniel Scally 	.mult = 0x85,
180ed9566ceSDaniel Scally 	.div = 0x04,
181ed9566ceSDaniel Scally 	.pix_div = 0x0a,
182ed9566ceSDaniel Scally 	.mipi_div = 0x05,
183ed9566ceSDaniel Scally };
184ed9566ceSDaniel Scally 
185df057b0dSDaniel Scally static const struct ov7251_pll1_cfg ov7251_pll1_cfg_24_mhz_240_mhz = {
186df057b0dSDaniel Scally 	.pre_div = 0x03,
187df057b0dSDaniel Scally 	.mult = 0x64,
188df057b0dSDaniel Scally 	.div = 0x01,
189df057b0dSDaniel Scally 	.pix_div = 0x0a,
190df057b0dSDaniel Scally 	.mipi_div = 0x05,
191df057b0dSDaniel Scally };
192df057b0dSDaniel Scally 
193ed9566ceSDaniel Scally static const struct ov7251_pll1_cfg ov7251_pll1_cfg_24_mhz_319_2_mhz = {
194ed9566ceSDaniel Scally 	.pre_div = 0x05,
195ed9566ceSDaniel Scally 	.mult = 0x85,
196ed9566ceSDaniel Scally 	.div = 0x02,
197ed9566ceSDaniel Scally 	.pix_div = 0x0a,
198ed9566ceSDaniel Scally 	.mipi_div = 0x05,
199ed9566ceSDaniel Scally };
200ed9566ceSDaniel Scally 
201ed9566ceSDaniel Scally static const struct ov7251_pll2_cfg ov7251_pll2_cfg_19_2_mhz = {
202ed9566ceSDaniel Scally 	.pre_div = 0x04,
203ed9566ceSDaniel Scally 	.mult = 0x32,
204ed9566ceSDaniel Scally 	.div = 0x00,
205ed9566ceSDaniel Scally 	.sys_div = 0x05,
206ed9566ceSDaniel Scally 	.adc_div = 0x04,
207ed9566ceSDaniel Scally };
208ed9566ceSDaniel Scally 
209df057b0dSDaniel Scally static const struct ov7251_pll2_cfg ov7251_pll2_cfg_24_mhz = {
210df057b0dSDaniel Scally 	.pre_div = 0x04,
211df057b0dSDaniel Scally 	.mult = 0x28,
212df057b0dSDaniel Scally 	.div = 0x00,
213df057b0dSDaniel Scally 	.sys_div = 0x05,
214df057b0dSDaniel Scally 	.adc_div = 0x04,
215df057b0dSDaniel Scally };
216df057b0dSDaniel Scally 
217ed9566ceSDaniel Scally static const struct ov7251_pll_cfgs ov7251_pll_cfgs_19_2_mhz = {
218ed9566ceSDaniel Scally 	.pll2 = &ov7251_pll2_cfg_19_2_mhz,
219ed9566ceSDaniel Scally 	.pll1 = {
220ed9566ceSDaniel Scally 		[OV7251_LINK_FREQ_240_MHZ] = &ov7251_pll1_cfg_19_2_mhz_240_mhz,
221ed9566ceSDaniel Scally 		[OV7251_LINK_FREQ_319_2_MHZ] = &ov7251_pll1_cfg_19_2_mhz_319_2_mhz,
222ed9566ceSDaniel Scally 	},
223ed9566ceSDaniel Scally };
224ed9566ceSDaniel Scally 
225df057b0dSDaniel Scally static const struct ov7251_pll_cfgs ov7251_pll_cfgs_24_mhz = {
226df057b0dSDaniel Scally 	.pll2 = &ov7251_pll2_cfg_24_mhz,
227df057b0dSDaniel Scally 	.pll1 = {
228df057b0dSDaniel Scally 		[OV7251_LINK_FREQ_240_MHZ] = &ov7251_pll1_cfg_24_mhz_240_mhz,
229ed9566ceSDaniel Scally 		[OV7251_LINK_FREQ_319_2_MHZ] = &ov7251_pll1_cfg_24_mhz_319_2_mhz,
230df057b0dSDaniel Scally 	},
231df057b0dSDaniel Scally };
232df057b0dSDaniel Scally 
233df057b0dSDaniel Scally static const struct ov7251_pll_cfgs *ov7251_pll_cfgs[] = {
234ed9566ceSDaniel Scally 	[OV7251_19_2_MHZ] = &ov7251_pll_cfgs_19_2_mhz,
235df057b0dSDaniel Scally 	[OV7251_24_MHZ] = &ov7251_pll_cfgs_24_mhz,
236df057b0dSDaniel Scally };
237df057b0dSDaniel Scally 
238d30bb512STodor Tomov static const struct reg_value ov7251_global_init_setting[] = {
239d30bb512STodor Tomov 	{ 0x0103, 0x01 },
240d30bb512STodor Tomov 	{ 0x303b, 0x02 },
241d30bb512STodor Tomov };
242d30bb512STodor Tomov 
243d30bb512STodor Tomov static const struct reg_value ov7251_setting_vga_30fps[] = {
244d30bb512STodor Tomov 	{ 0x3005, 0x00 },
245d30bb512STodor Tomov 	{ 0x3012, 0xc0 },
246d30bb512STodor Tomov 	{ 0x3013, 0xd2 },
247d30bb512STodor Tomov 	{ 0x3014, 0x04 },
248d30bb512STodor Tomov 	{ 0x3016, 0xf0 },
249d30bb512STodor Tomov 	{ 0x3017, 0xf0 },
250d30bb512STodor Tomov 	{ 0x3018, 0xf0 },
251d30bb512STodor Tomov 	{ 0x301a, 0xf0 },
252d30bb512STodor Tomov 	{ 0x301b, 0xf0 },
253d30bb512STodor Tomov 	{ 0x301c, 0xf0 },
254d30bb512STodor Tomov 	{ 0x3023, 0x05 },
255d30bb512STodor Tomov 	{ 0x3037, 0xf0 },
256d30bb512STodor Tomov 	{ 0x3106, 0xda },
257d30bb512STodor Tomov 	{ 0x3503, 0x07 },
258d30bb512STodor Tomov 	{ 0x3509, 0x10 },
259d30bb512STodor Tomov 	{ 0x3600, 0x1c },
260d30bb512STodor Tomov 	{ 0x3602, 0x62 },
261d30bb512STodor Tomov 	{ 0x3620, 0xb7 },
262d30bb512STodor Tomov 	{ 0x3622, 0x04 },
263d30bb512STodor Tomov 	{ 0x3626, 0x21 },
264d30bb512STodor Tomov 	{ 0x3627, 0x30 },
265d30bb512STodor Tomov 	{ 0x3630, 0x44 },
266d30bb512STodor Tomov 	{ 0x3631, 0x35 },
267d30bb512STodor Tomov 	{ 0x3634, 0x60 },
268d30bb512STodor Tomov 	{ 0x3636, 0x00 },
269d30bb512STodor Tomov 	{ 0x3662, 0x01 },
270d30bb512STodor Tomov 	{ 0x3663, 0x70 },
271d30bb512STodor Tomov 	{ 0x3664, 0x50 },
272d30bb512STodor Tomov 	{ 0x3666, 0x0a },
273d30bb512STodor Tomov 	{ 0x3669, 0x1a },
274d30bb512STodor Tomov 	{ 0x366a, 0x00 },
275d30bb512STodor Tomov 	{ 0x366b, 0x50 },
276d30bb512STodor Tomov 	{ 0x3673, 0x01 },
277d30bb512STodor Tomov 	{ 0x3674, 0xff },
278d30bb512STodor Tomov 	{ 0x3675, 0x03 },
279d30bb512STodor Tomov 	{ 0x3705, 0xc1 },
280d30bb512STodor Tomov 	{ 0x3709, 0x40 },
281d30bb512STodor Tomov 	{ 0x373c, 0x08 },
282d30bb512STodor Tomov 	{ 0x3742, 0x00 },
283d30bb512STodor Tomov 	{ 0x3757, 0xb3 },
284d30bb512STodor Tomov 	{ 0x3788, 0x00 },
285d30bb512STodor Tomov 	{ 0x37a8, 0x01 },
286d30bb512STodor Tomov 	{ 0x37a9, 0xc0 },
287d30bb512STodor Tomov 	{ 0x3800, 0x00 },
288d30bb512STodor Tomov 	{ 0x3801, 0x04 },
289d30bb512STodor Tomov 	{ 0x3802, 0x00 },
290d30bb512STodor Tomov 	{ 0x3803, 0x04 },
291d30bb512STodor Tomov 	{ 0x3804, 0x02 },
292d30bb512STodor Tomov 	{ 0x3805, 0x8b },
293d30bb512STodor Tomov 	{ 0x3806, 0x01 },
294d30bb512STodor Tomov 	{ 0x3807, 0xeb },
295d30bb512STodor Tomov 	{ 0x3808, 0x02 }, /* width high */
296d30bb512STodor Tomov 	{ 0x3809, 0x80 }, /* width low */
297d30bb512STodor Tomov 	{ 0x380a, 0x01 }, /* height high */
298d30bb512STodor Tomov 	{ 0x380b, 0xe0 }, /* height low */
299d30bb512STodor Tomov 	{ 0x380c, 0x03 }, /* total horiz timing high */
300d30bb512STodor Tomov 	{ 0x380d, 0xa0 }, /* total horiz timing low */
301d30bb512STodor Tomov 	{ 0x380e, 0x06 }, /* total vertical timing high */
302d30bb512STodor Tomov 	{ 0x380f, 0xbc }, /* total vertical timing low */
303d30bb512STodor Tomov 	{ 0x3810, 0x00 },
304d30bb512STodor Tomov 	{ 0x3811, 0x04 },
305d30bb512STodor Tomov 	{ 0x3812, 0x00 },
306d30bb512STodor Tomov 	{ 0x3813, 0x05 },
307d30bb512STodor Tomov 	{ 0x3814, 0x11 },
308d30bb512STodor Tomov 	{ 0x3815, 0x11 },
309d30bb512STodor Tomov 	{ 0x3820, 0x40 },
310d30bb512STodor Tomov 	{ 0x3821, 0x00 },
311d30bb512STodor Tomov 	{ 0x382f, 0x0e },
312d30bb512STodor Tomov 	{ 0x3832, 0x00 },
313d30bb512STodor Tomov 	{ 0x3833, 0x05 },
314d30bb512STodor Tomov 	{ 0x3834, 0x00 },
315d30bb512STodor Tomov 	{ 0x3835, 0x0c },
316d30bb512STodor Tomov 	{ 0x3837, 0x00 },
317d30bb512STodor Tomov 	{ 0x3b80, 0x00 },
318d30bb512STodor Tomov 	{ 0x3b81, 0xa5 },
319d30bb512STodor Tomov 	{ 0x3b82, 0x10 },
320d30bb512STodor Tomov 	{ 0x3b83, 0x00 },
321d30bb512STodor Tomov 	{ 0x3b84, 0x08 },
322d30bb512STodor Tomov 	{ 0x3b85, 0x00 },
323d30bb512STodor Tomov 	{ 0x3b86, 0x01 },
324d30bb512STodor Tomov 	{ 0x3b87, 0x00 },
325d30bb512STodor Tomov 	{ 0x3b88, 0x00 },
326d30bb512STodor Tomov 	{ 0x3b89, 0x00 },
327d30bb512STodor Tomov 	{ 0x3b8a, 0x00 },
328d30bb512STodor Tomov 	{ 0x3b8b, 0x05 },
329d30bb512STodor Tomov 	{ 0x3b8c, 0x00 },
330d30bb512STodor Tomov 	{ 0x3b8d, 0x00 },
331d30bb512STodor Tomov 	{ 0x3b8e, 0x00 },
332d30bb512STodor Tomov 	{ 0x3b8f, 0x1a },
333d30bb512STodor Tomov 	{ 0x3b94, 0x05 },
334d30bb512STodor Tomov 	{ 0x3b95, 0xf2 },
335d30bb512STodor Tomov 	{ 0x3b96, 0x40 },
336d30bb512STodor Tomov 	{ 0x3c00, 0x89 },
337d30bb512STodor Tomov 	{ 0x3c01, 0x63 },
338d30bb512STodor Tomov 	{ 0x3c02, 0x01 },
339d30bb512STodor Tomov 	{ 0x3c03, 0x00 },
340d30bb512STodor Tomov 	{ 0x3c04, 0x00 },
341d30bb512STodor Tomov 	{ 0x3c05, 0x03 },
342d30bb512STodor Tomov 	{ 0x3c06, 0x00 },
343d30bb512STodor Tomov 	{ 0x3c07, 0x06 },
344d30bb512STodor Tomov 	{ 0x3c0c, 0x01 },
345d30bb512STodor Tomov 	{ 0x3c0d, 0xd0 },
346d30bb512STodor Tomov 	{ 0x3c0e, 0x02 },
347d30bb512STodor Tomov 	{ 0x3c0f, 0x0a },
348d30bb512STodor Tomov 	{ 0x4001, 0x42 },
349d30bb512STodor Tomov 	{ 0x4004, 0x04 },
350d30bb512STodor Tomov 	{ 0x4005, 0x00 },
351d30bb512STodor Tomov 	{ 0x404e, 0x01 },
352d30bb512STodor Tomov 	{ 0x4300, 0xff },
353d30bb512STodor Tomov 	{ 0x4301, 0x00 },
354d30bb512STodor Tomov 	{ 0x4315, 0x00 },
355d30bb512STodor Tomov 	{ 0x4501, 0x48 },
356d30bb512STodor Tomov 	{ 0x4600, 0x00 },
357d30bb512STodor Tomov 	{ 0x4601, 0x4e },
358d30bb512STodor Tomov 	{ 0x4801, 0x0f },
359d30bb512STodor Tomov 	{ 0x4806, 0x0f },
360d30bb512STodor Tomov 	{ 0x4819, 0xaa },
361d30bb512STodor Tomov 	{ 0x4823, 0x3e },
362d30bb512STodor Tomov 	{ 0x4837, 0x19 },
363d30bb512STodor Tomov 	{ 0x4a0d, 0x00 },
364d30bb512STodor Tomov 	{ 0x4a47, 0x7f },
365d30bb512STodor Tomov 	{ 0x4a49, 0xf0 },
366d30bb512STodor Tomov 	{ 0x4a4b, 0x30 },
367d30bb512STodor Tomov 	{ 0x5000, 0x85 },
368d30bb512STodor Tomov 	{ 0x5001, 0x80 },
369d30bb512STodor Tomov };
370d30bb512STodor Tomov 
371d30bb512STodor Tomov static const struct reg_value ov7251_setting_vga_60fps[] = {
372d30bb512STodor Tomov 	{ 0x3005, 0x00 },
373d30bb512STodor Tomov 	{ 0x3012, 0xc0 },
374d30bb512STodor Tomov 	{ 0x3013, 0xd2 },
375d30bb512STodor Tomov 	{ 0x3014, 0x04 },
376d30bb512STodor Tomov 	{ 0x3016, 0x10 },
377d30bb512STodor Tomov 	{ 0x3017, 0x00 },
378d30bb512STodor Tomov 	{ 0x3018, 0x00 },
379d30bb512STodor Tomov 	{ 0x301a, 0x00 },
380d30bb512STodor Tomov 	{ 0x301b, 0x00 },
381d30bb512STodor Tomov 	{ 0x301c, 0x00 },
382d30bb512STodor Tomov 	{ 0x3023, 0x05 },
383d30bb512STodor Tomov 	{ 0x3037, 0xf0 },
384d30bb512STodor Tomov 	{ 0x3106, 0xda },
385d30bb512STodor Tomov 	{ 0x3503, 0x07 },
386d30bb512STodor Tomov 	{ 0x3509, 0x10 },
387d30bb512STodor Tomov 	{ 0x3600, 0x1c },
388d30bb512STodor Tomov 	{ 0x3602, 0x62 },
389d30bb512STodor Tomov 	{ 0x3620, 0xb7 },
390d30bb512STodor Tomov 	{ 0x3622, 0x04 },
391d30bb512STodor Tomov 	{ 0x3626, 0x21 },
392d30bb512STodor Tomov 	{ 0x3627, 0x30 },
393d30bb512STodor Tomov 	{ 0x3630, 0x44 },
394d30bb512STodor Tomov 	{ 0x3631, 0x35 },
395d30bb512STodor Tomov 	{ 0x3634, 0x60 },
396d30bb512STodor Tomov 	{ 0x3636, 0x00 },
397d30bb512STodor Tomov 	{ 0x3662, 0x01 },
398d30bb512STodor Tomov 	{ 0x3663, 0x70 },
399d30bb512STodor Tomov 	{ 0x3664, 0x50 },
400d30bb512STodor Tomov 	{ 0x3666, 0x0a },
401d30bb512STodor Tomov 	{ 0x3669, 0x1a },
402d30bb512STodor Tomov 	{ 0x366a, 0x00 },
403d30bb512STodor Tomov 	{ 0x366b, 0x50 },
404d30bb512STodor Tomov 	{ 0x3673, 0x01 },
405d30bb512STodor Tomov 	{ 0x3674, 0xff },
406d30bb512STodor Tomov 	{ 0x3675, 0x03 },
407d30bb512STodor Tomov 	{ 0x3705, 0xc1 },
408d30bb512STodor Tomov 	{ 0x3709, 0x40 },
409d30bb512STodor Tomov 	{ 0x373c, 0x08 },
410d30bb512STodor Tomov 	{ 0x3742, 0x00 },
411d30bb512STodor Tomov 	{ 0x3757, 0xb3 },
412d30bb512STodor Tomov 	{ 0x3788, 0x00 },
413d30bb512STodor Tomov 	{ 0x37a8, 0x01 },
414d30bb512STodor Tomov 	{ 0x37a9, 0xc0 },
415d30bb512STodor Tomov 	{ 0x3800, 0x00 },
416d30bb512STodor Tomov 	{ 0x3801, 0x04 },
417d30bb512STodor Tomov 	{ 0x3802, 0x00 },
418d30bb512STodor Tomov 	{ 0x3803, 0x04 },
419d30bb512STodor Tomov 	{ 0x3804, 0x02 },
420d30bb512STodor Tomov 	{ 0x3805, 0x8b },
421d30bb512STodor Tomov 	{ 0x3806, 0x01 },
422d30bb512STodor Tomov 	{ 0x3807, 0xeb },
423d30bb512STodor Tomov 	{ 0x3808, 0x02 }, /* width high */
424d30bb512STodor Tomov 	{ 0x3809, 0x80 }, /* width low */
425d30bb512STodor Tomov 	{ 0x380a, 0x01 }, /* height high */
426d30bb512STodor Tomov 	{ 0x380b, 0xe0 }, /* height low */
427d30bb512STodor Tomov 	{ 0x380c, 0x03 }, /* total horiz timing high */
428d30bb512STodor Tomov 	{ 0x380d, 0xa0 }, /* total horiz timing low */
429d30bb512STodor Tomov 	{ 0x380e, 0x03 }, /* total vertical timing high */
430d30bb512STodor Tomov 	{ 0x380f, 0x5c }, /* total vertical timing low */
431d30bb512STodor Tomov 	{ 0x3810, 0x00 },
432d30bb512STodor Tomov 	{ 0x3811, 0x04 },
433d30bb512STodor Tomov 	{ 0x3812, 0x00 },
434d30bb512STodor Tomov 	{ 0x3813, 0x05 },
435d30bb512STodor Tomov 	{ 0x3814, 0x11 },
436d30bb512STodor Tomov 	{ 0x3815, 0x11 },
437d30bb512STodor Tomov 	{ 0x3820, 0x40 },
438d30bb512STodor Tomov 	{ 0x3821, 0x00 },
439d30bb512STodor Tomov 	{ 0x382f, 0x0e },
440d30bb512STodor Tomov 	{ 0x3832, 0x00 },
441d30bb512STodor Tomov 	{ 0x3833, 0x05 },
442d30bb512STodor Tomov 	{ 0x3834, 0x00 },
443d30bb512STodor Tomov 	{ 0x3835, 0x0c },
444d30bb512STodor Tomov 	{ 0x3837, 0x00 },
445d30bb512STodor Tomov 	{ 0x3b80, 0x00 },
446d30bb512STodor Tomov 	{ 0x3b81, 0xa5 },
447d30bb512STodor Tomov 	{ 0x3b82, 0x10 },
448d30bb512STodor Tomov 	{ 0x3b83, 0x00 },
449d30bb512STodor Tomov 	{ 0x3b84, 0x08 },
450d30bb512STodor Tomov 	{ 0x3b85, 0x00 },
451d30bb512STodor Tomov 	{ 0x3b86, 0x01 },
452d30bb512STodor Tomov 	{ 0x3b87, 0x00 },
453d30bb512STodor Tomov 	{ 0x3b88, 0x00 },
454d30bb512STodor Tomov 	{ 0x3b89, 0x00 },
455d30bb512STodor Tomov 	{ 0x3b8a, 0x00 },
456d30bb512STodor Tomov 	{ 0x3b8b, 0x05 },
457d30bb512STodor Tomov 	{ 0x3b8c, 0x00 },
458d30bb512STodor Tomov 	{ 0x3b8d, 0x00 },
459d30bb512STodor Tomov 	{ 0x3b8e, 0x00 },
460d30bb512STodor Tomov 	{ 0x3b8f, 0x1a },
461d30bb512STodor Tomov 	{ 0x3b94, 0x05 },
462d30bb512STodor Tomov 	{ 0x3b95, 0xf2 },
463d30bb512STodor Tomov 	{ 0x3b96, 0x40 },
464d30bb512STodor Tomov 	{ 0x3c00, 0x89 },
465d30bb512STodor Tomov 	{ 0x3c01, 0x63 },
466d30bb512STodor Tomov 	{ 0x3c02, 0x01 },
467d30bb512STodor Tomov 	{ 0x3c03, 0x00 },
468d30bb512STodor Tomov 	{ 0x3c04, 0x00 },
469d30bb512STodor Tomov 	{ 0x3c05, 0x03 },
470d30bb512STodor Tomov 	{ 0x3c06, 0x00 },
471d30bb512STodor Tomov 	{ 0x3c07, 0x06 },
472d30bb512STodor Tomov 	{ 0x3c0c, 0x01 },
473d30bb512STodor Tomov 	{ 0x3c0d, 0xd0 },
474d30bb512STodor Tomov 	{ 0x3c0e, 0x02 },
475d30bb512STodor Tomov 	{ 0x3c0f, 0x0a },
476d30bb512STodor Tomov 	{ 0x4001, 0x42 },
477d30bb512STodor Tomov 	{ 0x4004, 0x04 },
478d30bb512STodor Tomov 	{ 0x4005, 0x00 },
479d30bb512STodor Tomov 	{ 0x404e, 0x01 },
480d30bb512STodor Tomov 	{ 0x4300, 0xff },
481d30bb512STodor Tomov 	{ 0x4301, 0x00 },
482d30bb512STodor Tomov 	{ 0x4315, 0x00 },
483d30bb512STodor Tomov 	{ 0x4501, 0x48 },
484d30bb512STodor Tomov 	{ 0x4600, 0x00 },
485d30bb512STodor Tomov 	{ 0x4601, 0x4e },
486d30bb512STodor Tomov 	{ 0x4801, 0x0f },
487d30bb512STodor Tomov 	{ 0x4806, 0x0f },
488d30bb512STodor Tomov 	{ 0x4819, 0xaa },
489d30bb512STodor Tomov 	{ 0x4823, 0x3e },
490d30bb512STodor Tomov 	{ 0x4837, 0x19 },
491d30bb512STodor Tomov 	{ 0x4a0d, 0x00 },
492d30bb512STodor Tomov 	{ 0x4a47, 0x7f },
493d30bb512STodor Tomov 	{ 0x4a49, 0xf0 },
494d30bb512STodor Tomov 	{ 0x4a4b, 0x30 },
495d30bb512STodor Tomov 	{ 0x5000, 0x85 },
496d30bb512STodor Tomov 	{ 0x5001, 0x80 },
497d30bb512STodor Tomov };
498d30bb512STodor Tomov 
499d30bb512STodor Tomov static const struct reg_value ov7251_setting_vga_90fps[] = {
500d30bb512STodor Tomov 	{ 0x3005, 0x00 },
501d30bb512STodor Tomov 	{ 0x3012, 0xc0 },
502d30bb512STodor Tomov 	{ 0x3013, 0xd2 },
503d30bb512STodor Tomov 	{ 0x3014, 0x04 },
504d30bb512STodor Tomov 	{ 0x3016, 0x10 },
505d30bb512STodor Tomov 	{ 0x3017, 0x00 },
506d30bb512STodor Tomov 	{ 0x3018, 0x00 },
507d30bb512STodor Tomov 	{ 0x301a, 0x00 },
508d30bb512STodor Tomov 	{ 0x301b, 0x00 },
509d30bb512STodor Tomov 	{ 0x301c, 0x00 },
510d30bb512STodor Tomov 	{ 0x3023, 0x05 },
511d30bb512STodor Tomov 	{ 0x3037, 0xf0 },
512d30bb512STodor Tomov 	{ 0x3106, 0xda },
513d30bb512STodor Tomov 	{ 0x3503, 0x07 },
514d30bb512STodor Tomov 	{ 0x3509, 0x10 },
515d30bb512STodor Tomov 	{ 0x3600, 0x1c },
516d30bb512STodor Tomov 	{ 0x3602, 0x62 },
517d30bb512STodor Tomov 	{ 0x3620, 0xb7 },
518d30bb512STodor Tomov 	{ 0x3622, 0x04 },
519d30bb512STodor Tomov 	{ 0x3626, 0x21 },
520d30bb512STodor Tomov 	{ 0x3627, 0x30 },
521d30bb512STodor Tomov 	{ 0x3630, 0x44 },
522d30bb512STodor Tomov 	{ 0x3631, 0x35 },
523d30bb512STodor Tomov 	{ 0x3634, 0x60 },
524d30bb512STodor Tomov 	{ 0x3636, 0x00 },
525d30bb512STodor Tomov 	{ 0x3662, 0x01 },
526d30bb512STodor Tomov 	{ 0x3663, 0x70 },
527d30bb512STodor Tomov 	{ 0x3664, 0x50 },
528d30bb512STodor Tomov 	{ 0x3666, 0x0a },
529d30bb512STodor Tomov 	{ 0x3669, 0x1a },
530d30bb512STodor Tomov 	{ 0x366a, 0x00 },
531d30bb512STodor Tomov 	{ 0x366b, 0x50 },
532d30bb512STodor Tomov 	{ 0x3673, 0x01 },
533d30bb512STodor Tomov 	{ 0x3674, 0xff },
534d30bb512STodor Tomov 	{ 0x3675, 0x03 },
535d30bb512STodor Tomov 	{ 0x3705, 0xc1 },
536d30bb512STodor Tomov 	{ 0x3709, 0x40 },
537d30bb512STodor Tomov 	{ 0x373c, 0x08 },
538d30bb512STodor Tomov 	{ 0x3742, 0x00 },
539d30bb512STodor Tomov 	{ 0x3757, 0xb3 },
540d30bb512STodor Tomov 	{ 0x3788, 0x00 },
541d30bb512STodor Tomov 	{ 0x37a8, 0x01 },
542d30bb512STodor Tomov 	{ 0x37a9, 0xc0 },
543d30bb512STodor Tomov 	{ 0x3800, 0x00 },
544d30bb512STodor Tomov 	{ 0x3801, 0x04 },
545d30bb512STodor Tomov 	{ 0x3802, 0x00 },
546d30bb512STodor Tomov 	{ 0x3803, 0x04 },
547d30bb512STodor Tomov 	{ 0x3804, 0x02 },
548d30bb512STodor Tomov 	{ 0x3805, 0x8b },
549d30bb512STodor Tomov 	{ 0x3806, 0x01 },
550d30bb512STodor Tomov 	{ 0x3807, 0xeb },
551d30bb512STodor Tomov 	{ 0x3808, 0x02 }, /* width high */
552d30bb512STodor Tomov 	{ 0x3809, 0x80 }, /* width low */
553d30bb512STodor Tomov 	{ 0x380a, 0x01 }, /* height high */
554d30bb512STodor Tomov 	{ 0x380b, 0xe0 }, /* height low */
555d30bb512STodor Tomov 	{ 0x380c, 0x03 }, /* total horiz timing high */
556d30bb512STodor Tomov 	{ 0x380d, 0xa0 }, /* total horiz timing low */
557d30bb512STodor Tomov 	{ 0x380e, 0x02 }, /* total vertical timing high */
558d30bb512STodor Tomov 	{ 0x380f, 0x3c }, /* total vertical timing low */
559d30bb512STodor Tomov 	{ 0x3810, 0x00 },
560d30bb512STodor Tomov 	{ 0x3811, 0x04 },
561d30bb512STodor Tomov 	{ 0x3812, 0x00 },
562d30bb512STodor Tomov 	{ 0x3813, 0x05 },
563d30bb512STodor Tomov 	{ 0x3814, 0x11 },
564d30bb512STodor Tomov 	{ 0x3815, 0x11 },
565d30bb512STodor Tomov 	{ 0x3820, 0x40 },
566d30bb512STodor Tomov 	{ 0x3821, 0x00 },
567d30bb512STodor Tomov 	{ 0x382f, 0x0e },
568d30bb512STodor Tomov 	{ 0x3832, 0x00 },
569d30bb512STodor Tomov 	{ 0x3833, 0x05 },
570d30bb512STodor Tomov 	{ 0x3834, 0x00 },
571d30bb512STodor Tomov 	{ 0x3835, 0x0c },
572d30bb512STodor Tomov 	{ 0x3837, 0x00 },
573d30bb512STodor Tomov 	{ 0x3b80, 0x00 },
574d30bb512STodor Tomov 	{ 0x3b81, 0xa5 },
575d30bb512STodor Tomov 	{ 0x3b82, 0x10 },
576d30bb512STodor Tomov 	{ 0x3b83, 0x00 },
577d30bb512STodor Tomov 	{ 0x3b84, 0x08 },
578d30bb512STodor Tomov 	{ 0x3b85, 0x00 },
579d30bb512STodor Tomov 	{ 0x3b86, 0x01 },
580d30bb512STodor Tomov 	{ 0x3b87, 0x00 },
581d30bb512STodor Tomov 	{ 0x3b88, 0x00 },
582d30bb512STodor Tomov 	{ 0x3b89, 0x00 },
583d30bb512STodor Tomov 	{ 0x3b8a, 0x00 },
584d30bb512STodor Tomov 	{ 0x3b8b, 0x05 },
585d30bb512STodor Tomov 	{ 0x3b8c, 0x00 },
586d30bb512STodor Tomov 	{ 0x3b8d, 0x00 },
587d30bb512STodor Tomov 	{ 0x3b8e, 0x00 },
588d30bb512STodor Tomov 	{ 0x3b8f, 0x1a },
589d30bb512STodor Tomov 	{ 0x3b94, 0x05 },
590d30bb512STodor Tomov 	{ 0x3b95, 0xf2 },
591d30bb512STodor Tomov 	{ 0x3b96, 0x40 },
592d30bb512STodor Tomov 	{ 0x3c00, 0x89 },
593d30bb512STodor Tomov 	{ 0x3c01, 0x63 },
594d30bb512STodor Tomov 	{ 0x3c02, 0x01 },
595d30bb512STodor Tomov 	{ 0x3c03, 0x00 },
596d30bb512STodor Tomov 	{ 0x3c04, 0x00 },
597d30bb512STodor Tomov 	{ 0x3c05, 0x03 },
598d30bb512STodor Tomov 	{ 0x3c06, 0x00 },
599d30bb512STodor Tomov 	{ 0x3c07, 0x06 },
600d30bb512STodor Tomov 	{ 0x3c0c, 0x01 },
601d30bb512STodor Tomov 	{ 0x3c0d, 0xd0 },
602d30bb512STodor Tomov 	{ 0x3c0e, 0x02 },
603d30bb512STodor Tomov 	{ 0x3c0f, 0x0a },
604d30bb512STodor Tomov 	{ 0x4001, 0x42 },
605d30bb512STodor Tomov 	{ 0x4004, 0x04 },
606d30bb512STodor Tomov 	{ 0x4005, 0x00 },
607d30bb512STodor Tomov 	{ 0x404e, 0x01 },
608d30bb512STodor Tomov 	{ 0x4300, 0xff },
609d30bb512STodor Tomov 	{ 0x4301, 0x00 },
610d30bb512STodor Tomov 	{ 0x4315, 0x00 },
611d30bb512STodor Tomov 	{ 0x4501, 0x48 },
612d30bb512STodor Tomov 	{ 0x4600, 0x00 },
613d30bb512STodor Tomov 	{ 0x4601, 0x4e },
614d30bb512STodor Tomov 	{ 0x4801, 0x0f },
615d30bb512STodor Tomov 	{ 0x4806, 0x0f },
616d30bb512STodor Tomov 	{ 0x4819, 0xaa },
617d30bb512STodor Tomov 	{ 0x4823, 0x3e },
618d30bb512STodor Tomov 	{ 0x4837, 0x19 },
619d30bb512STodor Tomov 	{ 0x4a0d, 0x00 },
620d30bb512STodor Tomov 	{ 0x4a47, 0x7f },
621d30bb512STodor Tomov 	{ 0x4a49, 0xf0 },
622d30bb512STodor Tomov 	{ 0x4a4b, 0x30 },
623d30bb512STodor Tomov 	{ 0x5000, 0x85 },
624d30bb512STodor Tomov 	{ 0x5001, 0x80 },
625d30bb512STodor Tomov };
626d30bb512STodor Tomov 
627df057b0dSDaniel Scally static const unsigned long supported_xclk_rates[] = {
628ed9566ceSDaniel Scally 	[OV7251_19_2_MHZ] = 19200000,
629df057b0dSDaniel Scally 	[OV7251_24_MHZ] = 24000000,
630df057b0dSDaniel Scally };
631df057b0dSDaniel Scally 
632d30bb512STodor Tomov static const s64 link_freq[] = {
6331757b44eSDaniel Scally 	[OV7251_LINK_FREQ_240_MHZ] = 240000000,
634ed9566ceSDaniel Scally 	[OV7251_LINK_FREQ_319_2_MHZ] = 319200000,
6351757b44eSDaniel Scally };
6361757b44eSDaniel Scally 
6371757b44eSDaniel Scally static const s64 pixel_rates[] = {
6381757b44eSDaniel Scally 	[OV7251_LINK_FREQ_240_MHZ] = 48000000,
639ed9566ceSDaniel Scally 	[OV7251_LINK_FREQ_319_2_MHZ] = 63840000,
640d30bb512STodor Tomov };
641d30bb512STodor Tomov 
642d30bb512STodor Tomov static const struct ov7251_mode_info ov7251_mode_info_data[] = {
643d30bb512STodor Tomov 	{
644d30bb512STodor Tomov 		.width = 640,
645d30bb512STodor Tomov 		.height = 480,
6461b598f41SDaniel Scally 		.vts = 1724,
647d30bb512STodor Tomov 		.data = ov7251_setting_vga_30fps,
648d30bb512STodor Tomov 		.data_size = ARRAY_SIZE(ov7251_setting_vga_30fps),
649d30bb512STodor Tomov 		.exposure_max = 1704,
650d30bb512STodor Tomov 		.exposure_def = 504,
651d30bb512STodor Tomov 		.timeperframe = {
652d30bb512STodor Tomov 			.numerator = 100,
653d30bb512STodor Tomov 			.denominator = 3000
654d30bb512STodor Tomov 		}
655d30bb512STodor Tomov 	},
656d30bb512STodor Tomov 	{
657d30bb512STodor Tomov 		.width = 640,
658d30bb512STodor Tomov 		.height = 480,
6591b598f41SDaniel Scally 		.vts = 860,
660d30bb512STodor Tomov 		.data = ov7251_setting_vga_60fps,
661d30bb512STodor Tomov 		.data_size = ARRAY_SIZE(ov7251_setting_vga_60fps),
662d30bb512STodor Tomov 		.exposure_max = 840,
663d30bb512STodor Tomov 		.exposure_def = 504,
664d30bb512STodor Tomov 		.timeperframe = {
665d30bb512STodor Tomov 			.numerator = 100,
666d30bb512STodor Tomov 			.denominator = 6014
667d30bb512STodor Tomov 		}
668d30bb512STodor Tomov 	},
669d30bb512STodor Tomov 	{
670d30bb512STodor Tomov 		.width = 640,
671d30bb512STodor Tomov 		.height = 480,
6721b598f41SDaniel Scally 		.vts = 572,
673d30bb512STodor Tomov 		.data = ov7251_setting_vga_90fps,
674d30bb512STodor Tomov 		.data_size = ARRAY_SIZE(ov7251_setting_vga_90fps),
675d30bb512STodor Tomov 		.exposure_max = 552,
676d30bb512STodor Tomov 		.exposure_def = 504,
677d30bb512STodor Tomov 		.timeperframe = {
678d30bb512STodor Tomov 			.numerator = 100,
679d30bb512STodor Tomov 			.denominator = 9043
680d30bb512STodor Tomov 		}
681d30bb512STodor Tomov 	},
682d30bb512STodor Tomov };
683d30bb512STodor Tomov 
ov7251_regulators_enable(struct ov7251 * ov7251)684d30bb512STodor Tomov static int ov7251_regulators_enable(struct ov7251 *ov7251)
685d30bb512STodor Tomov {
686d30bb512STodor Tomov 	int ret;
687d30bb512STodor Tomov 
688d30bb512STodor Tomov 	/* OV7251 power up sequence requires core regulator
689d30bb512STodor Tomov 	 * to be enabled not earlier than io regulator
690d30bb512STodor Tomov 	 */
691d30bb512STodor Tomov 
692d30bb512STodor Tomov 	ret = regulator_enable(ov7251->io_regulator);
693d30bb512STodor Tomov 	if (ret < 0) {
694d30bb512STodor Tomov 		dev_err(ov7251->dev, "set io voltage failed\n");
695d30bb512STodor Tomov 		return ret;
696d30bb512STodor Tomov 	}
697d30bb512STodor Tomov 
698d30bb512STodor Tomov 	ret = regulator_enable(ov7251->analog_regulator);
699d30bb512STodor Tomov 	if (ret) {
700d30bb512STodor Tomov 		dev_err(ov7251->dev, "set analog voltage failed\n");
701d30bb512STodor Tomov 		goto err_disable_io;
702d30bb512STodor Tomov 	}
703d30bb512STodor Tomov 
704d30bb512STodor Tomov 	ret = regulator_enable(ov7251->core_regulator);
705d30bb512STodor Tomov 	if (ret) {
706d30bb512STodor Tomov 		dev_err(ov7251->dev, "set core voltage failed\n");
707d30bb512STodor Tomov 		goto err_disable_analog;
708d30bb512STodor Tomov 	}
709d30bb512STodor Tomov 
710d30bb512STodor Tomov 	return 0;
711d30bb512STodor Tomov 
712d30bb512STodor Tomov err_disable_analog:
713d30bb512STodor Tomov 	regulator_disable(ov7251->analog_regulator);
714d30bb512STodor Tomov 
715d30bb512STodor Tomov err_disable_io:
716d30bb512STodor Tomov 	regulator_disable(ov7251->io_regulator);
717d30bb512STodor Tomov 
718d30bb512STodor Tomov 	return ret;
719d30bb512STodor Tomov }
720d30bb512STodor Tomov 
ov7251_regulators_disable(struct ov7251 * ov7251)721d30bb512STodor Tomov static void ov7251_regulators_disable(struct ov7251 *ov7251)
722d30bb512STodor Tomov {
723d30bb512STodor Tomov 	int ret;
724d30bb512STodor Tomov 
725d30bb512STodor Tomov 	ret = regulator_disable(ov7251->core_regulator);
726d30bb512STodor Tomov 	if (ret < 0)
727d30bb512STodor Tomov 		dev_err(ov7251->dev, "core regulator disable failed\n");
728d30bb512STodor Tomov 
729d30bb512STodor Tomov 	ret = regulator_disable(ov7251->analog_regulator);
730d30bb512STodor Tomov 	if (ret < 0)
731d30bb512STodor Tomov 		dev_err(ov7251->dev, "analog regulator disable failed\n");
732d30bb512STodor Tomov 
733d30bb512STodor Tomov 	ret = regulator_disable(ov7251->io_regulator);
734d30bb512STodor Tomov 	if (ret < 0)
735d30bb512STodor Tomov 		dev_err(ov7251->dev, "io regulator disable failed\n");
736d30bb512STodor Tomov }
737d30bb512STodor Tomov 
ov7251_write_reg(struct ov7251 * ov7251,u16 reg,u8 val)738d30bb512STodor Tomov static int ov7251_write_reg(struct ov7251 *ov7251, u16 reg, u8 val)
739d30bb512STodor Tomov {
740d30bb512STodor Tomov 	u8 regbuf[3];
741d30bb512STodor Tomov 	int ret;
742d30bb512STodor Tomov 
743d30bb512STodor Tomov 	regbuf[0] = reg >> 8;
744d30bb512STodor Tomov 	regbuf[1] = reg & 0xff;
745d30bb512STodor Tomov 	regbuf[2] = val;
746d30bb512STodor Tomov 
747d30bb512STodor Tomov 	ret = i2c_master_send(ov7251->i2c_client, regbuf, 3);
748d30bb512STodor Tomov 	if (ret < 0) {
749d30bb512STodor Tomov 		dev_err(ov7251->dev, "%s: write reg error %d: reg=%x, val=%x\n",
750d30bb512STodor Tomov 			__func__, ret, reg, val);
751d30bb512STodor Tomov 		return ret;
752d30bb512STodor Tomov 	}
753d30bb512STodor Tomov 
754d30bb512STodor Tomov 	return 0;
755d30bb512STodor Tomov }
756d30bb512STodor Tomov 
ov7251_write_seq_regs(struct ov7251 * ov7251,u16 reg,u8 * val,u8 num)757d30bb512STodor Tomov static int ov7251_write_seq_regs(struct ov7251 *ov7251, u16 reg, u8 *val,
758d30bb512STodor Tomov 				 u8 num)
759d30bb512STodor Tomov {
760d30bb512STodor Tomov 	u8 regbuf[5];
761d30bb512STodor Tomov 	u8 nregbuf = sizeof(reg) + num * sizeof(*val);
762d30bb512STodor Tomov 	int ret = 0;
763d30bb512STodor Tomov 
764d30bb512STodor Tomov 	if (nregbuf > sizeof(regbuf))
765d30bb512STodor Tomov 		return -EINVAL;
766d30bb512STodor Tomov 
767d30bb512STodor Tomov 	regbuf[0] = reg >> 8;
768d30bb512STodor Tomov 	regbuf[1] = reg & 0xff;
769d30bb512STodor Tomov 
770d30bb512STodor Tomov 	memcpy(regbuf + 2, val, num);
771d30bb512STodor Tomov 
772d30bb512STodor Tomov 	ret = i2c_master_send(ov7251->i2c_client, regbuf, nregbuf);
773d30bb512STodor Tomov 	if (ret < 0) {
774d30bb512STodor Tomov 		dev_err(ov7251->dev,
775d30bb512STodor Tomov 			"%s: write seq regs error %d: first reg=%x\n",
776d30bb512STodor Tomov 			__func__, ret, reg);
777d30bb512STodor Tomov 		return ret;
778d30bb512STodor Tomov 	}
779d30bb512STodor Tomov 
780d30bb512STodor Tomov 	return 0;
781d30bb512STodor Tomov }
782d30bb512STodor Tomov 
ov7251_read_reg(struct ov7251 * ov7251,u16 reg,u8 * val)783d30bb512STodor Tomov static int ov7251_read_reg(struct ov7251 *ov7251, u16 reg, u8 *val)
784d30bb512STodor Tomov {
785d30bb512STodor Tomov 	u8 regbuf[2];
786d30bb512STodor Tomov 	int ret;
787d30bb512STodor Tomov 
788d30bb512STodor Tomov 	regbuf[0] = reg >> 8;
789d30bb512STodor Tomov 	regbuf[1] = reg & 0xff;
790d30bb512STodor Tomov 
791d30bb512STodor Tomov 	ret = i2c_master_send(ov7251->i2c_client, regbuf, 2);
792d30bb512STodor Tomov 	if (ret < 0) {
793d30bb512STodor Tomov 		dev_err(ov7251->dev, "%s: write reg error %d: reg=%x\n",
794d30bb512STodor Tomov 			__func__, ret, reg);
795d30bb512STodor Tomov 		return ret;
796d30bb512STodor Tomov 	}
797d30bb512STodor Tomov 
798d30bb512STodor Tomov 	ret = i2c_master_recv(ov7251->i2c_client, val, 1);
799d30bb512STodor Tomov 	if (ret < 0) {
800d30bb512STodor Tomov 		dev_err(ov7251->dev, "%s: read reg error %d: reg=%x\n",
801d30bb512STodor Tomov 			__func__, ret, reg);
802d30bb512STodor Tomov 		return ret;
803d30bb512STodor Tomov 	}
804d30bb512STodor Tomov 
805d30bb512STodor Tomov 	return 0;
806d30bb512STodor Tomov }
807d30bb512STodor Tomov 
ov7251_pll_configure(struct ov7251 * ov7251)808df057b0dSDaniel Scally static int ov7251_pll_configure(struct ov7251 *ov7251)
809df057b0dSDaniel Scally {
810df057b0dSDaniel Scally 	const struct ov7251_pll_cfgs *configs;
811df057b0dSDaniel Scally 	int ret;
812df057b0dSDaniel Scally 
813df057b0dSDaniel Scally 	configs = ov7251->pll_cfgs;
814df057b0dSDaniel Scally 
815df057b0dSDaniel Scally 	ret = ov7251_write_reg(ov7251, OV7251_PLL1_PRE_DIV_REG,
816df057b0dSDaniel Scally 			       configs->pll1[ov7251->link_freq_idx]->pre_div);
817df057b0dSDaniel Scally 	if (ret < 0)
818df057b0dSDaniel Scally 		return ret;
819df057b0dSDaniel Scally 
820df057b0dSDaniel Scally 	ret = ov7251_write_reg(ov7251, OV7251_PLL1_MULT_REG,
821df057b0dSDaniel Scally 			       configs->pll1[ov7251->link_freq_idx]->mult);
822df057b0dSDaniel Scally 	if (ret < 0)
823df057b0dSDaniel Scally 		return ret;
824df057b0dSDaniel Scally 	ret = ov7251_write_reg(ov7251, OV7251_PLL1_DIVIDER_REG,
825df057b0dSDaniel Scally 			       configs->pll1[ov7251->link_freq_idx]->div);
826df057b0dSDaniel Scally 	if (ret < 0)
827df057b0dSDaniel Scally 		return ret;
828df057b0dSDaniel Scally 
829df057b0dSDaniel Scally 	ret = ov7251_write_reg(ov7251, OV7251_PLL1_PIX_DIV_REG,
830df057b0dSDaniel Scally 			       configs->pll1[ov7251->link_freq_idx]->pix_div);
831df057b0dSDaniel Scally 	if (ret < 0)
832df057b0dSDaniel Scally 		return ret;
833df057b0dSDaniel Scally 
834df057b0dSDaniel Scally 	ret = ov7251_write_reg(ov7251, OV7251_PLL1_MIPI_DIV_REG,
835df057b0dSDaniel Scally 			       configs->pll1[ov7251->link_freq_idx]->mipi_div);
836df057b0dSDaniel Scally 	if (ret < 0)
837df057b0dSDaniel Scally 		return ret;
838df057b0dSDaniel Scally 
839df057b0dSDaniel Scally 	ret = ov7251_write_reg(ov7251, OV7251_PLL2_PRE_DIV_REG,
840df057b0dSDaniel Scally 			       configs->pll2->pre_div);
841df057b0dSDaniel Scally 	if (ret < 0)
842df057b0dSDaniel Scally 		return ret;
843df057b0dSDaniel Scally 
844df057b0dSDaniel Scally 	ret = ov7251_write_reg(ov7251, OV7251_PLL2_MULT_REG,
845df057b0dSDaniel Scally 			       configs->pll2->mult);
846df057b0dSDaniel Scally 	if (ret < 0)
847df057b0dSDaniel Scally 		return ret;
848df057b0dSDaniel Scally 
849df057b0dSDaniel Scally 	ret = ov7251_write_reg(ov7251, OV7251_PLL2_DIVIDER_REG,
850df057b0dSDaniel Scally 			       configs->pll2->div);
851df057b0dSDaniel Scally 	if (ret < 0)
852df057b0dSDaniel Scally 		return ret;
853df057b0dSDaniel Scally 
854df057b0dSDaniel Scally 	ret = ov7251_write_reg(ov7251, OV7251_PLL2_SYS_DIV_REG,
855df057b0dSDaniel Scally 			       configs->pll2->sys_div);
856df057b0dSDaniel Scally 	if (ret < 0)
857df057b0dSDaniel Scally 		return ret;
858df057b0dSDaniel Scally 
859df057b0dSDaniel Scally 	ret = ov7251_write_reg(ov7251, OV7251_PLL2_ADC_DIV_REG,
860df057b0dSDaniel Scally 			       configs->pll2->adc_div);
861df057b0dSDaniel Scally 
862df057b0dSDaniel Scally 	return ret;
863df057b0dSDaniel Scally }
864df057b0dSDaniel Scally 
ov7251_set_exposure(struct ov7251 * ov7251,s32 exposure)865d30bb512STodor Tomov static int ov7251_set_exposure(struct ov7251 *ov7251, s32 exposure)
866d30bb512STodor Tomov {
867d30bb512STodor Tomov 	u16 reg;
868d30bb512STodor Tomov 	u8 val[3];
869d30bb512STodor Tomov 
870d30bb512STodor Tomov 	reg = OV7251_AEC_EXPO_0;
871d30bb512STodor Tomov 	val[0] = (exposure & 0xf000) >> 12; /* goes to OV7251_AEC_EXPO_0 */
872d30bb512STodor Tomov 	val[1] = (exposure & 0x0ff0) >> 4;  /* goes to OV7251_AEC_EXPO_1 */
873d30bb512STodor Tomov 	val[2] = (exposure & 0x000f) << 4;  /* goes to OV7251_AEC_EXPO_2 */
874d30bb512STodor Tomov 
875d30bb512STodor Tomov 	return ov7251_write_seq_regs(ov7251, reg, val, 3);
876d30bb512STodor Tomov }
877d30bb512STodor Tomov 
ov7251_set_gain(struct ov7251 * ov7251,s32 gain)878d30bb512STodor Tomov static int ov7251_set_gain(struct ov7251 *ov7251, s32 gain)
879d30bb512STodor Tomov {
880d30bb512STodor Tomov 	u16 reg;
881d30bb512STodor Tomov 	u8 val[2];
882d30bb512STodor Tomov 
883d30bb512STodor Tomov 	reg = OV7251_AEC_AGC_ADJ_0;
884d30bb512STodor Tomov 	val[0] = (gain & 0x0300) >> 8; /* goes to OV7251_AEC_AGC_ADJ_0 */
885d30bb512STodor Tomov 	val[1] = gain & 0xff;          /* goes to OV7251_AEC_AGC_ADJ_1 */
886d30bb512STodor Tomov 
887d30bb512STodor Tomov 	return ov7251_write_seq_regs(ov7251, reg, val, 2);
888d30bb512STodor Tomov }
889d30bb512STodor Tomov 
ov7251_set_register_array(struct ov7251 * ov7251,const struct reg_value * settings,unsigned int num_settings)890d30bb512STodor Tomov static int ov7251_set_register_array(struct ov7251 *ov7251,
891d30bb512STodor Tomov 				     const struct reg_value *settings,
892d30bb512STodor Tomov 				     unsigned int num_settings)
893d30bb512STodor Tomov {
894d30bb512STodor Tomov 	unsigned int i;
895d30bb512STodor Tomov 	int ret;
896d30bb512STodor Tomov 
897d30bb512STodor Tomov 	for (i = 0; i < num_settings; ++i, ++settings) {
898d30bb512STodor Tomov 		ret = ov7251_write_reg(ov7251, settings->reg, settings->val);
899d30bb512STodor Tomov 		if (ret < 0)
900d30bb512STodor Tomov 			return ret;
901d30bb512STodor Tomov 	}
902d30bb512STodor Tomov 
903d30bb512STodor Tomov 	return 0;
904d30bb512STodor Tomov }
905d30bb512STodor Tomov 
ov7251_set_power_on(struct device * dev)906207f4162SDaniel Scally static int ov7251_set_power_on(struct device *dev)
907d30bb512STodor Tomov {
908207f4162SDaniel Scally 	struct i2c_client *client = container_of(dev, struct i2c_client, dev);
909207f4162SDaniel Scally 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
910207f4162SDaniel Scally 	struct ov7251 *ov7251 = to_ov7251(sd);
911d30bb512STodor Tomov 	int ret;
912d30bb512STodor Tomov 	u32 wait_us;
913d30bb512STodor Tomov 
914d30bb512STodor Tomov 	ret = ov7251_regulators_enable(ov7251);
915d30bb512STodor Tomov 	if (ret < 0)
916d30bb512STodor Tomov 		return ret;
917d30bb512STodor Tomov 
918d30bb512STodor Tomov 	ret = clk_prepare_enable(ov7251->xclk);
919d30bb512STodor Tomov 	if (ret < 0) {
920d30bb512STodor Tomov 		dev_err(ov7251->dev, "clk prepare enable failed\n");
921d30bb512STodor Tomov 		ov7251_regulators_disable(ov7251);
922d30bb512STodor Tomov 		return ret;
923d30bb512STodor Tomov 	}
924d30bb512STodor Tomov 
925d30bb512STodor Tomov 	gpiod_set_value_cansleep(ov7251->enable_gpio, 1);
926d30bb512STodor Tomov 
927d30bb512STodor Tomov 	/* wait at least 65536 external clock cycles */
928d30bb512STodor Tomov 	wait_us = DIV_ROUND_UP(65536 * 1000,
929d30bb512STodor Tomov 			       DIV_ROUND_UP(ov7251->xclk_freq, 1000));
930d30bb512STodor Tomov 	usleep_range(wait_us, wait_us + 1000);
931d30bb512STodor Tomov 
9329e1d3012SDaniel Scally 	ret = ov7251_set_register_array(ov7251,
9339e1d3012SDaniel Scally 					ov7251_global_init_setting,
9349e1d3012SDaniel Scally 					ARRAY_SIZE(ov7251_global_init_setting));
9359e1d3012SDaniel Scally 	if (ret < 0) {
9369e1d3012SDaniel Scally 		dev_err(ov7251->dev, "error during global init\n");
9377a9795b3SYang Yingliang 		gpiod_set_value_cansleep(ov7251->enable_gpio, 0);
9387a9795b3SYang Yingliang 		clk_disable_unprepare(ov7251->xclk);
9399e1d3012SDaniel Scally 		ov7251_regulators_disable(ov7251);
9409e1d3012SDaniel Scally 		return ret;
9419e1d3012SDaniel Scally 	}
9429e1d3012SDaniel Scally 
9439e1d3012SDaniel Scally 	return ret;
944d30bb512STodor Tomov }
945d30bb512STodor Tomov 
ov7251_set_power_off(struct device * dev)946207f4162SDaniel Scally static int ov7251_set_power_off(struct device *dev)
947d30bb512STodor Tomov {
948207f4162SDaniel Scally 	struct i2c_client *client = container_of(dev, struct i2c_client, dev);
949207f4162SDaniel Scally 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
950207f4162SDaniel Scally 	struct ov7251 *ov7251 = to_ov7251(sd);
951207f4162SDaniel Scally 
952d30bb512STodor Tomov 	clk_disable_unprepare(ov7251->xclk);
953d30bb512STodor Tomov 	gpiod_set_value_cansleep(ov7251->enable_gpio, 0);
954d30bb512STodor Tomov 	ov7251_regulators_disable(ov7251);
955207f4162SDaniel Scally 
956207f4162SDaniel Scally 	return 0;
957d30bb512STodor Tomov }
958d30bb512STodor Tomov 
ov7251_set_hflip(struct ov7251 * ov7251,s32 value)959d30bb512STodor Tomov static int ov7251_set_hflip(struct ov7251 *ov7251, s32 value)
960d30bb512STodor Tomov {
961d30bb512STodor Tomov 	u8 val = ov7251->timing_format2;
962d30bb512STodor Tomov 	int ret;
963d30bb512STodor Tomov 
964d30bb512STodor Tomov 	if (value)
965d30bb512STodor Tomov 		val |= OV7251_TIMING_FORMAT2_MIRROR;
966d30bb512STodor Tomov 	else
967d30bb512STodor Tomov 		val &= ~OV7251_TIMING_FORMAT2_MIRROR;
968d30bb512STodor Tomov 
969d30bb512STodor Tomov 	ret = ov7251_write_reg(ov7251, OV7251_TIMING_FORMAT2, val);
970d30bb512STodor Tomov 	if (!ret)
971d30bb512STodor Tomov 		ov7251->timing_format2 = val;
972d30bb512STodor Tomov 
973d30bb512STodor Tomov 	return ret;
974d30bb512STodor Tomov }
975d30bb512STodor Tomov 
ov7251_set_vflip(struct ov7251 * ov7251,s32 value)976d30bb512STodor Tomov static int ov7251_set_vflip(struct ov7251 *ov7251, s32 value)
977d30bb512STodor Tomov {
978d30bb512STodor Tomov 	u8 val = ov7251->timing_format1;
979d30bb512STodor Tomov 	int ret;
980d30bb512STodor Tomov 
981d30bb512STodor Tomov 	if (value)
982d30bb512STodor Tomov 		val |= OV7251_TIMING_FORMAT1_VFLIP;
983d30bb512STodor Tomov 	else
984d30bb512STodor Tomov 		val &= ~OV7251_TIMING_FORMAT1_VFLIP;
985d30bb512STodor Tomov 
986d30bb512STodor Tomov 	ret = ov7251_write_reg(ov7251, OV7251_TIMING_FORMAT1, val);
987d30bb512STodor Tomov 	if (!ret)
988d30bb512STodor Tomov 		ov7251->timing_format1 = val;
989d30bb512STodor Tomov 
990d30bb512STodor Tomov 	return ret;
991d30bb512STodor Tomov }
992d30bb512STodor Tomov 
ov7251_set_test_pattern(struct ov7251 * ov7251,s32 value)993d30bb512STodor Tomov static int ov7251_set_test_pattern(struct ov7251 *ov7251, s32 value)
994d30bb512STodor Tomov {
995d30bb512STodor Tomov 	u8 val = ov7251->pre_isp_00;
996d30bb512STodor Tomov 	int ret;
997d30bb512STodor Tomov 
998d30bb512STodor Tomov 	if (value)
999d30bb512STodor Tomov 		val |= OV7251_PRE_ISP_00_TEST_PATTERN;
1000d30bb512STodor Tomov 	else
1001d30bb512STodor Tomov 		val &= ~OV7251_PRE_ISP_00_TEST_PATTERN;
1002d30bb512STodor Tomov 
1003d30bb512STodor Tomov 	ret = ov7251_write_reg(ov7251, OV7251_PRE_ISP_00, val);
1004d30bb512STodor Tomov 	if (!ret)
1005d30bb512STodor Tomov 		ov7251->pre_isp_00 = val;
1006d30bb512STodor Tomov 
1007d30bb512STodor Tomov 	return ret;
1008d30bb512STodor Tomov }
1009d30bb512STodor Tomov 
1010d30bb512STodor Tomov static const char * const ov7251_test_pattern_menu[] = {
1011d30bb512STodor Tomov 	"Disabled",
1012d30bb512STodor Tomov 	"Vertical Pattern Bars",
1013d30bb512STodor Tomov };
1014d30bb512STodor Tomov 
ov7251_vts_configure(struct ov7251 * ov7251,s32 vblank)10151b598f41SDaniel Scally static int ov7251_vts_configure(struct ov7251 *ov7251, s32 vblank)
10161b598f41SDaniel Scally {
10171b598f41SDaniel Scally 	u8 vts[2];
10181b598f41SDaniel Scally 
10191b598f41SDaniel Scally 	vts[0] = ((ov7251->current_mode->height + vblank) & 0xff00) >> 8;
10201b598f41SDaniel Scally 	vts[1] = ((ov7251->current_mode->height + vblank) & 0x00ff);
10211b598f41SDaniel Scally 
10221b598f41SDaniel Scally 	return ov7251_write_seq_regs(ov7251, OV7251_TIMING_VTS_REG, vts, 2);
10231b598f41SDaniel Scally }
10241b598f41SDaniel Scally 
ov7251_s_ctrl(struct v4l2_ctrl * ctrl)1025d30bb512STodor Tomov static int ov7251_s_ctrl(struct v4l2_ctrl *ctrl)
1026d30bb512STodor Tomov {
1027d30bb512STodor Tomov 	struct ov7251 *ov7251 = container_of(ctrl->handler,
1028d30bb512STodor Tomov 					     struct ov7251, ctrls);
1029d30bb512STodor Tomov 	int ret;
1030d30bb512STodor Tomov 
10311b598f41SDaniel Scally 	/* If VBLANK is altered we need to update exposure to compensate */
10321b598f41SDaniel Scally 	if (ctrl->id == V4L2_CID_VBLANK) {
10331b598f41SDaniel Scally 		int exposure_max;
10341b598f41SDaniel Scally 
10351b598f41SDaniel Scally 		exposure_max = ov7251->current_mode->height + ctrl->val -
10361b598f41SDaniel Scally 			       OV7251_INTEGRATION_MARGIN;
10371b598f41SDaniel Scally 		__v4l2_ctrl_modify_range(ov7251->exposure,
10381b598f41SDaniel Scally 					 ov7251->exposure->minimum,
10391b598f41SDaniel Scally 					 exposure_max,
10401b598f41SDaniel Scally 					 ov7251->exposure->step,
10411b598f41SDaniel Scally 					 min(ov7251->exposure->val,
10421b598f41SDaniel Scally 					     exposure_max));
10431b598f41SDaniel Scally 	}
10441b598f41SDaniel Scally 
1045d30bb512STodor Tomov 	/* v4l2_ctrl_lock() locks our mutex */
1046d30bb512STodor Tomov 
1047207f4162SDaniel Scally 	if (!pm_runtime_get_if_in_use(ov7251->dev))
1048d30bb512STodor Tomov 		return 0;
1049d30bb512STodor Tomov 
1050d30bb512STodor Tomov 	switch (ctrl->id) {
1051d30bb512STodor Tomov 	case V4L2_CID_EXPOSURE:
1052d30bb512STodor Tomov 		ret = ov7251_set_exposure(ov7251, ctrl->val);
1053d30bb512STodor Tomov 		break;
1054d30bb512STodor Tomov 	case V4L2_CID_GAIN:
1055d30bb512STodor Tomov 		ret = ov7251_set_gain(ov7251, ctrl->val);
1056d30bb512STodor Tomov 		break;
1057d30bb512STodor Tomov 	case V4L2_CID_TEST_PATTERN:
1058d30bb512STodor Tomov 		ret = ov7251_set_test_pattern(ov7251, ctrl->val);
1059d30bb512STodor Tomov 		break;
1060d30bb512STodor Tomov 	case V4L2_CID_HFLIP:
1061d30bb512STodor Tomov 		ret = ov7251_set_hflip(ov7251, ctrl->val);
1062d30bb512STodor Tomov 		break;
1063d30bb512STodor Tomov 	case V4L2_CID_VFLIP:
1064d30bb512STodor Tomov 		ret = ov7251_set_vflip(ov7251, ctrl->val);
1065d30bb512STodor Tomov 		break;
10661b598f41SDaniel Scally 	case V4L2_CID_VBLANK:
10671b598f41SDaniel Scally 		ret = ov7251_vts_configure(ov7251, ctrl->val);
10681b598f41SDaniel Scally 		break;
1069d30bb512STodor Tomov 	default:
1070d30bb512STodor Tomov 		ret = -EINVAL;
1071d30bb512STodor Tomov 		break;
1072d30bb512STodor Tomov 	}
1073d30bb512STodor Tomov 
1074207f4162SDaniel Scally 	pm_runtime_put(ov7251->dev);
1075207f4162SDaniel Scally 
1076d30bb512STodor Tomov 	return ret;
1077d30bb512STodor Tomov }
1078d30bb512STodor Tomov 
1079d30bb512STodor Tomov static const struct v4l2_ctrl_ops ov7251_ctrl_ops = {
1080d30bb512STodor Tomov 	.s_ctrl = ov7251_s_ctrl,
1081d30bb512STodor Tomov };
1082d30bb512STodor Tomov 
ov7251_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_mbus_code_enum * code)1083d30bb512STodor Tomov static int ov7251_enum_mbus_code(struct v4l2_subdev *sd,
10840d346d2aSTomi Valkeinen 				 struct v4l2_subdev_state *sd_state,
1085d30bb512STodor Tomov 				 struct v4l2_subdev_mbus_code_enum *code)
1086d30bb512STodor Tomov {
1087d30bb512STodor Tomov 	if (code->index > 0)
1088d30bb512STodor Tomov 		return -EINVAL;
1089d30bb512STodor Tomov 
1090d30bb512STodor Tomov 	code->code = MEDIA_BUS_FMT_Y10_1X10;
1091d30bb512STodor Tomov 
1092d30bb512STodor Tomov 	return 0;
1093d30bb512STodor Tomov }
1094d30bb512STodor Tomov 
ov7251_enum_frame_size(struct v4l2_subdev * subdev,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_size_enum * fse)1095d30bb512STodor Tomov static int ov7251_enum_frame_size(struct v4l2_subdev *subdev,
10960d346d2aSTomi Valkeinen 				  struct v4l2_subdev_state *sd_state,
1097d30bb512STodor Tomov 				  struct v4l2_subdev_frame_size_enum *fse)
1098d30bb512STodor Tomov {
1099d30bb512STodor Tomov 	if (fse->code != MEDIA_BUS_FMT_Y10_1X10)
1100d30bb512STodor Tomov 		return -EINVAL;
1101d30bb512STodor Tomov 
1102d30bb512STodor Tomov 	if (fse->index >= ARRAY_SIZE(ov7251_mode_info_data))
1103d30bb512STodor Tomov 		return -EINVAL;
1104d30bb512STodor Tomov 
1105d30bb512STodor Tomov 	fse->min_width = ov7251_mode_info_data[fse->index].width;
1106d30bb512STodor Tomov 	fse->max_width = ov7251_mode_info_data[fse->index].width;
1107d30bb512STodor Tomov 	fse->min_height = ov7251_mode_info_data[fse->index].height;
1108d30bb512STodor Tomov 	fse->max_height = ov7251_mode_info_data[fse->index].height;
1109d30bb512STodor Tomov 
1110d30bb512STodor Tomov 	return 0;
1111d30bb512STodor Tomov }
1112d30bb512STodor Tomov 
ov7251_enum_frame_ival(struct v4l2_subdev * subdev,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_interval_enum * fie)1113d30bb512STodor Tomov static int ov7251_enum_frame_ival(struct v4l2_subdev *subdev,
11140d346d2aSTomi Valkeinen 				  struct v4l2_subdev_state *sd_state,
1115d30bb512STodor Tomov 				  struct v4l2_subdev_frame_interval_enum *fie)
1116d30bb512STodor Tomov {
1117d30bb512STodor Tomov 	unsigned int index = fie->index;
1118d30bb512STodor Tomov 	unsigned int i;
1119d30bb512STodor Tomov 
1120d30bb512STodor Tomov 	for (i = 0; i < ARRAY_SIZE(ov7251_mode_info_data); i++) {
1121d30bb512STodor Tomov 		if (fie->width != ov7251_mode_info_data[i].width ||
1122d30bb512STodor Tomov 		    fie->height != ov7251_mode_info_data[i].height)
1123d30bb512STodor Tomov 			continue;
1124d30bb512STodor Tomov 
1125d30bb512STodor Tomov 		if (index-- == 0) {
1126d30bb512STodor Tomov 			fie->interval = ov7251_mode_info_data[i].timeperframe;
1127d30bb512STodor Tomov 			return 0;
1128d30bb512STodor Tomov 		}
1129d30bb512STodor Tomov 	}
1130d30bb512STodor Tomov 
1131d30bb512STodor Tomov 	return -EINVAL;
1132d30bb512STodor Tomov }
1133d30bb512STodor Tomov 
1134d30bb512STodor Tomov static struct v4l2_mbus_framefmt *
__ov7251_get_pad_format(struct ov7251 * ov7251,struct v4l2_subdev_state * sd_state,unsigned int pad,enum v4l2_subdev_format_whence which)1135d30bb512STodor Tomov __ov7251_get_pad_format(struct ov7251 *ov7251,
11360d346d2aSTomi Valkeinen 			struct v4l2_subdev_state *sd_state,
1137d30bb512STodor Tomov 			unsigned int pad,
1138d30bb512STodor Tomov 			enum v4l2_subdev_format_whence which)
1139d30bb512STodor Tomov {
1140d30bb512STodor Tomov 	switch (which) {
1141d30bb512STodor Tomov 	case V4L2_SUBDEV_FORMAT_TRY:
1142bc0e8d91SSakari Ailus 		return v4l2_subdev_state_get_format(sd_state, pad);
1143d30bb512STodor Tomov 	case V4L2_SUBDEV_FORMAT_ACTIVE:
1144d30bb512STodor Tomov 		return &ov7251->fmt;
1145d30bb512STodor Tomov 	default:
1146d30bb512STodor Tomov 		return NULL;
1147d30bb512STodor Tomov 	}
1148d30bb512STodor Tomov }
1149d30bb512STodor Tomov 
ov7251_get_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * format)1150d30bb512STodor Tomov static int ov7251_get_format(struct v4l2_subdev *sd,
11510d346d2aSTomi Valkeinen 			     struct v4l2_subdev_state *sd_state,
1152d30bb512STodor Tomov 			     struct v4l2_subdev_format *format)
1153d30bb512STodor Tomov {
1154d30bb512STodor Tomov 	struct ov7251 *ov7251 = to_ov7251(sd);
1155d30bb512STodor Tomov 
1156d30bb512STodor Tomov 	mutex_lock(&ov7251->lock);
11570d346d2aSTomi Valkeinen 	format->format = *__ov7251_get_pad_format(ov7251, sd_state,
11580d346d2aSTomi Valkeinen 						  format->pad,
1159d30bb512STodor Tomov 						  format->which);
1160d30bb512STodor Tomov 	mutex_unlock(&ov7251->lock);
1161d30bb512STodor Tomov 
1162d30bb512STodor Tomov 	return 0;
1163d30bb512STodor Tomov }
1164d30bb512STodor Tomov 
1165d30bb512STodor Tomov static struct v4l2_rect *
__ov7251_get_pad_crop(struct ov7251 * ov7251,struct v4l2_subdev_state * sd_state,unsigned int pad,enum v4l2_subdev_format_whence which)11660d346d2aSTomi Valkeinen __ov7251_get_pad_crop(struct ov7251 *ov7251,
11670d346d2aSTomi Valkeinen 		      struct v4l2_subdev_state *sd_state,
1168d30bb512STodor Tomov 		      unsigned int pad, enum v4l2_subdev_format_whence which)
1169d30bb512STodor Tomov {
1170d30bb512STodor Tomov 	switch (which) {
1171d30bb512STodor Tomov 	case V4L2_SUBDEV_FORMAT_TRY:
1172bc0e8d91SSakari Ailus 		return v4l2_subdev_state_get_crop(sd_state, pad);
1173d30bb512STodor Tomov 	case V4L2_SUBDEV_FORMAT_ACTIVE:
1174d30bb512STodor Tomov 		return &ov7251->crop;
1175d30bb512STodor Tomov 	default:
1176d30bb512STodor Tomov 		return NULL;
1177d30bb512STodor Tomov 	}
1178d30bb512STodor Tomov }
1179d30bb512STodor Tomov 
avg_fps(const struct v4l2_fract * t)1180d30bb512STodor Tomov static inline u32 avg_fps(const struct v4l2_fract *t)
1181d30bb512STodor Tomov {
1182d30bb512STodor Tomov 	return (t->denominator + (t->numerator >> 1)) / t->numerator;
1183d30bb512STodor Tomov }
1184d30bb512STodor Tomov 
1185d30bb512STodor Tomov static const struct ov7251_mode_info *
ov7251_find_mode_by_ival(struct ov7251 * ov7251,struct v4l2_fract * timeperframe)1186d30bb512STodor Tomov ov7251_find_mode_by_ival(struct ov7251 *ov7251, struct v4l2_fract *timeperframe)
1187d30bb512STodor Tomov {
1188d30bb512STodor Tomov 	const struct ov7251_mode_info *mode = ov7251->current_mode;
1189d30bb512STodor Tomov 	unsigned int fps_req = avg_fps(timeperframe);
1190d30bb512STodor Tomov 	unsigned int max_dist_match = (unsigned int) -1;
1191d30bb512STodor Tomov 	unsigned int i, n = 0;
1192d30bb512STodor Tomov 
1193d30bb512STodor Tomov 	for (i = 0; i < ARRAY_SIZE(ov7251_mode_info_data); i++) {
1194d30bb512STodor Tomov 		unsigned int dist;
1195d30bb512STodor Tomov 		unsigned int fps_tmp;
1196d30bb512STodor Tomov 
1197d30bb512STodor Tomov 		if (mode->width != ov7251_mode_info_data[i].width ||
1198d30bb512STodor Tomov 		    mode->height != ov7251_mode_info_data[i].height)
1199d30bb512STodor Tomov 			continue;
1200d30bb512STodor Tomov 
1201d30bb512STodor Tomov 		fps_tmp = avg_fps(&ov7251_mode_info_data[i].timeperframe);
1202d30bb512STodor Tomov 
1203d30bb512STodor Tomov 		dist = abs(fps_req - fps_tmp);
1204d30bb512STodor Tomov 
1205d30bb512STodor Tomov 		if (dist < max_dist_match) {
1206d30bb512STodor Tomov 			n = i;
1207d30bb512STodor Tomov 			max_dist_match = dist;
1208d30bb512STodor Tomov 		}
1209d30bb512STodor Tomov 	}
1210d30bb512STodor Tomov 
1211d30bb512STodor Tomov 	return &ov7251_mode_info_data[n];
1212d30bb512STodor Tomov }
1213d30bb512STodor Tomov 
ov7251_set_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * format)1214d30bb512STodor Tomov static int ov7251_set_format(struct v4l2_subdev *sd,
12150d346d2aSTomi Valkeinen 			     struct v4l2_subdev_state *sd_state,
1216d30bb512STodor Tomov 			     struct v4l2_subdev_format *format)
1217d30bb512STodor Tomov {
1218d30bb512STodor Tomov 	struct ov7251 *ov7251 = to_ov7251(sd);
1219d30bb512STodor Tomov 	struct v4l2_mbus_framefmt *__format;
12201b598f41SDaniel Scally 	int vblank_max, vblank_def;
1221d30bb512STodor Tomov 	struct v4l2_rect *__crop;
1222d30bb512STodor Tomov 	const struct ov7251_mode_info *new_mode;
1223d30bb512STodor Tomov 	int ret = 0;
1224d30bb512STodor Tomov 
1225d30bb512STodor Tomov 	mutex_lock(&ov7251->lock);
1226d30bb512STodor Tomov 
12270d346d2aSTomi Valkeinen 	__crop = __ov7251_get_pad_crop(ov7251, sd_state, format->pad,
12280d346d2aSTomi Valkeinen 				       format->which);
1229d30bb512STodor Tomov 
1230d30bb512STodor Tomov 	new_mode = v4l2_find_nearest_size(ov7251_mode_info_data,
1231d30bb512STodor Tomov 				ARRAY_SIZE(ov7251_mode_info_data),
1232d30bb512STodor Tomov 				width, height,
1233d30bb512STodor Tomov 				format->format.width, format->format.height);
1234d30bb512STodor Tomov 
1235d30bb512STodor Tomov 	__crop->width = new_mode->width;
1236d30bb512STodor Tomov 	__crop->height = new_mode->height;
1237d30bb512STodor Tomov 
1238d30bb512STodor Tomov 	if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
1239d30bb512STodor Tomov 		ret = __v4l2_ctrl_modify_range(ov7251->exposure,
1240d30bb512STodor Tomov 					       1, new_mode->exposure_max,
1241d30bb512STodor Tomov 					       1, new_mode->exposure_def);
1242d30bb512STodor Tomov 		if (ret < 0)
1243d30bb512STodor Tomov 			goto exit;
1244d30bb512STodor Tomov 
1245d30bb512STodor Tomov 		ret = __v4l2_ctrl_s_ctrl(ov7251->exposure,
1246d30bb512STodor Tomov 					 new_mode->exposure_def);
1247d30bb512STodor Tomov 		if (ret < 0)
1248d30bb512STodor Tomov 			goto exit;
1249d30bb512STodor Tomov 
1250d30bb512STodor Tomov 		ret = __v4l2_ctrl_s_ctrl(ov7251->gain, 16);
1251d30bb512STodor Tomov 		if (ret < 0)
1252d30bb512STodor Tomov 			goto exit;
1253d30bb512STodor Tomov 
12541b598f41SDaniel Scally 		vblank_max = OV7251_TIMING_MAX_VTS - new_mode->height;
12551b598f41SDaniel Scally 		vblank_def = new_mode->vts - new_mode->height;
12561b598f41SDaniel Scally 		ret = __v4l2_ctrl_modify_range(ov7251->vblank,
12571b598f41SDaniel Scally 					       OV7251_TIMING_MIN_VTS,
12581b598f41SDaniel Scally 					       vblank_max, 1, vblank_def);
12591b598f41SDaniel Scally 		if (ret < 0)
12601b598f41SDaniel Scally 			goto exit;
12611b598f41SDaniel Scally 
1262d30bb512STodor Tomov 		ov7251->current_mode = new_mode;
1263d30bb512STodor Tomov 	}
1264d30bb512STodor Tomov 
12650d346d2aSTomi Valkeinen 	__format = __ov7251_get_pad_format(ov7251, sd_state, format->pad,
1266d30bb512STodor Tomov 					   format->which);
1267d30bb512STodor Tomov 	__format->width = __crop->width;
1268d30bb512STodor Tomov 	__format->height = __crop->height;
1269d30bb512STodor Tomov 	__format->code = MEDIA_BUS_FMT_Y10_1X10;
1270d30bb512STodor Tomov 	__format->field = V4L2_FIELD_NONE;
1271d30bb512STodor Tomov 	__format->colorspace = V4L2_COLORSPACE_SRGB;
1272d30bb512STodor Tomov 	__format->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(__format->colorspace);
1273d30bb512STodor Tomov 	__format->quantization = V4L2_MAP_QUANTIZATION_DEFAULT(true,
1274d30bb512STodor Tomov 				__format->colorspace, __format->ycbcr_enc);
1275d30bb512STodor Tomov 	__format->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(__format->colorspace);
1276d30bb512STodor Tomov 
1277d30bb512STodor Tomov 	format->format = *__format;
1278d30bb512STodor Tomov 
1279d30bb512STodor Tomov exit:
1280d30bb512STodor Tomov 	mutex_unlock(&ov7251->lock);
1281d30bb512STodor Tomov 
1282d30bb512STodor Tomov 	return ret;
1283d30bb512STodor Tomov }
1284d30bb512STodor Tomov 
ov7251_init_state(struct v4l2_subdev * subdev,struct v4l2_subdev_state * sd_state)12855755be5fSLaurent Pinchart static int ov7251_init_state(struct v4l2_subdev *subdev,
12860d346d2aSTomi Valkeinen 			     struct v4l2_subdev_state *sd_state)
1287d30bb512STodor Tomov {
1288d30bb512STodor Tomov 	struct v4l2_subdev_format fmt = {
12890d346d2aSTomi Valkeinen 		.which = sd_state ? V4L2_SUBDEV_FORMAT_TRY
1290d30bb512STodor Tomov 		: V4L2_SUBDEV_FORMAT_ACTIVE,
1291d30bb512STodor Tomov 		.format = {
1292d30bb512STodor Tomov 			.width = 640,
1293d30bb512STodor Tomov 			.height = 480
1294d30bb512STodor Tomov 		}
1295d30bb512STodor Tomov 	};
1296d30bb512STodor Tomov 
12970d346d2aSTomi Valkeinen 	ov7251_set_format(subdev, sd_state, &fmt);
1298d30bb512STodor Tomov 
1299d30bb512STodor Tomov 	return 0;
1300d30bb512STodor Tomov }
1301d30bb512STodor Tomov 
ov7251_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_selection * sel)1302d30bb512STodor Tomov static int ov7251_get_selection(struct v4l2_subdev *sd,
13030d346d2aSTomi Valkeinen 				struct v4l2_subdev_state *sd_state,
1304d30bb512STodor Tomov 				struct v4l2_subdev_selection *sel)
1305d30bb512STodor Tomov {
1306d30bb512STodor Tomov 	struct ov7251 *ov7251 = to_ov7251(sd);
1307d30bb512STodor Tomov 
130877ec83cdSDaniel Scally 	switch (sel->target) {
130977ec83cdSDaniel Scally 	case V4L2_SEL_TGT_CROP_DEFAULT:
131077ec83cdSDaniel Scally 	case V4L2_SEL_TGT_CROP:
1311d30bb512STodor Tomov 	mutex_lock(&ov7251->lock);
13120d346d2aSTomi Valkeinen 		sel->r = *__ov7251_get_pad_crop(ov7251, sd_state, sel->pad,
1313d30bb512STodor Tomov 						sel->which);
1314d30bb512STodor Tomov 		mutex_unlock(&ov7251->lock);
131577ec83cdSDaniel Scally 		break;
131677ec83cdSDaniel Scally 	case V4L2_SEL_TGT_NATIVE_SIZE:
131777ec83cdSDaniel Scally 		sel->r.top = 0;
131877ec83cdSDaniel Scally 		sel->r.left = 0;
131977ec83cdSDaniel Scally 		sel->r.width = OV7251_NATIVE_WIDTH;
132077ec83cdSDaniel Scally 		sel->r.height = OV7251_NATIVE_HEIGHT;
132177ec83cdSDaniel Scally 		break;
132277ec83cdSDaniel Scally 	case V4L2_SEL_TGT_CROP_BOUNDS:
132377ec83cdSDaniel Scally 		sel->r.top = OV7251_ACTIVE_START_TOP;
132477ec83cdSDaniel Scally 		sel->r.left = OV7251_ACTIVE_START_LEFT;
132577ec83cdSDaniel Scally 		sel->r.width = OV7251_ACTIVE_WIDTH;
132677ec83cdSDaniel Scally 		sel->r.height = OV7251_ACTIVE_HEIGHT;
132777ec83cdSDaniel Scally 		break;
132877ec83cdSDaniel Scally 	default:
132977ec83cdSDaniel Scally 		return -EINVAL;
133077ec83cdSDaniel Scally 	}
1331d30bb512STodor Tomov 
1332d30bb512STodor Tomov 	return 0;
1333d30bb512STodor Tomov }
1334d30bb512STodor Tomov 
ov7251_s_stream(struct v4l2_subdev * subdev,int enable)1335d30bb512STodor Tomov static int ov7251_s_stream(struct v4l2_subdev *subdev, int enable)
1336d30bb512STodor Tomov {
1337d30bb512STodor Tomov 	struct ov7251 *ov7251 = to_ov7251(subdev);
1338d30bb512STodor Tomov 	int ret;
1339d30bb512STodor Tomov 
1340d30bb512STodor Tomov 	mutex_lock(&ov7251->lock);
1341d30bb512STodor Tomov 
1342d30bb512STodor Tomov 	if (enable) {
1343b92f8f35SLaurent Pinchart 		ret = pm_runtime_resume_and_get(ov7251->dev);
1344b92f8f35SLaurent Pinchart 		if (ret) {
1345b92f8f35SLaurent Pinchart 			mutex_unlock(&ov7251->lock);
1346b92f8f35SLaurent Pinchart 			return ret;
1347b92f8f35SLaurent Pinchart 		}
1348207f4162SDaniel Scally 
1349df057b0dSDaniel Scally 		ret = ov7251_pll_configure(ov7251);
1350207f4162SDaniel Scally 		if (ret) {
1351207f4162SDaniel Scally 			dev_err(ov7251->dev, "error configuring PLLs\n");
1352207f4162SDaniel Scally 			goto err_power_down;
1353207f4162SDaniel Scally 		}
1354df057b0dSDaniel Scally 
1355d30bb512STodor Tomov 		ret = ov7251_set_register_array(ov7251,
1356d30bb512STodor Tomov 					ov7251->current_mode->data,
1357d30bb512STodor Tomov 					ov7251->current_mode->data_size);
1358d30bb512STodor Tomov 		if (ret < 0) {
1359d30bb512STodor Tomov 			dev_err(ov7251->dev, "could not set mode %dx%d\n",
1360d30bb512STodor Tomov 				ov7251->current_mode->width,
1361d30bb512STodor Tomov 				ov7251->current_mode->height);
1362207f4162SDaniel Scally 			goto err_power_down;
1363d30bb512STodor Tomov 		}
1364d30bb512STodor Tomov 		ret = __v4l2_ctrl_handler_setup(&ov7251->ctrls);
1365d30bb512STodor Tomov 		if (ret < 0) {
1366d30bb512STodor Tomov 			dev_err(ov7251->dev, "could not sync v4l2 controls\n");
1367207f4162SDaniel Scally 			goto err_power_down;
1368d30bb512STodor Tomov 		}
1369d30bb512STodor Tomov 		ret = ov7251_write_reg(ov7251, OV7251_SC_MODE_SELECT,
1370d30bb512STodor Tomov 				       OV7251_SC_MODE_SELECT_STREAMING);
1371207f4162SDaniel Scally 		if (ret)
1372207f4162SDaniel Scally 			goto err_power_down;
1373d30bb512STodor Tomov 	} else {
1374d30bb512STodor Tomov 		ret = ov7251_write_reg(ov7251, OV7251_SC_MODE_SELECT,
1375d30bb512STodor Tomov 				       OV7251_SC_MODE_SELECT_SW_STANDBY);
1376207f4162SDaniel Scally 		pm_runtime_put(ov7251->dev);
1377d30bb512STodor Tomov 	}
1378d30bb512STodor Tomov 
1379d30bb512STodor Tomov 	mutex_unlock(&ov7251->lock);
1380207f4162SDaniel Scally 	return ret;
1381d30bb512STodor Tomov 
1382207f4162SDaniel Scally err_power_down:
1383fda0f59aSSakari Ailus 	pm_runtime_put(ov7251->dev);
13844d52db40SMauro Carvalho Chehab 	mutex_unlock(&ov7251->lock);
1385d30bb512STodor Tomov 	return ret;
1386d30bb512STodor Tomov }
1387d30bb512STodor Tomov 
ov7251_get_frame_interval(struct v4l2_subdev * subdev,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_interval * fi)1388d30bb512STodor Tomov static int ov7251_get_frame_interval(struct v4l2_subdev *subdev,
1389287fe160SLaurent Pinchart 				     struct v4l2_subdev_state *sd_state,
1390d30bb512STodor Tomov 				     struct v4l2_subdev_frame_interval *fi)
1391d30bb512STodor Tomov {
1392d30bb512STodor Tomov 	struct ov7251 *ov7251 = to_ov7251(subdev);
1393d30bb512STodor Tomov 
1394*805d4311SLaurent Pinchart 	/*
1395*805d4311SLaurent Pinchart 	 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2
1396*805d4311SLaurent Pinchart 	 * subdev active state API.
1397*805d4311SLaurent Pinchart 	 */
1398*805d4311SLaurent Pinchart 	if (fi->which != V4L2_SUBDEV_FORMAT_ACTIVE)
1399*805d4311SLaurent Pinchart 		return -EINVAL;
1400*805d4311SLaurent Pinchart 
1401d30bb512STodor Tomov 	mutex_lock(&ov7251->lock);
1402d30bb512STodor Tomov 	fi->interval = ov7251->current_mode->timeperframe;
1403d30bb512STodor Tomov 	mutex_unlock(&ov7251->lock);
1404d30bb512STodor Tomov 
1405d30bb512STodor Tomov 	return 0;
1406d30bb512STodor Tomov }
1407d30bb512STodor Tomov 
ov7251_set_frame_interval(struct v4l2_subdev * subdev,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_interval * fi)1408d30bb512STodor Tomov static int ov7251_set_frame_interval(struct v4l2_subdev *subdev,
1409287fe160SLaurent Pinchart 				     struct v4l2_subdev_state *sd_state,
1410d30bb512STodor Tomov 				     struct v4l2_subdev_frame_interval *fi)
1411d30bb512STodor Tomov {
1412d30bb512STodor Tomov 	struct ov7251 *ov7251 = to_ov7251(subdev);
1413d30bb512STodor Tomov 	const struct ov7251_mode_info *new_mode;
1414d30bb512STodor Tomov 	int ret = 0;
1415d30bb512STodor Tomov 
1416*805d4311SLaurent Pinchart 	/*
1417*805d4311SLaurent Pinchart 	 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2
1418*805d4311SLaurent Pinchart 	 * subdev active state API.
1419*805d4311SLaurent Pinchart 	 */
1420*805d4311SLaurent Pinchart 	if (fi->which != V4L2_SUBDEV_FORMAT_ACTIVE)
1421*805d4311SLaurent Pinchart 		return -EINVAL;
1422*805d4311SLaurent Pinchart 
1423d30bb512STodor Tomov 	mutex_lock(&ov7251->lock);
1424d30bb512STodor Tomov 	new_mode = ov7251_find_mode_by_ival(ov7251, &fi->interval);
1425d30bb512STodor Tomov 
1426d30bb512STodor Tomov 	if (new_mode != ov7251->current_mode) {
1427d30bb512STodor Tomov 		ret = __v4l2_ctrl_modify_range(ov7251->exposure,
1428d30bb512STodor Tomov 					       1, new_mode->exposure_max,
1429d30bb512STodor Tomov 					       1, new_mode->exposure_def);
1430d30bb512STodor Tomov 		if (ret < 0)
1431d30bb512STodor Tomov 			goto exit;
1432d30bb512STodor Tomov 
1433d30bb512STodor Tomov 		ret = __v4l2_ctrl_s_ctrl(ov7251->exposure,
1434d30bb512STodor Tomov 					 new_mode->exposure_def);
1435d30bb512STodor Tomov 		if (ret < 0)
1436d30bb512STodor Tomov 			goto exit;
1437d30bb512STodor Tomov 
1438d30bb512STodor Tomov 		ret = __v4l2_ctrl_s_ctrl(ov7251->gain, 16);
1439d30bb512STodor Tomov 		if (ret < 0)
1440d30bb512STodor Tomov 			goto exit;
1441d30bb512STodor Tomov 
1442d30bb512STodor Tomov 		ov7251->current_mode = new_mode;
1443d30bb512STodor Tomov 	}
1444d30bb512STodor Tomov 
1445d30bb512STodor Tomov 	fi->interval = ov7251->current_mode->timeperframe;
1446d30bb512STodor Tomov 
1447d30bb512STodor Tomov exit:
1448d30bb512STodor Tomov 	mutex_unlock(&ov7251->lock);
1449d30bb512STodor Tomov 
1450d30bb512STodor Tomov 	return ret;
1451d30bb512STodor Tomov }
1452d30bb512STodor Tomov 
1453d30bb512STodor Tomov static const struct v4l2_subdev_video_ops ov7251_video_ops = {
1454d30bb512STodor Tomov 	.s_stream = ov7251_s_stream,
1455d30bb512STodor Tomov };
1456d30bb512STodor Tomov 
1457d30bb512STodor Tomov static const struct v4l2_subdev_pad_ops ov7251_subdev_pad_ops = {
1458d30bb512STodor Tomov 	.enum_mbus_code = ov7251_enum_mbus_code,
1459d30bb512STodor Tomov 	.enum_frame_size = ov7251_enum_frame_size,
1460d30bb512STodor Tomov 	.enum_frame_interval = ov7251_enum_frame_ival,
1461d30bb512STodor Tomov 	.get_fmt = ov7251_get_format,
1462d30bb512STodor Tomov 	.set_fmt = ov7251_set_format,
1463d30bb512STodor Tomov 	.get_selection = ov7251_get_selection,
1464287fe160SLaurent Pinchart 	.get_frame_interval = ov7251_get_frame_interval,
1465287fe160SLaurent Pinchart 	.set_frame_interval = ov7251_set_frame_interval,
1466d30bb512STodor Tomov };
1467d30bb512STodor Tomov 
1468d30bb512STodor Tomov static const struct v4l2_subdev_ops ov7251_subdev_ops = {
1469d30bb512STodor Tomov 	.video = &ov7251_video_ops,
1470d30bb512STodor Tomov 	.pad = &ov7251_subdev_pad_ops,
1471d30bb512STodor Tomov };
1472d30bb512STodor Tomov 
14735755be5fSLaurent Pinchart static const struct v4l2_subdev_internal_ops ov7251_internal_ops = {
14745755be5fSLaurent Pinchart 	.init_state = ov7251_init_state,
14755755be5fSLaurent Pinchart };
14765755be5fSLaurent Pinchart 
ov7251_check_hwcfg(struct ov7251 * ov7251)1477cc125aaaSDaniel Scally static int ov7251_check_hwcfg(struct ov7251 *ov7251)
1478cc125aaaSDaniel Scally {
1479cc125aaaSDaniel Scally 	struct fwnode_handle *fwnode = dev_fwnode(ov7251->dev);
1480cc125aaaSDaniel Scally 	struct v4l2_fwnode_endpoint bus_cfg = {
1481cc125aaaSDaniel Scally 		.bus_type = V4L2_MBUS_CSI2_DPHY,
1482cc125aaaSDaniel Scally 	};
1483cc125aaaSDaniel Scally 	struct fwnode_handle *endpoint;
1484cc125aaaSDaniel Scally 	unsigned int i, j;
1485cc125aaaSDaniel Scally 	int ret;
1486cc125aaaSDaniel Scally 
1487cc125aaaSDaniel Scally 	endpoint = fwnode_graph_get_next_endpoint(fwnode, NULL);
1488cc125aaaSDaniel Scally 	if (!endpoint)
1489cc125aaaSDaniel Scally 		return -EPROBE_DEFER; /* could be provided by cio2-bridge */
1490cc125aaaSDaniel Scally 
1491cc125aaaSDaniel Scally 	ret = v4l2_fwnode_endpoint_alloc_parse(endpoint, &bus_cfg);
1492cc125aaaSDaniel Scally 	fwnode_handle_put(endpoint);
1493cc125aaaSDaniel Scally 	if (ret)
1494cc125aaaSDaniel Scally 		return dev_err_probe(ov7251->dev, ret,
1495cc125aaaSDaniel Scally 				     "parsing endpoint node failed\n");
1496cc125aaaSDaniel Scally 
1497cc125aaaSDaniel Scally 	if (!bus_cfg.nr_of_link_frequencies) {
1498cc125aaaSDaniel Scally 		ret = dev_err_probe(ov7251->dev, -EINVAL,
1499cc125aaaSDaniel Scally 				    "no link frequencies defined\n");
1500cc125aaaSDaniel Scally 		goto out_free_bus_cfg;
1501cc125aaaSDaniel Scally 	}
1502cc125aaaSDaniel Scally 
1503cc125aaaSDaniel Scally 	for (i = 0; i < bus_cfg.nr_of_link_frequencies; i++) {
1504cc125aaaSDaniel Scally 		for (j = 0; j < ARRAY_SIZE(link_freq); j++)
1505cc125aaaSDaniel Scally 			if (bus_cfg.link_frequencies[i] == link_freq[j])
1506cc125aaaSDaniel Scally 				break;
1507cc125aaaSDaniel Scally 
1508cc125aaaSDaniel Scally 		if (j < ARRAY_SIZE(link_freq))
1509cc125aaaSDaniel Scally 			break;
1510cc125aaaSDaniel Scally 	}
1511cc125aaaSDaniel Scally 
1512cc125aaaSDaniel Scally 	if (i == bus_cfg.nr_of_link_frequencies) {
1513cc125aaaSDaniel Scally 		ret = dev_err_probe(ov7251->dev, -EINVAL,
1514cc125aaaSDaniel Scally 				    "no supported link freq found\n");
1515cc125aaaSDaniel Scally 		goto out_free_bus_cfg;
1516cc125aaaSDaniel Scally 	}
1517cc125aaaSDaniel Scally 
1518cc125aaaSDaniel Scally 	ov7251->link_freq_idx = i;
1519cc125aaaSDaniel Scally 
1520cc125aaaSDaniel Scally out_free_bus_cfg:
1521cc125aaaSDaniel Scally 	v4l2_fwnode_endpoint_free(&bus_cfg);
1522cc125aaaSDaniel Scally 
1523cc125aaaSDaniel Scally 	return ret;
1524cc125aaaSDaniel Scally }
1525cc125aaaSDaniel Scally 
ov7251_detect_chip(struct ov7251 * ov7251)1526e92932c3SDaniel Scally static int ov7251_detect_chip(struct ov7251 *ov7251)
1527e92932c3SDaniel Scally {
1528e92932c3SDaniel Scally 	u8 chip_id_high, chip_id_low, chip_rev;
1529e92932c3SDaniel Scally 	int ret;
1530e92932c3SDaniel Scally 
1531e92932c3SDaniel Scally 	ret = ov7251_read_reg(ov7251, OV7251_CHIP_ID_HIGH, &chip_id_high);
1532e92932c3SDaniel Scally 	if (ret < 0 || chip_id_high != OV7251_CHIP_ID_HIGH_BYTE)
1533e92932c3SDaniel Scally 		return dev_err_probe(ov7251->dev, -ENODEV,
1534e92932c3SDaniel Scally 				     "could not read ID high\n");
1535e92932c3SDaniel Scally 
1536e92932c3SDaniel Scally 	ret = ov7251_read_reg(ov7251, OV7251_CHIP_ID_LOW, &chip_id_low);
1537e92932c3SDaniel Scally 	if (ret < 0 || chip_id_low != OV7251_CHIP_ID_LOW_BYTE)
1538e92932c3SDaniel Scally 		return dev_err_probe(ov7251->dev, -ENODEV,
1539e92932c3SDaniel Scally 				     "could not read ID low\n");
1540e92932c3SDaniel Scally 
1541e92932c3SDaniel Scally 	ret = ov7251_read_reg(ov7251, OV7251_SC_GP_IO_IN1, &chip_rev);
1542e92932c3SDaniel Scally 	if (ret < 0)
1543e92932c3SDaniel Scally 		return dev_err_probe(ov7251->dev, -ENODEV,
1544e92932c3SDaniel Scally 				     "could not read revision\n");
1545e92932c3SDaniel Scally 	chip_rev >>= 4;
1546e92932c3SDaniel Scally 
1547e92932c3SDaniel Scally 	dev_info(ov7251->dev,
1548e92932c3SDaniel Scally 		 "OV7251 revision %x (%s) detected at address 0x%02x\n",
1549e92932c3SDaniel Scally 		 chip_rev,
1550e92932c3SDaniel Scally 		 chip_rev == 0x4 ? "1A / 1B" :
1551e92932c3SDaniel Scally 		 chip_rev == 0x5 ? "1C / 1D" :
1552e92932c3SDaniel Scally 		 chip_rev == 0x6 ? "1E" :
1553e92932c3SDaniel Scally 		 chip_rev == 0x7 ? "1F" : "unknown",
1554e92932c3SDaniel Scally 		 ov7251->i2c_client->addr);
1555e92932c3SDaniel Scally 
1556e92932c3SDaniel Scally 	return 0;
1557e92932c3SDaniel Scally }
1558e92932c3SDaniel Scally 
ov7251_init_ctrls(struct ov7251 * ov7251)15595aaef13dSDaniel Scally static int ov7251_init_ctrls(struct ov7251 *ov7251)
15605aaef13dSDaniel Scally {
15611b598f41SDaniel Scally 	int vblank_max, vblank_def;
15625aaef13dSDaniel Scally 	s64 pixel_rate;
156326066ae6SDaniel Scally 	int hblank;
15645aaef13dSDaniel Scally 
15655aaef13dSDaniel Scally 	v4l2_ctrl_handler_init(&ov7251->ctrls, 7);
15665aaef13dSDaniel Scally 	ov7251->ctrls.lock = &ov7251->lock;
15675aaef13dSDaniel Scally 
15685aaef13dSDaniel Scally 	v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops,
15695aaef13dSDaniel Scally 			  V4L2_CID_HFLIP, 0, 1, 1, 0);
15705aaef13dSDaniel Scally 	v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops,
15715aaef13dSDaniel Scally 			  V4L2_CID_VFLIP, 0, 1, 1, 0);
15725aaef13dSDaniel Scally 	ov7251->exposure = v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops,
15735aaef13dSDaniel Scally 					     V4L2_CID_EXPOSURE, 1, 32, 1, 32);
15745aaef13dSDaniel Scally 	ov7251->gain = v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops,
15755aaef13dSDaniel Scally 					 V4L2_CID_GAIN, 16, 1023, 1, 16);
15765aaef13dSDaniel Scally 	v4l2_ctrl_new_std_menu_items(&ov7251->ctrls, &ov7251_ctrl_ops,
15775aaef13dSDaniel Scally 				     V4L2_CID_TEST_PATTERN,
15785aaef13dSDaniel Scally 				     ARRAY_SIZE(ov7251_test_pattern_menu) - 1,
15795aaef13dSDaniel Scally 				     0, 0, ov7251_test_pattern_menu);
15805aaef13dSDaniel Scally 
15815aaef13dSDaniel Scally 	pixel_rate = pixel_rates[ov7251->link_freq_idx];
15825aaef13dSDaniel Scally 	ov7251->pixel_clock = v4l2_ctrl_new_std(&ov7251->ctrls,
15835aaef13dSDaniel Scally 						&ov7251_ctrl_ops,
15845aaef13dSDaniel Scally 						V4L2_CID_PIXEL_RATE,
15855aaef13dSDaniel Scally 						pixel_rate, INT_MAX,
15865aaef13dSDaniel Scally 						pixel_rate, pixel_rate);
15875aaef13dSDaniel Scally 	ov7251->link_freq = v4l2_ctrl_new_int_menu(&ov7251->ctrls,
15885aaef13dSDaniel Scally 						   &ov7251_ctrl_ops,
15895aaef13dSDaniel Scally 						   V4L2_CID_LINK_FREQ,
15905aaef13dSDaniel Scally 						   ARRAY_SIZE(link_freq) - 1,
15915aaef13dSDaniel Scally 						   ov7251->link_freq_idx,
15925aaef13dSDaniel Scally 						   link_freq);
15935aaef13dSDaniel Scally 	if (ov7251->link_freq)
15945aaef13dSDaniel Scally 		ov7251->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
15955aaef13dSDaniel Scally 	if (ov7251->pixel_clock)
15965aaef13dSDaniel Scally 		ov7251->pixel_clock->flags |= V4L2_CTRL_FLAG_READ_ONLY;
15975aaef13dSDaniel Scally 
159826066ae6SDaniel Scally 	hblank = OV7251_FIXED_PPL - ov7251->current_mode->width;
159926066ae6SDaniel Scally 	ov7251->hblank = v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops,
160026066ae6SDaniel Scally 					   V4L2_CID_HBLANK, hblank, hblank, 1,
160126066ae6SDaniel Scally 					   hblank);
160226066ae6SDaniel Scally 	if (ov7251->hblank)
160326066ae6SDaniel Scally 		ov7251->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
160426066ae6SDaniel Scally 
16051b598f41SDaniel Scally 	vblank_max = OV7251_TIMING_MAX_VTS - ov7251->current_mode->height;
16061b598f41SDaniel Scally 	vblank_def = ov7251->current_mode->vts - ov7251->current_mode->height;
16071b598f41SDaniel Scally 	ov7251->vblank = v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops,
16081b598f41SDaniel Scally 					   V4L2_CID_VBLANK,
16091b598f41SDaniel Scally 					   OV7251_TIMING_MIN_VTS, vblank_max, 1,
16101b598f41SDaniel Scally 					   vblank_def);
16111b598f41SDaniel Scally 
16125aaef13dSDaniel Scally 	ov7251->sd.ctrl_handler = &ov7251->ctrls;
16135aaef13dSDaniel Scally 
16145aaef13dSDaniel Scally 	if (ov7251->ctrls.error) {
16155aaef13dSDaniel Scally 		v4l2_ctrl_handler_free(&ov7251->ctrls);
16165aaef13dSDaniel Scally 		return ov7251->ctrls.error;
16175aaef13dSDaniel Scally 	}
16185aaef13dSDaniel Scally 
16195aaef13dSDaniel Scally 	return 0;
16205aaef13dSDaniel Scally }
16215aaef13dSDaniel Scally 
ov7251_probe(struct i2c_client * client)1622d30bb512STodor Tomov static int ov7251_probe(struct i2c_client *client)
1623d30bb512STodor Tomov {
1624d30bb512STodor Tomov 	struct device *dev = &client->dev;
1625d30bb512STodor Tomov 	struct ov7251 *ov7251;
1626ed9566ceSDaniel Scally 	unsigned int rate = 0, clk_rate = 0;
1627d30bb512STodor Tomov 	int ret;
1628df057b0dSDaniel Scally 	int i;
1629d30bb512STodor Tomov 
1630d30bb512STodor Tomov 	ov7251 = devm_kzalloc(dev, sizeof(struct ov7251), GFP_KERNEL);
1631d30bb512STodor Tomov 	if (!ov7251)
1632d30bb512STodor Tomov 		return -ENOMEM;
1633d30bb512STodor Tomov 
1634d30bb512STodor Tomov 	ov7251->i2c_client = client;
1635d30bb512STodor Tomov 	ov7251->dev = dev;
1636d30bb512STodor Tomov 
1637cc125aaaSDaniel Scally 	ret = ov7251_check_hwcfg(ov7251);
1638cc125aaaSDaniel Scally 	if (ret)
1639d30bb512STodor Tomov 		return ret;
1640d30bb512STodor Tomov 
1641d30bb512STodor Tomov 	/* get system clock (xclk) */
1642ed9566ceSDaniel Scally 	ov7251->xclk = devm_clk_get_optional(dev, NULL);
1643ed9566ceSDaniel Scally 	if (IS_ERR(ov7251->xclk))
1644ed9566ceSDaniel Scally 		return dev_err_probe(dev, PTR_ERR(ov7251->xclk),
1645ed9566ceSDaniel Scally 				     "could not get xclk");
1646d30bb512STodor Tomov 
1647ed9566ceSDaniel Scally 	/*
1648ed9566ceSDaniel Scally 	 * We could have either a 24MHz or 19.2MHz clock rate from either DT or
1649ed9566ceSDaniel Scally 	 * ACPI. We also need to support the IPU3 case which will have both an
1650ed9566ceSDaniel Scally 	 * external clock AND a clock-frequency property.
1651ed9566ceSDaniel Scally 	 */
1652d30bb512STodor Tomov 	ret = fwnode_property_read_u32(dev_fwnode(dev), "clock-frequency",
1653ed9566ceSDaniel Scally 				       &rate);
1654ed9566ceSDaniel Scally 	if (ret && !ov7251->xclk)
1655ed9566ceSDaniel Scally 		return dev_err_probe(dev, ret, "invalid clock config\n");
1656ed9566ceSDaniel Scally 
1657ed9566ceSDaniel Scally 	clk_rate = clk_get_rate(ov7251->xclk);
1658ed9566ceSDaniel Scally 	ov7251->xclk_freq = clk_rate ? clk_rate : rate;
1659ed9566ceSDaniel Scally 
1660ed9566ceSDaniel Scally 	if (ov7251->xclk_freq == 0)
1661ed9566ceSDaniel Scally 		return dev_err_probe(dev, -EINVAL, "invalid clock frequency\n");
1662ed9566ceSDaniel Scally 
1663ed9566ceSDaniel Scally 	if (!ret && ov7251->xclk) {
1664ed9566ceSDaniel Scally 		ret = clk_set_rate(ov7251->xclk, rate);
1665ed9566ceSDaniel Scally 		if (ret)
1666ed9566ceSDaniel Scally 			return dev_err_probe(dev, ret,
1667ed9566ceSDaniel Scally 					     "failed to set clock rate\n");
1668d30bb512STodor Tomov 	}
1669d30bb512STodor Tomov 
1670df057b0dSDaniel Scally 	for (i = 0; i < ARRAY_SIZE(supported_xclk_rates); i++)
1671df057b0dSDaniel Scally 		if (ov7251->xclk_freq == supported_xclk_rates[i])
1672df057b0dSDaniel Scally 			break;
1673df057b0dSDaniel Scally 
1674df057b0dSDaniel Scally 	if (i == ARRAY_SIZE(supported_xclk_rates))
1675df057b0dSDaniel Scally 		return dev_err_probe(dev, -EINVAL,
1676df057b0dSDaniel Scally 				     "clock rate %u Hz is unsupported\n",
1677df057b0dSDaniel Scally 				     ov7251->xclk_freq);
1678df057b0dSDaniel Scally 
1679df057b0dSDaniel Scally 	ov7251->pll_cfgs = ov7251_pll_cfgs[i];
1680d30bb512STodor Tomov 
1681d30bb512STodor Tomov 	ov7251->io_regulator = devm_regulator_get(dev, "vdddo");
1682d30bb512STodor Tomov 	if (IS_ERR(ov7251->io_regulator)) {
1683d30bb512STodor Tomov 		dev_err(dev, "cannot get io regulator\n");
1684d30bb512STodor Tomov 		return PTR_ERR(ov7251->io_regulator);
1685d30bb512STodor Tomov 	}
1686d30bb512STodor Tomov 
1687d30bb512STodor Tomov 	ov7251->core_regulator = devm_regulator_get(dev, "vddd");
1688d30bb512STodor Tomov 	if (IS_ERR(ov7251->core_regulator)) {
1689d30bb512STodor Tomov 		dev_err(dev, "cannot get core regulator\n");
1690d30bb512STodor Tomov 		return PTR_ERR(ov7251->core_regulator);
1691d30bb512STodor Tomov 	}
1692d30bb512STodor Tomov 
1693d30bb512STodor Tomov 	ov7251->analog_regulator = devm_regulator_get(dev, "vdda");
1694d30bb512STodor Tomov 	if (IS_ERR(ov7251->analog_regulator)) {
1695d30bb512STodor Tomov 		dev_err(dev, "cannot get analog regulator\n");
1696d30bb512STodor Tomov 		return PTR_ERR(ov7251->analog_regulator);
1697d30bb512STodor Tomov 	}
1698d30bb512STodor Tomov 
1699d30bb512STodor Tomov 	ov7251->enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_HIGH);
1700d30bb512STodor Tomov 	if (IS_ERR(ov7251->enable_gpio)) {
1701d30bb512STodor Tomov 		dev_err(dev, "cannot get enable gpio\n");
1702d30bb512STodor Tomov 		return PTR_ERR(ov7251->enable_gpio);
1703d30bb512STodor Tomov 	}
1704d30bb512STodor Tomov 
1705d30bb512STodor Tomov 	mutex_init(&ov7251->lock);
1706d30bb512STodor Tomov 
170726066ae6SDaniel Scally 	ov7251->current_mode = &ov7251_mode_info_data[0];
17085aaef13dSDaniel Scally 	ret = ov7251_init_ctrls(ov7251);
17095aaef13dSDaniel Scally 	if (ret) {
17105aaef13dSDaniel Scally 		dev_err_probe(dev, ret, "error during v4l2 ctrl init\n");
17115aaef13dSDaniel Scally 		goto destroy_mutex;
1712d30bb512STodor Tomov 	}
1713d30bb512STodor Tomov 
1714d30bb512STodor Tomov 	v4l2_i2c_subdev_init(&ov7251->sd, client, &ov7251_subdev_ops);
17155755be5fSLaurent Pinchart 	ov7251->sd.internal_ops = &ov7251_internal_ops;
1716d30bb512STodor Tomov 	ov7251->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1717d30bb512STodor Tomov 	ov7251->pad.flags = MEDIA_PAD_FL_SOURCE;
1718d30bb512STodor Tomov 	ov7251->sd.dev = &client->dev;
1719d30bb512STodor Tomov 	ov7251->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1720d30bb512STodor Tomov 
1721d30bb512STodor Tomov 	ret = media_entity_pads_init(&ov7251->sd.entity, 1, &ov7251->pad);
1722d30bb512STodor Tomov 	if (ret < 0) {
1723d30bb512STodor Tomov 		dev_err(dev, "could not register media entity\n");
1724d30bb512STodor Tomov 		goto free_ctrl;
1725d30bb512STodor Tomov 	}
1726d30bb512STodor Tomov 
1727207f4162SDaniel Scally 	ret = ov7251_set_power_on(ov7251->dev);
1728207f4162SDaniel Scally 	if (ret)
1729d30bb512STodor Tomov 		goto free_entity;
1730d30bb512STodor Tomov 
1731e92932c3SDaniel Scally 	ret = ov7251_detect_chip(ov7251);
1732e92932c3SDaniel Scally 	if (ret)
1733d30bb512STodor Tomov 		goto power_down;
1734d30bb512STodor Tomov 
1735207f4162SDaniel Scally 	pm_runtime_set_active(&client->dev);
1736207f4162SDaniel Scally 	pm_runtime_get_noresume(&client->dev);
1737207f4162SDaniel Scally 	pm_runtime_enable(&client->dev);
1738d30bb512STodor Tomov 
1739d30bb512STodor Tomov 	ret = ov7251_read_reg(ov7251, OV7251_PRE_ISP_00,
1740d30bb512STodor Tomov 			      &ov7251->pre_isp_00);
1741d30bb512STodor Tomov 	if (ret < 0) {
1742d30bb512STodor Tomov 		dev_err(dev, "could not read test pattern value\n");
1743d30bb512STodor Tomov 		ret = -ENODEV;
1744207f4162SDaniel Scally 		goto err_pm_runtime;
1745d30bb512STodor Tomov 	}
1746d30bb512STodor Tomov 
1747d30bb512STodor Tomov 	ret = ov7251_read_reg(ov7251, OV7251_TIMING_FORMAT1,
1748d30bb512STodor Tomov 			      &ov7251->timing_format1);
1749d30bb512STodor Tomov 	if (ret < 0) {
1750d30bb512STodor Tomov 		dev_err(dev, "could not read vflip value\n");
1751d30bb512STodor Tomov 		ret = -ENODEV;
1752207f4162SDaniel Scally 		goto err_pm_runtime;
1753d30bb512STodor Tomov 	}
1754d30bb512STodor Tomov 
1755d30bb512STodor Tomov 	ret = ov7251_read_reg(ov7251, OV7251_TIMING_FORMAT2,
1756d30bb512STodor Tomov 			      &ov7251->timing_format2);
1757d30bb512STodor Tomov 	if (ret < 0) {
1758d30bb512STodor Tomov 		dev_err(dev, "could not read hflip value\n");
1759d30bb512STodor Tomov 		ret = -ENODEV;
1760207f4162SDaniel Scally 		goto err_pm_runtime;
1761d30bb512STodor Tomov 	}
1762d30bb512STodor Tomov 
1763207f4162SDaniel Scally 	pm_runtime_set_autosuspend_delay(&client->dev, 1000);
1764207f4162SDaniel Scally 	pm_runtime_use_autosuspend(&client->dev);
1765207f4162SDaniel Scally 	pm_runtime_put_autosuspend(&client->dev);
1766d30bb512STodor Tomov 
1767d30bb512STodor Tomov 	ret = v4l2_async_register_subdev(&ov7251->sd);
1768d30bb512STodor Tomov 	if (ret < 0) {
1769d30bb512STodor Tomov 		dev_err(dev, "could not register v4l2 device\n");
1770d30bb512STodor Tomov 		goto free_entity;
1771d30bb512STodor Tomov 	}
1772d30bb512STodor Tomov 
17735755be5fSLaurent Pinchart 	ov7251_init_state(&ov7251->sd, NULL);
1774d30bb512STodor Tomov 
1775d30bb512STodor Tomov 	return 0;
1776d30bb512STodor Tomov 
1777207f4162SDaniel Scally err_pm_runtime:
1778207f4162SDaniel Scally 	pm_runtime_disable(ov7251->dev);
1779207f4162SDaniel Scally 	pm_runtime_put_noidle(ov7251->dev);
1780d30bb512STodor Tomov power_down:
1781207f4162SDaniel Scally 	ov7251_set_power_off(ov7251->dev);
1782d30bb512STodor Tomov free_entity:
1783d30bb512STodor Tomov 	media_entity_cleanup(&ov7251->sd.entity);
1784d30bb512STodor Tomov free_ctrl:
1785d30bb512STodor Tomov 	v4l2_ctrl_handler_free(&ov7251->ctrls);
17865aaef13dSDaniel Scally destroy_mutex:
1787d30bb512STodor Tomov 	mutex_destroy(&ov7251->lock);
1788d30bb512STodor Tomov 
1789d30bb512STodor Tomov 	return ret;
1790d30bb512STodor Tomov }
1791d30bb512STodor Tomov 
ov7251_remove(struct i2c_client * client)1792ed5c2f5fSUwe Kleine-König static void ov7251_remove(struct i2c_client *client)
1793d30bb512STodor Tomov {
1794d30bb512STodor Tomov 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
1795d30bb512STodor Tomov 	struct ov7251 *ov7251 = to_ov7251(sd);
1796d30bb512STodor Tomov 
1797d30bb512STodor Tomov 	v4l2_async_unregister_subdev(&ov7251->sd);
1798d30bb512STodor Tomov 	media_entity_cleanup(&ov7251->sd.entity);
1799d30bb512STodor Tomov 	v4l2_ctrl_handler_free(&ov7251->ctrls);
1800d30bb512STodor Tomov 	mutex_destroy(&ov7251->lock);
1801d30bb512STodor Tomov 
1802207f4162SDaniel Scally 	pm_runtime_disable(ov7251->dev);
1803207f4162SDaniel Scally 	if (!pm_runtime_status_suspended(ov7251->dev))
1804207f4162SDaniel Scally 		ov7251_set_power_off(ov7251->dev);
1805207f4162SDaniel Scally 	pm_runtime_set_suspended(ov7251->dev);
1806d30bb512STodor Tomov }
1807d30bb512STodor Tomov 
1808207f4162SDaniel Scally static const struct dev_pm_ops ov7251_pm_ops = {
1809207f4162SDaniel Scally 	SET_RUNTIME_PM_OPS(ov7251_set_power_off, ov7251_set_power_on, NULL)
1810207f4162SDaniel Scally };
1811207f4162SDaniel Scally 
1812d30bb512STodor Tomov static const struct of_device_id ov7251_of_match[] = {
1813d30bb512STodor Tomov 	{ .compatible = "ovti,ov7251" },
1814d30bb512STodor Tomov 	{ /* sentinel */ }
1815d30bb512STodor Tomov };
1816d30bb512STodor Tomov MODULE_DEVICE_TABLE(of, ov7251_of_match);
1817d30bb512STodor Tomov 
18186766cff6SDaniel Scally static const struct acpi_device_id ov7251_acpi_match[] = {
18196766cff6SDaniel Scally 	{ "INT347E" },
18206766cff6SDaniel Scally 	{ }
18216766cff6SDaniel Scally };
18226766cff6SDaniel Scally MODULE_DEVICE_TABLE(acpi, ov7251_acpi_match);
18236766cff6SDaniel Scally 
1824d30bb512STodor Tomov static struct i2c_driver ov7251_i2c_driver = {
1825d30bb512STodor Tomov 	.driver = {
1826d30bb512STodor Tomov 		.of_match_table = ov7251_of_match,
18276766cff6SDaniel Scally 		.acpi_match_table = ov7251_acpi_match,
1828d30bb512STodor Tomov 		.name  = "ov7251",
1829207f4162SDaniel Scally 		.pm = &ov7251_pm_ops,
1830d30bb512STodor Tomov 	},
1831aaeb31c0SUwe Kleine-König 	.probe = ov7251_probe,
1832d30bb512STodor Tomov 	.remove = ov7251_remove,
1833d30bb512STodor Tomov };
1834d30bb512STodor Tomov 
1835d30bb512STodor Tomov module_i2c_driver(ov7251_i2c_driver);
1836d30bb512STodor Tomov 
1837d30bb512STodor Tomov MODULE_DESCRIPTION("Omnivision OV7251 Camera Driver");
1838d30bb512STodor Tomov MODULE_AUTHOR("Todor Tomov <todor.tomov@linaro.org>");
1839d30bb512STodor Tomov MODULE_LICENSE("GPL v2");
1840