1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * V4L2 sensor driver for OmniVision OV64A40 4 * 5 * Copyright (C) 2023 Ideas On Board Oy 6 * Copyright (C) 2023 Arducam 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/i2c.h> 13 #include <linux/mod_devicetable.h> 14 #include <linux/module.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/regulator/consumer.h> 17 18 #include <media/v4l2-cci.h> 19 #include <media/v4l2-ctrls.h> 20 #include <media/v4l2-device.h> 21 #include <media/v4l2-event.h> 22 #include <media/v4l2-fwnode.h> 23 #include <media/v4l2-mediabus.h> 24 #include <media/v4l2-subdev.h> 25 26 #define OV64A40_XCLK_FREQ 24000000 27 28 #define OV64A40_NATIVE_WIDTH 9286 29 #define OV64A40_NATIVE_HEIGHT 6976 30 #define OV64A40_PIXEL_ARRAY_TOP 0 31 #define OV64A40_PIXEL_ARRAY_LEFT 0 32 #define OV64A40_PIXEL_ARRAY_WIDTH 9248 33 #define OV64A40_PIXEL_ARRAY_HEIGHT 6944 34 35 #define OV64A40_PIXEL_RATE 300000000 36 37 #define OV64A40_LINK_FREQ_360M 360000000 38 #define OV64A40_LINK_FREQ_456M 456000000 39 40 #define OV64A40_PLL1_PRE_DIV0 CCI_REG8(0x0301) 41 #define OV64A40_PLL1_PRE_DIV CCI_REG8(0x0303) 42 #define OV64A40_PLL1_MULTIPLIER CCI_REG16(0x0304) 43 #define OV64A40_PLL1_M_DIV CCI_REG8(0x0307) 44 #define OV64A40_PLL2_SEL_BAK_SA1 CCI_REG8(0x0320) 45 #define OV64A40_PLL2_PRE_DIV CCI_REG8(0x0323) 46 #define OV64A40_PLL2_MULTIPLIER CCI_REG16(0x0324) 47 #define OV64A40_PLL2_PRE_DIV0 CCI_REG8(0x0326) 48 #define OV64A40_PLL2_DIVDAC CCI_REG8(0x0329) 49 #define OV64A40_PLL2_DIVSP CCI_REG8(0x032d) 50 #define OV64A40_PLL2_DACPREDIV CCI_REG8(0x032e) 51 52 /* TODO: validate vblank_min, it's not characterized in the datasheet. */ 53 #define OV64A40_VBLANK_MIN 128 54 #define OV64A40_VTS_MAX 0xffffff 55 56 #define OV64A40_REG_MEC_LONG_EXPO CCI_REG24(0x3500) 57 #define OV64A40_EXPOSURE_MIN 16 58 #define OV64A40_EXPOSURE_MARGIN 32 59 60 #define OV64A40_REG_MEC_LONG_GAIN CCI_REG16(0x3508) 61 #define OV64A40_ANA_GAIN_MIN 0x80 62 #define OV64A40_ANA_GAIN_MAX 0x7ff 63 #define OV64A40_ANA_GAIN_DEFAULT 0x80 64 65 #define OV64A40_REG_TIMING_CTRL0 CCI_REG16(0x3800) 66 #define OV64A40_REG_TIMING_CTRL2 CCI_REG16(0x3802) 67 #define OV64A40_REG_TIMING_CTRL4 CCI_REG16(0x3804) 68 #define OV64A40_REG_TIMING_CTRL6 CCI_REG16(0x3806) 69 #define OV64A40_REG_TIMING_CTRL8 CCI_REG16(0x3808) 70 #define OV64A40_REG_TIMING_CTRLA CCI_REG16(0x380a) 71 #define OV64A40_REG_TIMING_CTRLC CCI_REG16(0x380c) 72 #define OV64A40_REG_TIMING_CTRLE CCI_REG16(0x380e) 73 #define OV64A40_REG_TIMING_CTRL10 CCI_REG16(0x3810) 74 #define OV64A40_REG_TIMING_CTRL12 CCI_REG16(0x3812) 75 76 /* 77 * Careful: a typo in the datasheet calls this register 78 * OV64A40_REG_TIMING_CTRL20. 79 */ 80 #define OV64A40_REG_TIMING_CTRL14 CCI_REG8(0x3814) 81 #define OV64A40_REG_TIMING_CTRL15 CCI_REG8(0x3815) 82 #define OV64A40_ODD_INC_SHIFT 4 83 #define OV64A40_SKIPPING_CONFIG(_odd, _even) \ 84 (((_odd) << OV64A40_ODD_INC_SHIFT) | (_even)) 85 86 #define OV64A40_REG_TIMING_CTRL_20 CCI_REG8(0x3820) 87 #define OV64A40_TIMING_CTRL_20_VFLIP BIT(2) 88 #define OV64A40_TIMING_CTRL_20_VBIN BIT(1) 89 90 #define OV64A40_REG_TIMING_CTRL_21 CCI_REG8(0x3821) 91 #define OV64A40_TIMING_CTRL_21_HBIN BIT(4) 92 #define OV64A40_TIMING_CTRL_21_HFLIP BIT(2) 93 #define OV64A40_TIMING_CTRL_21_DSPEED BIT(0) 94 #define OV64A40_TIMING_CTRL_21_HBIN_CONF \ 95 (OV64A40_TIMING_CTRL_21_HBIN | \ 96 OV64A40_TIMING_CTRL_21_DSPEED) 97 98 #define OV64A40_REG_TIMINGS_VTS_HIGH CCI_REG8(0x3840) 99 #define OV64A40_REG_TIMINGS_VTS_MID CCI_REG8(0x380e) 100 #define OV64A40_REG_TIMINGS_VTS_LOW CCI_REG8(0x380f) 101 102 /* The test pattern control is weirdly named PRE_ISP_2325_D2V2_TOP_1 in TRM. */ 103 #define OV64A40_REG_TEST_PATTERN CCI_REG8(0x50c1) 104 #define OV64A40_TEST_PATTERN_DISABLED 0x00 105 #define OV64A40_TEST_PATTERN_TYPE1 BIT(0) 106 #define OV64A40_TEST_PATTERN_TYPE2 (BIT(4) | BIT(0)) 107 #define OV64A40_TEST_PATTERN_TYPE3 (BIT(5) | BIT(0)) 108 #define OV64A40_TEST_PATTERN_TYPE4 (BIT(5) | BIT(4) | BIT(0)) 109 110 #define OV64A40_REG_CHIP_ID CCI_REG24(0x300a) 111 #define OV64A40_CHIP_ID 0x566441 112 113 #define OV64A40_REG_SMIA CCI_REG8(0x0100) 114 #define OV64A40_REG_SMIA_STREAMING BIT(0) 115 116 enum ov64a40_link_freq_ids { 117 OV64A40_LINK_FREQ_456M_ID, 118 OV64A40_LINK_FREQ_360M_ID, 119 OV64A40_NUM_LINK_FREQ, 120 }; 121 122 static const char * const ov64a40_supply_names[] = { 123 /* Supplies can be enabled in any order */ 124 "avdd", /* Analog (2.8V) supply */ 125 "dovdd", /* Digital Core (1.8V) supply */ 126 "dvdd", /* IF (1.1V) supply */ 127 }; 128 129 static const char * const ov64a40_test_pattern_menu[] = { 130 "Disabled", 131 "Type1", 132 "Type2", 133 "Type3", 134 "Type4", 135 }; 136 137 static const int ov64a40_test_pattern_val[] = { 138 OV64A40_TEST_PATTERN_DISABLED, 139 OV64A40_TEST_PATTERN_TYPE1, 140 OV64A40_TEST_PATTERN_TYPE2, 141 OV64A40_TEST_PATTERN_TYPE3, 142 OV64A40_TEST_PATTERN_TYPE4, 143 }; 144 145 static const unsigned int ov64a40_mbus_codes[] = { 146 MEDIA_BUS_FMT_SBGGR10_1X10, 147 MEDIA_BUS_FMT_SGRBG10_1X10, 148 MEDIA_BUS_FMT_SGBRG10_1X10, 149 MEDIA_BUS_FMT_SRGGB10_1X10, 150 }; 151 152 static const struct cci_reg_sequence ov64a40_init[] = { 153 { CCI_REG8(0x0103), 0x01 }, { CCI_REG8(0x0301), 0x88 }, 154 { CCI_REG8(0x0304), 0x00 }, { CCI_REG8(0x0305), 0x96 }, 155 { CCI_REG8(0x0306), 0x03 }, { CCI_REG8(0x0307), 0x00 }, 156 { CCI_REG8(0x0345), 0x2c }, { CCI_REG8(0x034a), 0x02 }, 157 { CCI_REG8(0x034b), 0x02 }, { CCI_REG8(0x0350), 0xc0 }, 158 { CCI_REG8(0x0360), 0x09 }, { CCI_REG8(0x3012), 0x31 }, 159 { CCI_REG8(0x3015), 0xf0 }, { CCI_REG8(0x3017), 0xf0 }, 160 { CCI_REG8(0x301d), 0xf6 }, { CCI_REG8(0x301e), 0xf1 }, 161 { CCI_REG8(0x3022), 0xf0 }, { CCI_REG8(0x3400), 0x08 }, 162 { CCI_REG8(0x3608), 0x41 }, { CCI_REG8(0x3421), 0x02 }, 163 { CCI_REG8(0x3500), 0x00 }, { CCI_REG8(0x3501), 0x00 }, 164 { CCI_REG8(0x3502), 0x18 }, { CCI_REG8(0x3504), 0x0c }, 165 { CCI_REG8(0x3508), 0x01 }, { CCI_REG8(0x3509), 0x00 }, 166 { CCI_REG8(0x350a), 0x01 }, { CCI_REG8(0x350b), 0x00 }, 167 { CCI_REG8(0x350b), 0x00 }, { CCI_REG8(0x3540), 0x00 }, 168 { CCI_REG8(0x3541), 0x00 }, { CCI_REG8(0x3542), 0x08 }, 169 { CCI_REG8(0x3548), 0x01 }, { CCI_REG8(0x3549), 0xa0 }, 170 { CCI_REG8(0x3549), 0x00 }, { CCI_REG8(0x3549), 0x00 }, 171 { CCI_REG8(0x3549), 0x00 }, { CCI_REG8(0x3580), 0x00 }, 172 { CCI_REG8(0x3581), 0x00 }, { CCI_REG8(0x3582), 0x04 }, 173 { CCI_REG8(0x3588), 0x01 }, { CCI_REG8(0x3589), 0xf0 }, 174 { CCI_REG8(0x3589), 0x00 }, { CCI_REG8(0x3589), 0x00 }, 175 { CCI_REG8(0x3589), 0x00 }, { CCI_REG8(0x360d), 0x83 }, 176 { CCI_REG8(0x3616), 0xa0 }, { CCI_REG8(0x3617), 0x31 }, 177 { CCI_REG8(0x3623), 0x10 }, { CCI_REG8(0x3633), 0x03 }, 178 { CCI_REG8(0x3634), 0x03 }, { CCI_REG8(0x3635), 0x77 }, 179 { CCI_REG8(0x3640), 0x19 }, { CCI_REG8(0x3641), 0x80 }, 180 { CCI_REG8(0x364d), 0x0f }, { CCI_REG8(0x3680), 0x80 }, 181 { CCI_REG8(0x3682), 0x00 }, { CCI_REG8(0x3683), 0x00 }, 182 { CCI_REG8(0x3684), 0x07 }, { CCI_REG8(0x3688), 0x01 }, 183 { CCI_REG8(0x3689), 0x08 }, { CCI_REG8(0x368a), 0x26 }, 184 { CCI_REG8(0x368b), 0xc8 }, { CCI_REG8(0x368e), 0x70 }, 185 { CCI_REG8(0x368f), 0x00 }, { CCI_REG8(0x3692), 0x04 }, 186 { CCI_REG8(0x3693), 0x00 }, { CCI_REG8(0x3696), 0xd1 }, 187 { CCI_REG8(0x3697), 0xe0 }, { CCI_REG8(0x3698), 0x80 }, 188 { CCI_REG8(0x3699), 0x2b }, { CCI_REG8(0x369a), 0x00 }, 189 { CCI_REG8(0x369d), 0x00 }, { CCI_REG8(0x369e), 0x14 }, 190 { CCI_REG8(0x369f), 0x20 }, { CCI_REG8(0x36a5), 0x80 }, 191 { CCI_REG8(0x36a6), 0x00 }, { CCI_REG8(0x36a7), 0x00 }, 192 { CCI_REG8(0x36a8), 0x00 }, { CCI_REG8(0x36b5), 0x17 }, 193 { CCI_REG8(0x3701), 0x30 }, { CCI_REG8(0x3706), 0x2b }, 194 { CCI_REG8(0x3709), 0x8d }, { CCI_REG8(0x370b), 0x4f }, 195 { CCI_REG8(0x3711), 0x00 }, { CCI_REG8(0x3712), 0x01 }, 196 { CCI_REG8(0x3713), 0x00 }, { CCI_REG8(0x3720), 0x08 }, 197 { CCI_REG8(0x3727), 0x22 }, { CCI_REG8(0x3728), 0x01 }, 198 { CCI_REG8(0x375e), 0x00 }, { CCI_REG8(0x3760), 0x08 }, 199 { CCI_REG8(0x3761), 0x10 }, { CCI_REG8(0x3762), 0x08 }, 200 { CCI_REG8(0x3765), 0x10 }, { CCI_REG8(0x3766), 0x18 }, 201 { CCI_REG8(0x376a), 0x08 }, { CCI_REG8(0x376b), 0x00 }, 202 { CCI_REG8(0x376d), 0x1b }, { CCI_REG8(0x3791), 0x2b }, 203 { CCI_REG8(0x3793), 0x2b }, { CCI_REG8(0x3795), 0x2b }, 204 { CCI_REG8(0x3797), 0x4f }, { CCI_REG8(0x3799), 0x4f }, 205 { CCI_REG8(0x379b), 0x4f }, { CCI_REG8(0x37a0), 0x22 }, 206 { CCI_REG8(0x37da), 0x04 }, { CCI_REG8(0x37f9), 0x02 }, 207 { CCI_REG8(0x37fa), 0x02 }, { CCI_REG8(0x37fb), 0x02 }, 208 { CCI_REG8(0x3814), 0x11 }, { CCI_REG8(0x3815), 0x11 }, 209 { CCI_REG8(0x3820), 0x40 }, { CCI_REG8(0x3821), 0x04 }, 210 { CCI_REG8(0x3822), 0x00 }, { CCI_REG8(0x3823), 0x04 }, 211 { CCI_REG8(0x3827), 0x08 }, { CCI_REG8(0x3828), 0x00 }, 212 { CCI_REG8(0x382a), 0x81 }, { CCI_REG8(0x382e), 0x70 }, 213 { CCI_REG8(0x3837), 0x10 }, { CCI_REG8(0x3839), 0x00 }, 214 { CCI_REG8(0x383b), 0x00 }, { CCI_REG8(0x383c), 0x00 }, 215 { CCI_REG8(0x383d), 0x10 }, { CCI_REG8(0x383f), 0x00 }, 216 { CCI_REG8(0x384c), 0x02 }, { CCI_REG8(0x384d), 0x8c }, 217 { CCI_REG8(0x3852), 0x00 }, { CCI_REG8(0x3856), 0x10 }, 218 { CCI_REG8(0x3857), 0x10 }, { CCI_REG8(0x3858), 0x20 }, 219 { CCI_REG8(0x3859), 0x20 }, { CCI_REG8(0x3894), 0x00 }, 220 { CCI_REG8(0x3895), 0x00 }, { CCI_REG8(0x3896), 0x00 }, 221 { CCI_REG8(0x3897), 0x00 }, { CCI_REG8(0x3900), 0x40 }, 222 { CCI_REG8(0x3aed), 0x6e }, { CCI_REG8(0x3af1), 0x73 }, 223 { CCI_REG8(0x3d86), 0x12 }, { CCI_REG8(0x3d87), 0x30 }, 224 { CCI_REG8(0x3d8c), 0xab }, { CCI_REG8(0x3d8d), 0xb0 }, 225 { CCI_REG8(0x3f00), 0x12 }, { CCI_REG8(0x3f00), 0x12 }, 226 { CCI_REG8(0x3f00), 0x12 }, { CCI_REG8(0x3f01), 0x03 }, 227 { CCI_REG8(0x4009), 0x01 }, { CCI_REG8(0x400e), 0xc6 }, 228 { CCI_REG8(0x400f), 0x00 }, { CCI_REG8(0x4010), 0x28 }, 229 { CCI_REG8(0x4011), 0x01 }, { CCI_REG8(0x4012), 0x0c }, 230 { CCI_REG8(0x4015), 0x00 }, { CCI_REG8(0x4016), 0x1f }, 231 { CCI_REG8(0x4017), 0x00 }, { CCI_REG8(0x4018), 0x07 }, 232 { CCI_REG8(0x401a), 0x40 }, { CCI_REG8(0x4028), 0x01 }, 233 { CCI_REG8(0x4504), 0x00 }, { CCI_REG8(0x4506), 0x01 }, 234 { CCI_REG8(0x4508), 0x00 }, { CCI_REG8(0x4509), 0x35 }, 235 { CCI_REG8(0x450a), 0x08 }, { CCI_REG8(0x450c), 0x00 }, 236 { CCI_REG8(0x450d), 0x20 }, { CCI_REG8(0x450e), 0x00 }, 237 { CCI_REG8(0x450f), 0x20 }, { CCI_REG8(0x451e), 0x00 }, 238 { CCI_REG8(0x451f), 0x00 }, { CCI_REG8(0x4523), 0x00 }, 239 { CCI_REG8(0x4526), 0x00 }, { CCI_REG8(0x4527), 0x18 }, 240 { CCI_REG8(0x4580), 0x01 }, { CCI_REG8(0x4583), 0x00 }, 241 { CCI_REG8(0x4584), 0x00 }, { CCI_REG8(0x45c0), 0xa1 }, 242 { CCI_REG8(0x4602), 0x08 }, { CCI_REG8(0x4603), 0x05 }, 243 { CCI_REG8(0x4606), 0x12 }, { CCI_REG8(0x4607), 0x30 }, 244 { CCI_REG8(0x460b), 0x00 }, { CCI_REG8(0x460d), 0x00 }, 245 { CCI_REG8(0x4640), 0x00 }, { CCI_REG8(0x4641), 0x24 }, 246 { CCI_REG8(0x4643), 0x08 }, { CCI_REG8(0x4645), 0x14 }, 247 { CCI_REG8(0x4648), 0x0a }, { CCI_REG8(0x4649), 0x06 }, 248 { CCI_REG8(0x464a), 0x00 }, { CCI_REG8(0x464b), 0x30 }, 249 { CCI_REG8(0x4800), 0x04 }, { CCI_REG8(0x4802), 0x02 }, 250 { CCI_REG8(0x480b), 0x10 }, { CCI_REG8(0x480c), 0x80 }, 251 { CCI_REG8(0x480e), 0x04 }, { CCI_REG8(0x480f), 0x32 }, 252 { CCI_REG8(0x481b), 0x12 }, { CCI_REG8(0x4833), 0x30 }, 253 { CCI_REG8(0x4837), 0x08 }, { CCI_REG8(0x484b), 0x27 }, 254 { CCI_REG8(0x4850), 0x42 }, { CCI_REG8(0x4851), 0xaa }, 255 { CCI_REG8(0x4860), 0x01 }, { CCI_REG8(0x4861), 0xec }, 256 { CCI_REG8(0x4862), 0x25 }, { CCI_REG8(0x4888), 0x00 }, 257 { CCI_REG8(0x4889), 0x03 }, { CCI_REG8(0x488c), 0x60 }, 258 { CCI_REG8(0x4910), 0x28 }, { CCI_REG8(0x4911), 0x01 }, 259 { CCI_REG8(0x4912), 0x0c }, { CCI_REG8(0x491a), 0x40 }, 260 { CCI_REG8(0x4915), 0x00 }, { CCI_REG8(0x4916), 0x0f }, 261 { CCI_REG8(0x4917), 0x00 }, { CCI_REG8(0x4918), 0x07 }, 262 { CCI_REG8(0x4a10), 0x28 }, { CCI_REG8(0x4a11), 0x01 }, 263 { CCI_REG8(0x4a12), 0x0c }, { CCI_REG8(0x4a1a), 0x40 }, 264 { CCI_REG8(0x4a15), 0x00 }, { CCI_REG8(0x4a16), 0x0f }, 265 { CCI_REG8(0x4a17), 0x00 }, { CCI_REG8(0x4a18), 0x07 }, 266 { CCI_REG8(0x4d00), 0x04 }, { CCI_REG8(0x4d01), 0x5a }, 267 { CCI_REG8(0x4d02), 0xbb }, { CCI_REG8(0x4d03), 0x84 }, 268 { CCI_REG8(0x4d04), 0xd1 }, { CCI_REG8(0x4d05), 0x68 }, 269 { CCI_REG8(0xc4fa), 0x10 }, { CCI_REG8(0x3b56), 0x0a }, 270 { CCI_REG8(0x3b57), 0x0a }, { CCI_REG8(0x3b58), 0x0c }, 271 { CCI_REG8(0x3b59), 0x10 }, { CCI_REG8(0x3a1d), 0x30 }, 272 { CCI_REG8(0x3a1e), 0x30 }, { CCI_REG8(0x3a21), 0x30 }, 273 { CCI_REG8(0x3a22), 0x30 }, { CCI_REG8(0x3992), 0x02 }, 274 { CCI_REG8(0x399e), 0x02 }, { CCI_REG8(0x39fb), 0x30 }, 275 { CCI_REG8(0x39fc), 0x30 }, { CCI_REG8(0x39fd), 0x30 }, 276 { CCI_REG8(0x39fe), 0x30 }, { CCI_REG8(0x3a6d), 0x83 }, 277 { CCI_REG8(0x3a5e), 0x83 }, { CCI_REG8(0xc500), 0x12 }, 278 { CCI_REG8(0xc501), 0x12 }, { CCI_REG8(0xc502), 0x12 }, 279 { CCI_REG8(0xc503), 0x12 }, { CCI_REG8(0xc505), 0x12 }, 280 { CCI_REG8(0xc506), 0x12 }, { CCI_REG8(0xc507), 0x12 }, 281 { CCI_REG8(0xc508), 0x12 }, { CCI_REG8(0x3a77), 0x12 }, 282 { CCI_REG8(0x3a73), 0x12 }, { CCI_REG8(0x3a7b), 0x12 }, 283 { CCI_REG8(0x3a7f), 0x12 }, { CCI_REG8(0x3b2e), 0x13 }, 284 { CCI_REG8(0x3b29), 0x13 }, { CCI_REG8(0xc439), 0x13 }, 285 { CCI_REG8(0xc469), 0x13 }, { CCI_REG8(0xc41c), 0x89 }, 286 { CCI_REG8(0x3618), 0x80 }, { CCI_REG8(0xc514), 0x51 }, 287 { CCI_REG8(0xc515), 0x2c }, { CCI_REG8(0xc516), 0x16 }, 288 { CCI_REG8(0xc517), 0x0d }, { CCI_REG8(0x3615), 0x7f }, 289 { CCI_REG8(0x3632), 0x99 }, { CCI_REG8(0x3642), 0x00 }, 290 { CCI_REG8(0x3645), 0x80 }, { CCI_REG8(0x3702), 0x2a }, 291 { CCI_REG8(0x3703), 0x2a }, { CCI_REG8(0x3708), 0x2f }, 292 { CCI_REG8(0x3721), 0x15 }, { CCI_REG8(0x3744), 0x28 }, 293 { CCI_REG8(0x3991), 0x0c }, { CCI_REG8(0x371d), 0x24 }, 294 { CCI_REG8(0x371f), 0x0c }, { CCI_REG8(0x374b), 0x03 }, 295 { CCI_REG8(0x37d0), 0x00 }, { CCI_REG8(0x391d), 0x55 }, 296 { CCI_REG8(0x391e), 0x52 }, { CCI_REG8(0x399d), 0x0c }, 297 { CCI_REG8(0x3a2f), 0x01 }, { CCI_REG8(0x3a30), 0x01 }, 298 { CCI_REG8(0x3a31), 0x01 }, { CCI_REG8(0x3a32), 0x01 }, 299 { CCI_REG8(0x3a34), 0x01 }, { CCI_REG8(0x3a35), 0x01 }, 300 { CCI_REG8(0x3a36), 0x01 }, { CCI_REG8(0x3a37), 0x01 }, 301 { CCI_REG8(0x3a43), 0x01 }, { CCI_REG8(0x3a44), 0x01 }, 302 { CCI_REG8(0x3a45), 0x01 }, { CCI_REG8(0x3a46), 0x01 }, 303 { CCI_REG8(0x3a48), 0x01 }, { CCI_REG8(0x3a49), 0x01 }, 304 { CCI_REG8(0x3a4a), 0x01 }, { CCI_REG8(0x3a4b), 0x01 }, 305 { CCI_REG8(0x3a50), 0x14 }, { CCI_REG8(0x3a54), 0x14 }, 306 { CCI_REG8(0x3a60), 0x20 }, { CCI_REG8(0x3a6f), 0x20 }, 307 { CCI_REG8(0x3ac5), 0x01 }, { CCI_REG8(0x3ac6), 0x01 }, 308 { CCI_REG8(0x3ac7), 0x01 }, { CCI_REG8(0x3ac8), 0x01 }, 309 { CCI_REG8(0x3ac9), 0x01 }, { CCI_REG8(0x3aca), 0x01 }, 310 { CCI_REG8(0x3acb), 0x01 }, { CCI_REG8(0x3acc), 0x01 }, 311 { CCI_REG8(0x3acd), 0x01 }, { CCI_REG8(0x3ace), 0x01 }, 312 { CCI_REG8(0x3acf), 0x01 }, { CCI_REG8(0x3ad0), 0x01 }, 313 { CCI_REG8(0x3ad1), 0x01 }, { CCI_REG8(0x3ad2), 0x01 }, 314 { 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CCI_REG8(0x3bf7), 0xcd }, { CCI_REG8(0x3bf8), 0xcd }, 1988 { CCI_REG8(0x3bf9), 0xcd }, { CCI_REG8(0x3bfa), 0xcd }, 1989 { CCI_REG8(0x3bfb), 0xcd }, { CCI_REG8(0x3bfc), 0xcd }, 1990 { CCI_REG8(0x3bfd), 0xcd }, { CCI_REG8(0x3bfe), 0xcd }, 1991 { CCI_REG8(0x3bff), 0xcd }, { CCI_REG8(0x3c00), 0xcd }, 1992 { CCI_REG8(0x3c01), 0xcd }, { CCI_REG8(0x3c02), 0xcd }, 1993 { CCI_REG8(0x3c03), 0xcd }, { CCI_REG8(0x3c04), 0xcd }, 1994 { CCI_REG8(0x3c05), 0xcd }, { CCI_REG8(0x3c06), 0xcd }, 1995 { CCI_REG8(0x3c07), 0xcd }, { CCI_REG8(0x3c08), 0xcd }, 1996 { CCI_REG8(0x3c09), 0xcd }, { CCI_REG8(0x3c0a), 0xcd }, 1997 { CCI_REG8(0x3c0b), 0xcd }, { CCI_REG8(0x3c0c), 0xcd }, 1998 { CCI_REG8(0x3c0d), 0xcd }, { CCI_REG8(0x3c0e), 0xcd }, 1999 { CCI_REG8(0x3c0f), 0xcd }, { CCI_REG8(0x3c10), 0xcd }, 2000 { CCI_REG8(0x3c11), 0xcd }, { CCI_REG8(0x3c12), 0xcd }, 2001 { CCI_REG8(0x3c13), 0xcd }, { CCI_REG8(0x3c14), 0xcd }, 2002 { CCI_REG8(0x3c15), 0xcd }, { CCI_REG8(0x3c16), 0xcd }, 2003 { CCI_REG8(0x3c17), 0xcd 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CCI_REG8(0x3d7f), 0x40 }, { CCI_REG8(0x3d80), 0x40 }, 2184 { CCI_REG8(0x3d81), 0x40 }, { CCI_REG8(0x3d82), 0x40 }, 2185 { CCI_REG8(0x3d83), 0x40 }, { CCI_REG8(0x3d84), 0x40 }, 2186 { CCI_REG8(0x3d85), 0x40 }, { CCI_REG8(0x3d86), 0x40 }, 2187 { CCI_REG8(0x3d87), 0x40 }, { CCI_REG8(0x3d88), 0x40 }, 2188 { CCI_REG8(0x3d89), 0x40 }, { CCI_REG8(0x3d8a), 0x40 }, 2189 { CCI_REG8(0x3d8b), 0x40 }, { CCI_REG8(0x3d8c), 0x40 }, 2190 { CCI_REG8(0x3d8d), 0x40 }, { CCI_REG8(0x3d8e), 0x40 }, 2191 { CCI_REG8(0x3d8f), 0x40 }, { CCI_REG8(0x3d90), 0x40 }, 2192 { CCI_REG8(0x3d91), 0x40 }, { CCI_REG8(0x3d92), 0x40 }, 2193 { CCI_REG8(0x3d93), 0x40 }, { CCI_REG8(0x3d94), 0x40 }, 2194 { CCI_REG8(0x3d95), 0x40 }, { CCI_REG8(0x3d96), 0x40 }, 2195 { CCI_REG8(0x3d97), 0x40 }, { CCI_REG8(0x3d98), 0x40 }, 2196 { CCI_REG8(0x3d99), 0x40 }, { CCI_REG8(0x3d9a), 0x40 }, 2197 { CCI_REG8(0x3d9b), 0x40 }, { CCI_REG8(0x3d9c), 0x40 }, 2198 { CCI_REG8(0x3d9d), 0x40 }, { CCI_REG8(0x3d9e), 0x40 }, 2199 { CCI_REG8(0x3d9f), 0x40 }, { CCI_REG8(0x3da0), 0x40 }, 2200 { CCI_REG8(0x3da1), 0x40 }, { CCI_REG8(0x3da2), 0x40 }, 2201 { CCI_REG8(0x3da3), 0x40 }, { CCI_REG8(0x3da4), 0x40 }, 2202 { CCI_REG8(0x3da5), 0x40 }, { CCI_REG8(0x3da6), 0x40 }, 2203 { CCI_REG8(0x3da7), 0x40 }, { CCI_REG8(0x3da8), 0x40 }, 2204 { CCI_REG8(0x3da9), 0x40 }, { CCI_REG8(0x3daa), 0x40 }, 2205 { CCI_REG8(0x3dab), 0x40 }, { CCI_REG8(0x3dac), 0x40 }, 2206 { CCI_REG8(0x3dad), 0x40 }, { CCI_REG8(0x3dae), 0x40 }, 2207 { CCI_REG8(0x3daf), 0x40 }, { CCI_REG8(0x3db0), 0x40 }, 2208 { CCI_REG8(0x3db1), 0x40 }, { CCI_REG8(0x3db2), 0x40 }, 2209 { CCI_REG8(0x3db3), 0x40 }, { CCI_REG8(0x3db4), 0x40 }, 2210 { CCI_REG8(0x3db5), 0x40 }, { CCI_REG8(0x3db6), 0x40 }, 2211 { CCI_REG8(0x3db7), 0x40 }, { CCI_REG8(0x3db8), 0x40 }, 2212 { CCI_REG8(0x3db9), 0x40 }, { CCI_REG8(0x3dba), 0x40 }, 2213 { CCI_REG8(0x3dbb), 0x40 }, { CCI_REG8(0x3dbc), 0x40 }, 2214 { CCI_REG8(0x3dbd), 0x40 }, { CCI_REG8(0x3dbe), 0x40 }, 2215 { CCI_REG8(0x3dbf), 0xcd }, { CCI_REG8(0x3dc0), 0xcd }, 2216 { CCI_REG8(0x3dc1), 0xcd }, { CCI_REG8(0x3dc2), 0xcd }, 2217 { CCI_REG8(0x3dc3), 0xcd }, { CCI_REG8(0x3dc4), 0xcd }, 2218 { CCI_REG8(0x3dc5), 0xcd }, { CCI_REG8(0x3dc6), 0xcd }, 2219 { CCI_REG8(0x3dc7), 0xcd }, { CCI_REG8(0x3dc8), 0xcd }, 2220 { CCI_REG8(0x3dc9), 0xcd }, { CCI_REG8(0x3dca), 0xcd }, 2221 { CCI_REG8(0x3dcb), 0xcd }, { CCI_REG8(0x3dcc), 0xcd }, 2222 { CCI_REG8(0x3dcd), 0xcd }, { CCI_REG8(0x3dce), 0xcd }, 2223 { CCI_REG8(0x3dcf), 0xcd }, { CCI_REG8(0x3dd0), 0xcd }, 2224 { CCI_REG8(0x3dd1), 0xcd }, { CCI_REG8(0x3dd2), 0xcd }, 2225 { CCI_REG8(0x3dd3), 0xcd }, { CCI_REG8(0x3dd4), 0xcd }, 2226 { CCI_REG8(0x3dd5), 0xcd }, { CCI_REG8(0x3dd6), 0xcd }, 2227 { CCI_REG8(0x3dd7), 0xcd }, { CCI_REG8(0x3dd8), 0xcd }, 2228 { CCI_REG8(0x3dd9), 0xcd }, { CCI_REG8(0x3dda), 0xcd }, 2229 { CCI_REG8(0x3ddb), 0xcd }, { CCI_REG8(0x3ddc), 0xcd }, 2230 { CCI_REG8(0x3ddd), 0xcd }, { CCI_REG8(0x3dde), 0xcd }, 2231 { CCI_REG8(0x3ddf), 0xcd }, { CCI_REG8(0x3de0), 0xcd }, 2232 { CCI_REG8(0x3de1), 0xcd }, { CCI_REG8(0x3de2), 0xcd }, 2233 { CCI_REG8(0x3de3), 0xcd }, { CCI_REG8(0x3de4), 0xcd }, 2234 { CCI_REG8(0x3de5), 0xcd }, { CCI_REG8(0x3de6), 0xcd }, 2235 { CCI_REG8(0x3de7), 0xcd }, { CCI_REG8(0x3de8), 0xcd }, 2236 { CCI_REG8(0x3de9), 0xcd }, { CCI_REG8(0x3dea), 0xcd }, 2237 { CCI_REG8(0x3deb), 0xcd }, { CCI_REG8(0x3dec), 0xcd }, 2238 { CCI_REG8(0x3ded), 0xcd }, { CCI_REG8(0x3dee), 0xcd }, 2239 { CCI_REG8(0x3def), 0xcd }, { CCI_REG8(0x3df0), 0xcd }, 2240 { CCI_REG8(0x3df1), 0xcd }, { CCI_REG8(0x3df2), 0xcd }, 2241 { CCI_REG8(0x3df3), 0xcd }, { CCI_REG8(0x3df4), 0xcd }, 2242 { CCI_REG8(0x3df5), 0xcd }, { CCI_REG8(0x3df6), 0xcd }, 2243 { CCI_REG8(0x3df7), 0xcd }, { CCI_REG8(0x3df8), 0xcd }, 2244 { CCI_REG8(0x3df9), 0xcd }, { CCI_REG8(0x3dfa), 0xcd }, 2245 { CCI_REG8(0x3dfb), 0xcd }, { CCI_REG8(0x3dfc), 0xcd }, 2246 { CCI_REG8(0x3dfd), 0xcd }, { CCI_REG8(0x3dfe), 0xcd }, 2247 { CCI_REG8(0x3dff), 0xcd }, { CCI_REG8(0x3e00), 0xcd }, 2248 { CCI_REG8(0x3e01), 0xcd }, { CCI_REG8(0x3e02), 0xcd }, 2249 { CCI_REG8(0x3e03), 0xcd }, { CCI_REG8(0x3e04), 0xcd }, 2250 { CCI_REG8(0x3e05), 0xcd }, { CCI_REG8(0x3e06), 0xcd }, 2251 { CCI_REG8(0x3e07), 0xcd }, { CCI_REG8(0x3e08), 0xcd }, 2252 { CCI_REG8(0x3e09), 0xcd }, { CCI_REG8(0x3e0a), 0xcd }, 2253 { CCI_REG8(0x3e0b), 0xcd }, { CCI_REG8(0x3e0c), 0xcd }, 2254 { CCI_REG8(0x3e0d), 0xcd }, { CCI_REG8(0x3e0e), 0xcd }, 2255 { CCI_REG8(0x3e0f), 0xcd }, { CCI_REG8(0x3e10), 0xcd }, 2256 { CCI_REG8(0x3e11), 0xcd }, { CCI_REG8(0x3e12), 0xcd }, 2257 { CCI_REG8(0x3e13), 0xcd }, { CCI_REG8(0x3e14), 0xcd }, 2258 { CCI_REG8(0x3e15), 0xcd }, { CCI_REG8(0x3e16), 0xcd }, 2259 { CCI_REG8(0x3e17), 0xcd }, { CCI_REG8(0x3e18), 0xcd }, 2260 { CCI_REG8(0x3e19), 0xcd }, { CCI_REG8(0x3e1a), 0xcd }, 2261 { CCI_REG8(0x3e1b), 0xcd }, { CCI_REG8(0x3e1c), 0xcd }, 2262 { CCI_REG8(0x3e1d), 0xcd }, { CCI_REG8(0x3e1e), 0xcd }, 2263 { CCI_REG8(0x3e1f), 0xcd }, { CCI_REG8(0x3e20), 0xcd }, 2264 { CCI_REG8(0x3e21), 0xcd }, { CCI_REG8(0x3e22), 0xcd }, 2265 { CCI_REG8(0x3e23), 0xcd }, { CCI_REG8(0x3e24), 0xcd }, 2266 { CCI_REG8(0x3e25), 0xcd }, { CCI_REG8(0x3e26), 0xcd }, 2267 { CCI_REG8(0x3e27), 0xcd }, { CCI_REG8(0x3e28), 0xcd }, 2268 { CCI_REG8(0x3e29), 0xcd }, { CCI_REG8(0x3e2a), 0xcd }, 2269 { CCI_REG8(0x3e2b), 0xcd }, { CCI_REG8(0x3e2c), 0xcd }, 2270 { CCI_REG8(0x3e2d), 0xcd }, { CCI_REG8(0x3e2e), 0xcd }, 2271 { CCI_REG8(0x3e2f), 0xcd }, { CCI_REG8(0x3e30), 0xcd }, 2272 { CCI_REG8(0x3e31), 0xcd }, { CCI_REG8(0x3e32), 0xcd }, 2273 { CCI_REG8(0x3e33), 0xcd }, { CCI_REG8(0x3e34), 0xcd }, 2274 { CCI_REG8(0x3e35), 0xcd }, { CCI_REG8(0x3e36), 0xcd }, 2275 { CCI_REG8(0x3e37), 0xcd }, { CCI_REG8(0x3e38), 0xcd }, 2276 { CCI_REG8(0x3e39), 0xcd }, { CCI_REG8(0x3e3a), 0xcd }, 2277 { CCI_REG8(0x3e3b), 0xcd }, { CCI_REG8(0x3e3c), 0xcd }, 2278 { CCI_REG8(0x3e3d), 0xcd }, { CCI_REG8(0x3e3e), 0xcd }, 2279 { CCI_REG8(0x3e3f), 0xcd }, { CCI_REG8(0x3e40), 0xcd }, 2280 { CCI_REG8(0x3e41), 0xcd }, { CCI_REG8(0x3e42), 0xcd }, 2281 { CCI_REG8(0x3e43), 0xcd }, { CCI_REG8(0x3e44), 0xcd }, 2282 { CCI_REG8(0x3e45), 0xcd }, { CCI_REG8(0x3e46), 0xcd }, 2283 { CCI_REG8(0x3e47), 0xcd }, { CCI_REG8(0x3e48), 0xcd }, 2284 { CCI_REG8(0x3e49), 0xcd }, { CCI_REG8(0x3e4a), 0xcd }, 2285 { CCI_REG8(0x3e4b), 0xcd }, { CCI_REG8(0x3e4c), 0xcd }, 2286 { CCI_REG8(0x3e4d), 0xcd }, { CCI_REG8(0x3e4e), 0xcd }, 2287 { CCI_REG8(0x3e4f), 0xcd }, { CCI_REG8(0x3e50), 0xcd }, 2288 { CCI_REG8(0x3e51), 0xcd }, { CCI_REG8(0x3e52), 0xcd }, 2289 { CCI_REG8(0x3e53), 0xcd }, { CCI_REG8(0x3e54), 0xcd }, 2290 { CCI_REG8(0x3e55), 0xcd }, { CCI_REG8(0x3e56), 0xcd }, 2291 { CCI_REG8(0x3e57), 0xcd }, { CCI_REG8(0x3e58), 0xcd }, 2292 { CCI_REG8(0x3e59), 0xcd }, { CCI_REG8(0x3e5a), 0xcd }, 2293 { CCI_REG8(0x3e5b), 0xcd }, { CCI_REG8(0x3e5c), 0xcd }, 2294 { CCI_REG8(0x3e5d), 0xcd }, { CCI_REG8(0x3e5e), 0xcd }, 2295 { CCI_REG8(0x3e5f), 0xcd }, { CCI_REG8(0x3e60), 0xcd }, 2296 { CCI_REG8(0x3e61), 0xcd }, { CCI_REG8(0x3e62), 0xcd }, 2297 { CCI_REG8(0x3e63), 0xcd }, { CCI_REG8(0x3e64), 0xcd }, 2298 { CCI_REG8(0x3e65), 0xcd }, { CCI_REG8(0x3e66), 0xcd }, 2299 { CCI_REG8(0x3e67), 0xcd }, { CCI_REG8(0x3e68), 0xcd }, 2300 { CCI_REG8(0x3e69), 0xcd }, { CCI_REG8(0x3e6a), 0xcd }, 2301 { CCI_REG8(0x3e6b), 0xcd }, { CCI_REG8(0x3e6c), 0xcd }, 2302 { CCI_REG8(0x3e6d), 0xcd }, { CCI_REG8(0x3e6e), 0xcd }, 2303 { CCI_REG8(0x3e6f), 0xcd }, { CCI_REG8(0x3e70), 0xcd }, 2304 { CCI_REG8(0x3e71), 0xcd }, { CCI_REG8(0x3e72), 0xcd }, 2305 { CCI_REG8(0x3e73), 0xcd }, { CCI_REG8(0x3e74), 0xcd }, 2306 { CCI_REG8(0x3e75), 0xcd }, { CCI_REG8(0x3e76), 0xcd }, 2307 { CCI_REG8(0x3e77), 0xcd }, { CCI_REG8(0x3e78), 0xcd }, 2308 { CCI_REG8(0x3e79), 0xcd }, { CCI_REG8(0x3e7a), 0xcd }, 2309 { CCI_REG8(0x3e7b), 0xcd }, { CCI_REG8(0x3e7c), 0xcd }, 2310 { CCI_REG8(0x3e7d), 0xcd }, { CCI_REG8(0x3e7e), 0xcd }, 2311 { CCI_REG8(0x3e7f), 0xcd }, { CCI_REG8(0x3e80), 0xcd }, 2312 { CCI_REG8(0x3e81), 0xcd }, { CCI_REG8(0x3e82), 0xcd }, 2313 { CCI_REG8(0x3e83), 0xcd }, { CCI_REG8(0x3e84), 0xcd }, 2314 { CCI_REG8(0x3e85), 0xcd }, { CCI_REG8(0x3e86), 0xcd }, 2315 { CCI_REG8(0x3e87), 0xcd }, { CCI_REG8(0x3e88), 0xcd }, 2316 { CCI_REG8(0x3e89), 0xcd }, { CCI_REG8(0x3e8a), 0xcd }, 2317 { CCI_REG8(0x3e8b), 0xcd }, { CCI_REG8(0x3e8c), 0xcd }, 2318 { CCI_REG8(0x3e8d), 0xcd }, { CCI_REG8(0x3e8e), 0xcd }, 2319 { CCI_REG8(0x3e8f), 0xcd }, { CCI_REG8(0x3e90), 0xcd }, 2320 { CCI_REG8(0x3e91), 0xcd }, { CCI_REG8(0x3e92), 0xcd }, 2321 { CCI_REG8(0x3e93), 0xcd }, { CCI_REG8(0x3e94), 0xcd }, 2322 { CCI_REG8(0x3e95), 0xcd }, { CCI_REG8(0x3e96), 0xcd }, 2323 { CCI_REG8(0x3e97), 0xcd }, { CCI_REG8(0x3e98), 0xcd }, 2324 { CCI_REG8(0x3e99), 0xcd }, { CCI_REG8(0x3e9a), 0xcd }, 2325 { CCI_REG8(0x3e9b), 0xcd }, { CCI_REG8(0x3e9c), 0xcd }, 2326 { CCI_REG8(0x3e9d), 0xcd }, { CCI_REG8(0x3e9e), 0xcd }, 2327 { CCI_REG8(0x3e9f), 0xcd }, { CCI_REG8(0xfff9), 0x06 }, 2328 { CCI_REG8(0xc03f), 0x01 }, { CCI_REG8(0xc03e), 0x08 }, 2329 { CCI_REG8(0xc02c), 0xff }, { CCI_REG8(0xc005), 0x06 }, 2330 { CCI_REG8(0xc006), 0x30 }, { CCI_REG8(0xc007), 0xc0 }, 2331 { CCI_REG8(0xc027), 0x01 }, { CCI_REG8(0x30c0), 0x05 }, 2332 { CCI_REG8(0x30c1), 0x9f }, { CCI_REG8(0x30c2), 0x06 }, 2333 { CCI_REG8(0x30c3), 0x5f }, { CCI_REG8(0x30c4), 0x80 }, 2334 { CCI_REG8(0x30c5), 0x08 }, { CCI_REG8(0x30c6), 0x39 }, 2335 { CCI_REG8(0x30c7), 0x00 }, { CCI_REG8(0xc046), 0x20 }, 2336 { CCI_REG8(0xc043), 0x01 }, { CCI_REG8(0xc04b), 0x01 }, 2337 { CCI_REG8(0x0102), 0x01 }, { CCI_REG8(0x0100), 0x00 }, 2338 { CCI_REG8(0x0102), 0x00 }, { CCI_REG8(0x3015), 0xf0 }, 2339 { CCI_REG8(0x3018), 0xf0 }, { CCI_REG8(0x301c), 0xf0 }, 2340 { CCI_REG8(0x301d), 0xf6 }, { CCI_REG8(0x301e), 0xf1 } 2341 }; 2342 2343 static const struct cci_reg_sequence ov64a40_9248x6944[] = { 2344 { CCI_REG8(0x0305), 0x98 }, { CCI_REG8(0x0306), 0x04 }, 2345 { CCI_REG8(0x0307), 0x01 }, { CCI_REG8(0x4837), 0x1a }, 2346 { CCI_REG8(0x4888), 0x10 }, { CCI_REG8(0x4860), 0x00 }, 2347 { CCI_REG8(0x4850), 0x43 }, { CCI_REG8(0x480C), 0x92 }, 2348 { CCI_REG8(0x5001), 0x21 } 2349 }; 2350 2351 static const struct cci_reg_sequence ov64a40_8000x6000[] = { 2352 { CCI_REG8(0x0305), 0x98 }, { CCI_REG8(0x0306), 0x04 }, 2353 { CCI_REG8(0x0307), 0x01 }, { CCI_REG8(0x4837), 0x1a }, 2354 { CCI_REG8(0x4888), 0x10 }, { CCI_REG8(0x4860), 0x00 }, 2355 { CCI_REG8(0x4850), 0x43 }, { CCI_REG8(0x480C), 0x92 }, 2356 { CCI_REG8(0x5001), 0x21 } 2357 }; 2358 2359 static const struct cci_reg_sequence ov64a40_4624_3472[] = { 2360 { CCI_REG8(0x034b), 0x02 }, { CCI_REG8(0x3504), 0x08 }, 2361 { CCI_REG8(0x360d), 0x82 }, { CCI_REG8(0x368a), 0x2e }, 2362 { CCI_REG8(0x3712), 0x50 }, { CCI_REG8(0x3822), 0x00 }, 2363 { CCI_REG8(0x3827), 0x40 }, { CCI_REG8(0x383d), 0x08 }, 2364 { CCI_REG8(0x383f), 0x00 }, { CCI_REG8(0x384c), 0x02 }, 2365 { CCI_REG8(0x384d), 0xba }, { CCI_REG8(0x3852), 0x00 }, 2366 { CCI_REG8(0x3856), 0x08 }, { CCI_REG8(0x3857), 0x08 }, 2367 { CCI_REG8(0x3858), 0x10 }, { CCI_REG8(0x3859), 0x10 }, 2368 { CCI_REG8(0x4016), 0x0f }, { CCI_REG8(0x4018), 0x03 }, 2369 { CCI_REG8(0x4504), 0x1e }, { CCI_REG8(0x4523), 0x41 }, 2370 { CCI_REG8(0x45c0), 0x01 }, { CCI_REG8(0x4641), 0x12 }, 2371 { CCI_REG8(0x4643), 0x0c }, { CCI_REG8(0x4915), 0x02 }, 2372 { CCI_REG8(0x4916), 0x1d }, { CCI_REG8(0x4a15), 0x02 }, 2373 { CCI_REG8(0x4a16), 0x1d }, { CCI_REG8(0x3703), 0x72 }, 2374 { CCI_REG8(0x3709), 0xe6 }, { CCI_REG8(0x3a60), 0x68 }, 2375 { CCI_REG8(0x3a6f), 0x68 }, { CCI_REG8(0x3a5e), 0xdc }, 2376 { CCI_REG8(0x3a6d), 0xdc }, { CCI_REG8(0x3721), 0xc9 }, 2377 { CCI_REG8(0x5250), 0x06 }, { CCI_REG8(0x527a), 0x00 }, 2378 { CCI_REG8(0x527b), 0x65 }, { CCI_REG8(0x527c), 0x00 }, 2379 { CCI_REG8(0x527d), 0x82 }, { CCI_REG8(0x5280), 0x24 }, 2380 { CCI_REG8(0x5281), 0x40 }, { CCI_REG8(0x5282), 0x1b }, 2381 { CCI_REG8(0x5283), 0x40 }, { CCI_REG8(0x5284), 0x24 }, 2382 { CCI_REG8(0x5285), 0x40 }, { CCI_REG8(0x5286), 0x1b }, 2383 { CCI_REG8(0x5287), 0x40 }, { CCI_REG8(0x5200), 0x24 }, 2384 { CCI_REG8(0x5201), 0x40 }, { CCI_REG8(0x5202), 0x1b }, 2385 { CCI_REG8(0x5203), 0x40 }, { CCI_REG8(0x481b), 0x35 }, 2386 { CCI_REG8(0x4862), 0x25 }, { CCI_REG8(0x3400), 0x00 }, 2387 { CCI_REG8(0x3421), 0x23 }, { CCI_REG8(0x3422), 0xfc }, 2388 { CCI_REG8(0x3423), 0x07 }, { CCI_REG8(0x3424), 0x01 }, 2389 { CCI_REG8(0x3425), 0x04 }, { CCI_REG8(0x3426), 0x50 }, 2390 { CCI_REG8(0x3427), 0x55 }, { CCI_REG8(0x3428), 0x15 }, 2391 { CCI_REG8(0x3429), 0x00 }, { CCI_REG8(0x3025), 0x03 }, 2392 { CCI_REG8(0x5250), 0x06 }, { CCI_REG8(0x0305), 0x98 }, 2393 { CCI_REG8(0x0306), 0x04 }, { CCI_REG8(0x0307), 0x01 }, 2394 { CCI_REG8(0x4837), 0x1a }, { CCI_REG8(0x4888), 0x10 }, 2395 { CCI_REG8(0x4860), 0x00 }, { CCI_REG8(0x4850), 0x43 }, 2396 { CCI_REG8(0x480C), 0x92 }, { CCI_REG8(0x5001), 0x21 } 2397 }; 2398 2399 static const struct cci_reg_sequence ov64a40_3840x2160[] = { 2400 { CCI_REG8(0x034a), 0x05 }, { CCI_REG8(0x034b), 0x05 }, 2401 { CCI_REG8(0x3504), 0x08 }, { CCI_REG8(0x360d), 0x82 }, 2402 { CCI_REG8(0x368a), 0x2e }, { CCI_REG8(0x3712), 0x50 }, 2403 { CCI_REG8(0x3822), 0x00 }, { CCI_REG8(0x3827), 0x40 }, 2404 { CCI_REG8(0x383d), 0x08 }, { CCI_REG8(0x383f), 0x00 }, 2405 { CCI_REG8(0x384c), 0x02 }, { CCI_REG8(0x384d), 0xba }, 2406 { CCI_REG8(0x3852), 0x00 }, { CCI_REG8(0x3856), 0x08 }, 2407 { CCI_REG8(0x3857), 0x08 }, { CCI_REG8(0x3858), 0x10 }, 2408 { CCI_REG8(0x3859), 0x10 }, { CCI_REG8(0x4016), 0x0f }, 2409 { CCI_REG8(0x4018), 0x03 }, { CCI_REG8(0x4504), 0x1e }, 2410 { CCI_REG8(0x4523), 0x41 }, { CCI_REG8(0x45c0), 0x01 }, 2411 { CCI_REG8(0x4641), 0x12 }, { CCI_REG8(0x4643), 0x0c }, 2412 { CCI_REG8(0x4915), 0x02 }, { CCI_REG8(0x4916), 0x1d }, 2413 { CCI_REG8(0x4a15), 0x02 }, { CCI_REG8(0x4a16), 0x1d }, 2414 { CCI_REG8(0x3703), 0x72 }, { CCI_REG8(0x3709), 0xe6 }, 2415 { CCI_REG8(0x3a60), 0x68 }, { CCI_REG8(0x3a6f), 0x68 }, 2416 { CCI_REG8(0x3a5e), 0xdc }, { CCI_REG8(0x3a6d), 0xdc }, 2417 { CCI_REG8(0x3721), 0xc9 }, { CCI_REG8(0x5250), 0x06 }, 2418 { CCI_REG8(0x527a), 0x00 }, { CCI_REG8(0x527b), 0x65 }, 2419 { CCI_REG8(0x527c), 0x00 }, { CCI_REG8(0x527d), 0x82 }, 2420 { CCI_REG8(0x5280), 0x24 }, { CCI_REG8(0x5281), 0x40 }, 2421 { CCI_REG8(0x5282), 0x1b }, { CCI_REG8(0x5283), 0x40 }, 2422 { CCI_REG8(0x5284), 0x24 }, { CCI_REG8(0x5285), 0x40 }, 2423 { CCI_REG8(0x5286), 0x1b }, { CCI_REG8(0x5287), 0x40 }, 2424 { CCI_REG8(0x5200), 0x24 }, { CCI_REG8(0x5201), 0x40 }, 2425 { CCI_REG8(0x5202), 0x1b }, { CCI_REG8(0x5203), 0x40 }, 2426 { CCI_REG8(0x481b), 0x35 }, { CCI_REG8(0x4862), 0x25 }, 2427 { CCI_REG8(0x3400), 0x00 }, { CCI_REG8(0x3421), 0x23 }, 2428 { CCI_REG8(0x3422), 0xfc }, { CCI_REG8(0x3423), 0x07 }, 2429 { CCI_REG8(0x3424), 0x01 }, { CCI_REG8(0x3425), 0x04 }, 2430 { CCI_REG8(0x3426), 0x50 }, { CCI_REG8(0x3427), 0x55 }, 2431 { CCI_REG8(0x3428), 0x15 }, { CCI_REG8(0x3429), 0x00 }, 2432 { CCI_REG8(0x3025), 0x03 }, { CCI_REG8(0x5250), 0x06 }, 2433 { CCI_REG8(0x0305), 0x98 }, { CCI_REG8(0x0306), 0x04 }, 2434 { CCI_REG8(0x0345), 0x90 }, { CCI_REG8(0x0307), 0x01 }, 2435 { CCI_REG8(0x4837), 0x1a }, { CCI_REG8(0x4888), 0x10 }, 2436 { CCI_REG8(0x4860), 0x00 }, { CCI_REG8(0x4850), 0x43 }, 2437 { CCI_REG8(0x480C), 0x92 }, { CCI_REG8(0x5001), 0x21 }, 2438 { CCI_REG8(0x5000), 0x01 } 2439 }; 2440 2441 static const struct cci_reg_sequence ov64a40_2312_1736[] = { 2442 { CCI_REG8(0x034b), 0x02 }, { CCI_REG8(0x3504), 0x08 }, 2443 { CCI_REG8(0x360d), 0x82 }, { CCI_REG8(0x368a), 0x2e }, 2444 { CCI_REG8(0x3712), 0x00 }, { CCI_REG8(0x3822), 0x08 }, 2445 { CCI_REG8(0x3827), 0x40 }, { CCI_REG8(0x383d), 0x04 }, 2446 { CCI_REG8(0x383f), 0x00 }, { CCI_REG8(0x384c), 0x01 }, 2447 { CCI_REG8(0x384d), 0x12 }, { CCI_REG8(0x3852), 0x00 }, 2448 { CCI_REG8(0x3856), 0x04 }, { CCI_REG8(0x3857), 0x04 }, 2449 { CCI_REG8(0x3858), 0x08 }, { CCI_REG8(0x3859), 0x08 }, 2450 { CCI_REG8(0x4016), 0x07 }, { CCI_REG8(0x4018), 0x01 }, 2451 { CCI_REG8(0x4504), 0x00 }, { CCI_REG8(0x4523), 0x00 }, 2452 { CCI_REG8(0x45c0), 0x01 }, { CCI_REG8(0x4641), 0x24 }, 2453 { CCI_REG8(0x4643), 0x0c }, { CCI_REG8(0x4837), 0x0b }, 2454 { CCI_REG8(0x4915), 0x02 }, { CCI_REG8(0x4916), 0x1d }, 2455 { CCI_REG8(0x4a15), 0x02 }, { CCI_REG8(0x4a16), 0x1d }, 2456 { CCI_REG8(0x5000), 0x55 }, { CCI_REG8(0x5001), 0x00 }, 2457 { CCI_REG8(0x5002), 0x35 }, { CCI_REG8(0x5004), 0xc0 }, 2458 { CCI_REG8(0x5068), 0x02 }, { CCI_REG8(0x3703), 0x6a }, 2459 { CCI_REG8(0x3709), 0xa3 }, { CCI_REG8(0x3a60), 0x60 }, 2460 { CCI_REG8(0x3a6f), 0x60 }, { CCI_REG8(0x3a5e), 0x99 }, 2461 { CCI_REG8(0x3a6d), 0x99 }, { CCI_REG8(0x3721), 0xc1 }, 2462 { CCI_REG8(0x5250), 0x06 }, { CCI_REG8(0x527a), 0x00 }, 2463 { CCI_REG8(0x527b), 0x65 }, { CCI_REG8(0x527c), 0x00 }, 2464 { CCI_REG8(0x527d), 0x82 }, { CCI_REG8(0x5280), 0x24 }, 2465 { CCI_REG8(0x5281), 0x40 }, { CCI_REG8(0x5282), 0x1b }, 2466 { CCI_REG8(0x5283), 0x40 }, { CCI_REG8(0x5284), 0x24 }, 2467 { CCI_REG8(0x5285), 0x40 }, { CCI_REG8(0x5286), 0x1b }, 2468 { CCI_REG8(0x5287), 0x40 }, { CCI_REG8(0x5200), 0x24 }, 2469 { CCI_REG8(0x5201), 0x40 }, { CCI_REG8(0x5202), 0x1b }, 2470 { CCI_REG8(0x5203), 0x40 }, { CCI_REG8(0x3684), 0x05 }, 2471 { CCI_REG8(0x481b), 0x20 }, { CCI_REG8(0x51b0), 0x38 }, 2472 { CCI_REG8(0x51b3), 0x0e }, { CCI_REG8(0x51b5), 0x04 }, 2473 { CCI_REG8(0x51b6), 0x00 }, { CCI_REG8(0x51b7), 0x00 }, 2474 { CCI_REG8(0x51b9), 0x70 }, { CCI_REG8(0x51bb), 0x10 }, 2475 { CCI_REG8(0x51bc), 0x00 }, { CCI_REG8(0x51bd), 0x00 }, 2476 { CCI_REG8(0x51b0), 0x38 }, { CCI_REG8(0x54b0), 0x38 }, 2477 { CCI_REG8(0x54b3), 0x0e }, { CCI_REG8(0x54b5), 0x04 }, 2478 { CCI_REG8(0x54b6), 0x00 }, { CCI_REG8(0x54b7), 0x00 }, 2479 { CCI_REG8(0x54b9), 0x70 }, { CCI_REG8(0x54bb), 0x10 }, 2480 { CCI_REG8(0x54bc), 0x00 }, { CCI_REG8(0x54bd), 0x00 }, 2481 { CCI_REG8(0x57b0), 0x38 }, { CCI_REG8(0x57b3), 0x0e }, 2482 { CCI_REG8(0x57b5), 0x04 }, { CCI_REG8(0x57b6), 0x00 }, 2483 { CCI_REG8(0x57b7), 0x00 }, { CCI_REG8(0x57b9), 0x70 }, 2484 { CCI_REG8(0x57bb), 0x10 }, { CCI_REG8(0x57bc), 0x00 }, 2485 { CCI_REG8(0x57bd), 0x00 }, { CCI_REG8(0x0305), 0x98 }, 2486 { CCI_REG8(0x0306), 0x04 }, { CCI_REG8(0x0307), 0x01 }, 2487 { CCI_REG8(0x4837), 0x1a }, { CCI_REG8(0x4888), 0x10 }, 2488 { CCI_REG8(0x4860), 0x00 }, { CCI_REG8(0x4850), 0x43 }, 2489 { CCI_REG8(0x480C), 0x92 } 2490 }; 2491 2492 static const struct cci_reg_sequence ov64a40_1920x1080[] = { 2493 { CCI_REG8(0x034b), 0x02 }, { CCI_REG8(0x3504), 0x08 }, 2494 { CCI_REG8(0x360d), 0x82 }, { CCI_REG8(0x368a), 0x2e }, 2495 { CCI_REG8(0x3712), 0x00 }, { CCI_REG8(0x3822), 0x08 }, 2496 { CCI_REG8(0x3827), 0x40 }, { CCI_REG8(0x383d), 0x04 }, 2497 { CCI_REG8(0x383f), 0x00 }, { CCI_REG8(0x384c), 0x01 }, 2498 { CCI_REG8(0x384d), 0x12 }, { CCI_REG8(0x3852), 0x00 }, 2499 { CCI_REG8(0x3856), 0x04 }, { CCI_REG8(0x3857), 0x04 }, 2500 { CCI_REG8(0x3858), 0x08 }, { CCI_REG8(0x3859), 0x08 }, 2501 { CCI_REG8(0x4016), 0x07 }, { CCI_REG8(0x4018), 0x01 }, 2502 { CCI_REG8(0x4504), 0x00 }, { CCI_REG8(0x4523), 0x00 }, 2503 { CCI_REG8(0x45c0), 0x01 }, { CCI_REG8(0x4641), 0x24 }, 2504 { CCI_REG8(0x4643), 0x0c }, { CCI_REG8(0x4837), 0x0b }, 2505 { CCI_REG8(0x4915), 0x02 }, { CCI_REG8(0x4916), 0x1d }, 2506 { CCI_REG8(0x4a15), 0x02 }, { CCI_REG8(0x4a16), 0x1d }, 2507 { CCI_REG8(0x5000), 0x55 }, { CCI_REG8(0x5001), 0x00 }, 2508 { CCI_REG8(0x5002), 0x35 }, { CCI_REG8(0x5004), 0xc0 }, 2509 { CCI_REG8(0x5068), 0x02 }, { CCI_REG8(0x3703), 0x6a }, 2510 { CCI_REG8(0x3709), 0xa3 }, { CCI_REG8(0x3a60), 0x60 }, 2511 { CCI_REG8(0x3a6f), 0x60 }, { CCI_REG8(0x3a5e), 0x99 }, 2512 { CCI_REG8(0x3a6d), 0x99 }, { CCI_REG8(0x3721), 0xc1 }, 2513 { CCI_REG8(0x5250), 0x06 }, { CCI_REG8(0x527a), 0x00 }, 2514 { CCI_REG8(0x527b), 0x65 }, { CCI_REG8(0x527c), 0x00 }, 2515 { CCI_REG8(0x527d), 0x82 }, { CCI_REG8(0x5280), 0x24 }, 2516 { CCI_REG8(0x5281), 0x40 }, { CCI_REG8(0x5282), 0x1b }, 2517 { CCI_REG8(0x5283), 0x40 }, { CCI_REG8(0x5284), 0x24 }, 2518 { CCI_REG8(0x5285), 0x40 }, { CCI_REG8(0x5286), 0x1b }, 2519 { CCI_REG8(0x5287), 0x40 }, { CCI_REG8(0x5200), 0x24 }, 2520 { CCI_REG8(0x5201), 0x40 }, { CCI_REG8(0x5202), 0x1b }, 2521 { CCI_REG8(0x5203), 0x40 }, { CCI_REG8(0x3684), 0x05 }, 2522 { CCI_REG8(0x481b), 0x20 }, { CCI_REG8(0x51b0), 0x38 }, 2523 { CCI_REG8(0x51b3), 0x0e }, { CCI_REG8(0x51b5), 0x04 }, 2524 { CCI_REG8(0x51b6), 0x00 }, { CCI_REG8(0x51b7), 0x00 }, 2525 { CCI_REG8(0x51b9), 0x70 }, { CCI_REG8(0x51bb), 0x10 }, 2526 { CCI_REG8(0x51bc), 0x00 }, { CCI_REG8(0x51bd), 0x00 }, 2527 { CCI_REG8(0x51b0), 0x38 }, { CCI_REG8(0x54b0), 0x38 }, 2528 { CCI_REG8(0x54b3), 0x0e }, { CCI_REG8(0x54b5), 0x04 }, 2529 { CCI_REG8(0x54b6), 0x00 }, { CCI_REG8(0x54b7), 0x00 }, 2530 { CCI_REG8(0x54b9), 0x70 }, { CCI_REG8(0x54bb), 0x10 }, 2531 { CCI_REG8(0x54bc), 0x00 }, { CCI_REG8(0x54bd), 0x00 }, 2532 { CCI_REG8(0x57b0), 0x38 }, { CCI_REG8(0x57b3), 0x0e }, 2533 { CCI_REG8(0x57b5), 0x04 }, { CCI_REG8(0x57b6), 0x00 }, 2534 { CCI_REG8(0x57b7), 0x00 }, { CCI_REG8(0x57b9), 0x70 }, 2535 { CCI_REG8(0x57bb), 0x10 }, { CCI_REG8(0x57bc), 0x00 }, 2536 { CCI_REG8(0x57bd), 0x00 }, { CCI_REG8(0x0305), 0x98 }, 2537 { CCI_REG8(0x0306), 0x04 }, { CCI_REG8(0x0307), 0x01 }, 2538 { CCI_REG8(0x4837), 0x1a }, { CCI_REG8(0x4888), 0x10 }, 2539 { CCI_REG8(0x4860), 0x00 }, { CCI_REG8(0x4850), 0x43 }, 2540 { CCI_REG8(0x480C), 0x92 } 2541 }; 2542 2543 /* 456MHz MIPI link frequency with 24MHz input clock. */ 2544 static const struct cci_reg_sequence ov64a40_pll_config[] = { 2545 { OV64A40_PLL1_PRE_DIV0, 0x88 }, 2546 { OV64A40_PLL1_PRE_DIV, 0x02 }, 2547 { OV64A40_PLL1_MULTIPLIER, 0x0098 }, 2548 { OV64A40_PLL1_M_DIV, 0x01 }, 2549 { OV64A40_PLL2_SEL_BAK_SA1, 0x00 }, 2550 { OV64A40_PLL2_PRE_DIV, 0x12 }, 2551 { OV64A40_PLL2_MULTIPLIER, 0x0190 }, 2552 { OV64A40_PLL2_PRE_DIV0, 0xd7 }, 2553 { OV64A40_PLL2_DIVSP, 0x00 }, 2554 { OV64A40_PLL2_DIVDAC, 0x00 }, 2555 { OV64A40_PLL2_DACPREDIV, 0x00 } 2556 }; 2557 2558 struct ov64a40_reglist { 2559 unsigned int num_regs; 2560 const struct cci_reg_sequence *regvals; 2561 }; 2562 2563 struct ov64a40_subsampling { 2564 unsigned int x_odd_inc; 2565 unsigned int x_even_inc; 2566 unsigned int y_odd_inc; 2567 unsigned int y_even_inc; 2568 bool vbin; 2569 bool hbin; 2570 }; 2571 2572 static struct ov64a40_mode { 2573 unsigned int width; 2574 unsigned int height; 2575 struct ov64a40_timings { 2576 unsigned int vts; 2577 unsigned int ppl; 2578 } timings_default[OV64A40_NUM_LINK_FREQ]; 2579 const struct ov64a40_reglist reglist; 2580 struct v4l2_rect analogue_crop; 2581 struct v4l2_rect digital_crop; 2582 struct ov64a40_subsampling subsampling; 2583 } ov64a40_modes[] = { 2584 /* Full resolution */ 2585 { 2586 .width = 9248, 2587 .height = 6944, 2588 .timings_default = { 2589 /* 2.6 FPS */ 2590 [OV64A40_LINK_FREQ_456M_ID] = { 2591 .vts = 7072, 2592 .ppl = 4072, 2593 }, 2594 /* 2 FPS */ 2595 [OV64A40_LINK_FREQ_360M_ID] = { 2596 .vts = 7072, 2597 .ppl = 5248, 2598 }, 2599 }, 2600 .reglist = { 2601 .num_regs = ARRAY_SIZE(ov64a40_9248x6944), 2602 .regvals = ov64a40_9248x6944, 2603 }, 2604 .analogue_crop = { 2605 .left = 0, 2606 .top = 0, 2607 .width = 9280, 2608 .height = 6976, 2609 }, 2610 .digital_crop = { 2611 .left = 17, 2612 .top = 16, 2613 .width = 9248, 2614 .height = 6944, 2615 }, 2616 .subsampling = { 2617 .x_odd_inc = 1, 2618 .x_even_inc = 1, 2619 .y_odd_inc = 1, 2620 .y_even_inc = 1, 2621 .vbin = false, 2622 .hbin = false, 2623 }, 2624 }, 2625 /* Analogue crop + digital crop */ 2626 { 2627 .width = 8000, 2628 .height = 6000, 2629 .timings_default = { 2630 /* 3.0 FPS */ 2631 [OV64A40_LINK_FREQ_456M_ID] = { 2632 .vts = 6400, 2633 .ppl = 3848, 2634 }, 2635 /* 2.5 FPS */ 2636 [OV64A40_LINK_FREQ_360M_ID] = { 2637 .vts = 6304, 2638 .ppl = 4736, 2639 }, 2640 }, 2641 .reglist = { 2642 .num_regs = ARRAY_SIZE(ov64a40_8000x6000), 2643 .regvals = ov64a40_8000x6000, 2644 }, 2645 .analogue_crop = { 2646 .left = 624, 2647 .top = 472, 2648 .width = 8048, 2649 .height = 6032, 2650 }, 2651 .digital_crop = { 2652 .left = 17, 2653 .top = 16, 2654 .width = 8000, 2655 .height = 6000, 2656 }, 2657 .subsampling = { 2658 .x_odd_inc = 1, 2659 .x_even_inc = 1, 2660 .y_odd_inc = 1, 2661 .y_even_inc = 1, 2662 .vbin = false, 2663 .hbin = false, 2664 }, 2665 }, 2666 /* 2x2 downscaled */ 2667 { 2668 .width = 4624, 2669 .height = 3472, 2670 .timings_default = { 2671 /* 10 FPS */ 2672 [OV64A40_LINK_FREQ_456M_ID] = { 2673 .vts = 3533, 2674 .ppl = 2112, 2675 }, 2676 /* 7 FPS */ 2677 [OV64A40_LINK_FREQ_360M_ID] = { 2678 .vts = 3939, 2679 .ppl = 2720, 2680 }, 2681 }, 2682 .reglist = { 2683 .num_regs = ARRAY_SIZE(ov64a40_4624_3472), 2684 .regvals = ov64a40_4624_3472, 2685 }, 2686 .analogue_crop = { 2687 .left = 0, 2688 .top = 0, 2689 .width = 9280, 2690 .height = 6976, 2691 }, 2692 .digital_crop = { 2693 .left = 9, 2694 .top = 8, 2695 .width = 4624, 2696 .height = 3472, 2697 }, 2698 .subsampling = { 2699 .x_odd_inc = 3, 2700 .x_even_inc = 1, 2701 .y_odd_inc = 1, 2702 .y_even_inc = 1, 2703 .vbin = true, 2704 .hbin = false, 2705 }, 2706 }, 2707 /* Analogue crop + 2x2 downscale + digital crop */ 2708 { 2709 .width = 3840, 2710 .height = 2160, 2711 .timings_default = { 2712 /* 20 FPS */ 2713 [OV64A40_LINK_FREQ_456M_ID] = { 2714 .vts = 2218, 2715 .ppl = 1690, 2716 }, 2717 /* 15 FPS */ 2718 [OV64A40_LINK_FREQ_360M_ID] = { 2719 .vts = 2270, 2720 .ppl = 2202, 2721 }, 2722 }, 2723 .reglist = { 2724 .num_regs = ARRAY_SIZE(ov64a40_3840x2160), 2725 .regvals = ov64a40_3840x2160, 2726 }, 2727 .analogue_crop = { 2728 .left = 784, 2729 .top = 1312, 2730 .width = 7712, 2731 .height = 4352, 2732 }, 2733 .digital_crop = { 2734 .left = 9, 2735 .top = 8, 2736 .width = 3840, 2737 .height = 2160, 2738 }, 2739 .subsampling = { 2740 .x_odd_inc = 3, 2741 .x_even_inc = 1, 2742 .y_odd_inc = 1, 2743 .y_even_inc = 1, 2744 .vbin = true, 2745 .hbin = false, 2746 }, 2747 }, 2748 /* 4x4 downscaled */ 2749 { 2750 .width = 2312, 2751 .height = 1736, 2752 .timings_default = { 2753 /* 30 FPS */ 2754 [OV64A40_LINK_FREQ_456M_ID] = { 2755 .vts = 1998, 2756 .ppl = 1248, 2757 }, 2758 /* 25 FPS */ 2759 [OV64A40_LINK_FREQ_360M_ID] = { 2760 .vts = 1994, 2761 .ppl = 1504, 2762 }, 2763 }, 2764 .reglist = { 2765 .num_regs = ARRAY_SIZE(ov64a40_2312_1736), 2766 .regvals = ov64a40_2312_1736, 2767 }, 2768 .analogue_crop = { 2769 .left = 0, 2770 .top = 0, 2771 .width = 9280, 2772 .height = 6976, 2773 }, 2774 .digital_crop = { 2775 .left = 5, 2776 .top = 4, 2777 .width = 2312, 2778 .height = 1736, 2779 }, 2780 .subsampling = { 2781 .x_odd_inc = 3, 2782 .x_even_inc = 1, 2783 .y_odd_inc = 3, 2784 .y_even_inc = 1, 2785 .vbin = true, 2786 .hbin = true, 2787 }, 2788 }, 2789 /* Analogue crop + 4x4 downscale + digital crop */ 2790 { 2791 .width = 1920, 2792 .height = 1080, 2793 .timings_default = { 2794 /* 60 FPS */ 2795 [OV64A40_LINK_FREQ_456M_ID] = { 2796 .vts = 1397, 2797 .ppl = 880, 2798 }, 2799 /* 45 FPS */ 2800 [OV64A40_LINK_FREQ_360M_ID] = { 2801 .vts = 1216, 2802 .ppl = 1360, 2803 }, 2804 }, 2805 .reglist = { 2806 .num_regs = ARRAY_SIZE(ov64a40_1920x1080), 2807 .regvals = ov64a40_1920x1080, 2808 }, 2809 .analogue_crop = { 2810 .left = 784, 2811 .top = 1312, 2812 .width = 7712, 2813 .height = 4352, 2814 }, 2815 .digital_crop = { 2816 .left = 7, 2817 .top = 6, 2818 .width = 1920, 2819 .height = 1080, 2820 }, 2821 .subsampling = { 2822 .x_odd_inc = 3, 2823 .x_even_inc = 1, 2824 .y_odd_inc = 3, 2825 .y_even_inc = 1, 2826 .vbin = true, 2827 .hbin = true, 2828 }, 2829 }, 2830 }; 2831 2832 struct ov64a40 { 2833 struct device *dev; 2834 2835 struct v4l2_subdev sd; 2836 struct media_pad pad; 2837 2838 struct regmap *cci; 2839 2840 struct ov64a40_mode *mode; 2841 2842 struct clk *xclk; 2843 2844 struct gpio_desc *reset_gpio; 2845 struct regulator_bulk_data supplies[ARRAY_SIZE(ov64a40_supply_names)]; 2846 2847 s64 *link_frequencies; 2848 unsigned int num_link_frequencies; 2849 2850 struct v4l2_ctrl_handler ctrl_handler; 2851 struct v4l2_ctrl *exposure; 2852 struct v4l2_ctrl *link_freq; 2853 struct v4l2_ctrl *vblank; 2854 struct v4l2_ctrl *hblank; 2855 struct v4l2_ctrl *vflip; 2856 struct v4l2_ctrl *hflip; 2857 }; 2858 2859 static inline struct ov64a40 *sd_to_ov64a40(struct v4l2_subdev *sd) 2860 { 2861 return container_of_const(sd, struct ov64a40, sd); 2862 } 2863 2864 static const struct ov64a40_timings * 2865 ov64a40_get_timings(struct ov64a40 *ov64a40, unsigned int link_freq_index) 2866 { 2867 s64 link_freq = ov64a40->link_frequencies[link_freq_index]; 2868 unsigned int timings_index = link_freq == OV64A40_LINK_FREQ_360M 2869 ? OV64A40_LINK_FREQ_360M_ID 2870 : OV64A40_LINK_FREQ_456M_ID; 2871 2872 return &ov64a40->mode->timings_default[timings_index]; 2873 } 2874 2875 static int ov64a40_program_geometry(struct ov64a40 *ov64a40) 2876 { 2877 struct ov64a40_mode *mode = ov64a40->mode; 2878 struct v4l2_rect *anacrop = &mode->analogue_crop; 2879 struct v4l2_rect *digicrop = &mode->digital_crop; 2880 const struct ov64a40_timings *timings; 2881 int ret = 0; 2882 2883 /* Analogue crop. */ 2884 cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRL0, 2885 anacrop->left, &ret); 2886 cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRL2, 2887 anacrop->top, &ret); 2888 cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRL4, 2889 anacrop->width + anacrop->left - 1, &ret); 2890 cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRL6, 2891 anacrop->height + anacrop->top - 1, &ret); 2892 2893 /* ISP windowing. */ 2894 cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRL10, 2895 digicrop->left, &ret); 2896 cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRL12, 2897 digicrop->top, &ret); 2898 cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRL8, 2899 digicrop->width, &ret); 2900 cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRLA, 2901 digicrop->height, &ret); 2902 2903 /* Total timings. */ 2904 timings = ov64a40_get_timings(ov64a40, ov64a40->link_freq->cur.val); 2905 cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRLC, timings->ppl, &ret); 2906 cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRLE, timings->vts, &ret); 2907 2908 return ret; 2909 } 2910 2911 static int ov64a40_program_subsampling(struct ov64a40 *ov64a40) 2912 { 2913 struct ov64a40_subsampling *subsampling = &ov64a40->mode->subsampling; 2914 int ret = 0; 2915 2916 /* Skipping configuration */ 2917 cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRL14, 2918 OV64A40_SKIPPING_CONFIG(subsampling->x_odd_inc, 2919 subsampling->x_even_inc), &ret); 2920 cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRL15, 2921 OV64A40_SKIPPING_CONFIG(subsampling->y_odd_inc, 2922 subsampling->y_even_inc), &ret); 2923 2924 /* Binning configuration */ 2925 cci_update_bits(ov64a40->cci, OV64A40_REG_TIMING_CTRL_20, 2926 OV64A40_TIMING_CTRL_20_VBIN, 2927 subsampling->vbin ? OV64A40_TIMING_CTRL_20_VBIN : 0, 2928 &ret); 2929 cci_update_bits(ov64a40->cci, OV64A40_REG_TIMING_CTRL_21, 2930 OV64A40_TIMING_CTRL_21_HBIN_CONF, 2931 subsampling->hbin ? 2932 OV64A40_TIMING_CTRL_21_HBIN_CONF : 0, &ret); 2933 2934 return ret; 2935 } 2936 2937 static int ov64a40_start_streaming(struct ov64a40 *ov64a40, 2938 struct v4l2_subdev_state *state) 2939 { 2940 const struct ov64a40_reglist *reglist = &ov64a40->mode->reglist; 2941 const struct ov64a40_timings *timings; 2942 unsigned long delay; 2943 int ret; 2944 2945 ret = pm_runtime_resume_and_get(ov64a40->dev); 2946 if (ret < 0) 2947 return ret; 2948 2949 ret = cci_multi_reg_write(ov64a40->cci, ov64a40_init, 2950 ARRAY_SIZE(ov64a40_init), NULL); 2951 if (ret) 2952 goto error_power_off; 2953 2954 ret = cci_multi_reg_write(ov64a40->cci, reglist->regvals, 2955 reglist->num_regs, NULL); 2956 if (ret) 2957 goto error_power_off; 2958 2959 ret = ov64a40_program_geometry(ov64a40); 2960 if (ret) 2961 goto error_power_off; 2962 2963 ret = ov64a40_program_subsampling(ov64a40); 2964 if (ret) 2965 goto error_power_off; 2966 2967 ret = __v4l2_ctrl_handler_setup(&ov64a40->ctrl_handler); 2968 if (ret) 2969 goto error_power_off; 2970 2971 ret = cci_write(ov64a40->cci, OV64A40_REG_SMIA, 2972 OV64A40_REG_SMIA_STREAMING, NULL); 2973 if (ret) 2974 goto error_power_off; 2975 2976 /* Link frequency and flips cannot change while streaming. */ 2977 __v4l2_ctrl_grab(ov64a40->link_freq, true); 2978 __v4l2_ctrl_grab(ov64a40->vflip, true); 2979 __v4l2_ctrl_grab(ov64a40->hflip, true); 2980 2981 /* delay: max(4096 xclk pulses, 150usec) + exposure time */ 2982 timings = ov64a40_get_timings(ov64a40, ov64a40->link_freq->cur.val); 2983 delay = DIV_ROUND_UP(4096, OV64A40_XCLK_FREQ / 1000 / 1000); 2984 delay = max(delay, 150ul); 2985 2986 /* The sensor has an internal x4 multiplier on the line length. */ 2987 delay += DIV_ROUND_UP(timings->ppl * 4 * ov64a40->exposure->cur.val, 2988 OV64A40_PIXEL_RATE / 1000 / 1000); 2989 fsleep(delay); 2990 2991 return 0; 2992 2993 error_power_off: 2994 pm_runtime_mark_last_busy(ov64a40->dev); 2995 pm_runtime_put_autosuspend(ov64a40->dev); 2996 2997 return ret; 2998 } 2999 3000 static int ov64a40_stop_streaming(struct ov64a40 *ov64a40, 3001 struct v4l2_subdev_state *state) 3002 { 3003 cci_update_bits(ov64a40->cci, OV64A40_REG_SMIA, BIT(0), 0, NULL); 3004 pm_runtime_mark_last_busy(ov64a40->dev); 3005 pm_runtime_put_autosuspend(ov64a40->dev); 3006 3007 __v4l2_ctrl_grab(ov64a40->link_freq, false); 3008 __v4l2_ctrl_grab(ov64a40->vflip, false); 3009 __v4l2_ctrl_grab(ov64a40->hflip, false); 3010 3011 return 0; 3012 } 3013 3014 static int ov64a40_set_stream(struct v4l2_subdev *sd, int enable) 3015 { 3016 struct ov64a40 *ov64a40 = sd_to_ov64a40(sd); 3017 struct v4l2_subdev_state *state; 3018 int ret; 3019 3020 state = v4l2_subdev_lock_and_get_active_state(sd); 3021 if (enable) 3022 ret = ov64a40_start_streaming(ov64a40, state); 3023 else 3024 ret = ov64a40_stop_streaming(ov64a40, state); 3025 v4l2_subdev_unlock_state(state); 3026 3027 return ret; 3028 } 3029 3030 static const struct v4l2_subdev_video_ops ov64a40_video_ops = { 3031 .s_stream = ov64a40_set_stream, 3032 }; 3033 3034 static u32 ov64a40_mbus_code(struct ov64a40 *ov64a40) 3035 { 3036 unsigned int index = ov64a40->hflip->val << 1 | ov64a40->vflip->val; 3037 3038 return ov64a40_mbus_codes[index]; 3039 } 3040 3041 static void ov64a40_update_pad_fmt(struct ov64a40 *ov64a40, 3042 struct ov64a40_mode *mode, 3043 struct v4l2_mbus_framefmt *fmt) 3044 { 3045 fmt->code = ov64a40_mbus_code(ov64a40); 3046 fmt->width = mode->width; 3047 fmt->height = mode->height; 3048 fmt->field = V4L2_FIELD_NONE; 3049 fmt->colorspace = V4L2_COLORSPACE_RAW; 3050 fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE; 3051 fmt->xfer_func = V4L2_XFER_FUNC_NONE; 3052 fmt->ycbcr_enc = V4L2_YCBCR_ENC_601; 3053 } 3054 3055 static int ov64a40_init_state(struct v4l2_subdev *sd, 3056 struct v4l2_subdev_state *state) 3057 { 3058 struct ov64a40 *ov64a40 = sd_to_ov64a40(sd); 3059 struct v4l2_mbus_framefmt *format; 3060 struct v4l2_rect *crop; 3061 3062 format = v4l2_subdev_state_get_format(state, 0); 3063 ov64a40_update_pad_fmt(ov64a40, &ov64a40_modes[0], format); 3064 3065 crop = v4l2_subdev_state_get_crop(state, 0); 3066 crop->top = OV64A40_PIXEL_ARRAY_TOP; 3067 crop->left = OV64A40_PIXEL_ARRAY_LEFT; 3068 crop->width = OV64A40_PIXEL_ARRAY_WIDTH; 3069 crop->height = OV64A40_PIXEL_ARRAY_HEIGHT; 3070 3071 return 0; 3072 } 3073 3074 static int ov64a40_enum_mbus_code(struct v4l2_subdev *sd, 3075 struct v4l2_subdev_state *state, 3076 struct v4l2_subdev_mbus_code_enum *code) 3077 { 3078 struct ov64a40 *ov64a40 = sd_to_ov64a40(sd); 3079 3080 if (code->index) 3081 return -EINVAL; 3082 3083 code->code = ov64a40_mbus_code(ov64a40); 3084 3085 return 0; 3086 } 3087 3088 static int ov64a40_enum_frame_size(struct v4l2_subdev *sd, 3089 struct v4l2_subdev_state *state, 3090 struct v4l2_subdev_frame_size_enum *fse) 3091 { 3092 struct ov64a40 *ov64a40 = sd_to_ov64a40(sd); 3093 struct ov64a40_mode *mode; 3094 u32 code; 3095 3096 if (fse->index >= ARRAY_SIZE(ov64a40_modes)) 3097 return -EINVAL; 3098 3099 code = ov64a40_mbus_code(ov64a40); 3100 if (fse->code != code) 3101 return -EINVAL; 3102 3103 mode = &ov64a40_modes[fse->index]; 3104 fse->min_width = mode->width; 3105 fse->max_width = mode->width; 3106 fse->min_height = mode->height; 3107 fse->max_height = mode->height; 3108 3109 return 0; 3110 } 3111 3112 static int ov64a40_get_selection(struct v4l2_subdev *sd, 3113 struct v4l2_subdev_state *state, 3114 struct v4l2_subdev_selection *sel) 3115 { 3116 switch (sel->target) { 3117 case V4L2_SEL_TGT_CROP: 3118 sel->r = *v4l2_subdev_state_get_crop(state, 0); 3119 3120 return 0; 3121 3122 case V4L2_SEL_TGT_NATIVE_SIZE: 3123 sel->r.top = 0; 3124 sel->r.left = 0; 3125 sel->r.width = OV64A40_NATIVE_WIDTH; 3126 sel->r.height = OV64A40_NATIVE_HEIGHT; 3127 3128 return 0; 3129 3130 case V4L2_SEL_TGT_CROP_DEFAULT: 3131 case V4L2_SEL_TGT_CROP_BOUNDS: 3132 sel->r.top = OV64A40_PIXEL_ARRAY_TOP; 3133 sel->r.left = OV64A40_PIXEL_ARRAY_LEFT; 3134 sel->r.width = OV64A40_PIXEL_ARRAY_WIDTH; 3135 sel->r.height = OV64A40_PIXEL_ARRAY_HEIGHT; 3136 3137 return 0; 3138 } 3139 3140 return -EINVAL; 3141 } 3142 3143 static int ov64a40_set_format(struct v4l2_subdev *sd, 3144 struct v4l2_subdev_state *state, 3145 struct v4l2_subdev_format *fmt) 3146 { 3147 struct ov64a40 *ov64a40 = sd_to_ov64a40(sd); 3148 struct v4l2_mbus_framefmt *format; 3149 struct ov64a40_mode *mode; 3150 3151 mode = v4l2_find_nearest_size(ov64a40_modes, 3152 ARRAY_SIZE(ov64a40_modes), 3153 width, height, 3154 fmt->format.width, fmt->format.height); 3155 3156 ov64a40_update_pad_fmt(ov64a40, mode, &fmt->format); 3157 3158 format = v4l2_subdev_state_get_format(state, 0); 3159 if (ov64a40->mode == mode && format->code == fmt->format.code) 3160 return 0; 3161 3162 if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) { 3163 const struct ov64a40_timings *timings; 3164 int vblank_max, vblank_def; 3165 int hblank_val; 3166 int exp_max; 3167 3168 ov64a40->mode = mode; 3169 *v4l2_subdev_state_get_crop(state, 0) = mode->analogue_crop; 3170 3171 /* Update control limits according to the new mode. */ 3172 timings = ov64a40_get_timings(ov64a40, 3173 ov64a40->link_freq->cur.val); 3174 vblank_max = OV64A40_VTS_MAX - mode->height; 3175 vblank_def = timings->vts - mode->height; 3176 __v4l2_ctrl_modify_range(ov64a40->vblank, OV64A40_VBLANK_MIN, 3177 vblank_max, 1, vblank_def); 3178 __v4l2_ctrl_s_ctrl(ov64a40->vblank, vblank_def); 3179 3180 exp_max = timings->vts - OV64A40_EXPOSURE_MARGIN; 3181 __v4l2_ctrl_modify_range(ov64a40->exposure, 3182 OV64A40_EXPOSURE_MIN, exp_max, 3183 1, OV64A40_EXPOSURE_MIN); 3184 3185 hblank_val = timings->ppl * 4 - mode->width; 3186 __v4l2_ctrl_modify_range(ov64a40->hblank, 3187 hblank_val, hblank_val, 1, hblank_val); 3188 } 3189 3190 *format = fmt->format; 3191 3192 return 0; 3193 } 3194 3195 static const struct v4l2_subdev_pad_ops ov64a40_pad_ops = { 3196 .enum_mbus_code = ov64a40_enum_mbus_code, 3197 .enum_frame_size = ov64a40_enum_frame_size, 3198 .get_fmt = v4l2_subdev_get_fmt, 3199 .set_fmt = ov64a40_set_format, 3200 .get_selection = ov64a40_get_selection, 3201 }; 3202 3203 static const struct v4l2_subdev_core_ops ov64a40_core_ops = { 3204 .subscribe_event = v4l2_ctrl_subdev_subscribe_event, 3205 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 3206 }; 3207 3208 static const struct v4l2_subdev_ops ov64a40_subdev_ops = { 3209 .core = &ov64a40_core_ops, 3210 .video = &ov64a40_video_ops, 3211 .pad = &ov64a40_pad_ops, 3212 }; 3213 3214 static const struct v4l2_subdev_internal_ops ov64a40_internal_ops = { 3215 .init_state = ov64a40_init_state, 3216 }; 3217 3218 static int ov64a40_power_on(struct device *dev) 3219 { 3220 struct v4l2_subdev *sd = dev_get_drvdata(dev); 3221 struct ov64a40 *ov64a40 = sd_to_ov64a40(sd); 3222 int ret; 3223 3224 ret = clk_prepare_enable(ov64a40->xclk); 3225 if (ret) 3226 return ret; 3227 3228 ret = regulator_bulk_enable(ARRAY_SIZE(ov64a40_supply_names), 3229 ov64a40->supplies); 3230 if (ret) { 3231 clk_disable_unprepare(ov64a40->xclk); 3232 dev_err(dev, "Failed to enable regulators: %d\n", ret); 3233 return ret; 3234 } 3235 3236 gpiod_set_value_cansleep(ov64a40->reset_gpio, 0); 3237 3238 fsleep(5000); 3239 3240 return 0; 3241 } 3242 3243 static int ov64a40_power_off(struct device *dev) 3244 { 3245 struct v4l2_subdev *sd = dev_get_drvdata(dev); 3246 struct ov64a40 *ov64a40 = sd_to_ov64a40(sd); 3247 3248 gpiod_set_value_cansleep(ov64a40->reset_gpio, 1); 3249 regulator_bulk_disable(ARRAY_SIZE(ov64a40_supply_names), 3250 ov64a40->supplies); 3251 clk_disable_unprepare(ov64a40->xclk); 3252 3253 return 0; 3254 } 3255 3256 static int ov64a40_link_freq_config(struct ov64a40 *ov64a40, int link_freq_id) 3257 { 3258 s64 link_frequency; 3259 int ret = 0; 3260 3261 /* Default 456MHz with 24MHz input clock. */ 3262 cci_multi_reg_write(ov64a40->cci, ov64a40_pll_config, 3263 ARRAY_SIZE(ov64a40_pll_config), &ret); 3264 3265 /* Decrease the PLL1 multiplier to obtain 360MHz mipi link frequency. */ 3266 link_frequency = ov64a40->link_frequencies[link_freq_id]; 3267 if (link_frequency == OV64A40_LINK_FREQ_360M) 3268 cci_write(ov64a40->cci, OV64A40_PLL1_MULTIPLIER, 0x0078, &ret); 3269 3270 return ret; 3271 } 3272 3273 static int ov64a40_set_ctrl(struct v4l2_ctrl *ctrl) 3274 { 3275 struct ov64a40 *ov64a40 = container_of(ctrl->handler, struct ov64a40, 3276 ctrl_handler); 3277 int pm_status; 3278 int ret = 0; 3279 3280 if (ctrl->id == V4L2_CID_VBLANK) { 3281 int exp_max = ov64a40->mode->height + ctrl->val 3282 - OV64A40_EXPOSURE_MARGIN; 3283 int exp_val = min(ov64a40->exposure->cur.val, exp_max); 3284 3285 __v4l2_ctrl_modify_range(ov64a40->exposure, 3286 ov64a40->exposure->minimum, 3287 exp_max, 1, exp_val); 3288 } 3289 3290 pm_status = pm_runtime_get_if_active(ov64a40->dev); 3291 if (!pm_status) 3292 return 0; 3293 3294 switch (ctrl->id) { 3295 case V4L2_CID_EXPOSURE: 3296 ret = cci_write(ov64a40->cci, OV64A40_REG_MEC_LONG_EXPO, 3297 ctrl->val, NULL); 3298 break; 3299 case V4L2_CID_ANALOGUE_GAIN: 3300 ret = cci_write(ov64a40->cci, OV64A40_REG_MEC_LONG_GAIN, 3301 ctrl->val << 1, NULL); 3302 break; 3303 case V4L2_CID_VBLANK: { 3304 int vts = ctrl->val + ov64a40->mode->height; 3305 3306 cci_write(ov64a40->cci, OV64A40_REG_TIMINGS_VTS_LOW, vts, &ret); 3307 cci_write(ov64a40->cci, OV64A40_REG_TIMINGS_VTS_MID, 3308 (vts >> 8), &ret); 3309 cci_write(ov64a40->cci, OV64A40_REG_TIMINGS_VTS_HIGH, 3310 (vts >> 16), &ret); 3311 break; 3312 } 3313 case V4L2_CID_VFLIP: 3314 ret = cci_update_bits(ov64a40->cci, OV64A40_REG_TIMING_CTRL_20, 3315 OV64A40_TIMING_CTRL_20_VFLIP, 3316 ctrl->val << 2, 3317 NULL); 3318 break; 3319 case V4L2_CID_HFLIP: 3320 ret = cci_update_bits(ov64a40->cci, OV64A40_REG_TIMING_CTRL_21, 3321 OV64A40_TIMING_CTRL_21_HFLIP, 3322 ctrl->val ? 0 3323 : OV64A40_TIMING_CTRL_21_HFLIP, 3324 NULL); 3325 break; 3326 case V4L2_CID_TEST_PATTERN: 3327 ret = cci_write(ov64a40->cci, OV64A40_REG_TEST_PATTERN, 3328 ov64a40_test_pattern_val[ctrl->val], NULL); 3329 break; 3330 case V4L2_CID_LINK_FREQ: 3331 ret = ov64a40_link_freq_config(ov64a40, ctrl->val); 3332 break; 3333 default: 3334 dev_err(ov64a40->dev, "Unhandled control: %#x\n", ctrl->id); 3335 ret = -EINVAL; 3336 break; 3337 } 3338 3339 if (pm_status > 0) { 3340 pm_runtime_mark_last_busy(ov64a40->dev); 3341 pm_runtime_put_autosuspend(ov64a40->dev); 3342 } 3343 3344 return ret; 3345 } 3346 3347 static const struct v4l2_ctrl_ops ov64a40_ctrl_ops = { 3348 .s_ctrl = ov64a40_set_ctrl, 3349 }; 3350 3351 static int ov64a40_init_controls(struct ov64a40 *ov64a40) 3352 { 3353 int exp_max, hblank_val, vblank_max, vblank_def; 3354 struct v4l2_ctrl_handler *hdlr = &ov64a40->ctrl_handler; 3355 struct v4l2_fwnode_device_properties props; 3356 const struct ov64a40_timings *timings; 3357 int ret; 3358 3359 ret = v4l2_ctrl_handler_init(hdlr, 11); 3360 if (ret) 3361 return ret; 3362 3363 v4l2_ctrl_new_std(hdlr, &ov64a40_ctrl_ops, V4L2_CID_PIXEL_RATE, 3364 OV64A40_PIXEL_RATE, OV64A40_PIXEL_RATE, 1, 3365 OV64A40_PIXEL_RATE); 3366 3367 ov64a40->link_freq = 3368 v4l2_ctrl_new_int_menu(hdlr, &ov64a40_ctrl_ops, 3369 V4L2_CID_LINK_FREQ, 3370 ov64a40->num_link_frequencies - 1, 3371 0, ov64a40->link_frequencies); 3372 3373 v4l2_ctrl_new_std_menu_items(hdlr, &ov64a40_ctrl_ops, 3374 V4L2_CID_TEST_PATTERN, 3375 ARRAY_SIZE(ov64a40_test_pattern_menu) - 1, 3376 0, 0, ov64a40_test_pattern_menu); 3377 3378 timings = ov64a40_get_timings(ov64a40, 0); 3379 exp_max = timings->vts - OV64A40_EXPOSURE_MARGIN; 3380 ov64a40->exposure = v4l2_ctrl_new_std(hdlr, &ov64a40_ctrl_ops, 3381 V4L2_CID_EXPOSURE, 3382 OV64A40_EXPOSURE_MIN, exp_max, 1, 3383 OV64A40_EXPOSURE_MIN); 3384 3385 hblank_val = timings->ppl * 4 - ov64a40->mode->width; 3386 ov64a40->hblank = v4l2_ctrl_new_std(hdlr, &ov64a40_ctrl_ops, 3387 V4L2_CID_HBLANK, hblank_val, 3388 hblank_val, 1, hblank_val); 3389 if (ov64a40->hblank) 3390 ov64a40->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; 3391 3392 vblank_def = timings->vts - ov64a40->mode->height; 3393 vblank_max = OV64A40_VTS_MAX - ov64a40->mode->height; 3394 ov64a40->vblank = v4l2_ctrl_new_std(hdlr, &ov64a40_ctrl_ops, 3395 V4L2_CID_VBLANK, OV64A40_VBLANK_MIN, 3396 vblank_max, 1, vblank_def); 3397 3398 v4l2_ctrl_new_std(hdlr, &ov64a40_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, 3399 OV64A40_ANA_GAIN_MIN, OV64A40_ANA_GAIN_MAX, 1, 3400 OV64A40_ANA_GAIN_DEFAULT); 3401 3402 ov64a40->hflip = v4l2_ctrl_new_std(hdlr, &ov64a40_ctrl_ops, 3403 V4L2_CID_HFLIP, 0, 1, 1, 0); 3404 if (ov64a40->hflip) 3405 ov64a40->hflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT; 3406 3407 ov64a40->vflip = v4l2_ctrl_new_std(hdlr, &ov64a40_ctrl_ops, 3408 V4L2_CID_VFLIP, 0, 1, 1, 0); 3409 if (ov64a40->vflip) 3410 ov64a40->vflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT; 3411 3412 if (hdlr->error) { 3413 ret = hdlr->error; 3414 dev_err(ov64a40->dev, "control init failed: %d\n", ret); 3415 goto error_free_hdlr; 3416 } 3417 3418 ret = v4l2_fwnode_device_parse(ov64a40->dev, &props); 3419 if (ret) 3420 goto error_free_hdlr; 3421 3422 ret = v4l2_ctrl_new_fwnode_properties(hdlr, &ov64a40_ctrl_ops, 3423 &props); 3424 if (ret) 3425 goto error_free_hdlr; 3426 3427 ov64a40->sd.ctrl_handler = hdlr; 3428 3429 return 0; 3430 3431 error_free_hdlr: 3432 v4l2_ctrl_handler_free(hdlr); 3433 return ret; 3434 } 3435 3436 static int ov64a40_identify(struct ov64a40 *ov64a40) 3437 { 3438 int ret; 3439 u64 id; 3440 3441 ret = cci_read(ov64a40->cci, OV64A40_REG_CHIP_ID, &id, NULL); 3442 if (ret) { 3443 dev_err(ov64a40->dev, "Failed to read chip id: %d\n", ret); 3444 return ret; 3445 } 3446 3447 if (id != OV64A40_CHIP_ID) { 3448 dev_err(ov64a40->dev, "chip id mismatch: %#llx\n", id); 3449 return -ENODEV; 3450 } 3451 3452 dev_dbg(ov64a40->dev, "OV64A40 chip identified: %#llx\n", id); 3453 3454 return 0; 3455 } 3456 3457 static int ov64a40_parse_dt(struct ov64a40 *ov64a40) 3458 { 3459 struct v4l2_fwnode_endpoint v4l2_fwnode = { 3460 .bus_type = V4L2_MBUS_CSI2_DPHY 3461 }; 3462 struct fwnode_handle *endpoint; 3463 unsigned int i; 3464 int ret; 3465 3466 endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(ov64a40->dev), 3467 NULL); 3468 if (!endpoint) { 3469 dev_err(ov64a40->dev, "Failed to find endpoint\n"); 3470 return -EINVAL; 3471 } 3472 3473 ret = v4l2_fwnode_endpoint_alloc_parse(endpoint, &v4l2_fwnode); 3474 fwnode_handle_put(endpoint); 3475 if (ret) { 3476 dev_err(ov64a40->dev, "Failed to parse endpoint\n"); 3477 return ret; 3478 } 3479 3480 if (v4l2_fwnode.bus.mipi_csi2.num_data_lanes != 2) { 3481 dev_err(ov64a40->dev, "Unsupported number of data lanes: %u\n", 3482 v4l2_fwnode.bus.mipi_csi2.num_data_lanes); 3483 v4l2_fwnode_endpoint_free(&v4l2_fwnode); 3484 return -EINVAL; 3485 } 3486 3487 if (!v4l2_fwnode.nr_of_link_frequencies) { 3488 dev_warn(ov64a40->dev, "no link frequencies defined\n"); 3489 v4l2_fwnode_endpoint_free(&v4l2_fwnode); 3490 return -EINVAL; 3491 } 3492 3493 if (v4l2_fwnode.nr_of_link_frequencies > 2) { 3494 dev_warn(ov64a40->dev, 3495 "Unsupported number of link frequencies\n"); 3496 v4l2_fwnode_endpoint_free(&v4l2_fwnode); 3497 return -EINVAL; 3498 } 3499 3500 ov64a40->link_frequencies = 3501 devm_kcalloc(ov64a40->dev, v4l2_fwnode.nr_of_link_frequencies, 3502 sizeof(v4l2_fwnode.link_frequencies[0]), 3503 GFP_KERNEL); 3504 if (!ov64a40->link_frequencies) { 3505 v4l2_fwnode_endpoint_free(&v4l2_fwnode); 3506 return -ENOMEM; 3507 } 3508 ov64a40->num_link_frequencies = v4l2_fwnode.nr_of_link_frequencies; 3509 3510 for (i = 0; i < v4l2_fwnode.nr_of_link_frequencies; ++i) { 3511 if (v4l2_fwnode.link_frequencies[i] != OV64A40_LINK_FREQ_360M && 3512 v4l2_fwnode.link_frequencies[i] != OV64A40_LINK_FREQ_456M) { 3513 dev_err(ov64a40->dev, 3514 "Unsupported link frequency %lld\n", 3515 v4l2_fwnode.link_frequencies[i]); 3516 v4l2_fwnode_endpoint_free(&v4l2_fwnode); 3517 return -EINVAL; 3518 } 3519 3520 ov64a40->link_frequencies[i] = v4l2_fwnode.link_frequencies[i]; 3521 } 3522 3523 v4l2_fwnode_endpoint_free(&v4l2_fwnode); 3524 3525 return 0; 3526 } 3527 3528 static int ov64a40_get_regulators(struct ov64a40 *ov64a40) 3529 { 3530 struct i2c_client *client = v4l2_get_subdevdata(&ov64a40->sd); 3531 unsigned int i; 3532 3533 for (i = 0; i < ARRAY_SIZE(ov64a40_supply_names); i++) 3534 ov64a40->supplies[i].supply = ov64a40_supply_names[i]; 3535 3536 return devm_regulator_bulk_get(&client->dev, 3537 ARRAY_SIZE(ov64a40_supply_names), 3538 ov64a40->supplies); 3539 } 3540 3541 static int ov64a40_probe(struct i2c_client *client) 3542 { 3543 struct ov64a40 *ov64a40; 3544 u32 xclk_freq; 3545 int ret; 3546 3547 ov64a40 = devm_kzalloc(&client->dev, sizeof(*ov64a40), GFP_KERNEL); 3548 if (!ov64a40) 3549 return -ENOMEM; 3550 3551 ov64a40->dev = &client->dev; 3552 v4l2_i2c_subdev_init(&ov64a40->sd, client, &ov64a40_subdev_ops); 3553 3554 ov64a40->cci = devm_cci_regmap_init_i2c(client, 16); 3555 if (IS_ERR(ov64a40->cci)) { 3556 dev_err(&client->dev, "Failed to initialize CCI\n"); 3557 return PTR_ERR(ov64a40->cci); 3558 } 3559 3560 ov64a40->xclk = devm_clk_get(&client->dev, NULL); 3561 if (IS_ERR(ov64a40->xclk)) 3562 return dev_err_probe(&client->dev, PTR_ERR(ov64a40->xclk), 3563 "Failed to get clock\n"); 3564 3565 xclk_freq = clk_get_rate(ov64a40->xclk); 3566 if (xclk_freq != OV64A40_XCLK_FREQ) { 3567 dev_err(&client->dev, "Unsupported xclk frequency %u\n", 3568 xclk_freq); 3569 return -EINVAL; 3570 } 3571 3572 ret = ov64a40_get_regulators(ov64a40); 3573 if (ret) 3574 return ret; 3575 3576 ov64a40->reset_gpio = devm_gpiod_get_optional(&client->dev, "reset", 3577 GPIOD_OUT_LOW); 3578 if (IS_ERR(ov64a40->reset_gpio)) 3579 return dev_err_probe(&client->dev, PTR_ERR(ov64a40->reset_gpio), 3580 "Failed to get reset gpio\n"); 3581 3582 ret = ov64a40_parse_dt(ov64a40); 3583 if (ret) 3584 return ret; 3585 3586 ret = ov64a40_power_on(&client->dev); 3587 if (ret) 3588 return ret; 3589 3590 ret = ov64a40_identify(ov64a40); 3591 if (ret) 3592 goto error_poweroff; 3593 3594 ov64a40->mode = &ov64a40_modes[0]; 3595 3596 pm_runtime_set_active(&client->dev); 3597 pm_runtime_get_noresume(&client->dev); 3598 pm_runtime_enable(&client->dev); 3599 pm_runtime_set_autosuspend_delay(&client->dev, 1000); 3600 pm_runtime_use_autosuspend(&client->dev); 3601 3602 ret = ov64a40_init_controls(ov64a40); 3603 if (ret) 3604 goto error_poweroff; 3605 3606 /* Initialize subdev */ 3607 ov64a40->sd.internal_ops = &ov64a40_internal_ops; 3608 ov64a40->sd.flags = V4L2_SUBDEV_FL_HAS_DEVNODE 3609 | V4L2_SUBDEV_FL_HAS_EVENTS; 3610 ov64a40->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 3611 3612 ov64a40->pad.flags = MEDIA_PAD_FL_SOURCE; 3613 ret = media_entity_pads_init(&ov64a40->sd.entity, 1, &ov64a40->pad); 3614 if (ret) { 3615 dev_err(&client->dev, "failed to init entity pads: %d\n", ret); 3616 goto error_handler_free; 3617 } 3618 3619 ov64a40->sd.state_lock = ov64a40->ctrl_handler.lock; 3620 ret = v4l2_subdev_init_finalize(&ov64a40->sd); 3621 if (ret < 0) { 3622 dev_err(&client->dev, "subdev init error: %d\n", ret); 3623 goto error_media_entity; 3624 } 3625 3626 ret = v4l2_async_register_subdev_sensor(&ov64a40->sd); 3627 if (ret < 0) { 3628 dev_err(&client->dev, 3629 "failed to register sensor sub-device: %d\n", ret); 3630 goto error_subdev_cleanup; 3631 } 3632 3633 pm_runtime_mark_last_busy(&client->dev); 3634 pm_runtime_put_autosuspend(&client->dev); 3635 3636 return 0; 3637 3638 error_subdev_cleanup: 3639 v4l2_subdev_cleanup(&ov64a40->sd); 3640 error_media_entity: 3641 media_entity_cleanup(&ov64a40->sd.entity); 3642 error_handler_free: 3643 v4l2_ctrl_handler_free(ov64a40->sd.ctrl_handler); 3644 error_poweroff: 3645 ov64a40_power_off(&client->dev); 3646 pm_runtime_set_suspended(&client->dev); 3647 3648 return ret; 3649 } 3650 3651 static void ov64a40_remove(struct i2c_client *client) 3652 { 3653 struct v4l2_subdev *sd = i2c_get_clientdata(client); 3654 3655 v4l2_async_unregister_subdev(sd); 3656 v4l2_subdev_cleanup(sd); 3657 media_entity_cleanup(&sd->entity); 3658 v4l2_ctrl_handler_free(sd->ctrl_handler); 3659 3660 pm_runtime_disable(&client->dev); 3661 if (!pm_runtime_status_suspended(&client->dev)) 3662 ov64a40_power_off(&client->dev); 3663 pm_runtime_set_suspended(&client->dev); 3664 } 3665 3666 static const struct of_device_id ov64a40_of_ids[] = { 3667 { .compatible = "ovti,ov64a40" }, 3668 { /* sentinel */ } 3669 }; 3670 MODULE_DEVICE_TABLE(of, ov64a40_of_ids); 3671 3672 static const struct dev_pm_ops ov64a40_pm_ops = { 3673 SET_RUNTIME_PM_OPS(ov64a40_power_off, ov64a40_power_on, NULL) 3674 }; 3675 3676 static struct i2c_driver ov64a40_i2c_driver = { 3677 .driver = { 3678 .name = "ov64a40", 3679 .of_match_table = ov64a40_of_ids, 3680 .pm = &ov64a40_pm_ops, 3681 }, 3682 .probe = ov64a40_probe, 3683 .remove = ov64a40_remove, 3684 }; 3685 3686 module_i2c_driver(ov64a40_i2c_driver); 3687 3688 MODULE_AUTHOR("Jacopo Mondi <jacopo.mondi@ideasonboard.com>"); 3689 MODULE_DESCRIPTION("OmniVision OV64A40 sensor driver"); 3690 MODULE_LICENSE("GPL"); 3691