1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2020 Intel Corporation. 3 4 #include <asm/unaligned.h> 5 #include <linux/acpi.h> 6 #include <linux/delay.h> 7 #include <linux/i2c.h> 8 #include <linux/module.h> 9 #include <linux/pm_runtime.h> 10 #include <linux/nvmem-provider.h> 11 #include <linux/regmap.h> 12 #include <media/v4l2-ctrls.h> 13 #include <media/v4l2-device.h> 14 #include <media/v4l2-fwnode.h> 15 16 #define OV2740_LINK_FREQ_360MHZ 360000000ULL 17 #define OV2740_SCLK 72000000LL 18 #define OV2740_MCLK 19200000 19 #define OV2740_DATA_LANES 2 20 #define OV2740_RGB_DEPTH 10 21 22 #define OV2740_REG_CHIP_ID 0x300a 23 #define OV2740_CHIP_ID 0x2740 24 25 #define OV2740_REG_MODE_SELECT 0x0100 26 #define OV2740_MODE_STANDBY 0x00 27 #define OV2740_MODE_STREAMING 0x01 28 29 /* vertical-timings from sensor */ 30 #define OV2740_REG_VTS 0x380e 31 #define OV2740_VTS_DEF 0x088a 32 #define OV2740_VTS_MIN 0x0460 33 #define OV2740_VTS_MAX 0x7fff 34 35 /* horizontal-timings from sensor */ 36 #define OV2740_REG_HTS 0x380c 37 38 /* Exposure controls from sensor */ 39 #define OV2740_REG_EXPOSURE 0x3500 40 #define OV2740_EXPOSURE_MIN 4 41 #define OV2740_EXPOSURE_MAX_MARGIN 8 42 #define OV2740_EXPOSURE_STEP 1 43 44 /* Analog gain controls from sensor */ 45 #define OV2740_REG_ANALOG_GAIN 0x3508 46 #define OV2740_ANAL_GAIN_MIN 128 47 #define OV2740_ANAL_GAIN_MAX 1983 48 #define OV2740_ANAL_GAIN_STEP 1 49 50 /* Digital gain controls from sensor */ 51 #define OV2740_REG_MWB_R_GAIN 0x500a 52 #define OV2740_REG_MWB_G_GAIN 0x500c 53 #define OV2740_REG_MWB_B_GAIN 0x500e 54 #define OV2740_DGTL_GAIN_MIN 1024 55 #define OV2740_DGTL_GAIN_MAX 4095 56 #define OV2740_DGTL_GAIN_STEP 1 57 #define OV2740_DGTL_GAIN_DEFAULT 1024 58 59 /* Test Pattern Control */ 60 #define OV2740_REG_TEST_PATTERN 0x5040 61 #define OV2740_TEST_PATTERN_ENABLE BIT(7) 62 #define OV2740_TEST_PATTERN_BAR_SHIFT 2 63 64 /* Group Access */ 65 #define OV2740_REG_GROUP_ACCESS 0x3208 66 #define OV2740_GROUP_HOLD_START 0x0 67 #define OV2740_GROUP_HOLD_END 0x10 68 #define OV2740_GROUP_HOLD_LAUNCH 0xa0 69 70 /* ISP CTRL00 */ 71 #define OV2740_REG_ISP_CTRL00 0x5000 72 /* ISP CTRL01 */ 73 #define OV2740_REG_ISP_CTRL01 0x5001 74 /* Customer Addresses: 0x7010 - 0x710F */ 75 #define CUSTOMER_USE_OTP_SIZE 0x100 76 /* OTP registers from sensor */ 77 #define OV2740_REG_OTP_CUSTOMER 0x7010 78 79 struct nvm_data { 80 struct nvmem_device *nvmem; 81 struct regmap *regmap; 82 char *nvm_buffer; 83 }; 84 85 enum { 86 OV2740_LINK_FREQ_360MHZ_INDEX, 87 }; 88 89 struct ov2740_reg { 90 u16 address; 91 u8 val; 92 }; 93 94 struct ov2740_reg_list { 95 u32 num_of_regs; 96 const struct ov2740_reg *regs; 97 }; 98 99 struct ov2740_link_freq_config { 100 const struct ov2740_reg_list reg_list; 101 }; 102 103 struct ov2740_mode { 104 /* Frame width in pixels */ 105 u32 width; 106 107 /* Frame height in pixels */ 108 u32 height; 109 110 /* Horizontal timining size */ 111 u32 hts; 112 113 /* Default vertical timining size */ 114 u32 vts_def; 115 116 /* Min vertical timining size */ 117 u32 vts_min; 118 119 /* Link frequency needed for this resolution */ 120 u32 link_freq_index; 121 122 /* Sensor register settings for this resolution */ 123 const struct ov2740_reg_list reg_list; 124 }; 125 126 static const struct ov2740_reg mipi_data_rate_720mbps[] = { 127 {0x0103, 0x01}, 128 {0x0302, 0x4b}, 129 {0x030d, 0x4b}, 130 {0x030e, 0x02}, 131 {0x030a, 0x01}, 132 {0x0312, 0x11}, 133 }; 134 135 static const struct ov2740_reg mode_1932x1092_regs[] = { 136 {0x3000, 0x00}, 137 {0x3018, 0x32}, 138 {0x3031, 0x0a}, 139 {0x3080, 0x08}, 140 {0x3083, 0xB4}, 141 {0x3103, 0x00}, 142 {0x3104, 0x01}, 143 {0x3106, 0x01}, 144 {0x3500, 0x00}, 145 {0x3501, 0x44}, 146 {0x3502, 0x40}, 147 {0x3503, 0x88}, 148 {0x3507, 0x00}, 149 {0x3508, 0x00}, 150 {0x3509, 0x80}, 151 {0x350c, 0x00}, 152 {0x350d, 0x80}, 153 {0x3510, 0x00}, 154 {0x3511, 0x00}, 155 {0x3512, 0x20}, 156 {0x3632, 0x00}, 157 {0x3633, 0x10}, 158 {0x3634, 0x10}, 159 {0x3635, 0x10}, 160 {0x3645, 0x13}, 161 {0x3646, 0x81}, 162 {0x3636, 0x10}, 163 {0x3651, 0x0a}, 164 {0x3656, 0x02}, 165 {0x3659, 0x04}, 166 {0x365a, 0xda}, 167 {0x365b, 0xa2}, 168 {0x365c, 0x04}, 169 {0x365d, 0x1d}, 170 {0x365e, 0x1a}, 171 {0x3662, 0xd7}, 172 {0x3667, 0x78}, 173 {0x3669, 0x0a}, 174 {0x366a, 0x92}, 175 {0x3700, 0x54}, 176 {0x3702, 0x10}, 177 {0x3706, 0x42}, 178 {0x3709, 0x30}, 179 {0x370b, 0xc2}, 180 {0x3714, 0x63}, 181 {0x3715, 0x01}, 182 {0x3716, 0x00}, 183 {0x371a, 0x3e}, 184 {0x3732, 0x0e}, 185 {0x3733, 0x10}, 186 {0x375f, 0x0e}, 187 {0x3768, 0x30}, 188 {0x3769, 0x44}, 189 {0x376a, 0x22}, 190 {0x377b, 0x20}, 191 {0x377c, 0x00}, 192 {0x377d, 0x0c}, 193 {0x3798, 0x00}, 194 {0x37a1, 0x55}, 195 {0x37a8, 0x6d}, 196 {0x37c2, 0x04}, 197 {0x37c5, 0x00}, 198 {0x37c8, 0x00}, 199 {0x3800, 0x00}, 200 {0x3801, 0x00}, 201 {0x3802, 0x00}, 202 {0x3803, 0x00}, 203 {0x3804, 0x07}, 204 {0x3805, 0x8f}, 205 {0x3806, 0x04}, 206 {0x3807, 0x47}, 207 {0x3808, 0x07}, 208 {0x3809, 0x88}, 209 {0x380a, 0x04}, 210 {0x380b, 0x40}, 211 {0x380c, 0x04}, 212 {0x380d, 0x38}, 213 {0x380e, 0x04}, 214 {0x380f, 0x60}, 215 {0x3810, 0x00}, 216 {0x3811, 0x04}, 217 {0x3812, 0x00}, 218 {0x3813, 0x04}, 219 {0x3814, 0x01}, 220 {0x3815, 0x01}, 221 {0x3820, 0x80}, 222 {0x3821, 0x46}, 223 {0x3822, 0x84}, 224 {0x3829, 0x00}, 225 {0x382a, 0x01}, 226 {0x382b, 0x01}, 227 {0x3830, 0x04}, 228 {0x3836, 0x01}, 229 {0x3837, 0x08}, 230 {0x3839, 0x01}, 231 {0x383a, 0x00}, 232 {0x383b, 0x08}, 233 {0x383c, 0x00}, 234 {0x3f0b, 0x00}, 235 {0x4001, 0x20}, 236 {0x4009, 0x07}, 237 {0x4003, 0x10}, 238 {0x4010, 0xe0}, 239 {0x4016, 0x00}, 240 {0x4017, 0x10}, 241 {0x4044, 0x02}, 242 {0x4304, 0x08}, 243 {0x4307, 0x30}, 244 {0x4320, 0x80}, 245 {0x4322, 0x00}, 246 {0x4323, 0x00}, 247 {0x4324, 0x00}, 248 {0x4325, 0x00}, 249 {0x4326, 0x00}, 250 {0x4327, 0x00}, 251 {0x4328, 0x00}, 252 {0x4329, 0x00}, 253 {0x432c, 0x03}, 254 {0x432d, 0x81}, 255 {0x4501, 0x84}, 256 {0x4502, 0x40}, 257 {0x4503, 0x18}, 258 {0x4504, 0x04}, 259 {0x4508, 0x02}, 260 {0x4601, 0x10}, 261 {0x4800, 0x00}, 262 {0x4816, 0x52}, 263 {0x4837, 0x16}, 264 {0x5000, 0x7f}, 265 {0x5001, 0x00}, 266 {0x5005, 0x38}, 267 {0x501e, 0x0d}, 268 {0x5040, 0x00}, 269 {0x5901, 0x00}, 270 {0x3800, 0x00}, 271 {0x3801, 0x00}, 272 {0x3802, 0x00}, 273 {0x3803, 0x00}, 274 {0x3804, 0x07}, 275 {0x3805, 0x8f}, 276 {0x3806, 0x04}, 277 {0x3807, 0x47}, 278 {0x3808, 0x07}, 279 {0x3809, 0x8c}, 280 {0x380a, 0x04}, 281 {0x380b, 0x44}, 282 {0x3810, 0x00}, 283 {0x3811, 0x00}, 284 {0x3812, 0x00}, 285 {0x3813, 0x01}, 286 }; 287 288 static const char * const ov2740_test_pattern_menu[] = { 289 "Disabled", 290 "Color Bar", 291 "Top-Bottom Darker Color Bar", 292 "Right-Left Darker Color Bar", 293 "Bottom-Top Darker Color Bar", 294 }; 295 296 static const s64 link_freq_menu_items[] = { 297 OV2740_LINK_FREQ_360MHZ, 298 }; 299 300 static const struct ov2740_link_freq_config link_freq_configs[] = { 301 [OV2740_LINK_FREQ_360MHZ_INDEX] = { 302 .reg_list = { 303 .num_of_regs = ARRAY_SIZE(mipi_data_rate_720mbps), 304 .regs = mipi_data_rate_720mbps, 305 } 306 }, 307 }; 308 309 static const struct ov2740_mode supported_modes[] = { 310 { 311 .width = 1932, 312 .height = 1092, 313 .hts = 1080, 314 .vts_def = OV2740_VTS_DEF, 315 .vts_min = OV2740_VTS_MIN, 316 .reg_list = { 317 .num_of_regs = ARRAY_SIZE(mode_1932x1092_regs), 318 .regs = mode_1932x1092_regs, 319 }, 320 .link_freq_index = OV2740_LINK_FREQ_360MHZ_INDEX, 321 }, 322 }; 323 324 struct ov2740 { 325 struct v4l2_subdev sd; 326 struct media_pad pad; 327 struct v4l2_ctrl_handler ctrl_handler; 328 329 /* V4L2 Controls */ 330 struct v4l2_ctrl *link_freq; 331 struct v4l2_ctrl *pixel_rate; 332 struct v4l2_ctrl *vblank; 333 struct v4l2_ctrl *hblank; 334 struct v4l2_ctrl *exposure; 335 336 /* Current mode */ 337 const struct ov2740_mode *cur_mode; 338 339 /* NVM data inforamtion */ 340 struct nvm_data *nvm; 341 342 /* True if the device has been identified */ 343 bool identified; 344 }; 345 346 static inline struct ov2740 *to_ov2740(struct v4l2_subdev *subdev) 347 { 348 return container_of(subdev, struct ov2740, sd); 349 } 350 351 static u64 to_pixel_rate(u32 f_index) 352 { 353 u64 pixel_rate = link_freq_menu_items[f_index] * 2 * OV2740_DATA_LANES; 354 355 do_div(pixel_rate, OV2740_RGB_DEPTH); 356 357 return pixel_rate; 358 } 359 360 static u64 to_pixels_per_line(u32 hts, u32 f_index) 361 { 362 u64 ppl = hts * to_pixel_rate(f_index); 363 364 do_div(ppl, OV2740_SCLK); 365 366 return ppl; 367 } 368 369 static int ov2740_read_reg(struct ov2740 *ov2740, u16 reg, u16 len, u32 *val) 370 { 371 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 372 struct i2c_msg msgs[2]; 373 u8 addr_buf[2]; 374 u8 data_buf[4] = {0}; 375 int ret; 376 377 if (len > sizeof(data_buf)) 378 return -EINVAL; 379 380 put_unaligned_be16(reg, addr_buf); 381 msgs[0].addr = client->addr; 382 msgs[0].flags = 0; 383 msgs[0].len = sizeof(addr_buf); 384 msgs[0].buf = addr_buf; 385 msgs[1].addr = client->addr; 386 msgs[1].flags = I2C_M_RD; 387 msgs[1].len = len; 388 msgs[1].buf = &data_buf[sizeof(data_buf) - len]; 389 390 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); 391 if (ret != ARRAY_SIZE(msgs)) 392 return ret < 0 ? ret : -EIO; 393 394 *val = get_unaligned_be32(data_buf); 395 396 return 0; 397 } 398 399 static int ov2740_write_reg(struct ov2740 *ov2740, u16 reg, u16 len, u32 val) 400 { 401 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 402 u8 buf[6]; 403 int ret; 404 405 if (len > 4) 406 return -EINVAL; 407 408 put_unaligned_be16(reg, buf); 409 put_unaligned_be32(val << 8 * (4 - len), buf + 2); 410 411 ret = i2c_master_send(client, buf, len + 2); 412 if (ret != len + 2) 413 return ret < 0 ? ret : -EIO; 414 415 return 0; 416 } 417 418 static int ov2740_write_reg_list(struct ov2740 *ov2740, 419 const struct ov2740_reg_list *r_list) 420 { 421 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 422 unsigned int i; 423 int ret; 424 425 for (i = 0; i < r_list->num_of_regs; i++) { 426 ret = ov2740_write_reg(ov2740, r_list->regs[i].address, 1, 427 r_list->regs[i].val); 428 if (ret) { 429 dev_err_ratelimited(&client->dev, 430 "write reg 0x%4.4x return err = %d\n", 431 r_list->regs[i].address, ret); 432 return ret; 433 } 434 } 435 436 return 0; 437 } 438 439 static int ov2740_identify_module(struct ov2740 *ov2740) 440 { 441 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 442 int ret; 443 u32 val; 444 445 if (ov2740->identified) 446 return 0; 447 448 ret = ov2740_read_reg(ov2740, OV2740_REG_CHIP_ID, 3, &val); 449 if (ret) 450 return ret; 451 452 if (val != OV2740_CHIP_ID) { 453 dev_err(&client->dev, "chip id mismatch: %x != %x\n", 454 OV2740_CHIP_ID, val); 455 return -ENXIO; 456 } 457 458 ov2740->identified = true; 459 460 return 0; 461 } 462 463 static int ov2740_update_digital_gain(struct ov2740 *ov2740, u32 d_gain) 464 { 465 int ret; 466 467 ret = ov2740_write_reg(ov2740, OV2740_REG_GROUP_ACCESS, 1, 468 OV2740_GROUP_HOLD_START); 469 if (ret) 470 return ret; 471 472 ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_R_GAIN, 2, d_gain); 473 if (ret) 474 return ret; 475 476 ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_G_GAIN, 2, d_gain); 477 if (ret) 478 return ret; 479 480 ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_B_GAIN, 2, d_gain); 481 if (ret) 482 return ret; 483 484 ret = ov2740_write_reg(ov2740, OV2740_REG_GROUP_ACCESS, 1, 485 OV2740_GROUP_HOLD_END); 486 if (ret) 487 return ret; 488 489 ret = ov2740_write_reg(ov2740, OV2740_REG_GROUP_ACCESS, 1, 490 OV2740_GROUP_HOLD_LAUNCH); 491 return ret; 492 } 493 494 static int ov2740_test_pattern(struct ov2740 *ov2740, u32 pattern) 495 { 496 if (pattern) 497 pattern = (pattern - 1) << OV2740_TEST_PATTERN_BAR_SHIFT | 498 OV2740_TEST_PATTERN_ENABLE; 499 500 return ov2740_write_reg(ov2740, OV2740_REG_TEST_PATTERN, 1, pattern); 501 } 502 503 static int ov2740_set_ctrl(struct v4l2_ctrl *ctrl) 504 { 505 struct ov2740 *ov2740 = container_of(ctrl->handler, 506 struct ov2740, ctrl_handler); 507 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 508 s64 exposure_max; 509 int ret; 510 511 /* Propagate change of current control to all related controls */ 512 if (ctrl->id == V4L2_CID_VBLANK) { 513 /* Update max exposure while meeting expected vblanking */ 514 exposure_max = ov2740->cur_mode->height + ctrl->val - 515 OV2740_EXPOSURE_MAX_MARGIN; 516 __v4l2_ctrl_modify_range(ov2740->exposure, 517 ov2740->exposure->minimum, 518 exposure_max, ov2740->exposure->step, 519 exposure_max); 520 } 521 522 /* V4L2 controls values will be applied only when power is already up */ 523 if (!pm_runtime_get_if_in_use(&client->dev)) 524 return 0; 525 526 switch (ctrl->id) { 527 case V4L2_CID_ANALOGUE_GAIN: 528 ret = ov2740_write_reg(ov2740, OV2740_REG_ANALOG_GAIN, 2, 529 ctrl->val); 530 break; 531 532 case V4L2_CID_DIGITAL_GAIN: 533 ret = ov2740_update_digital_gain(ov2740, ctrl->val); 534 break; 535 536 case V4L2_CID_EXPOSURE: 537 /* 4 least significant bits of expsoure are fractional part */ 538 ret = ov2740_write_reg(ov2740, OV2740_REG_EXPOSURE, 3, 539 ctrl->val << 4); 540 break; 541 542 case V4L2_CID_VBLANK: 543 ret = ov2740_write_reg(ov2740, OV2740_REG_VTS, 2, 544 ov2740->cur_mode->height + ctrl->val); 545 break; 546 547 case V4L2_CID_TEST_PATTERN: 548 ret = ov2740_test_pattern(ov2740, ctrl->val); 549 break; 550 551 default: 552 ret = -EINVAL; 553 break; 554 } 555 556 pm_runtime_put(&client->dev); 557 558 return ret; 559 } 560 561 static const struct v4l2_ctrl_ops ov2740_ctrl_ops = { 562 .s_ctrl = ov2740_set_ctrl, 563 }; 564 565 static int ov2740_init_controls(struct ov2740 *ov2740) 566 { 567 struct v4l2_ctrl_handler *ctrl_hdlr; 568 const struct ov2740_mode *cur_mode; 569 s64 exposure_max, h_blank, pixel_rate; 570 u32 vblank_min, vblank_max, vblank_default; 571 int size; 572 int ret; 573 574 ctrl_hdlr = &ov2740->ctrl_handler; 575 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 8); 576 if (ret) 577 return ret; 578 579 cur_mode = ov2740->cur_mode; 580 size = ARRAY_SIZE(link_freq_menu_items); 581 582 ov2740->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, &ov2740_ctrl_ops, 583 V4L2_CID_LINK_FREQ, 584 size - 1, 0, 585 link_freq_menu_items); 586 if (ov2740->link_freq) 587 ov2740->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; 588 589 pixel_rate = to_pixel_rate(OV2740_LINK_FREQ_360MHZ_INDEX); 590 ov2740->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, 591 V4L2_CID_PIXEL_RATE, 0, 592 pixel_rate, 1, pixel_rate); 593 594 vblank_min = cur_mode->vts_min - cur_mode->height; 595 vblank_max = OV2740_VTS_MAX - cur_mode->height; 596 vblank_default = cur_mode->vts_def - cur_mode->height; 597 ov2740->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, 598 V4L2_CID_VBLANK, vblank_min, 599 vblank_max, 1, vblank_default); 600 601 h_blank = to_pixels_per_line(cur_mode->hts, cur_mode->link_freq_index); 602 h_blank -= cur_mode->width; 603 ov2740->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, 604 V4L2_CID_HBLANK, h_blank, h_blank, 1, 605 h_blank); 606 if (ov2740->hblank) 607 ov2740->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; 608 609 v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, 610 OV2740_ANAL_GAIN_MIN, OV2740_ANAL_GAIN_MAX, 611 OV2740_ANAL_GAIN_STEP, OV2740_ANAL_GAIN_MIN); 612 v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, V4L2_CID_DIGITAL_GAIN, 613 OV2740_DGTL_GAIN_MIN, OV2740_DGTL_GAIN_MAX, 614 OV2740_DGTL_GAIN_STEP, OV2740_DGTL_GAIN_DEFAULT); 615 exposure_max = cur_mode->vts_def - OV2740_EXPOSURE_MAX_MARGIN; 616 ov2740->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, 617 V4L2_CID_EXPOSURE, 618 OV2740_EXPOSURE_MIN, exposure_max, 619 OV2740_EXPOSURE_STEP, 620 exposure_max); 621 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov2740_ctrl_ops, 622 V4L2_CID_TEST_PATTERN, 623 ARRAY_SIZE(ov2740_test_pattern_menu) - 1, 624 0, 0, ov2740_test_pattern_menu); 625 if (ctrl_hdlr->error) { 626 v4l2_ctrl_handler_free(ctrl_hdlr); 627 return ctrl_hdlr->error; 628 } 629 630 ov2740->sd.ctrl_handler = ctrl_hdlr; 631 632 return 0; 633 } 634 635 static void ov2740_update_pad_format(const struct ov2740_mode *mode, 636 struct v4l2_mbus_framefmt *fmt) 637 { 638 fmt->width = mode->width; 639 fmt->height = mode->height; 640 fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10; 641 fmt->field = V4L2_FIELD_NONE; 642 } 643 644 static int ov2740_load_otp_data(struct nvm_data *nvm) 645 { 646 struct device *dev = regmap_get_device(nvm->regmap); 647 struct ov2740 *ov2740 = to_ov2740(dev_get_drvdata(dev)); 648 u32 isp_ctrl00 = 0; 649 u32 isp_ctrl01 = 0; 650 int ret; 651 652 if (nvm->nvm_buffer) 653 return 0; 654 655 nvm->nvm_buffer = kzalloc(CUSTOMER_USE_OTP_SIZE, GFP_KERNEL); 656 if (!nvm->nvm_buffer) 657 return -ENOMEM; 658 659 ret = ov2740_read_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, &isp_ctrl00); 660 if (ret) { 661 dev_err(dev, "failed to read ISP CTRL00\n"); 662 goto err; 663 } 664 665 ret = ov2740_read_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, &isp_ctrl01); 666 if (ret) { 667 dev_err(dev, "failed to read ISP CTRL01\n"); 668 goto err; 669 } 670 671 /* Clear bit 5 of ISP CTRL00 */ 672 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, 673 isp_ctrl00 & ~BIT(5)); 674 if (ret) { 675 dev_err(dev, "failed to set ISP CTRL00\n"); 676 goto err; 677 } 678 679 /* Clear bit 7 of ISP CTRL01 */ 680 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, 681 isp_ctrl01 & ~BIT(7)); 682 if (ret) { 683 dev_err(dev, "failed to set ISP CTRL01\n"); 684 goto err; 685 } 686 687 ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1, 688 OV2740_MODE_STREAMING); 689 if (ret) { 690 dev_err(dev, "failed to set streaming mode\n"); 691 goto err; 692 } 693 694 /* 695 * Users are not allowed to access OTP-related registers and memory 696 * during the 20 ms period after streaming starts (0x100 = 0x01). 697 */ 698 msleep(20); 699 700 ret = regmap_bulk_read(nvm->regmap, OV2740_REG_OTP_CUSTOMER, 701 nvm->nvm_buffer, CUSTOMER_USE_OTP_SIZE); 702 if (ret) { 703 dev_err(dev, "failed to read OTP data, ret %d\n", ret); 704 goto err; 705 } 706 707 ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1, 708 OV2740_MODE_STANDBY); 709 if (ret) { 710 dev_err(dev, "failed to set streaming mode\n"); 711 goto err; 712 } 713 714 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, isp_ctrl01); 715 if (ret) { 716 dev_err(dev, "failed to set ISP CTRL01\n"); 717 goto err; 718 } 719 720 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, isp_ctrl00); 721 if (ret) { 722 dev_err(dev, "failed to set ISP CTRL00\n"); 723 goto err; 724 } 725 726 return 0; 727 err: 728 kfree(nvm->nvm_buffer); 729 nvm->nvm_buffer = NULL; 730 731 return ret; 732 } 733 734 static int ov2740_start_streaming(struct ov2740 *ov2740) 735 { 736 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 737 const struct ov2740_reg_list *reg_list; 738 int link_freq_index; 739 int ret; 740 741 ret = ov2740_identify_module(ov2740); 742 if (ret) 743 return ret; 744 745 if (ov2740->nvm) 746 ov2740_load_otp_data(ov2740->nvm); 747 748 link_freq_index = ov2740->cur_mode->link_freq_index; 749 reg_list = &link_freq_configs[link_freq_index].reg_list; 750 ret = ov2740_write_reg_list(ov2740, reg_list); 751 if (ret) { 752 dev_err(&client->dev, "failed to set plls\n"); 753 return ret; 754 } 755 756 reg_list = &ov2740->cur_mode->reg_list; 757 ret = ov2740_write_reg_list(ov2740, reg_list); 758 if (ret) { 759 dev_err(&client->dev, "failed to set mode\n"); 760 return ret; 761 } 762 763 ret = __v4l2_ctrl_handler_setup(ov2740->sd.ctrl_handler); 764 if (ret) 765 return ret; 766 767 ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1, 768 OV2740_MODE_STREAMING); 769 if (ret) 770 dev_err(&client->dev, "failed to start streaming\n"); 771 772 return ret; 773 } 774 775 static void ov2740_stop_streaming(struct ov2740 *ov2740) 776 { 777 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 778 779 if (ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1, 780 OV2740_MODE_STANDBY)) 781 dev_err(&client->dev, "failed to stop streaming\n"); 782 } 783 784 static int ov2740_set_stream(struct v4l2_subdev *sd, int enable) 785 { 786 struct ov2740 *ov2740 = to_ov2740(sd); 787 struct i2c_client *client = v4l2_get_subdevdata(sd); 788 struct v4l2_subdev_state *sd_state; 789 int ret = 0; 790 791 sd_state = v4l2_subdev_lock_and_get_active_state(&ov2740->sd); 792 793 if (enable) { 794 ret = pm_runtime_resume_and_get(&client->dev); 795 if (ret < 0) 796 goto out_unlock; 797 798 ret = ov2740_start_streaming(ov2740); 799 if (ret) { 800 enable = 0; 801 ov2740_stop_streaming(ov2740); 802 pm_runtime_put(&client->dev); 803 } 804 } else { 805 ov2740_stop_streaming(ov2740); 806 pm_runtime_put(&client->dev); 807 } 808 809 out_unlock: 810 v4l2_subdev_unlock_state(sd_state); 811 812 return ret; 813 } 814 815 static int ov2740_set_format(struct v4l2_subdev *sd, 816 struct v4l2_subdev_state *sd_state, 817 struct v4l2_subdev_format *fmt) 818 { 819 struct ov2740 *ov2740 = to_ov2740(sd); 820 const struct ov2740_mode *mode; 821 s32 vblank_def, h_blank; 822 823 mode = v4l2_find_nearest_size(supported_modes, 824 ARRAY_SIZE(supported_modes), width, 825 height, fmt->format.width, 826 fmt->format.height); 827 828 ov2740_update_pad_format(mode, &fmt->format); 829 *v4l2_subdev_state_get_format(sd_state, fmt->pad) = fmt->format; 830 831 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) 832 return 0; 833 834 ov2740->cur_mode = mode; 835 __v4l2_ctrl_s_ctrl(ov2740->link_freq, mode->link_freq_index); 836 __v4l2_ctrl_s_ctrl_int64(ov2740->pixel_rate, 837 to_pixel_rate(mode->link_freq_index)); 838 839 /* Update limits and set FPS to default */ 840 vblank_def = mode->vts_def - mode->height; 841 __v4l2_ctrl_modify_range(ov2740->vblank, 842 mode->vts_min - mode->height, 843 OV2740_VTS_MAX - mode->height, 1, vblank_def); 844 __v4l2_ctrl_s_ctrl(ov2740->vblank, vblank_def); 845 h_blank = to_pixels_per_line(mode->hts, mode->link_freq_index) - 846 mode->width; 847 __v4l2_ctrl_modify_range(ov2740->hblank, h_blank, h_blank, 1, h_blank); 848 849 return 0; 850 } 851 852 static int ov2740_enum_mbus_code(struct v4l2_subdev *sd, 853 struct v4l2_subdev_state *sd_state, 854 struct v4l2_subdev_mbus_code_enum *code) 855 { 856 if (code->index > 0) 857 return -EINVAL; 858 859 code->code = MEDIA_BUS_FMT_SGRBG10_1X10; 860 861 return 0; 862 } 863 864 static int ov2740_enum_frame_size(struct v4l2_subdev *sd, 865 struct v4l2_subdev_state *sd_state, 866 struct v4l2_subdev_frame_size_enum *fse) 867 { 868 if (fse->index >= ARRAY_SIZE(supported_modes)) 869 return -EINVAL; 870 871 if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10) 872 return -EINVAL; 873 874 fse->min_width = supported_modes[fse->index].width; 875 fse->max_width = fse->min_width; 876 fse->min_height = supported_modes[fse->index].height; 877 fse->max_height = fse->min_height; 878 879 return 0; 880 } 881 882 static int ov2740_init_state(struct v4l2_subdev *sd, 883 struct v4l2_subdev_state *sd_state) 884 { 885 ov2740_update_pad_format(&supported_modes[0], 886 v4l2_subdev_state_get_format(sd_state, 0)); 887 888 return 0; 889 } 890 891 static const struct v4l2_subdev_video_ops ov2740_video_ops = { 892 .s_stream = ov2740_set_stream, 893 }; 894 895 static const struct v4l2_subdev_pad_ops ov2740_pad_ops = { 896 .get_fmt = v4l2_subdev_get_fmt, 897 .set_fmt = ov2740_set_format, 898 .enum_mbus_code = ov2740_enum_mbus_code, 899 .enum_frame_size = ov2740_enum_frame_size, 900 }; 901 902 static const struct v4l2_subdev_ops ov2740_subdev_ops = { 903 .video = &ov2740_video_ops, 904 .pad = &ov2740_pad_ops, 905 }; 906 907 static const struct v4l2_subdev_internal_ops ov2740_internal_ops = { 908 .init_state = ov2740_init_state, 909 }; 910 911 static const struct media_entity_operations ov2740_subdev_entity_ops = { 912 .link_validate = v4l2_subdev_link_validate, 913 }; 914 915 static int ov2740_check_hwcfg(struct device *dev) 916 { 917 struct fwnode_handle *ep; 918 struct fwnode_handle *fwnode = dev_fwnode(dev); 919 struct v4l2_fwnode_endpoint bus_cfg = { 920 .bus_type = V4L2_MBUS_CSI2_DPHY 921 }; 922 u32 mclk; 923 int ret; 924 unsigned int i, j; 925 926 ret = fwnode_property_read_u32(fwnode, "clock-frequency", &mclk); 927 if (ret) 928 return ret; 929 930 if (mclk != OV2740_MCLK) 931 return dev_err_probe(dev, -EINVAL, 932 "external clock %d is not supported\n", 933 mclk); 934 935 ep = fwnode_graph_get_next_endpoint(fwnode, NULL); 936 if (!ep) 937 return -EPROBE_DEFER; 938 939 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg); 940 fwnode_handle_put(ep); 941 if (ret) 942 return ret; 943 944 if (bus_cfg.bus.mipi_csi2.num_data_lanes != OV2740_DATA_LANES) { 945 ret = dev_err_probe(dev, -EINVAL, 946 "number of CSI2 data lanes %d is not supported\n", 947 bus_cfg.bus.mipi_csi2.num_data_lanes); 948 goto check_hwcfg_error; 949 } 950 951 if (!bus_cfg.nr_of_link_frequencies) { 952 ret = dev_err_probe(dev, -EINVAL, "no link frequencies defined\n"); 953 goto check_hwcfg_error; 954 } 955 956 for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) { 957 for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) { 958 if (link_freq_menu_items[i] == 959 bus_cfg.link_frequencies[j]) 960 break; 961 } 962 963 if (j == bus_cfg.nr_of_link_frequencies) { 964 ret = dev_err_probe(dev, -EINVAL, 965 "no link frequency %lld supported\n", 966 link_freq_menu_items[i]); 967 goto check_hwcfg_error; 968 } 969 } 970 971 check_hwcfg_error: 972 v4l2_fwnode_endpoint_free(&bus_cfg); 973 974 return ret; 975 } 976 977 static void ov2740_remove(struct i2c_client *client) 978 { 979 struct v4l2_subdev *sd = i2c_get_clientdata(client); 980 981 v4l2_async_unregister_subdev(sd); 982 media_entity_cleanup(&sd->entity); 983 v4l2_subdev_cleanup(sd); 984 v4l2_ctrl_handler_free(sd->ctrl_handler); 985 pm_runtime_disable(&client->dev); 986 } 987 988 static int ov2740_nvmem_read(void *priv, unsigned int off, void *val, 989 size_t count) 990 { 991 struct nvm_data *nvm = priv; 992 struct device *dev = regmap_get_device(nvm->regmap); 993 struct ov2740 *ov2740 = to_ov2740(dev_get_drvdata(dev)); 994 struct v4l2_subdev_state *sd_state; 995 int ret = 0; 996 997 /* Serialise sensor access */ 998 sd_state = v4l2_subdev_lock_and_get_active_state(&ov2740->sd); 999 1000 if (nvm->nvm_buffer) { 1001 memcpy(val, nvm->nvm_buffer + off, count); 1002 goto exit; 1003 } 1004 1005 ret = pm_runtime_resume_and_get(dev); 1006 if (ret < 0) { 1007 goto exit; 1008 } 1009 1010 ret = ov2740_load_otp_data(nvm); 1011 if (!ret) 1012 memcpy(val, nvm->nvm_buffer + off, count); 1013 1014 pm_runtime_put(dev); 1015 exit: 1016 v4l2_subdev_unlock_state(sd_state); 1017 return ret; 1018 } 1019 1020 static int ov2740_register_nvmem(struct i2c_client *client, 1021 struct ov2740 *ov2740) 1022 { 1023 struct nvm_data *nvm; 1024 struct regmap_config regmap_config = { }; 1025 struct nvmem_config nvmem_config = { }; 1026 struct regmap *regmap; 1027 struct device *dev = &client->dev; 1028 1029 nvm = devm_kzalloc(dev, sizeof(*nvm), GFP_KERNEL); 1030 if (!nvm) 1031 return -ENOMEM; 1032 1033 regmap_config.val_bits = 8; 1034 regmap_config.reg_bits = 16; 1035 regmap_config.disable_locking = true; 1036 regmap = devm_regmap_init_i2c(client, ®map_config); 1037 if (IS_ERR(regmap)) 1038 return PTR_ERR(regmap); 1039 1040 nvm->regmap = regmap; 1041 1042 nvmem_config.name = dev_name(dev); 1043 nvmem_config.dev = dev; 1044 nvmem_config.read_only = true; 1045 nvmem_config.root_only = true; 1046 nvmem_config.owner = THIS_MODULE; 1047 nvmem_config.compat = true; 1048 nvmem_config.base_dev = dev; 1049 nvmem_config.reg_read = ov2740_nvmem_read; 1050 nvmem_config.reg_write = NULL; 1051 nvmem_config.priv = nvm; 1052 nvmem_config.stride = 1; 1053 nvmem_config.word_size = 1; 1054 nvmem_config.size = CUSTOMER_USE_OTP_SIZE; 1055 1056 nvm->nvmem = devm_nvmem_register(dev, &nvmem_config); 1057 if (IS_ERR(nvm->nvmem)) 1058 return PTR_ERR(nvm->nvmem); 1059 1060 ov2740->nvm = nvm; 1061 return 0; 1062 } 1063 1064 static int ov2740_probe(struct i2c_client *client) 1065 { 1066 struct device *dev = &client->dev; 1067 struct ov2740 *ov2740; 1068 bool full_power; 1069 int ret; 1070 1071 ret = ov2740_check_hwcfg(&client->dev); 1072 if (ret) 1073 return dev_err_probe(dev, ret, "failed to check HW configuration\n"); 1074 1075 ov2740 = devm_kzalloc(&client->dev, sizeof(*ov2740), GFP_KERNEL); 1076 if (!ov2740) 1077 return -ENOMEM; 1078 1079 v4l2_i2c_subdev_init(&ov2740->sd, client, &ov2740_subdev_ops); 1080 ov2740->sd.internal_ops = &ov2740_internal_ops; 1081 full_power = acpi_dev_state_d0(&client->dev); 1082 if (full_power) { 1083 ret = ov2740_identify_module(ov2740); 1084 if (ret) 1085 return dev_err_probe(dev, ret, "failed to find sensor\n"); 1086 } 1087 1088 ov2740->cur_mode = &supported_modes[0]; 1089 ret = ov2740_init_controls(ov2740); 1090 if (ret) { 1091 dev_err_probe(dev, ret, "failed to init controls\n"); 1092 goto probe_error_v4l2_ctrl_handler_free; 1093 } 1094 1095 ov2740->sd.state_lock = ov2740->ctrl_handler.lock; 1096 ov2740->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1097 ov2740->sd.entity.ops = &ov2740_subdev_entity_ops; 1098 ov2740->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1099 ov2740->pad.flags = MEDIA_PAD_FL_SOURCE; 1100 ret = media_entity_pads_init(&ov2740->sd.entity, 1, &ov2740->pad); 1101 if (ret) { 1102 dev_err_probe(dev, ret, "failed to init entity pads\n"); 1103 goto probe_error_v4l2_ctrl_handler_free; 1104 } 1105 1106 ret = v4l2_subdev_init_finalize(&ov2740->sd); 1107 if (ret) 1108 goto probe_error_media_entity_cleanup; 1109 1110 /* Set the device's state to active if it's in D0 state. */ 1111 if (full_power) 1112 pm_runtime_set_active(&client->dev); 1113 pm_runtime_enable(&client->dev); 1114 pm_runtime_idle(&client->dev); 1115 1116 ret = v4l2_async_register_subdev_sensor(&ov2740->sd); 1117 if (ret < 0) { 1118 dev_err_probe(dev, ret, "failed to register V4L2 subdev\n"); 1119 goto probe_error_v4l2_subdev_cleanup; 1120 } 1121 1122 ret = ov2740_register_nvmem(client, ov2740); 1123 if (ret) 1124 dev_warn(&client->dev, "register nvmem failed, ret %d\n", ret); 1125 1126 return 0; 1127 1128 probe_error_v4l2_subdev_cleanup: 1129 v4l2_subdev_cleanup(&ov2740->sd); 1130 1131 probe_error_media_entity_cleanup: 1132 media_entity_cleanup(&ov2740->sd.entity); 1133 pm_runtime_disable(&client->dev); 1134 pm_runtime_set_suspended(&client->dev); 1135 1136 probe_error_v4l2_ctrl_handler_free: 1137 v4l2_ctrl_handler_free(ov2740->sd.ctrl_handler); 1138 1139 return ret; 1140 } 1141 1142 static const struct acpi_device_id ov2740_acpi_ids[] = { 1143 {"INT3474"}, 1144 {} 1145 }; 1146 1147 MODULE_DEVICE_TABLE(acpi, ov2740_acpi_ids); 1148 1149 static struct i2c_driver ov2740_i2c_driver = { 1150 .driver = { 1151 .name = "ov2740", 1152 .acpi_match_table = ov2740_acpi_ids, 1153 }, 1154 .probe = ov2740_probe, 1155 .remove = ov2740_remove, 1156 .flags = I2C_DRV_ACPI_WAIVE_D0_PROBE, 1157 }; 1158 1159 module_i2c_driver(ov2740_i2c_driver); 1160 1161 MODULE_AUTHOR("Qiu, Tianshu <tian.shu.qiu@intel.com>"); 1162 MODULE_AUTHOR("Shawn Tu"); 1163 MODULE_AUTHOR("Bingbu Cao <bingbu.cao@intel.com>"); 1164 MODULE_DESCRIPTION("OmniVision OV2740 sensor driver"); 1165 MODULE_LICENSE("GPL v2"); 1166