1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2020 Intel Corporation. 3 4 #include <linux/unaligned.h> 5 #include <linux/acpi.h> 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/gpio/consumer.h> 9 #include <linux/i2c.h> 10 #include <linux/module.h> 11 #include <linux/pm_runtime.h> 12 #include <linux/nvmem-provider.h> 13 #include <linux/regmap.h> 14 #include <linux/regulator/consumer.h> 15 #include <media/v4l2-ctrls.h> 16 #include <media/v4l2-device.h> 17 #include <media/v4l2-fwnode.h> 18 19 #define OV2740_LINK_FREQ_360MHZ 360000000ULL 20 #define OV2740_LINK_FREQ_180MHZ 180000000ULL 21 #define OV2740_SCLK 72000000LL 22 #define OV2740_MCLK 19200000 23 #define OV2740_DATA_LANES 2 24 #define OV2740_RGB_DEPTH 10 25 26 #define OV2740_REG_CHIP_ID 0x300a 27 #define OV2740_CHIP_ID 0x2740 28 29 #define OV2740_REG_MODE_SELECT 0x0100 30 #define OV2740_MODE_STANDBY 0x00 31 #define OV2740_MODE_STREAMING 0x01 32 33 /* vertical-timings from sensor */ 34 #define OV2740_REG_VTS 0x380e 35 36 /* horizontal-timings from sensor */ 37 #define OV2740_REG_HTS 0x380c 38 39 /* Exposure controls from sensor */ 40 #define OV2740_REG_EXPOSURE 0x3500 41 #define OV2740_EXPOSURE_MIN 4 42 #define OV2740_EXPOSURE_MAX_MARGIN 8 43 #define OV2740_EXPOSURE_STEP 1 44 45 /* Analog gain controls from sensor */ 46 #define OV2740_REG_ANALOG_GAIN 0x3508 47 #define OV2740_ANAL_GAIN_MIN 128 48 #define OV2740_ANAL_GAIN_MAX 1983 49 #define OV2740_ANAL_GAIN_STEP 1 50 51 /* Digital gain controls from sensor */ 52 #define OV2740_REG_MWB_R_GAIN 0x500a 53 #define OV2740_REG_MWB_G_GAIN 0x500c 54 #define OV2740_REG_MWB_B_GAIN 0x500e 55 #define OV2740_DGTL_GAIN_MIN 1024 56 #define OV2740_DGTL_GAIN_MAX 4095 57 #define OV2740_DGTL_GAIN_STEP 1 58 #define OV2740_DGTL_GAIN_DEFAULT 1024 59 60 /* Test Pattern Control */ 61 #define OV2740_REG_TEST_PATTERN 0x5040 62 #define OV2740_TEST_PATTERN_ENABLE BIT(7) 63 #define OV2740_TEST_PATTERN_BAR_SHIFT 2 64 65 /* Group Access */ 66 #define OV2740_REG_GROUP_ACCESS 0x3208 67 #define OV2740_GROUP_HOLD_START 0x0 68 #define OV2740_GROUP_HOLD_END 0x10 69 #define OV2740_GROUP_HOLD_LAUNCH 0xa0 70 71 /* ISP CTRL00 */ 72 #define OV2740_REG_ISP_CTRL00 0x5000 73 /* ISP CTRL01 */ 74 #define OV2740_REG_ISP_CTRL01 0x5001 75 /* Customer Addresses: 0x7010 - 0x710F */ 76 #define CUSTOMER_USE_OTP_SIZE 0x100 77 /* OTP registers from sensor */ 78 #define OV2740_REG_OTP_CUSTOMER 0x7010 79 80 static const char * const ov2740_supply_name[] = { 81 "AVDD", 82 "DOVDD", 83 "DVDD", 84 }; 85 86 struct nvm_data { 87 struct nvmem_device *nvmem; 88 struct regmap *regmap; 89 char *nvm_buffer; 90 }; 91 92 enum { 93 OV2740_LINK_FREQ_360MHZ_INDEX, 94 OV2740_LINK_FREQ_180MHZ_INDEX, 95 }; 96 97 struct ov2740_reg { 98 u16 address; 99 u8 val; 100 }; 101 102 struct ov2740_reg_list { 103 u32 num_of_regs; 104 const struct ov2740_reg *regs; 105 }; 106 107 struct ov2740_link_freq_config { 108 const struct ov2740_reg_list reg_list; 109 }; 110 111 struct ov2740_mode { 112 /* Frame width in pixels */ 113 u32 width; 114 115 /* Frame height in pixels */ 116 u32 height; 117 118 /* Horizontal timining size */ 119 u32 hts; 120 121 /* Default vertical timining size */ 122 u32 vts_def; 123 124 /* Min vertical timining size */ 125 u32 vts_min; 126 127 /* Max vertical timining size */ 128 u32 vts_max; 129 130 /* Link frequency needed for this resolution */ 131 u32 link_freq_index; 132 133 /* Sensor register settings for this resolution */ 134 const struct ov2740_reg_list reg_list; 135 }; 136 137 static const struct ov2740_reg mipi_data_rate_720mbps[] = { 138 {0x0302, 0x4b}, 139 {0x030d, 0x4b}, 140 {0x030e, 0x02}, 141 {0x030a, 0x01}, 142 {0x0312, 0x11}, 143 }; 144 145 static const struct ov2740_reg mipi_data_rate_360mbps[] = { 146 {0x0302, 0x4b}, 147 {0x0303, 0x01}, 148 {0x030d, 0x4b}, 149 {0x030e, 0x02}, 150 {0x030a, 0x01}, 151 {0x0312, 0x11}, 152 {0x4837, 0x2c}, 153 }; 154 155 static const struct ov2740_reg mode_1932x1092_regs_360mhz[] = { 156 {0x3000, 0x00}, 157 {0x3018, 0x32}, 158 {0x3031, 0x0a}, 159 {0x3080, 0x08}, 160 {0x3083, 0xB4}, 161 {0x3103, 0x00}, 162 {0x3104, 0x01}, 163 {0x3106, 0x01}, 164 {0x3500, 0x00}, 165 {0x3501, 0x44}, 166 {0x3502, 0x40}, 167 {0x3503, 0x88}, 168 {0x3507, 0x00}, 169 {0x3508, 0x00}, 170 {0x3509, 0x80}, 171 {0x350c, 0x00}, 172 {0x350d, 0x80}, 173 {0x3510, 0x00}, 174 {0x3511, 0x00}, 175 {0x3512, 0x20}, 176 {0x3632, 0x00}, 177 {0x3633, 0x10}, 178 {0x3634, 0x10}, 179 {0x3635, 0x10}, 180 {0x3645, 0x13}, 181 {0x3646, 0x81}, 182 {0x3636, 0x10}, 183 {0x3651, 0x0a}, 184 {0x3656, 0x02}, 185 {0x3659, 0x04}, 186 {0x365a, 0xda}, 187 {0x365b, 0xa2}, 188 {0x365c, 0x04}, 189 {0x365d, 0x1d}, 190 {0x365e, 0x1a}, 191 {0x3662, 0xd7}, 192 {0x3667, 0x78}, 193 {0x3669, 0x0a}, 194 {0x366a, 0x92}, 195 {0x3700, 0x54}, 196 {0x3702, 0x10}, 197 {0x3706, 0x42}, 198 {0x3709, 0x30}, 199 {0x370b, 0xc2}, 200 {0x3714, 0x63}, 201 {0x3715, 0x01}, 202 {0x3716, 0x00}, 203 {0x371a, 0x3e}, 204 {0x3732, 0x0e}, 205 {0x3733, 0x10}, 206 {0x375f, 0x0e}, 207 {0x3768, 0x30}, 208 {0x3769, 0x44}, 209 {0x376a, 0x22}, 210 {0x377b, 0x20}, 211 {0x377c, 0x00}, 212 {0x377d, 0x0c}, 213 {0x3798, 0x00}, 214 {0x37a1, 0x55}, 215 {0x37a8, 0x6d}, 216 {0x37c2, 0x04}, 217 {0x37c5, 0x00}, 218 {0x37c8, 0x00}, 219 {0x3800, 0x00}, 220 {0x3801, 0x00}, 221 {0x3802, 0x00}, 222 {0x3803, 0x00}, 223 {0x3804, 0x07}, 224 {0x3805, 0x8f}, 225 {0x3806, 0x04}, 226 {0x3807, 0x47}, 227 {0x3808, 0x07}, 228 {0x3809, 0x88}, 229 {0x380a, 0x04}, 230 {0x380b, 0x40}, 231 {0x380c, 0x04}, 232 {0x380d, 0x38}, 233 {0x380e, 0x04}, 234 {0x380f, 0x60}, 235 {0x3810, 0x00}, 236 {0x3811, 0x04}, 237 {0x3812, 0x00}, 238 {0x3813, 0x04}, 239 {0x3814, 0x01}, 240 {0x3815, 0x01}, 241 {0x3820, 0x80}, 242 {0x3821, 0x46}, 243 {0x3822, 0x84}, 244 {0x3829, 0x00}, 245 {0x382a, 0x01}, 246 {0x382b, 0x01}, 247 {0x3830, 0x04}, 248 {0x3836, 0x01}, 249 {0x3837, 0x08}, 250 {0x3839, 0x01}, 251 {0x383a, 0x00}, 252 {0x383b, 0x08}, 253 {0x383c, 0x00}, 254 {0x3f0b, 0x00}, 255 {0x4001, 0x20}, 256 {0x4009, 0x07}, 257 {0x4003, 0x10}, 258 {0x4010, 0xe0}, 259 {0x4016, 0x00}, 260 {0x4017, 0x10}, 261 {0x4044, 0x02}, 262 {0x4304, 0x08}, 263 {0x4307, 0x30}, 264 {0x4320, 0x80}, 265 {0x4322, 0x00}, 266 {0x4323, 0x00}, 267 {0x4324, 0x00}, 268 {0x4325, 0x00}, 269 {0x4326, 0x00}, 270 {0x4327, 0x00}, 271 {0x4328, 0x00}, 272 {0x4329, 0x00}, 273 {0x432c, 0x03}, 274 {0x432d, 0x81}, 275 {0x4501, 0x84}, 276 {0x4502, 0x40}, 277 {0x4503, 0x18}, 278 {0x4504, 0x04}, 279 {0x4508, 0x02}, 280 {0x4601, 0x10}, 281 {0x4800, 0x00}, 282 {0x4816, 0x52}, 283 {0x4837, 0x16}, 284 {0x5000, 0x7f}, 285 {0x5001, 0x00}, 286 {0x5005, 0x38}, 287 {0x501e, 0x0d}, 288 {0x5040, 0x00}, 289 {0x5901, 0x00}, 290 {0x3800, 0x00}, 291 {0x3801, 0x00}, 292 {0x3802, 0x00}, 293 {0x3803, 0x00}, 294 {0x3804, 0x07}, 295 {0x3805, 0x8f}, 296 {0x3806, 0x04}, 297 {0x3807, 0x47}, 298 {0x3808, 0x07}, 299 {0x3809, 0x8c}, 300 {0x380a, 0x04}, 301 {0x380b, 0x44}, 302 {0x3810, 0x00}, 303 {0x3811, 0x00}, 304 {0x3812, 0x00}, 305 {0x3813, 0x01}, 306 }; 307 308 static const struct ov2740_reg mode_1932x1092_regs_180mhz[] = { 309 {0x3000, 0x00}, 310 {0x3018, 0x32}, /* 0x32 for 2 lanes, 0x12 for 1 lane */ 311 {0x3031, 0x0a}, 312 {0x3080, 0x08}, 313 {0x3083, 0xB4}, 314 {0x3103, 0x00}, 315 {0x3104, 0x01}, 316 {0x3106, 0x01}, 317 {0x3500, 0x00}, 318 {0x3501, 0x44}, 319 {0x3502, 0x40}, 320 {0x3503, 0x88}, 321 {0x3507, 0x00}, 322 {0x3508, 0x00}, 323 {0x3509, 0x80}, 324 {0x350c, 0x00}, 325 {0x350d, 0x80}, 326 {0x3510, 0x00}, 327 {0x3511, 0x00}, 328 {0x3512, 0x20}, 329 {0x3632, 0x00}, 330 {0x3633, 0x10}, 331 {0x3634, 0x10}, 332 {0x3635, 0x10}, 333 {0x3645, 0x13}, 334 {0x3646, 0x81}, 335 {0x3636, 0x10}, 336 {0x3651, 0x0a}, 337 {0x3656, 0x02}, 338 {0x3659, 0x04}, 339 {0x365a, 0xda}, 340 {0x365b, 0xa2}, 341 {0x365c, 0x04}, 342 {0x365d, 0x1d}, 343 {0x365e, 0x1a}, 344 {0x3662, 0xd7}, 345 {0x3667, 0x78}, 346 {0x3669, 0x0a}, 347 {0x366a, 0x92}, 348 {0x3700, 0x54}, 349 {0x3702, 0x10}, 350 {0x3706, 0x42}, 351 {0x3709, 0x30}, 352 {0x370b, 0xc2}, 353 {0x3714, 0x63}, 354 {0x3715, 0x01}, 355 {0x3716, 0x00}, 356 {0x371a, 0x3e}, 357 {0x3732, 0x0e}, 358 {0x3733, 0x10}, 359 {0x375f, 0x0e}, 360 {0x3768, 0x30}, 361 {0x3769, 0x44}, 362 {0x376a, 0x22}, 363 {0x377b, 0x20}, 364 {0x377c, 0x00}, 365 {0x377d, 0x0c}, 366 {0x3798, 0x00}, 367 {0x37a1, 0x55}, 368 {0x37a8, 0x6d}, 369 {0x37c2, 0x04}, 370 {0x37c5, 0x00}, 371 {0x37c8, 0x00}, 372 {0x3800, 0x00}, 373 {0x3801, 0x00}, 374 {0x3802, 0x00}, 375 {0x3803, 0x00}, 376 {0x3804, 0x07}, 377 {0x3805, 0x8f}, 378 {0x3806, 0x04}, 379 {0x3807, 0x47}, 380 {0x3808, 0x07}, 381 {0x3809, 0x88}, 382 {0x380a, 0x04}, 383 {0x380b, 0x40}, 384 {0x380c, 0x08}, 385 {0x380d, 0x70}, 386 {0x380e, 0x04}, 387 {0x380f, 0x56}, 388 {0x3810, 0x00}, 389 {0x3811, 0x04}, 390 {0x3812, 0x00}, 391 {0x3813, 0x04}, 392 {0x3814, 0x01}, 393 {0x3815, 0x01}, 394 {0x3820, 0x80}, 395 {0x3821, 0x46}, 396 {0x3822, 0x84}, 397 {0x3829, 0x00}, 398 {0x382a, 0x01}, 399 {0x382b, 0x01}, 400 {0x3830, 0x04}, 401 {0x3836, 0x01}, 402 {0x3837, 0x08}, 403 {0x3839, 0x01}, 404 {0x383a, 0x00}, 405 {0x383b, 0x08}, 406 {0x383c, 0x00}, 407 {0x3f0b, 0x00}, 408 {0x4001, 0x20}, 409 {0x4009, 0x07}, 410 {0x4003, 0x10}, 411 {0x4010, 0xe0}, 412 {0x4016, 0x00}, 413 {0x4017, 0x10}, 414 {0x4044, 0x02}, 415 {0x4304, 0x08}, 416 {0x4307, 0x30}, 417 {0x4320, 0x80}, 418 {0x4322, 0x00}, 419 {0x4323, 0x00}, 420 {0x4324, 0x00}, 421 {0x4325, 0x00}, 422 {0x4326, 0x00}, 423 {0x4327, 0x00}, 424 {0x4328, 0x00}, 425 {0x4329, 0x00}, 426 {0x432c, 0x03}, 427 {0x432d, 0x81}, 428 {0x4501, 0x84}, 429 {0x4502, 0x40}, 430 {0x4503, 0x18}, 431 {0x4504, 0x04}, 432 {0x4508, 0x02}, 433 {0x4601, 0x10}, 434 {0x4800, 0x00}, 435 {0x4816, 0x52}, 436 {0x5000, 0x73}, /* 0x7f enable DPC */ 437 {0x5001, 0x00}, 438 {0x5005, 0x38}, 439 {0x501e, 0x0d}, 440 {0x5040, 0x00}, 441 {0x5901, 0x00}, 442 {0x3800, 0x00}, 443 {0x3801, 0x00}, 444 {0x3802, 0x00}, 445 {0x3803, 0x00}, 446 {0x3804, 0x07}, 447 {0x3805, 0x8f}, 448 {0x3806, 0x04}, 449 {0x3807, 0x47}, 450 {0x3808, 0x07}, 451 {0x3809, 0x8c}, 452 {0x380a, 0x04}, 453 {0x380b, 0x44}, 454 {0x3810, 0x00}, 455 {0x3811, 0x00}, 456 {0x3812, 0x00}, 457 {0x3813, 0x01}, 458 {0x4003, 0x40}, /* set Black level to 0x40 */ 459 }; 460 461 static const char * const ov2740_test_pattern_menu[] = { 462 "Disabled", 463 "Color Bar", 464 "Top-Bottom Darker Color Bar", 465 "Right-Left Darker Color Bar", 466 "Bottom-Top Darker Color Bar", 467 }; 468 469 static const s64 link_freq_menu_items[] = { 470 OV2740_LINK_FREQ_360MHZ, 471 OV2740_LINK_FREQ_180MHZ, 472 }; 473 474 static const struct ov2740_link_freq_config link_freq_configs[] = { 475 [OV2740_LINK_FREQ_360MHZ_INDEX] = { 476 .reg_list = { 477 .num_of_regs = ARRAY_SIZE(mipi_data_rate_720mbps), 478 .regs = mipi_data_rate_720mbps, 479 } 480 }, 481 [OV2740_LINK_FREQ_180MHZ_INDEX] = { 482 .reg_list = { 483 .num_of_regs = ARRAY_SIZE(mipi_data_rate_360mbps), 484 .regs = mipi_data_rate_360mbps, 485 } 486 }, 487 }; 488 489 static const struct ov2740_mode supported_modes_360mhz[] = { 490 { 491 .width = 1932, 492 .height = 1092, 493 .hts = 2160, 494 .vts_min = 1120, 495 .vts_def = 2186, 496 .vts_max = 32767, 497 .reg_list = { 498 .num_of_regs = ARRAY_SIZE(mode_1932x1092_regs_360mhz), 499 .regs = mode_1932x1092_regs_360mhz, 500 }, 501 .link_freq_index = OV2740_LINK_FREQ_360MHZ_INDEX, 502 }, 503 }; 504 505 static const struct ov2740_mode supported_modes_180mhz[] = { 506 { 507 .width = 1932, 508 .height = 1092, 509 .hts = 2160, 510 .vts_min = 1110, 511 .vts_def = 1110, 512 .vts_max = 2047, 513 .reg_list = { 514 .num_of_regs = ARRAY_SIZE(mode_1932x1092_regs_180mhz), 515 .regs = mode_1932x1092_regs_180mhz, 516 }, 517 .link_freq_index = OV2740_LINK_FREQ_180MHZ_INDEX, 518 }, 519 }; 520 521 struct ov2740 { 522 struct v4l2_subdev sd; 523 struct media_pad pad; 524 struct v4l2_ctrl_handler ctrl_handler; 525 526 /* V4L2 Controls */ 527 struct v4l2_ctrl *link_freq; 528 struct v4l2_ctrl *pixel_rate; 529 struct v4l2_ctrl *vblank; 530 struct v4l2_ctrl *hblank; 531 struct v4l2_ctrl *exposure; 532 533 /* GPIOs, clocks, regulators */ 534 struct gpio_desc *reset_gpio; 535 struct gpio_desc *powerdown_gpio; 536 struct clk *clk; 537 struct regulator_bulk_data supplies[ARRAY_SIZE(ov2740_supply_name)]; 538 539 /* Current mode */ 540 const struct ov2740_mode *cur_mode; 541 542 /* NVM data information */ 543 struct nvm_data *nvm; 544 545 /* Supported modes */ 546 const struct ov2740_mode *supported_modes; 547 int supported_modes_count; 548 549 /* True if the device has been identified */ 550 bool identified; 551 }; 552 553 static inline struct ov2740 *to_ov2740(struct v4l2_subdev *subdev) 554 { 555 return container_of(subdev, struct ov2740, sd); 556 } 557 558 static u64 to_pixel_rate(u32 f_index) 559 { 560 u64 pixel_rate = link_freq_menu_items[f_index] * 2 * OV2740_DATA_LANES; 561 562 do_div(pixel_rate, OV2740_RGB_DEPTH); 563 564 return pixel_rate; 565 } 566 567 static int ov2740_read_reg(struct ov2740 *ov2740, u16 reg, u16 len, u32 *val) 568 { 569 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 570 struct i2c_msg msgs[2]; 571 u8 addr_buf[2]; 572 u8 data_buf[4] = {0}; 573 int ret; 574 575 if (len > sizeof(data_buf)) 576 return -EINVAL; 577 578 put_unaligned_be16(reg, addr_buf); 579 msgs[0].addr = client->addr; 580 msgs[0].flags = 0; 581 msgs[0].len = sizeof(addr_buf); 582 msgs[0].buf = addr_buf; 583 msgs[1].addr = client->addr; 584 msgs[1].flags = I2C_M_RD; 585 msgs[1].len = len; 586 msgs[1].buf = &data_buf[sizeof(data_buf) - len]; 587 588 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); 589 if (ret != ARRAY_SIZE(msgs)) 590 return ret < 0 ? ret : -EIO; 591 592 *val = get_unaligned_be32(data_buf); 593 594 return 0; 595 } 596 597 static int ov2740_write_reg(struct ov2740 *ov2740, u16 reg, u16 len, u32 val) 598 { 599 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 600 u8 buf[6]; 601 int ret; 602 603 if (len > 4) 604 return -EINVAL; 605 606 put_unaligned_be16(reg, buf); 607 put_unaligned_be32(val << 8 * (4 - len), buf + 2); 608 609 ret = i2c_master_send(client, buf, len + 2); 610 if (ret != len + 2) 611 return ret < 0 ? ret : -EIO; 612 613 return 0; 614 } 615 616 static int ov2740_write_reg_list(struct ov2740 *ov2740, 617 const struct ov2740_reg_list *r_list) 618 { 619 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 620 unsigned int i; 621 int ret; 622 623 for (i = 0; i < r_list->num_of_regs; i++) { 624 ret = ov2740_write_reg(ov2740, r_list->regs[i].address, 1, 625 r_list->regs[i].val); 626 if (ret) { 627 dev_err_ratelimited(&client->dev, 628 "write reg 0x%4.4x return err = %d\n", 629 r_list->regs[i].address, ret); 630 return ret; 631 } 632 } 633 634 return 0; 635 } 636 637 static int ov2740_identify_module(struct ov2740 *ov2740) 638 { 639 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 640 int ret; 641 u32 val; 642 643 if (ov2740->identified) 644 return 0; 645 646 ret = ov2740_read_reg(ov2740, OV2740_REG_CHIP_ID, 3, &val); 647 if (ret) 648 return ret; 649 650 if (val != OV2740_CHIP_ID) { 651 dev_err(&client->dev, "chip id mismatch: %x != %x\n", 652 OV2740_CHIP_ID, val); 653 return -ENXIO; 654 } 655 656 dev_dbg(&client->dev, "chip id: 0x%x\n", val); 657 658 ov2740->identified = true; 659 660 return 0; 661 } 662 663 static int ov2740_update_digital_gain(struct ov2740 *ov2740, u32 d_gain) 664 { 665 int ret; 666 667 ret = ov2740_write_reg(ov2740, OV2740_REG_GROUP_ACCESS, 1, 668 OV2740_GROUP_HOLD_START); 669 if (ret) 670 return ret; 671 672 ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_R_GAIN, 2, d_gain); 673 if (ret) 674 return ret; 675 676 ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_G_GAIN, 2, d_gain); 677 if (ret) 678 return ret; 679 680 ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_B_GAIN, 2, d_gain); 681 if (ret) 682 return ret; 683 684 ret = ov2740_write_reg(ov2740, OV2740_REG_GROUP_ACCESS, 1, 685 OV2740_GROUP_HOLD_END); 686 if (ret) 687 return ret; 688 689 ret = ov2740_write_reg(ov2740, OV2740_REG_GROUP_ACCESS, 1, 690 OV2740_GROUP_HOLD_LAUNCH); 691 return ret; 692 } 693 694 static int ov2740_test_pattern(struct ov2740 *ov2740, u32 pattern) 695 { 696 if (pattern) 697 pattern = (pattern - 1) << OV2740_TEST_PATTERN_BAR_SHIFT | 698 OV2740_TEST_PATTERN_ENABLE; 699 700 return ov2740_write_reg(ov2740, OV2740_REG_TEST_PATTERN, 1, pattern); 701 } 702 703 static int ov2740_set_ctrl(struct v4l2_ctrl *ctrl) 704 { 705 struct ov2740 *ov2740 = container_of(ctrl->handler, 706 struct ov2740, ctrl_handler); 707 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 708 s64 exposure_max; 709 int ret; 710 711 /* Propagate change of current control to all related controls */ 712 if (ctrl->id == V4L2_CID_VBLANK) { 713 /* Update max exposure while meeting expected vblanking */ 714 exposure_max = ov2740->cur_mode->height + ctrl->val - 715 OV2740_EXPOSURE_MAX_MARGIN; 716 __v4l2_ctrl_modify_range(ov2740->exposure, 717 ov2740->exposure->minimum, 718 exposure_max, ov2740->exposure->step, 719 exposure_max); 720 } 721 722 /* V4L2 controls values will be applied only when power is already up */ 723 if (!pm_runtime_get_if_in_use(&client->dev)) 724 return 0; 725 726 switch (ctrl->id) { 727 case V4L2_CID_ANALOGUE_GAIN: 728 ret = ov2740_write_reg(ov2740, OV2740_REG_ANALOG_GAIN, 2, 729 ctrl->val); 730 break; 731 732 case V4L2_CID_DIGITAL_GAIN: 733 ret = ov2740_update_digital_gain(ov2740, ctrl->val); 734 break; 735 736 case V4L2_CID_EXPOSURE: 737 /* 4 least significant bits of expsoure are fractional part */ 738 ret = ov2740_write_reg(ov2740, OV2740_REG_EXPOSURE, 3, 739 ctrl->val << 4); 740 break; 741 742 case V4L2_CID_VBLANK: 743 ret = ov2740_write_reg(ov2740, OV2740_REG_VTS, 2, 744 ov2740->cur_mode->height + ctrl->val); 745 break; 746 747 case V4L2_CID_TEST_PATTERN: 748 ret = ov2740_test_pattern(ov2740, ctrl->val); 749 break; 750 751 default: 752 ret = -EINVAL; 753 break; 754 } 755 756 pm_runtime_put(&client->dev); 757 758 return ret; 759 } 760 761 static const struct v4l2_ctrl_ops ov2740_ctrl_ops = { 762 .s_ctrl = ov2740_set_ctrl, 763 }; 764 765 static int ov2740_init_controls(struct ov2740 *ov2740) 766 { 767 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 768 struct v4l2_ctrl_handler *ctrl_hdlr; 769 s64 exposure_max, h_blank, pixel_rate; 770 u32 vblank_min, vblank_max, vblank_default; 771 struct v4l2_fwnode_device_properties props; 772 int ret; 773 774 ctrl_hdlr = &ov2740->ctrl_handler; 775 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 10); 776 if (ret) 777 return ret; 778 779 ov2740->link_freq = 780 v4l2_ctrl_new_int_menu(ctrl_hdlr, &ov2740_ctrl_ops, 781 V4L2_CID_LINK_FREQ, 782 ARRAY_SIZE(link_freq_menu_items) - 1, 783 ov2740->supported_modes->link_freq_index, 784 link_freq_menu_items); 785 if (ov2740->link_freq) 786 ov2740->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; 787 788 pixel_rate = to_pixel_rate(ov2740->supported_modes->link_freq_index); 789 ov2740->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, 790 V4L2_CID_PIXEL_RATE, 0, 791 pixel_rate, 1, pixel_rate); 792 793 vblank_min = ov2740->cur_mode->vts_min - ov2740->cur_mode->height; 794 vblank_max = ov2740->cur_mode->vts_max - ov2740->cur_mode->height; 795 vblank_default = ov2740->cur_mode->vts_def - ov2740->cur_mode->height; 796 ov2740->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, 797 V4L2_CID_VBLANK, vblank_min, 798 vblank_max, 1, vblank_default); 799 800 h_blank = ov2740->cur_mode->hts - ov2740->cur_mode->width; 801 ov2740->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, 802 V4L2_CID_HBLANK, h_blank, h_blank, 1, 803 h_blank); 804 if (ov2740->hblank) 805 ov2740->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; 806 807 v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, 808 OV2740_ANAL_GAIN_MIN, OV2740_ANAL_GAIN_MAX, 809 OV2740_ANAL_GAIN_STEP, OV2740_ANAL_GAIN_MIN); 810 v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, V4L2_CID_DIGITAL_GAIN, 811 OV2740_DGTL_GAIN_MIN, OV2740_DGTL_GAIN_MAX, 812 OV2740_DGTL_GAIN_STEP, OV2740_DGTL_GAIN_DEFAULT); 813 exposure_max = ov2740->cur_mode->vts_def - OV2740_EXPOSURE_MAX_MARGIN; 814 ov2740->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, 815 V4L2_CID_EXPOSURE, 816 OV2740_EXPOSURE_MIN, exposure_max, 817 OV2740_EXPOSURE_STEP, 818 exposure_max); 819 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov2740_ctrl_ops, 820 V4L2_CID_TEST_PATTERN, 821 ARRAY_SIZE(ov2740_test_pattern_menu) - 1, 822 0, 0, ov2740_test_pattern_menu); 823 824 ret = v4l2_fwnode_device_parse(&client->dev, &props); 825 if (ret) { 826 v4l2_ctrl_handler_free(ctrl_hdlr); 827 return ret; 828 } 829 830 v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &ov2740_ctrl_ops, &props); 831 832 if (ctrl_hdlr->error) { 833 v4l2_ctrl_handler_free(ctrl_hdlr); 834 return ctrl_hdlr->error; 835 } 836 837 ov2740->sd.ctrl_handler = ctrl_hdlr; 838 839 return 0; 840 } 841 842 static void ov2740_update_pad_format(const struct ov2740_mode *mode, 843 struct v4l2_mbus_framefmt *fmt) 844 { 845 fmt->width = mode->width; 846 fmt->height = mode->height; 847 fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10; 848 fmt->field = V4L2_FIELD_NONE; 849 } 850 851 static int ov2740_load_otp_data(struct nvm_data *nvm) 852 { 853 struct device *dev = regmap_get_device(nvm->regmap); 854 struct ov2740 *ov2740 = to_ov2740(dev_get_drvdata(dev)); 855 u32 isp_ctrl00 = 0; 856 u32 isp_ctrl01 = 0; 857 int ret; 858 859 if (nvm->nvm_buffer) 860 return 0; 861 862 nvm->nvm_buffer = kzalloc(CUSTOMER_USE_OTP_SIZE, GFP_KERNEL); 863 if (!nvm->nvm_buffer) 864 return -ENOMEM; 865 866 ret = ov2740_read_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, &isp_ctrl00); 867 if (ret) { 868 dev_err(dev, "failed to read ISP CTRL00\n"); 869 goto err; 870 } 871 872 ret = ov2740_read_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, &isp_ctrl01); 873 if (ret) { 874 dev_err(dev, "failed to read ISP CTRL01\n"); 875 goto err; 876 } 877 878 /* Clear bit 5 of ISP CTRL00 */ 879 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, 880 isp_ctrl00 & ~BIT(5)); 881 if (ret) { 882 dev_err(dev, "failed to set ISP CTRL00\n"); 883 goto err; 884 } 885 886 /* Clear bit 7 of ISP CTRL01 */ 887 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, 888 isp_ctrl01 & ~BIT(7)); 889 if (ret) { 890 dev_err(dev, "failed to set ISP CTRL01\n"); 891 goto err; 892 } 893 894 ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1, 895 OV2740_MODE_STREAMING); 896 if (ret) { 897 dev_err(dev, "failed to set streaming mode\n"); 898 goto err; 899 } 900 901 /* 902 * Users are not allowed to access OTP-related registers and memory 903 * during the 20 ms period after streaming starts (0x100 = 0x01). 904 */ 905 msleep(20); 906 907 ret = regmap_bulk_read(nvm->regmap, OV2740_REG_OTP_CUSTOMER, 908 nvm->nvm_buffer, CUSTOMER_USE_OTP_SIZE); 909 if (ret) { 910 dev_err(dev, "failed to read OTP data, ret %d\n", ret); 911 goto err; 912 } 913 914 ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1, 915 OV2740_MODE_STANDBY); 916 if (ret) { 917 dev_err(dev, "failed to set streaming mode\n"); 918 goto err; 919 } 920 921 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, isp_ctrl01); 922 if (ret) { 923 dev_err(dev, "failed to set ISP CTRL01\n"); 924 goto err; 925 } 926 927 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, isp_ctrl00); 928 if (ret) { 929 dev_err(dev, "failed to set ISP CTRL00\n"); 930 goto err; 931 } 932 933 return 0; 934 err: 935 kfree(nvm->nvm_buffer); 936 nvm->nvm_buffer = NULL; 937 938 return ret; 939 } 940 941 static int ov2740_start_streaming(struct ov2740 *ov2740) 942 { 943 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 944 const struct ov2740_reg_list *reg_list; 945 int link_freq_index; 946 int ret; 947 948 ret = ov2740_identify_module(ov2740); 949 if (ret) 950 return ret; 951 952 if (ov2740->nvm) 953 ov2740_load_otp_data(ov2740->nvm); 954 955 /* Reset the sensor */ 956 ret = ov2740_write_reg(ov2740, 0x0103, 1, 0x01); 957 if (ret) { 958 dev_err(&client->dev, "failed to reset\n"); 959 return ret; 960 } 961 962 usleep_range(10000, 15000); 963 964 link_freq_index = ov2740->cur_mode->link_freq_index; 965 reg_list = &link_freq_configs[link_freq_index].reg_list; 966 ret = ov2740_write_reg_list(ov2740, reg_list); 967 if (ret) { 968 dev_err(&client->dev, "failed to set plls\n"); 969 return ret; 970 } 971 972 reg_list = &ov2740->cur_mode->reg_list; 973 ret = ov2740_write_reg_list(ov2740, reg_list); 974 if (ret) { 975 dev_err(&client->dev, "failed to set mode\n"); 976 return ret; 977 } 978 979 ret = __v4l2_ctrl_handler_setup(ov2740->sd.ctrl_handler); 980 if (ret) 981 return ret; 982 983 ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1, 984 OV2740_MODE_STREAMING); 985 if (ret) 986 dev_err(&client->dev, "failed to start streaming\n"); 987 988 return ret; 989 } 990 991 static void ov2740_stop_streaming(struct ov2740 *ov2740) 992 { 993 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 994 995 if (ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1, 996 OV2740_MODE_STANDBY)) 997 dev_err(&client->dev, "failed to stop streaming\n"); 998 } 999 1000 static int ov2740_set_stream(struct v4l2_subdev *sd, int enable) 1001 { 1002 struct ov2740 *ov2740 = to_ov2740(sd); 1003 struct i2c_client *client = v4l2_get_subdevdata(sd); 1004 struct v4l2_subdev_state *sd_state; 1005 int ret = 0; 1006 1007 sd_state = v4l2_subdev_lock_and_get_active_state(&ov2740->sd); 1008 1009 if (enable) { 1010 ret = pm_runtime_resume_and_get(&client->dev); 1011 if (ret < 0) 1012 goto out_unlock; 1013 1014 ret = ov2740_start_streaming(ov2740); 1015 if (ret) { 1016 enable = 0; 1017 ov2740_stop_streaming(ov2740); 1018 pm_runtime_put(&client->dev); 1019 } 1020 } else { 1021 ov2740_stop_streaming(ov2740); 1022 pm_runtime_put(&client->dev); 1023 } 1024 1025 out_unlock: 1026 v4l2_subdev_unlock_state(sd_state); 1027 1028 return ret; 1029 } 1030 1031 static int ov2740_set_format(struct v4l2_subdev *sd, 1032 struct v4l2_subdev_state *sd_state, 1033 struct v4l2_subdev_format *fmt) 1034 { 1035 struct ov2740 *ov2740 = to_ov2740(sd); 1036 const struct ov2740_mode *mode; 1037 s32 vblank_def, h_blank; 1038 1039 mode = v4l2_find_nearest_size(ov2740->supported_modes, 1040 ov2740->supported_modes_count, 1041 width, height, 1042 fmt->format.width, fmt->format.height); 1043 1044 ov2740_update_pad_format(mode, &fmt->format); 1045 *v4l2_subdev_state_get_format(sd_state, fmt->pad) = fmt->format; 1046 1047 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) 1048 return 0; 1049 1050 ov2740->cur_mode = mode; 1051 __v4l2_ctrl_s_ctrl(ov2740->link_freq, mode->link_freq_index); 1052 __v4l2_ctrl_s_ctrl_int64(ov2740->pixel_rate, 1053 to_pixel_rate(mode->link_freq_index)); 1054 1055 /* Update limits and set FPS to default */ 1056 vblank_def = mode->vts_def - mode->height; 1057 __v4l2_ctrl_modify_range(ov2740->vblank, 1058 mode->vts_min - mode->height, 1059 mode->vts_max - mode->height, 1, vblank_def); 1060 __v4l2_ctrl_s_ctrl(ov2740->vblank, vblank_def); 1061 h_blank = mode->hts - mode->width; 1062 __v4l2_ctrl_modify_range(ov2740->hblank, h_blank, h_blank, 1, h_blank); 1063 1064 return 0; 1065 } 1066 1067 static int ov2740_enum_mbus_code(struct v4l2_subdev *sd, 1068 struct v4l2_subdev_state *sd_state, 1069 struct v4l2_subdev_mbus_code_enum *code) 1070 { 1071 if (code->index > 0) 1072 return -EINVAL; 1073 1074 code->code = MEDIA_BUS_FMT_SGRBG10_1X10; 1075 1076 return 0; 1077 } 1078 1079 static int ov2740_enum_frame_size(struct v4l2_subdev *sd, 1080 struct v4l2_subdev_state *sd_state, 1081 struct v4l2_subdev_frame_size_enum *fse) 1082 { 1083 struct ov2740 *ov2740 = to_ov2740(sd); 1084 const struct ov2740_mode *supported_modes = ov2740->supported_modes; 1085 1086 if (fse->index >= ov2740->supported_modes_count) 1087 return -EINVAL; 1088 1089 if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10) 1090 return -EINVAL; 1091 1092 fse->min_width = supported_modes[fse->index].width; 1093 fse->max_width = fse->min_width; 1094 fse->min_height = supported_modes[fse->index].height; 1095 fse->max_height = fse->min_height; 1096 1097 return 0; 1098 } 1099 1100 static int ov2740_init_state(struct v4l2_subdev *sd, 1101 struct v4l2_subdev_state *sd_state) 1102 { 1103 struct ov2740 *ov2740 = to_ov2740(sd); 1104 1105 ov2740_update_pad_format(&ov2740->supported_modes[0], 1106 v4l2_subdev_state_get_format(sd_state, 0)); 1107 return 0; 1108 } 1109 1110 static const struct v4l2_subdev_video_ops ov2740_video_ops = { 1111 .s_stream = ov2740_set_stream, 1112 }; 1113 1114 static const struct v4l2_subdev_pad_ops ov2740_pad_ops = { 1115 .get_fmt = v4l2_subdev_get_fmt, 1116 .set_fmt = ov2740_set_format, 1117 .enum_mbus_code = ov2740_enum_mbus_code, 1118 .enum_frame_size = ov2740_enum_frame_size, 1119 }; 1120 1121 static const struct v4l2_subdev_ops ov2740_subdev_ops = { 1122 .video = &ov2740_video_ops, 1123 .pad = &ov2740_pad_ops, 1124 }; 1125 1126 static const struct v4l2_subdev_internal_ops ov2740_internal_ops = { 1127 .init_state = ov2740_init_state, 1128 }; 1129 1130 static const struct media_entity_operations ov2740_subdev_entity_ops = { 1131 .link_validate = v4l2_subdev_link_validate, 1132 }; 1133 1134 static int ov2740_check_hwcfg(struct device *dev) 1135 { 1136 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1137 struct ov2740 *ov2740 = to_ov2740(sd); 1138 struct fwnode_handle *ep; 1139 struct fwnode_handle *fwnode = dev_fwnode(dev); 1140 struct v4l2_fwnode_endpoint bus_cfg = { 1141 .bus_type = V4L2_MBUS_CSI2_DPHY 1142 }; 1143 u32 mclk; 1144 int ret; 1145 unsigned int i, j; 1146 1147 /* 1148 * Sometimes the fwnode graph is initialized by the bridge driver, 1149 * wait for this. 1150 */ 1151 ep = fwnode_graph_get_next_endpoint(fwnode, NULL); 1152 if (!ep) 1153 return dev_err_probe(dev, -EPROBE_DEFER, 1154 "waiting for fwnode graph endpoint\n"); 1155 1156 ret = fwnode_property_read_u32(fwnode, "clock-frequency", &mclk); 1157 if (ret) { 1158 fwnode_handle_put(ep); 1159 return dev_err_probe(dev, ret, 1160 "reading clock-frequency property\n"); 1161 } 1162 1163 if (mclk != OV2740_MCLK) { 1164 fwnode_handle_put(ep); 1165 return dev_err_probe(dev, -EINVAL, 1166 "external clock %d is not supported\n", 1167 mclk); 1168 } 1169 1170 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg); 1171 fwnode_handle_put(ep); 1172 if (ret) 1173 return dev_err_probe(dev, ret, "parsing endpoint failed\n"); 1174 1175 if (bus_cfg.bus.mipi_csi2.num_data_lanes != OV2740_DATA_LANES) { 1176 ret = dev_err_probe(dev, -EINVAL, 1177 "number of CSI2 data lanes %d is not supported\n", 1178 bus_cfg.bus.mipi_csi2.num_data_lanes); 1179 goto check_hwcfg_error; 1180 } 1181 1182 if (!bus_cfg.nr_of_link_frequencies) { 1183 ret = dev_err_probe(dev, -EINVAL, "no link frequencies defined\n"); 1184 goto check_hwcfg_error; 1185 } 1186 1187 for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) { 1188 for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) { 1189 if (link_freq_menu_items[i] == 1190 bus_cfg.link_frequencies[j]) 1191 break; 1192 } 1193 1194 if (j == bus_cfg.nr_of_link_frequencies) 1195 continue; 1196 1197 switch (i) { 1198 case OV2740_LINK_FREQ_360MHZ_INDEX: 1199 ov2740->supported_modes = supported_modes_360mhz; 1200 ov2740->supported_modes_count = 1201 ARRAY_SIZE(supported_modes_360mhz); 1202 break; 1203 case OV2740_LINK_FREQ_180MHZ_INDEX: 1204 ov2740->supported_modes = supported_modes_180mhz; 1205 ov2740->supported_modes_count = 1206 ARRAY_SIZE(supported_modes_180mhz); 1207 break; 1208 } 1209 1210 break; /* Prefer modes from first available link-freq */ 1211 } 1212 1213 if (!ov2740->supported_modes) 1214 ret = dev_err_probe(dev, -EINVAL, 1215 "no supported link frequencies\n"); 1216 1217 check_hwcfg_error: 1218 v4l2_fwnode_endpoint_free(&bus_cfg); 1219 1220 return ret; 1221 } 1222 1223 static void ov2740_remove(struct i2c_client *client) 1224 { 1225 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1226 1227 v4l2_async_unregister_subdev(sd); 1228 media_entity_cleanup(&sd->entity); 1229 v4l2_subdev_cleanup(sd); 1230 v4l2_ctrl_handler_free(sd->ctrl_handler); 1231 pm_runtime_disable(&client->dev); 1232 } 1233 1234 static int ov2740_nvmem_read(void *priv, unsigned int off, void *val, 1235 size_t count) 1236 { 1237 struct nvm_data *nvm = priv; 1238 struct device *dev = regmap_get_device(nvm->regmap); 1239 struct ov2740 *ov2740 = to_ov2740(dev_get_drvdata(dev)); 1240 struct v4l2_subdev_state *sd_state; 1241 int ret = 0; 1242 1243 /* Serialise sensor access */ 1244 sd_state = v4l2_subdev_lock_and_get_active_state(&ov2740->sd); 1245 1246 if (nvm->nvm_buffer) { 1247 memcpy(val, nvm->nvm_buffer + off, count); 1248 goto exit; 1249 } 1250 1251 ret = pm_runtime_resume_and_get(dev); 1252 if (ret < 0) { 1253 goto exit; 1254 } 1255 1256 ret = ov2740_load_otp_data(nvm); 1257 if (!ret) 1258 memcpy(val, nvm->nvm_buffer + off, count); 1259 1260 pm_runtime_put(dev); 1261 exit: 1262 v4l2_subdev_unlock_state(sd_state); 1263 return ret; 1264 } 1265 1266 static int ov2740_register_nvmem(struct i2c_client *client, 1267 struct ov2740 *ov2740) 1268 { 1269 struct nvm_data *nvm; 1270 struct regmap_config regmap_config = { }; 1271 struct nvmem_config nvmem_config = { }; 1272 struct regmap *regmap; 1273 struct device *dev = &client->dev; 1274 1275 nvm = devm_kzalloc(dev, sizeof(*nvm), GFP_KERNEL); 1276 if (!nvm) 1277 return -ENOMEM; 1278 1279 regmap_config.val_bits = 8; 1280 regmap_config.reg_bits = 16; 1281 regmap_config.disable_locking = true; 1282 regmap = devm_regmap_init_i2c(client, ®map_config); 1283 if (IS_ERR(regmap)) 1284 return PTR_ERR(regmap); 1285 1286 nvm->regmap = regmap; 1287 1288 nvmem_config.name = dev_name(dev); 1289 nvmem_config.dev = dev; 1290 nvmem_config.read_only = true; 1291 nvmem_config.root_only = true; 1292 nvmem_config.owner = THIS_MODULE; 1293 nvmem_config.compat = true; 1294 nvmem_config.base_dev = dev; 1295 nvmem_config.reg_read = ov2740_nvmem_read; 1296 nvmem_config.reg_write = NULL; 1297 nvmem_config.priv = nvm; 1298 nvmem_config.stride = 1; 1299 nvmem_config.word_size = 1; 1300 nvmem_config.size = CUSTOMER_USE_OTP_SIZE; 1301 1302 nvm->nvmem = devm_nvmem_register(dev, &nvmem_config); 1303 if (IS_ERR(nvm->nvmem)) 1304 return PTR_ERR(nvm->nvmem); 1305 1306 ov2740->nvm = nvm; 1307 return 0; 1308 } 1309 1310 static int ov2740_suspend(struct device *dev) 1311 { 1312 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1313 struct ov2740 *ov2740 = to_ov2740(sd); 1314 1315 gpiod_set_value_cansleep(ov2740->reset_gpio, 1); 1316 gpiod_set_value_cansleep(ov2740->powerdown_gpio, 1); 1317 clk_disable_unprepare(ov2740->clk); 1318 regulator_bulk_disable(ARRAY_SIZE(ov2740_supply_name), 1319 ov2740->supplies); 1320 return 0; 1321 } 1322 1323 static int ov2740_resume(struct device *dev) 1324 { 1325 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1326 struct ov2740 *ov2740 = to_ov2740(sd); 1327 int ret; 1328 1329 ret = regulator_bulk_enable(ARRAY_SIZE(ov2740_supply_name), 1330 ov2740->supplies); 1331 if (ret) 1332 return ret; 1333 1334 ret = clk_prepare_enable(ov2740->clk); 1335 if (ret) { 1336 regulator_bulk_disable(ARRAY_SIZE(ov2740_supply_name), 1337 ov2740->supplies); 1338 return ret; 1339 } 1340 1341 gpiod_set_value_cansleep(ov2740->powerdown_gpio, 0); 1342 gpiod_set_value_cansleep(ov2740->reset_gpio, 0); 1343 msleep(20); 1344 1345 return 0; 1346 } 1347 1348 static int ov2740_probe(struct i2c_client *client) 1349 { 1350 struct device *dev = &client->dev; 1351 struct ov2740 *ov2740; 1352 bool full_power; 1353 unsigned int i; 1354 int ret; 1355 1356 ov2740 = devm_kzalloc(&client->dev, sizeof(*ov2740), GFP_KERNEL); 1357 if (!ov2740) 1358 return -ENOMEM; 1359 1360 v4l2_i2c_subdev_init(&ov2740->sd, client, &ov2740_subdev_ops); 1361 ov2740->sd.internal_ops = &ov2740_internal_ops; 1362 1363 ret = ov2740_check_hwcfg(dev); 1364 if (ret) 1365 return ret; 1366 1367 ov2740->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); 1368 if (IS_ERR(ov2740->reset_gpio)) { 1369 return dev_err_probe(dev, PTR_ERR(ov2740->reset_gpio), 1370 "failed to get reset GPIO\n"); 1371 } 1372 1373 ov2740->powerdown_gpio = devm_gpiod_get_optional(dev, "powerdown", GPIOD_OUT_HIGH); 1374 if (IS_ERR(ov2740->powerdown_gpio)) { 1375 return dev_err_probe(dev, PTR_ERR(ov2740->powerdown_gpio), 1376 "failed to get powerdown GPIO\n"); 1377 } 1378 1379 if (ov2740->reset_gpio || ov2740->powerdown_gpio) { 1380 /* 1381 * Ensure reset/powerdown is asserted for at least 20 ms before 1382 * ov2740_resume() deasserts it. 1383 */ 1384 msleep(20); 1385 } 1386 1387 ov2740->clk = devm_clk_get_optional(dev, "clk"); 1388 if (IS_ERR(ov2740->clk)) 1389 return dev_err_probe(dev, PTR_ERR(ov2740->clk), 1390 "failed to get clock\n"); 1391 1392 for (i = 0; i < ARRAY_SIZE(ov2740_supply_name); i++) 1393 ov2740->supplies[i].supply = ov2740_supply_name[i]; 1394 1395 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ov2740_supply_name), 1396 ov2740->supplies); 1397 if (ret) 1398 return dev_err_probe(dev, ret, "failed to get regulators\n"); 1399 1400 full_power = acpi_dev_state_d0(&client->dev); 1401 if (full_power) { 1402 /* ACPI does not always clear the reset GPIO / enable the clock */ 1403 ret = ov2740_resume(dev); 1404 if (ret) 1405 return dev_err_probe(dev, ret, "failed to power on sensor\n"); 1406 1407 ret = ov2740_identify_module(ov2740); 1408 if (ret) { 1409 dev_err_probe(dev, ret, "failed to find sensor\n"); 1410 goto probe_error_power_off; 1411 } 1412 } 1413 1414 ov2740->cur_mode = &ov2740->supported_modes[0]; 1415 ret = ov2740_init_controls(ov2740); 1416 if (ret) { 1417 dev_err_probe(dev, ret, "failed to init controls\n"); 1418 goto probe_error_v4l2_ctrl_handler_free; 1419 } 1420 1421 ov2740->sd.state_lock = ov2740->ctrl_handler.lock; 1422 ov2740->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1423 ov2740->sd.entity.ops = &ov2740_subdev_entity_ops; 1424 ov2740->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1425 ov2740->pad.flags = MEDIA_PAD_FL_SOURCE; 1426 ret = media_entity_pads_init(&ov2740->sd.entity, 1, &ov2740->pad); 1427 if (ret) { 1428 dev_err_probe(dev, ret, "failed to init entity pads\n"); 1429 goto probe_error_v4l2_ctrl_handler_free; 1430 } 1431 1432 ret = v4l2_subdev_init_finalize(&ov2740->sd); 1433 if (ret) 1434 goto probe_error_media_entity_cleanup; 1435 1436 /* Set the device's state to active if it's in D0 state. */ 1437 if (full_power) 1438 pm_runtime_set_active(&client->dev); 1439 pm_runtime_enable(&client->dev); 1440 pm_runtime_idle(&client->dev); 1441 1442 ret = v4l2_async_register_subdev_sensor(&ov2740->sd); 1443 if (ret < 0) { 1444 dev_err_probe(dev, ret, "failed to register V4L2 subdev\n"); 1445 goto probe_error_v4l2_subdev_cleanup; 1446 } 1447 1448 ret = ov2740_register_nvmem(client, ov2740); 1449 if (ret) 1450 dev_warn(&client->dev, "register nvmem failed, ret %d\n", ret); 1451 1452 return 0; 1453 1454 probe_error_v4l2_subdev_cleanup: 1455 pm_runtime_disable(&client->dev); 1456 pm_runtime_set_suspended(&client->dev); 1457 v4l2_subdev_cleanup(&ov2740->sd); 1458 1459 probe_error_media_entity_cleanup: 1460 media_entity_cleanup(&ov2740->sd.entity); 1461 1462 probe_error_v4l2_ctrl_handler_free: 1463 v4l2_ctrl_handler_free(ov2740->sd.ctrl_handler); 1464 1465 probe_error_power_off: 1466 if (full_power) 1467 ov2740_suspend(dev); 1468 1469 return ret; 1470 } 1471 1472 static DEFINE_RUNTIME_DEV_PM_OPS(ov2740_pm_ops, ov2740_suspend, ov2740_resume, 1473 NULL); 1474 1475 static const struct acpi_device_id ov2740_acpi_ids[] = { 1476 {"INT3474"}, 1477 {} 1478 }; 1479 1480 MODULE_DEVICE_TABLE(acpi, ov2740_acpi_ids); 1481 1482 static struct i2c_driver ov2740_i2c_driver = { 1483 .driver = { 1484 .name = "ov2740", 1485 .acpi_match_table = ov2740_acpi_ids, 1486 .pm = pm_sleep_ptr(&ov2740_pm_ops), 1487 }, 1488 .probe = ov2740_probe, 1489 .remove = ov2740_remove, 1490 .flags = I2C_DRV_ACPI_WAIVE_D0_PROBE, 1491 }; 1492 1493 module_i2c_driver(ov2740_i2c_driver); 1494 1495 MODULE_AUTHOR("Qiu, Tianshu <tian.shu.qiu@intel.com>"); 1496 MODULE_AUTHOR("Shawn Tu"); 1497 MODULE_AUTHOR("Bingbu Cao <bingbu.cao@intel.com>"); 1498 MODULE_DESCRIPTION("OmniVision OV2740 sensor driver"); 1499 MODULE_LICENSE("GPL v2"); 1500