1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2020 Intel Corporation. 3 4 #include <asm/unaligned.h> 5 #include <linux/acpi.h> 6 #include <linux/delay.h> 7 #include <linux/i2c.h> 8 #include <linux/module.h> 9 #include <linux/pm_runtime.h> 10 #include <linux/nvmem-provider.h> 11 #include <linux/regmap.h> 12 #include <media/v4l2-ctrls.h> 13 #include <media/v4l2-device.h> 14 #include <media/v4l2-fwnode.h> 15 16 #define OV2740_LINK_FREQ_360MHZ 360000000ULL 17 #define OV2740_SCLK 72000000LL 18 #define OV2740_MCLK 19200000 19 #define OV2740_DATA_LANES 2 20 #define OV2740_RGB_DEPTH 10 21 22 #define OV2740_REG_CHIP_ID 0x300a 23 #define OV2740_CHIP_ID 0x2740 24 25 #define OV2740_REG_MODE_SELECT 0x0100 26 #define OV2740_MODE_STANDBY 0x00 27 #define OV2740_MODE_STREAMING 0x01 28 29 /* vertical-timings from sensor */ 30 #define OV2740_REG_VTS 0x380e 31 #define OV2740_VTS_DEF 0x088a 32 #define OV2740_VTS_MIN 0x0460 33 #define OV2740_VTS_MAX 0x7fff 34 35 /* horizontal-timings from sensor */ 36 #define OV2740_REG_HTS 0x380c 37 38 /* Exposure controls from sensor */ 39 #define OV2740_REG_EXPOSURE 0x3500 40 #define OV2740_EXPOSURE_MIN 4 41 #define OV2740_EXPOSURE_MAX_MARGIN 8 42 #define OV2740_EXPOSURE_STEP 1 43 44 /* Analog gain controls from sensor */ 45 #define OV2740_REG_ANALOG_GAIN 0x3508 46 #define OV2740_ANAL_GAIN_MIN 128 47 #define OV2740_ANAL_GAIN_MAX 1983 48 #define OV2740_ANAL_GAIN_STEP 1 49 50 /* Digital gain controls from sensor */ 51 #define OV2740_REG_MWB_R_GAIN 0x500a 52 #define OV2740_REG_MWB_G_GAIN 0x500c 53 #define OV2740_REG_MWB_B_GAIN 0x500e 54 #define OV2740_DGTL_GAIN_MIN 1024 55 #define OV2740_DGTL_GAIN_MAX 4095 56 #define OV2740_DGTL_GAIN_STEP 1 57 #define OV2740_DGTL_GAIN_DEFAULT 1024 58 59 /* Test Pattern Control */ 60 #define OV2740_REG_TEST_PATTERN 0x5040 61 #define OV2740_TEST_PATTERN_ENABLE BIT(7) 62 #define OV2740_TEST_PATTERN_BAR_SHIFT 2 63 64 /* Group Access */ 65 #define OV2740_REG_GROUP_ACCESS 0x3208 66 #define OV2740_GROUP_HOLD_START 0x0 67 #define OV2740_GROUP_HOLD_END 0x10 68 #define OV2740_GROUP_HOLD_LAUNCH 0xa0 69 70 /* ISP CTRL00 */ 71 #define OV2740_REG_ISP_CTRL00 0x5000 72 /* ISP CTRL01 */ 73 #define OV2740_REG_ISP_CTRL01 0x5001 74 /* Customer Addresses: 0x7010 - 0x710F */ 75 #define CUSTOMER_USE_OTP_SIZE 0x100 76 /* OTP registers from sensor */ 77 #define OV2740_REG_OTP_CUSTOMER 0x7010 78 79 struct nvm_data { 80 struct nvmem_device *nvmem; 81 struct regmap *regmap; 82 char *nvm_buffer; 83 }; 84 85 enum { 86 OV2740_LINK_FREQ_360MHZ_INDEX, 87 }; 88 89 struct ov2740_reg { 90 u16 address; 91 u8 val; 92 }; 93 94 struct ov2740_reg_list { 95 u32 num_of_regs; 96 const struct ov2740_reg *regs; 97 }; 98 99 struct ov2740_link_freq_config { 100 const struct ov2740_reg_list reg_list; 101 }; 102 103 struct ov2740_mode { 104 /* Frame width in pixels */ 105 u32 width; 106 107 /* Frame height in pixels */ 108 u32 height; 109 110 /* Horizontal timining size */ 111 u32 hts; 112 113 /* Default vertical timining size */ 114 u32 vts_def; 115 116 /* Min vertical timining size */ 117 u32 vts_min; 118 119 /* Link frequency needed for this resolution */ 120 u32 link_freq_index; 121 122 /* Sensor register settings for this resolution */ 123 const struct ov2740_reg_list reg_list; 124 }; 125 126 static const struct ov2740_reg mipi_data_rate_720mbps[] = { 127 {0x0103, 0x01}, 128 {0x0302, 0x4b}, 129 {0x030d, 0x4b}, 130 {0x030e, 0x02}, 131 {0x030a, 0x01}, 132 {0x0312, 0x11}, 133 }; 134 135 static const struct ov2740_reg mode_1932x1092_regs[] = { 136 {0x3000, 0x00}, 137 {0x3018, 0x32}, 138 {0x3031, 0x0a}, 139 {0x3080, 0x08}, 140 {0x3083, 0xB4}, 141 {0x3103, 0x00}, 142 {0x3104, 0x01}, 143 {0x3106, 0x01}, 144 {0x3500, 0x00}, 145 {0x3501, 0x44}, 146 {0x3502, 0x40}, 147 {0x3503, 0x88}, 148 {0x3507, 0x00}, 149 {0x3508, 0x00}, 150 {0x3509, 0x80}, 151 {0x350c, 0x00}, 152 {0x350d, 0x80}, 153 {0x3510, 0x00}, 154 {0x3511, 0x00}, 155 {0x3512, 0x20}, 156 {0x3632, 0x00}, 157 {0x3633, 0x10}, 158 {0x3634, 0x10}, 159 {0x3635, 0x10}, 160 {0x3645, 0x13}, 161 {0x3646, 0x81}, 162 {0x3636, 0x10}, 163 {0x3651, 0x0a}, 164 {0x3656, 0x02}, 165 {0x3659, 0x04}, 166 {0x365a, 0xda}, 167 {0x365b, 0xa2}, 168 {0x365c, 0x04}, 169 {0x365d, 0x1d}, 170 {0x365e, 0x1a}, 171 {0x3662, 0xd7}, 172 {0x3667, 0x78}, 173 {0x3669, 0x0a}, 174 {0x366a, 0x92}, 175 {0x3700, 0x54}, 176 {0x3702, 0x10}, 177 {0x3706, 0x42}, 178 {0x3709, 0x30}, 179 {0x370b, 0xc2}, 180 {0x3714, 0x63}, 181 {0x3715, 0x01}, 182 {0x3716, 0x00}, 183 {0x371a, 0x3e}, 184 {0x3732, 0x0e}, 185 {0x3733, 0x10}, 186 {0x375f, 0x0e}, 187 {0x3768, 0x30}, 188 {0x3769, 0x44}, 189 {0x376a, 0x22}, 190 {0x377b, 0x20}, 191 {0x377c, 0x00}, 192 {0x377d, 0x0c}, 193 {0x3798, 0x00}, 194 {0x37a1, 0x55}, 195 {0x37a8, 0x6d}, 196 {0x37c2, 0x04}, 197 {0x37c5, 0x00}, 198 {0x37c8, 0x00}, 199 {0x3800, 0x00}, 200 {0x3801, 0x00}, 201 {0x3802, 0x00}, 202 {0x3803, 0x00}, 203 {0x3804, 0x07}, 204 {0x3805, 0x8f}, 205 {0x3806, 0x04}, 206 {0x3807, 0x47}, 207 {0x3808, 0x07}, 208 {0x3809, 0x88}, 209 {0x380a, 0x04}, 210 {0x380b, 0x40}, 211 {0x380c, 0x04}, 212 {0x380d, 0x38}, 213 {0x380e, 0x04}, 214 {0x380f, 0x60}, 215 {0x3810, 0x00}, 216 {0x3811, 0x04}, 217 {0x3812, 0x00}, 218 {0x3813, 0x04}, 219 {0x3814, 0x01}, 220 {0x3815, 0x01}, 221 {0x3820, 0x80}, 222 {0x3821, 0x46}, 223 {0x3822, 0x84}, 224 {0x3829, 0x00}, 225 {0x382a, 0x01}, 226 {0x382b, 0x01}, 227 {0x3830, 0x04}, 228 {0x3836, 0x01}, 229 {0x3837, 0x08}, 230 {0x3839, 0x01}, 231 {0x383a, 0x00}, 232 {0x383b, 0x08}, 233 {0x383c, 0x00}, 234 {0x3f0b, 0x00}, 235 {0x4001, 0x20}, 236 {0x4009, 0x07}, 237 {0x4003, 0x10}, 238 {0x4010, 0xe0}, 239 {0x4016, 0x00}, 240 {0x4017, 0x10}, 241 {0x4044, 0x02}, 242 {0x4304, 0x08}, 243 {0x4307, 0x30}, 244 {0x4320, 0x80}, 245 {0x4322, 0x00}, 246 {0x4323, 0x00}, 247 {0x4324, 0x00}, 248 {0x4325, 0x00}, 249 {0x4326, 0x00}, 250 {0x4327, 0x00}, 251 {0x4328, 0x00}, 252 {0x4329, 0x00}, 253 {0x432c, 0x03}, 254 {0x432d, 0x81}, 255 {0x4501, 0x84}, 256 {0x4502, 0x40}, 257 {0x4503, 0x18}, 258 {0x4504, 0x04}, 259 {0x4508, 0x02}, 260 {0x4601, 0x10}, 261 {0x4800, 0x00}, 262 {0x4816, 0x52}, 263 {0x4837, 0x16}, 264 {0x5000, 0x7f}, 265 {0x5001, 0x00}, 266 {0x5005, 0x38}, 267 {0x501e, 0x0d}, 268 {0x5040, 0x00}, 269 {0x5901, 0x00}, 270 {0x3800, 0x00}, 271 {0x3801, 0x00}, 272 {0x3802, 0x00}, 273 {0x3803, 0x00}, 274 {0x3804, 0x07}, 275 {0x3805, 0x8f}, 276 {0x3806, 0x04}, 277 {0x3807, 0x47}, 278 {0x3808, 0x07}, 279 {0x3809, 0x8c}, 280 {0x380a, 0x04}, 281 {0x380b, 0x44}, 282 {0x3810, 0x00}, 283 {0x3811, 0x00}, 284 {0x3812, 0x00}, 285 {0x3813, 0x01}, 286 }; 287 288 static const char * const ov2740_test_pattern_menu[] = { 289 "Disabled", 290 "Color Bar", 291 "Top-Bottom Darker Color Bar", 292 "Right-Left Darker Color Bar", 293 "Bottom-Top Darker Color Bar", 294 }; 295 296 static const s64 link_freq_menu_items[] = { 297 OV2740_LINK_FREQ_360MHZ, 298 }; 299 300 static const struct ov2740_link_freq_config link_freq_configs[] = { 301 [OV2740_LINK_FREQ_360MHZ_INDEX] = { 302 .reg_list = { 303 .num_of_regs = ARRAY_SIZE(mipi_data_rate_720mbps), 304 .regs = mipi_data_rate_720mbps, 305 } 306 }, 307 }; 308 309 static const struct ov2740_mode supported_modes[] = { 310 { 311 .width = 1932, 312 .height = 1092, 313 .hts = 1080, 314 .vts_def = OV2740_VTS_DEF, 315 .vts_min = OV2740_VTS_MIN, 316 .reg_list = { 317 .num_of_regs = ARRAY_SIZE(mode_1932x1092_regs), 318 .regs = mode_1932x1092_regs, 319 }, 320 .link_freq_index = OV2740_LINK_FREQ_360MHZ_INDEX, 321 }, 322 }; 323 324 struct ov2740 { 325 struct v4l2_subdev sd; 326 struct media_pad pad; 327 struct v4l2_ctrl_handler ctrl_handler; 328 329 /* V4L2 Controls */ 330 struct v4l2_ctrl *link_freq; 331 struct v4l2_ctrl *pixel_rate; 332 struct v4l2_ctrl *vblank; 333 struct v4l2_ctrl *hblank; 334 struct v4l2_ctrl *exposure; 335 336 /* Current mode */ 337 const struct ov2740_mode *cur_mode; 338 339 /* To serialize asynchronus callbacks */ 340 struct mutex mutex; 341 342 /* NVM data inforamtion */ 343 struct nvm_data *nvm; 344 345 /* True if the device has been identified */ 346 bool identified; 347 }; 348 349 static inline struct ov2740 *to_ov2740(struct v4l2_subdev *subdev) 350 { 351 return container_of(subdev, struct ov2740, sd); 352 } 353 354 static u64 to_pixel_rate(u32 f_index) 355 { 356 u64 pixel_rate = link_freq_menu_items[f_index] * 2 * OV2740_DATA_LANES; 357 358 do_div(pixel_rate, OV2740_RGB_DEPTH); 359 360 return pixel_rate; 361 } 362 363 static u64 to_pixels_per_line(u32 hts, u32 f_index) 364 { 365 u64 ppl = hts * to_pixel_rate(f_index); 366 367 do_div(ppl, OV2740_SCLK); 368 369 return ppl; 370 } 371 372 static int ov2740_read_reg(struct ov2740 *ov2740, u16 reg, u16 len, u32 *val) 373 { 374 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 375 struct i2c_msg msgs[2]; 376 u8 addr_buf[2]; 377 u8 data_buf[4] = {0}; 378 int ret; 379 380 if (len > sizeof(data_buf)) 381 return -EINVAL; 382 383 put_unaligned_be16(reg, addr_buf); 384 msgs[0].addr = client->addr; 385 msgs[0].flags = 0; 386 msgs[0].len = sizeof(addr_buf); 387 msgs[0].buf = addr_buf; 388 msgs[1].addr = client->addr; 389 msgs[1].flags = I2C_M_RD; 390 msgs[1].len = len; 391 msgs[1].buf = &data_buf[sizeof(data_buf) - len]; 392 393 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); 394 if (ret != ARRAY_SIZE(msgs)) 395 return ret < 0 ? ret : -EIO; 396 397 *val = get_unaligned_be32(data_buf); 398 399 return 0; 400 } 401 402 static int ov2740_write_reg(struct ov2740 *ov2740, u16 reg, u16 len, u32 val) 403 { 404 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 405 u8 buf[6]; 406 int ret; 407 408 if (len > 4) 409 return -EINVAL; 410 411 put_unaligned_be16(reg, buf); 412 put_unaligned_be32(val << 8 * (4 - len), buf + 2); 413 414 ret = i2c_master_send(client, buf, len + 2); 415 if (ret != len + 2) 416 return ret < 0 ? ret : -EIO; 417 418 return 0; 419 } 420 421 static int ov2740_write_reg_list(struct ov2740 *ov2740, 422 const struct ov2740_reg_list *r_list) 423 { 424 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 425 unsigned int i; 426 int ret; 427 428 for (i = 0; i < r_list->num_of_regs; i++) { 429 ret = ov2740_write_reg(ov2740, r_list->regs[i].address, 1, 430 r_list->regs[i].val); 431 if (ret) { 432 dev_err_ratelimited(&client->dev, 433 "write reg 0x%4.4x return err = %d\n", 434 r_list->regs[i].address, ret); 435 return ret; 436 } 437 } 438 439 return 0; 440 } 441 442 static int ov2740_identify_module(struct ov2740 *ov2740) 443 { 444 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 445 int ret; 446 u32 val; 447 448 if (ov2740->identified) 449 return 0; 450 451 ret = ov2740_read_reg(ov2740, OV2740_REG_CHIP_ID, 3, &val); 452 if (ret) 453 return ret; 454 455 if (val != OV2740_CHIP_ID) { 456 dev_err(&client->dev, "chip id mismatch: %x != %x\n", 457 OV2740_CHIP_ID, val); 458 return -ENXIO; 459 } 460 461 ov2740->identified = true; 462 463 return 0; 464 } 465 466 static int ov2740_update_digital_gain(struct ov2740 *ov2740, u32 d_gain) 467 { 468 int ret; 469 470 ret = ov2740_write_reg(ov2740, OV2740_REG_GROUP_ACCESS, 1, 471 OV2740_GROUP_HOLD_START); 472 if (ret) 473 return ret; 474 475 ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_R_GAIN, 2, d_gain); 476 if (ret) 477 return ret; 478 479 ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_G_GAIN, 2, d_gain); 480 if (ret) 481 return ret; 482 483 ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_B_GAIN, 2, d_gain); 484 if (ret) 485 return ret; 486 487 ret = ov2740_write_reg(ov2740, OV2740_REG_GROUP_ACCESS, 1, 488 OV2740_GROUP_HOLD_END); 489 if (ret) 490 return ret; 491 492 ret = ov2740_write_reg(ov2740, OV2740_REG_GROUP_ACCESS, 1, 493 OV2740_GROUP_HOLD_LAUNCH); 494 return ret; 495 } 496 497 static int ov2740_test_pattern(struct ov2740 *ov2740, u32 pattern) 498 { 499 if (pattern) 500 pattern = (pattern - 1) << OV2740_TEST_PATTERN_BAR_SHIFT | 501 OV2740_TEST_PATTERN_ENABLE; 502 503 return ov2740_write_reg(ov2740, OV2740_REG_TEST_PATTERN, 1, pattern); 504 } 505 506 static int ov2740_set_ctrl(struct v4l2_ctrl *ctrl) 507 { 508 struct ov2740 *ov2740 = container_of(ctrl->handler, 509 struct ov2740, ctrl_handler); 510 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 511 s64 exposure_max; 512 int ret; 513 514 /* Propagate change of current control to all related controls */ 515 if (ctrl->id == V4L2_CID_VBLANK) { 516 /* Update max exposure while meeting expected vblanking */ 517 exposure_max = ov2740->cur_mode->height + ctrl->val - 518 OV2740_EXPOSURE_MAX_MARGIN; 519 __v4l2_ctrl_modify_range(ov2740->exposure, 520 ov2740->exposure->minimum, 521 exposure_max, ov2740->exposure->step, 522 exposure_max); 523 } 524 525 /* V4L2 controls values will be applied only when power is already up */ 526 if (!pm_runtime_get_if_in_use(&client->dev)) 527 return 0; 528 529 switch (ctrl->id) { 530 case V4L2_CID_ANALOGUE_GAIN: 531 ret = ov2740_write_reg(ov2740, OV2740_REG_ANALOG_GAIN, 2, 532 ctrl->val); 533 break; 534 535 case V4L2_CID_DIGITAL_GAIN: 536 ret = ov2740_update_digital_gain(ov2740, ctrl->val); 537 break; 538 539 case V4L2_CID_EXPOSURE: 540 /* 4 least significant bits of expsoure are fractional part */ 541 ret = ov2740_write_reg(ov2740, OV2740_REG_EXPOSURE, 3, 542 ctrl->val << 4); 543 break; 544 545 case V4L2_CID_VBLANK: 546 ret = ov2740_write_reg(ov2740, OV2740_REG_VTS, 2, 547 ov2740->cur_mode->height + ctrl->val); 548 break; 549 550 case V4L2_CID_TEST_PATTERN: 551 ret = ov2740_test_pattern(ov2740, ctrl->val); 552 break; 553 554 default: 555 ret = -EINVAL; 556 break; 557 } 558 559 pm_runtime_put(&client->dev); 560 561 return ret; 562 } 563 564 static const struct v4l2_ctrl_ops ov2740_ctrl_ops = { 565 .s_ctrl = ov2740_set_ctrl, 566 }; 567 568 static int ov2740_init_controls(struct ov2740 *ov2740) 569 { 570 struct v4l2_ctrl_handler *ctrl_hdlr; 571 const struct ov2740_mode *cur_mode; 572 s64 exposure_max, h_blank, pixel_rate; 573 u32 vblank_min, vblank_max, vblank_default; 574 int size; 575 int ret; 576 577 ctrl_hdlr = &ov2740->ctrl_handler; 578 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 8); 579 if (ret) 580 return ret; 581 582 ctrl_hdlr->lock = &ov2740->mutex; 583 cur_mode = ov2740->cur_mode; 584 size = ARRAY_SIZE(link_freq_menu_items); 585 586 ov2740->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, &ov2740_ctrl_ops, 587 V4L2_CID_LINK_FREQ, 588 size - 1, 0, 589 link_freq_menu_items); 590 if (ov2740->link_freq) 591 ov2740->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; 592 593 pixel_rate = to_pixel_rate(OV2740_LINK_FREQ_360MHZ_INDEX); 594 ov2740->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, 595 V4L2_CID_PIXEL_RATE, 0, 596 pixel_rate, 1, pixel_rate); 597 598 vblank_min = cur_mode->vts_min - cur_mode->height; 599 vblank_max = OV2740_VTS_MAX - cur_mode->height; 600 vblank_default = cur_mode->vts_def - cur_mode->height; 601 ov2740->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, 602 V4L2_CID_VBLANK, vblank_min, 603 vblank_max, 1, vblank_default); 604 605 h_blank = to_pixels_per_line(cur_mode->hts, cur_mode->link_freq_index); 606 h_blank -= cur_mode->width; 607 ov2740->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, 608 V4L2_CID_HBLANK, h_blank, h_blank, 1, 609 h_blank); 610 if (ov2740->hblank) 611 ov2740->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; 612 613 v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, 614 OV2740_ANAL_GAIN_MIN, OV2740_ANAL_GAIN_MAX, 615 OV2740_ANAL_GAIN_STEP, OV2740_ANAL_GAIN_MIN); 616 v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, V4L2_CID_DIGITAL_GAIN, 617 OV2740_DGTL_GAIN_MIN, OV2740_DGTL_GAIN_MAX, 618 OV2740_DGTL_GAIN_STEP, OV2740_DGTL_GAIN_DEFAULT); 619 exposure_max = cur_mode->vts_def - OV2740_EXPOSURE_MAX_MARGIN; 620 ov2740->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, 621 V4L2_CID_EXPOSURE, 622 OV2740_EXPOSURE_MIN, exposure_max, 623 OV2740_EXPOSURE_STEP, 624 exposure_max); 625 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov2740_ctrl_ops, 626 V4L2_CID_TEST_PATTERN, 627 ARRAY_SIZE(ov2740_test_pattern_menu) - 1, 628 0, 0, ov2740_test_pattern_menu); 629 if (ctrl_hdlr->error) { 630 v4l2_ctrl_handler_free(ctrl_hdlr); 631 return ctrl_hdlr->error; 632 } 633 634 ov2740->sd.ctrl_handler = ctrl_hdlr; 635 636 return 0; 637 } 638 639 static void ov2740_update_pad_format(const struct ov2740_mode *mode, 640 struct v4l2_mbus_framefmt *fmt) 641 { 642 fmt->width = mode->width; 643 fmt->height = mode->height; 644 fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10; 645 fmt->field = V4L2_FIELD_NONE; 646 } 647 648 static int ov2740_load_otp_data(struct nvm_data *nvm) 649 { 650 struct device *dev = regmap_get_device(nvm->regmap); 651 struct ov2740 *ov2740 = to_ov2740(dev_get_drvdata(dev)); 652 u32 isp_ctrl00 = 0; 653 u32 isp_ctrl01 = 0; 654 int ret; 655 656 if (nvm->nvm_buffer) 657 return 0; 658 659 nvm->nvm_buffer = kzalloc(CUSTOMER_USE_OTP_SIZE, GFP_KERNEL); 660 if (!nvm->nvm_buffer) 661 return -ENOMEM; 662 663 ret = ov2740_read_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, &isp_ctrl00); 664 if (ret) { 665 dev_err(dev, "failed to read ISP CTRL00\n"); 666 goto err; 667 } 668 669 ret = ov2740_read_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, &isp_ctrl01); 670 if (ret) { 671 dev_err(dev, "failed to read ISP CTRL01\n"); 672 goto err; 673 } 674 675 /* Clear bit 5 of ISP CTRL00 */ 676 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, 677 isp_ctrl00 & ~BIT(5)); 678 if (ret) { 679 dev_err(dev, "failed to set ISP CTRL00\n"); 680 goto err; 681 } 682 683 /* Clear bit 7 of ISP CTRL01 */ 684 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, 685 isp_ctrl01 & ~BIT(7)); 686 if (ret) { 687 dev_err(dev, "failed to set ISP CTRL01\n"); 688 goto err; 689 } 690 691 ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1, 692 OV2740_MODE_STREAMING); 693 if (ret) { 694 dev_err(dev, "failed to set streaming mode\n"); 695 goto err; 696 } 697 698 /* 699 * Users are not allowed to access OTP-related registers and memory 700 * during the 20 ms period after streaming starts (0x100 = 0x01). 701 */ 702 msleep(20); 703 704 ret = regmap_bulk_read(nvm->regmap, OV2740_REG_OTP_CUSTOMER, 705 nvm->nvm_buffer, CUSTOMER_USE_OTP_SIZE); 706 if (ret) { 707 dev_err(dev, "failed to read OTP data, ret %d\n", ret); 708 goto err; 709 } 710 711 ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1, 712 OV2740_MODE_STANDBY); 713 if (ret) { 714 dev_err(dev, "failed to set streaming mode\n"); 715 goto err; 716 } 717 718 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, isp_ctrl01); 719 if (ret) { 720 dev_err(dev, "failed to set ISP CTRL01\n"); 721 goto err; 722 } 723 724 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, isp_ctrl00); 725 if (ret) { 726 dev_err(dev, "failed to set ISP CTRL00\n"); 727 goto err; 728 } 729 730 return 0; 731 err: 732 kfree(nvm->nvm_buffer); 733 nvm->nvm_buffer = NULL; 734 735 return ret; 736 } 737 738 static int ov2740_start_streaming(struct ov2740 *ov2740) 739 { 740 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 741 const struct ov2740_reg_list *reg_list; 742 int link_freq_index; 743 int ret; 744 745 ret = ov2740_identify_module(ov2740); 746 if (ret) 747 return ret; 748 749 if (ov2740->nvm) 750 ov2740_load_otp_data(ov2740->nvm); 751 752 link_freq_index = ov2740->cur_mode->link_freq_index; 753 reg_list = &link_freq_configs[link_freq_index].reg_list; 754 ret = ov2740_write_reg_list(ov2740, reg_list); 755 if (ret) { 756 dev_err(&client->dev, "failed to set plls\n"); 757 return ret; 758 } 759 760 reg_list = &ov2740->cur_mode->reg_list; 761 ret = ov2740_write_reg_list(ov2740, reg_list); 762 if (ret) { 763 dev_err(&client->dev, "failed to set mode\n"); 764 return ret; 765 } 766 767 ret = __v4l2_ctrl_handler_setup(ov2740->sd.ctrl_handler); 768 if (ret) 769 return ret; 770 771 ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1, 772 OV2740_MODE_STREAMING); 773 if (ret) 774 dev_err(&client->dev, "failed to start streaming\n"); 775 776 return ret; 777 } 778 779 static void ov2740_stop_streaming(struct ov2740 *ov2740) 780 { 781 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 782 783 if (ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1, 784 OV2740_MODE_STANDBY)) 785 dev_err(&client->dev, "failed to stop streaming\n"); 786 } 787 788 static int ov2740_set_stream(struct v4l2_subdev *sd, int enable) 789 { 790 struct ov2740 *ov2740 = to_ov2740(sd); 791 struct i2c_client *client = v4l2_get_subdevdata(sd); 792 int ret = 0; 793 794 mutex_lock(&ov2740->mutex); 795 if (enable) { 796 ret = pm_runtime_resume_and_get(&client->dev); 797 if (ret < 0) { 798 mutex_unlock(&ov2740->mutex); 799 return ret; 800 } 801 802 ret = ov2740_start_streaming(ov2740); 803 if (ret) { 804 enable = 0; 805 ov2740_stop_streaming(ov2740); 806 pm_runtime_put(&client->dev); 807 } 808 } else { 809 ov2740_stop_streaming(ov2740); 810 pm_runtime_put(&client->dev); 811 } 812 813 mutex_unlock(&ov2740->mutex); 814 815 return ret; 816 } 817 818 static int ov2740_set_format(struct v4l2_subdev *sd, 819 struct v4l2_subdev_state *sd_state, 820 struct v4l2_subdev_format *fmt) 821 { 822 struct ov2740 *ov2740 = to_ov2740(sd); 823 const struct ov2740_mode *mode; 824 s32 vblank_def, h_blank; 825 826 mode = v4l2_find_nearest_size(supported_modes, 827 ARRAY_SIZE(supported_modes), width, 828 height, fmt->format.width, 829 fmt->format.height); 830 831 mutex_lock(&ov2740->mutex); 832 ov2740_update_pad_format(mode, &fmt->format); 833 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { 834 *v4l2_subdev_get_try_format(sd, sd_state, fmt->pad) = fmt->format; 835 } else { 836 ov2740->cur_mode = mode; 837 __v4l2_ctrl_s_ctrl(ov2740->link_freq, mode->link_freq_index); 838 __v4l2_ctrl_s_ctrl_int64(ov2740->pixel_rate, 839 to_pixel_rate(mode->link_freq_index)); 840 841 /* Update limits and set FPS to default */ 842 vblank_def = mode->vts_def - mode->height; 843 __v4l2_ctrl_modify_range(ov2740->vblank, 844 mode->vts_min - mode->height, 845 OV2740_VTS_MAX - mode->height, 1, 846 vblank_def); 847 __v4l2_ctrl_s_ctrl(ov2740->vblank, vblank_def); 848 h_blank = to_pixels_per_line(mode->hts, mode->link_freq_index) - 849 mode->width; 850 __v4l2_ctrl_modify_range(ov2740->hblank, h_blank, h_blank, 1, 851 h_blank); 852 } 853 mutex_unlock(&ov2740->mutex); 854 855 return 0; 856 } 857 858 static int ov2740_get_format(struct v4l2_subdev *sd, 859 struct v4l2_subdev_state *sd_state, 860 struct v4l2_subdev_format *fmt) 861 { 862 struct ov2740 *ov2740 = to_ov2740(sd); 863 864 mutex_lock(&ov2740->mutex); 865 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) 866 fmt->format = *v4l2_subdev_get_try_format(&ov2740->sd, 867 sd_state, 868 fmt->pad); 869 else 870 ov2740_update_pad_format(ov2740->cur_mode, &fmt->format); 871 872 mutex_unlock(&ov2740->mutex); 873 874 return 0; 875 } 876 877 static int ov2740_enum_mbus_code(struct v4l2_subdev *sd, 878 struct v4l2_subdev_state *sd_state, 879 struct v4l2_subdev_mbus_code_enum *code) 880 { 881 if (code->index > 0) 882 return -EINVAL; 883 884 code->code = MEDIA_BUS_FMT_SGRBG10_1X10; 885 886 return 0; 887 } 888 889 static int ov2740_enum_frame_size(struct v4l2_subdev *sd, 890 struct v4l2_subdev_state *sd_state, 891 struct v4l2_subdev_frame_size_enum *fse) 892 { 893 if (fse->index >= ARRAY_SIZE(supported_modes)) 894 return -EINVAL; 895 896 if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10) 897 return -EINVAL; 898 899 fse->min_width = supported_modes[fse->index].width; 900 fse->max_width = fse->min_width; 901 fse->min_height = supported_modes[fse->index].height; 902 fse->max_height = fse->min_height; 903 904 return 0; 905 } 906 907 static int ov2740_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) 908 { 909 struct ov2740 *ov2740 = to_ov2740(sd); 910 911 mutex_lock(&ov2740->mutex); 912 ov2740_update_pad_format(&supported_modes[0], 913 v4l2_subdev_get_try_format(sd, fh->state, 0)); 914 mutex_unlock(&ov2740->mutex); 915 916 return 0; 917 } 918 919 static const struct v4l2_subdev_video_ops ov2740_video_ops = { 920 .s_stream = ov2740_set_stream, 921 }; 922 923 static const struct v4l2_subdev_pad_ops ov2740_pad_ops = { 924 .set_fmt = ov2740_set_format, 925 .get_fmt = ov2740_get_format, 926 .enum_mbus_code = ov2740_enum_mbus_code, 927 .enum_frame_size = ov2740_enum_frame_size, 928 }; 929 930 static const struct v4l2_subdev_ops ov2740_subdev_ops = { 931 .video = &ov2740_video_ops, 932 .pad = &ov2740_pad_ops, 933 }; 934 935 static const struct media_entity_operations ov2740_subdev_entity_ops = { 936 .link_validate = v4l2_subdev_link_validate, 937 }; 938 939 static const struct v4l2_subdev_internal_ops ov2740_internal_ops = { 940 .open = ov2740_open, 941 }; 942 943 static int ov2740_check_hwcfg(struct device *dev) 944 { 945 struct fwnode_handle *ep; 946 struct fwnode_handle *fwnode = dev_fwnode(dev); 947 struct v4l2_fwnode_endpoint bus_cfg = { 948 .bus_type = V4L2_MBUS_CSI2_DPHY 949 }; 950 u32 mclk; 951 int ret; 952 unsigned int i, j; 953 954 ret = fwnode_property_read_u32(fwnode, "clock-frequency", &mclk); 955 if (ret) 956 return ret; 957 958 if (mclk != OV2740_MCLK) 959 return dev_err_probe(dev, -EINVAL, 960 "external clock %d is not supported\n", 961 mclk); 962 963 ep = fwnode_graph_get_next_endpoint(fwnode, NULL); 964 if (!ep) 965 return -ENXIO; 966 967 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg); 968 fwnode_handle_put(ep); 969 if (ret) 970 return ret; 971 972 if (bus_cfg.bus.mipi_csi2.num_data_lanes != OV2740_DATA_LANES) { 973 ret = dev_err_probe(dev, -EINVAL, 974 "number of CSI2 data lanes %d is not supported\n", 975 bus_cfg.bus.mipi_csi2.num_data_lanes); 976 goto check_hwcfg_error; 977 } 978 979 if (!bus_cfg.nr_of_link_frequencies) { 980 ret = dev_err_probe(dev, -EINVAL, "no link frequencies defined\n"); 981 goto check_hwcfg_error; 982 } 983 984 for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) { 985 for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) { 986 if (link_freq_menu_items[i] == 987 bus_cfg.link_frequencies[j]) 988 break; 989 } 990 991 if (j == bus_cfg.nr_of_link_frequencies) { 992 ret = dev_err_probe(dev, -EINVAL, 993 "no link frequency %lld supported\n", 994 link_freq_menu_items[i]); 995 goto check_hwcfg_error; 996 } 997 } 998 999 check_hwcfg_error: 1000 v4l2_fwnode_endpoint_free(&bus_cfg); 1001 1002 return ret; 1003 } 1004 1005 static void ov2740_remove(struct i2c_client *client) 1006 { 1007 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1008 struct ov2740 *ov2740 = to_ov2740(sd); 1009 1010 v4l2_async_unregister_subdev(sd); 1011 media_entity_cleanup(&sd->entity); 1012 v4l2_ctrl_handler_free(sd->ctrl_handler); 1013 pm_runtime_disable(&client->dev); 1014 mutex_destroy(&ov2740->mutex); 1015 } 1016 1017 static int ov2740_nvmem_read(void *priv, unsigned int off, void *val, 1018 size_t count) 1019 { 1020 struct nvm_data *nvm = priv; 1021 struct device *dev = regmap_get_device(nvm->regmap); 1022 struct ov2740 *ov2740 = to_ov2740(dev_get_drvdata(dev)); 1023 int ret = 0; 1024 1025 mutex_lock(&ov2740->mutex); 1026 1027 if (nvm->nvm_buffer) { 1028 memcpy(val, nvm->nvm_buffer + off, count); 1029 goto exit; 1030 } 1031 1032 ret = pm_runtime_resume_and_get(dev); 1033 if (ret < 0) { 1034 goto exit; 1035 } 1036 1037 ret = ov2740_load_otp_data(nvm); 1038 if (!ret) 1039 memcpy(val, nvm->nvm_buffer + off, count); 1040 1041 pm_runtime_put(dev); 1042 exit: 1043 mutex_unlock(&ov2740->mutex); 1044 return ret; 1045 } 1046 1047 static int ov2740_register_nvmem(struct i2c_client *client, 1048 struct ov2740 *ov2740) 1049 { 1050 struct nvm_data *nvm; 1051 struct regmap_config regmap_config = { }; 1052 struct nvmem_config nvmem_config = { }; 1053 struct regmap *regmap; 1054 struct device *dev = &client->dev; 1055 1056 nvm = devm_kzalloc(dev, sizeof(*nvm), GFP_KERNEL); 1057 if (!nvm) 1058 return -ENOMEM; 1059 1060 regmap_config.val_bits = 8; 1061 regmap_config.reg_bits = 16; 1062 regmap_config.disable_locking = true; 1063 regmap = devm_regmap_init_i2c(client, ®map_config); 1064 if (IS_ERR(regmap)) 1065 return PTR_ERR(regmap); 1066 1067 nvm->regmap = regmap; 1068 1069 nvmem_config.name = dev_name(dev); 1070 nvmem_config.dev = dev; 1071 nvmem_config.read_only = true; 1072 nvmem_config.root_only = true; 1073 nvmem_config.owner = THIS_MODULE; 1074 nvmem_config.compat = true; 1075 nvmem_config.base_dev = dev; 1076 nvmem_config.reg_read = ov2740_nvmem_read; 1077 nvmem_config.reg_write = NULL; 1078 nvmem_config.priv = nvm; 1079 nvmem_config.stride = 1; 1080 nvmem_config.word_size = 1; 1081 nvmem_config.size = CUSTOMER_USE_OTP_SIZE; 1082 1083 nvm->nvmem = devm_nvmem_register(dev, &nvmem_config); 1084 if (IS_ERR(nvm->nvmem)) 1085 return PTR_ERR(nvm->nvmem); 1086 1087 ov2740->nvm = nvm; 1088 return 0; 1089 } 1090 1091 static int ov2740_probe(struct i2c_client *client) 1092 { 1093 struct device *dev = &client->dev; 1094 struct ov2740 *ov2740; 1095 bool full_power; 1096 int ret; 1097 1098 ret = ov2740_check_hwcfg(&client->dev); 1099 if (ret) 1100 return dev_err_probe(dev, ret, "failed to check HW configuration\n"); 1101 1102 ov2740 = devm_kzalloc(&client->dev, sizeof(*ov2740), GFP_KERNEL); 1103 if (!ov2740) 1104 return -ENOMEM; 1105 1106 v4l2_i2c_subdev_init(&ov2740->sd, client, &ov2740_subdev_ops); 1107 full_power = acpi_dev_state_d0(&client->dev); 1108 if (full_power) { 1109 ret = ov2740_identify_module(ov2740); 1110 if (ret) 1111 return dev_err_probe(dev, ret, "failed to find sensor\n"); 1112 } 1113 1114 mutex_init(&ov2740->mutex); 1115 ov2740->cur_mode = &supported_modes[0]; 1116 ret = ov2740_init_controls(ov2740); 1117 if (ret) { 1118 dev_err_probe(dev, ret, "failed to init controls\n"); 1119 goto probe_error_v4l2_ctrl_handler_free; 1120 } 1121 1122 ov2740->sd.internal_ops = &ov2740_internal_ops; 1123 ov2740->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1124 ov2740->sd.entity.ops = &ov2740_subdev_entity_ops; 1125 ov2740->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1126 ov2740->pad.flags = MEDIA_PAD_FL_SOURCE; 1127 ret = media_entity_pads_init(&ov2740->sd.entity, 1, &ov2740->pad); 1128 if (ret) { 1129 dev_err_probe(dev, ret, "failed to init entity pads\n"); 1130 goto probe_error_v4l2_ctrl_handler_free; 1131 } 1132 1133 ret = v4l2_async_register_subdev_sensor(&ov2740->sd); 1134 if (ret < 0) { 1135 dev_err_probe(dev, ret, "failed to register V4L2 subdev\n"); 1136 goto probe_error_media_entity_cleanup; 1137 } 1138 1139 ret = ov2740_register_nvmem(client, ov2740); 1140 if (ret) 1141 dev_warn(&client->dev, "register nvmem failed, ret %d\n", ret); 1142 1143 /* Set the device's state to active if it's in D0 state. */ 1144 if (full_power) 1145 pm_runtime_set_active(&client->dev); 1146 pm_runtime_enable(&client->dev); 1147 pm_runtime_idle(&client->dev); 1148 1149 return 0; 1150 1151 probe_error_media_entity_cleanup: 1152 media_entity_cleanup(&ov2740->sd.entity); 1153 1154 probe_error_v4l2_ctrl_handler_free: 1155 v4l2_ctrl_handler_free(ov2740->sd.ctrl_handler); 1156 mutex_destroy(&ov2740->mutex); 1157 1158 return ret; 1159 } 1160 1161 static const struct acpi_device_id ov2740_acpi_ids[] = { 1162 {"INT3474"}, 1163 {} 1164 }; 1165 1166 MODULE_DEVICE_TABLE(acpi, ov2740_acpi_ids); 1167 1168 static struct i2c_driver ov2740_i2c_driver = { 1169 .driver = { 1170 .name = "ov2740", 1171 .acpi_match_table = ov2740_acpi_ids, 1172 }, 1173 .probe = ov2740_probe, 1174 .remove = ov2740_remove, 1175 .flags = I2C_DRV_ACPI_WAIVE_D0_PROBE, 1176 }; 1177 1178 module_i2c_driver(ov2740_i2c_driver); 1179 1180 MODULE_AUTHOR("Qiu, Tianshu <tian.shu.qiu@intel.com>"); 1181 MODULE_AUTHOR("Shawn Tu"); 1182 MODULE_AUTHOR("Bingbu Cao <bingbu.cao@intel.com>"); 1183 MODULE_DESCRIPTION("OmniVision OV2740 sensor driver"); 1184 MODULE_LICENSE("GPL v2"); 1185