1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ov2685 driver 4 * 5 * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/device.h> 10 #include <linux/delay.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/i2c.h> 13 #include <linux/module.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/regulator/consumer.h> 16 #include <linux/sysfs.h> 17 #include <media/media-entity.h> 18 #include <media/v4l2-async.h> 19 #include <media/v4l2-ctrls.h> 20 #include <media/v4l2-subdev.h> 21 22 #define CHIP_ID 0x2685 23 #define OV2685_REG_CHIP_ID 0x300a 24 25 #define OV2685_XVCLK_FREQ 24000000 26 27 #define REG_SC_CTRL_MODE 0x0100 28 #define SC_CTRL_MODE_STANDBY 0x0 29 #define SC_CTRL_MODE_STREAMING BIT(0) 30 31 #define OV2685_REG_EXPOSURE 0x3500 32 #define OV2685_EXPOSURE_MIN 4 33 #define OV2685_EXPOSURE_STEP 1 34 35 #define OV2685_REG_VTS 0x380e 36 #define OV2685_VTS_MAX 0x7fff 37 38 #define OV2685_REG_GAIN 0x350a 39 #define OV2685_GAIN_MIN 0 40 #define OV2685_GAIN_MAX 0x07ff 41 #define OV2685_GAIN_STEP 0x1 42 #define OV2685_GAIN_DEFAULT 0x0036 43 44 #define OV2685_REG_TEST_PATTERN 0x5080 45 #define OV2685_TEST_PATTERN_DISABLED 0x00 46 #define OV2685_TEST_PATTERN_COLOR_BAR 0x80 47 #define OV2685_TEST_PATTERN_RANDOM 0x81 48 #define OV2685_TEST_PATTERN_COLOR_BAR_FADE 0x88 49 #define OV2685_TEST_PATTERN_BW_SQUARE 0x92 50 #define OV2685_TEST_PATTERN_COLOR_SQUARE 0x82 51 52 #define REG_NULL 0xFFFF 53 54 #define OV2685_REG_VALUE_08BIT 1 55 #define OV2685_REG_VALUE_16BIT 2 56 #define OV2685_REG_VALUE_24BIT 3 57 58 #define OV2685_LANES 1 59 #define OV2685_BITS_PER_SAMPLE 10 60 61 static const char * const ov2685_supply_names[] = { 62 "avdd", /* Analog power */ 63 "dovdd", /* Digital I/O power */ 64 "dvdd", /* Digital core power */ 65 }; 66 67 #define OV2685_NUM_SUPPLIES ARRAY_SIZE(ov2685_supply_names) 68 69 struct regval { 70 u16 addr; 71 u8 val; 72 }; 73 74 struct ov2685_mode { 75 u32 width; 76 u32 height; 77 u32 exp_def; 78 u32 hts_def; 79 u32 vts_def; 80 const struct regval *reg_list; 81 }; 82 83 struct ov2685 { 84 struct i2c_client *client; 85 struct clk *xvclk; 86 struct gpio_desc *reset_gpio; 87 struct regulator_bulk_data supplies[OV2685_NUM_SUPPLIES]; 88 89 bool streaming; 90 struct mutex mutex; 91 struct v4l2_subdev subdev; 92 struct media_pad pad; 93 struct v4l2_ctrl *anal_gain; 94 struct v4l2_ctrl *exposure; 95 struct v4l2_ctrl *hblank; 96 struct v4l2_ctrl *vblank; 97 struct v4l2_ctrl *test_pattern; 98 struct v4l2_ctrl_handler ctrl_handler; 99 100 const struct ov2685_mode *cur_mode; 101 }; 102 103 #define to_ov2685(sd) container_of(sd, struct ov2685, subdev) 104 105 /* PLL settings bases on 24M xvclk */ 106 static struct regval ov2685_1600x1200_regs[] = { 107 {0x0103, 0x01}, 108 {0x0100, 0x00}, 109 {0x3002, 0x00}, 110 {0x3016, 0x1c}, 111 {0x3018, 0x44}, 112 {0x301d, 0xf0}, 113 {0x3020, 0x00}, 114 {0x3082, 0x37}, 115 {0x3083, 0x03}, 116 {0x3084, 0x09}, 117 {0x3085, 0x04}, 118 {0x3086, 0x00}, 119 {0x3087, 0x00}, 120 {0x3501, 0x4e}, 121 {0x3502, 0xe0}, 122 {0x3503, 0x27}, 123 {0x350b, 0x36}, 124 {0x3600, 0xb4}, 125 {0x3603, 0x35}, 126 {0x3604, 0x24}, 127 {0x3605, 0x00}, 128 {0x3620, 0x24}, 129 {0x3621, 0x34}, 130 {0x3622, 0x03}, 131 {0x3628, 0x10}, 132 {0x3705, 0x3c}, 133 {0x370a, 0x21}, 134 {0x370c, 0x50}, 135 {0x370d, 0xc0}, 136 {0x3717, 0x58}, 137 {0x3718, 0x80}, 138 {0x3720, 0x00}, 139 {0x3721, 0x09}, 140 {0x3722, 0x06}, 141 {0x3723, 0x59}, 142 {0x3738, 0x99}, 143 {0x3781, 0x80}, 144 {0x3784, 0x0c}, 145 {0x3789, 0x60}, 146 {0x3800, 0x00}, 147 {0x3801, 0x00}, 148 {0x3802, 0x00}, 149 {0x3803, 0x00}, 150 {0x3804, 0x06}, 151 {0x3805, 0x4f}, 152 {0x3806, 0x04}, 153 {0x3807, 0xbf}, 154 {0x3808, 0x06}, 155 {0x3809, 0x40}, 156 {0x380a, 0x04}, 157 {0x380b, 0xb0}, 158 {0x380c, 0x06}, 159 {0x380d, 0xa4}, 160 {0x380e, 0x05}, 161 {0x380f, 0x0e}, 162 {0x3810, 0x00}, 163 {0x3811, 0x08}, 164 {0x3812, 0x00}, 165 {0x3813, 0x08}, 166 {0x3814, 0x11}, 167 {0x3815, 0x11}, 168 {0x3819, 0x04}, 169 {0x3820, 0xc0}, 170 {0x3821, 0x00}, 171 {0x3a06, 0x01}, 172 {0x3a07, 0x84}, 173 {0x3a08, 0x01}, 174 {0x3a09, 0x43}, 175 {0x3a0a, 0x24}, 176 {0x3a0b, 0x60}, 177 {0x3a0c, 0x28}, 178 {0x3a0d, 0x60}, 179 {0x3a0e, 0x04}, 180 {0x3a0f, 0x8c}, 181 {0x3a10, 0x05}, 182 {0x3a11, 0x0c}, 183 {0x4000, 0x81}, 184 {0x4001, 0x40}, 185 {0x4008, 0x02}, 186 {0x4009, 0x09}, 187 {0x4300, 0x00}, 188 {0x430e, 0x00}, 189 {0x4602, 0x02}, 190 {0x481b, 0x40}, 191 {0x481f, 0x40}, 192 {0x4837, 0x18}, 193 {0x5000, 0x1f}, 194 {0x5001, 0x05}, 195 {0x5002, 0x30}, 196 {0x5003, 0x04}, 197 {0x5004, 0x00}, 198 {0x5005, 0x0c}, 199 {0x5280, 0x15}, 200 {0x5281, 0x06}, 201 {0x5282, 0x06}, 202 {0x5283, 0x08}, 203 {0x5284, 0x1c}, 204 {0x5285, 0x1c}, 205 {0x5286, 0x20}, 206 {0x5287, 0x10}, 207 {REG_NULL, 0x00} 208 }; 209 210 #define OV2685_LINK_FREQ_330MHZ 330000000 211 static const s64 link_freq_menu_items[] = { 212 OV2685_LINK_FREQ_330MHZ 213 }; 214 215 static const char * const ov2685_test_pattern_menu[] = { 216 "Disabled", 217 "Color Bar", 218 "Color Bar FADE", 219 "Random Data", 220 "Black White Square", 221 "Color Square" 222 }; 223 224 static const int ov2685_test_pattern_val[] = { 225 OV2685_TEST_PATTERN_DISABLED, 226 OV2685_TEST_PATTERN_COLOR_BAR, 227 OV2685_TEST_PATTERN_COLOR_BAR_FADE, 228 OV2685_TEST_PATTERN_RANDOM, 229 OV2685_TEST_PATTERN_BW_SQUARE, 230 OV2685_TEST_PATTERN_COLOR_SQUARE, 231 }; 232 233 static const struct ov2685_mode supported_modes[] = { 234 { 235 .width = 1600, 236 .height = 1200, 237 .exp_def = 0x04ee, 238 .hts_def = 0x06a4, 239 .vts_def = 0x050e, 240 .reg_list = ov2685_1600x1200_regs, 241 }, 242 }; 243 244 /* Write registers up to 4 at a time */ 245 static int ov2685_write_reg(struct i2c_client *client, u16 reg, 246 u32 len, u32 val) 247 { 248 u32 val_i, buf_i; 249 u8 buf[6]; 250 u8 *val_p; 251 __be32 val_be; 252 253 if (len > 4) 254 return -EINVAL; 255 256 buf[0] = reg >> 8; 257 buf[1] = reg & 0xff; 258 259 val_be = cpu_to_be32(val); 260 val_p = (u8 *)&val_be; 261 buf_i = 2; 262 val_i = 4 - len; 263 264 while (val_i < 4) 265 buf[buf_i++] = val_p[val_i++]; 266 267 if (i2c_master_send(client, buf, len + 2) != len + 2) 268 return -EIO; 269 270 return 0; 271 } 272 273 static int ov2685_write_array(struct i2c_client *client, 274 const struct regval *regs) 275 { 276 int ret = 0; 277 u32 i; 278 279 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) 280 ret = ov2685_write_reg(client, regs[i].addr, 281 OV2685_REG_VALUE_08BIT, regs[i].val); 282 283 return ret; 284 } 285 286 /* Read registers up to 4 at a time */ 287 static int ov2685_read_reg(struct i2c_client *client, u16 reg, 288 u32 len, u32 *val) 289 { 290 struct i2c_msg msgs[2]; 291 u8 *data_be_p; 292 __be32 data_be = 0; 293 __be16 reg_addr_be = cpu_to_be16(reg); 294 int ret; 295 296 if (len > 4) 297 return -EINVAL; 298 299 data_be_p = (u8 *)&data_be; 300 /* Write register address */ 301 msgs[0].addr = client->addr; 302 msgs[0].flags = 0; 303 msgs[0].len = 2; 304 msgs[0].buf = (u8 *)®_addr_be; 305 306 /* Read data from register */ 307 msgs[1].addr = client->addr; 308 msgs[1].flags = I2C_M_RD; 309 msgs[1].len = len; 310 msgs[1].buf = &data_be_p[4 - len]; 311 312 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); 313 if (ret != ARRAY_SIZE(msgs)) 314 return -EIO; 315 316 *val = be32_to_cpu(data_be); 317 318 return 0; 319 } 320 321 static void ov2685_fill_fmt(const struct ov2685_mode *mode, 322 struct v4l2_mbus_framefmt *fmt) 323 { 324 fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10; 325 fmt->width = mode->width; 326 fmt->height = mode->height; 327 fmt->field = V4L2_FIELD_NONE; 328 } 329 330 static int ov2685_set_fmt(struct v4l2_subdev *sd, 331 struct v4l2_subdev_pad_config *cfg, 332 struct v4l2_subdev_format *fmt) 333 { 334 struct ov2685 *ov2685 = to_ov2685(sd); 335 struct v4l2_mbus_framefmt *mbus_fmt = &fmt->format; 336 337 /* only one mode supported for now */ 338 ov2685_fill_fmt(ov2685->cur_mode, mbus_fmt); 339 340 return 0; 341 } 342 343 static int ov2685_get_fmt(struct v4l2_subdev *sd, 344 struct v4l2_subdev_pad_config *cfg, 345 struct v4l2_subdev_format *fmt) 346 { 347 struct ov2685 *ov2685 = to_ov2685(sd); 348 struct v4l2_mbus_framefmt *mbus_fmt = &fmt->format; 349 350 ov2685_fill_fmt(ov2685->cur_mode, mbus_fmt); 351 352 return 0; 353 } 354 355 static int ov2685_enum_mbus_code(struct v4l2_subdev *sd, 356 struct v4l2_subdev_pad_config *cfg, 357 struct v4l2_subdev_mbus_code_enum *code) 358 { 359 if (code->index >= ARRAY_SIZE(supported_modes)) 360 return -EINVAL; 361 362 code->code = MEDIA_BUS_FMT_SBGGR10_1X10; 363 364 return 0; 365 } 366 367 static int ov2685_enum_frame_sizes(struct v4l2_subdev *sd, 368 struct v4l2_subdev_pad_config *cfg, 369 struct v4l2_subdev_frame_size_enum *fse) 370 { 371 int index = fse->index; 372 373 if (index >= ARRAY_SIZE(supported_modes)) 374 return -EINVAL; 375 376 fse->code = MEDIA_BUS_FMT_SBGGR10_1X10; 377 378 fse->min_width = supported_modes[index].width; 379 fse->max_width = supported_modes[index].width; 380 fse->max_height = supported_modes[index].height; 381 fse->min_height = supported_modes[index].height; 382 383 return 0; 384 } 385 386 /* Calculate the delay in us by clock rate and clock cycles */ 387 static inline u32 ov2685_cal_delay(u32 cycles) 388 { 389 return DIV_ROUND_UP(cycles, OV2685_XVCLK_FREQ / 1000 / 1000); 390 } 391 392 static int __ov2685_power_on(struct ov2685 *ov2685) 393 { 394 int ret; 395 u32 delay_us; 396 struct device *dev = &ov2685->client->dev; 397 398 ret = clk_prepare_enable(ov2685->xvclk); 399 if (ret < 0) { 400 dev_err(dev, "Failed to enable xvclk\n"); 401 return ret; 402 } 403 404 gpiod_set_value_cansleep(ov2685->reset_gpio, 1); 405 406 ret = regulator_bulk_enable(OV2685_NUM_SUPPLIES, ov2685->supplies); 407 if (ret < 0) { 408 dev_err(dev, "Failed to enable regulators\n"); 409 goto disable_clk; 410 } 411 412 /* The minimum delay between power supplies and reset rising can be 0 */ 413 gpiod_set_value_cansleep(ov2685->reset_gpio, 0); 414 /* 8192 xvclk cycles prior to the first SCCB transaction */ 415 delay_us = ov2685_cal_delay(8192); 416 usleep_range(delay_us, delay_us * 2); 417 418 /* HACK: ov2685 would output messy data after reset(R0103), 419 * writing register before .s_stream() as a workaround 420 */ 421 ret = ov2685_write_array(ov2685->client, ov2685->cur_mode->reg_list); 422 if (ret) 423 goto disable_supplies; 424 425 return 0; 426 427 disable_supplies: 428 regulator_bulk_disable(OV2685_NUM_SUPPLIES, ov2685->supplies); 429 disable_clk: 430 clk_disable_unprepare(ov2685->xvclk); 431 432 return ret; 433 } 434 435 static void __ov2685_power_off(struct ov2685 *ov2685) 436 { 437 /* 512 xvclk cycles after the last SCCB transaction or MIPI frame end */ 438 u32 delay_us = ov2685_cal_delay(512); 439 440 usleep_range(delay_us, delay_us * 2); 441 clk_disable_unprepare(ov2685->xvclk); 442 gpiod_set_value_cansleep(ov2685->reset_gpio, 1); 443 regulator_bulk_disable(OV2685_NUM_SUPPLIES, ov2685->supplies); 444 } 445 446 static int ov2685_s_stream(struct v4l2_subdev *sd, int on) 447 { 448 struct ov2685 *ov2685 = to_ov2685(sd); 449 struct i2c_client *client = ov2685->client; 450 int ret = 0; 451 452 mutex_lock(&ov2685->mutex); 453 454 on = !!on; 455 if (on == ov2685->streaming) 456 goto unlock_and_return; 457 458 if (on) { 459 ret = pm_runtime_get_sync(&ov2685->client->dev); 460 if (ret < 0) { 461 pm_runtime_put_noidle(&client->dev); 462 goto unlock_and_return; 463 } 464 ret = __v4l2_ctrl_handler_setup(&ov2685->ctrl_handler); 465 if (ret) { 466 pm_runtime_put(&client->dev); 467 goto unlock_and_return; 468 } 469 ret = ov2685_write_reg(client, REG_SC_CTRL_MODE, 470 OV2685_REG_VALUE_08BIT, SC_CTRL_MODE_STREAMING); 471 if (ret) { 472 pm_runtime_put(&client->dev); 473 goto unlock_and_return; 474 } 475 } else { 476 ov2685_write_reg(client, REG_SC_CTRL_MODE, 477 OV2685_REG_VALUE_08BIT, SC_CTRL_MODE_STANDBY); 478 pm_runtime_put(&ov2685->client->dev); 479 } 480 481 ov2685->streaming = on; 482 483 unlock_and_return: 484 mutex_unlock(&ov2685->mutex); 485 486 return ret; 487 } 488 489 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 490 static int ov2685_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) 491 { 492 struct ov2685 *ov2685 = to_ov2685(sd); 493 struct v4l2_mbus_framefmt *try_fmt; 494 495 mutex_lock(&ov2685->mutex); 496 497 try_fmt = v4l2_subdev_get_try_format(sd, fh->pad, 0); 498 /* Initialize try_fmt */ 499 ov2685_fill_fmt(&supported_modes[0], try_fmt); 500 501 mutex_unlock(&ov2685->mutex); 502 503 return 0; 504 } 505 #endif 506 507 static int __maybe_unused ov2685_runtime_resume(struct device *dev) 508 { 509 struct v4l2_subdev *sd = dev_get_drvdata(dev); 510 struct ov2685 *ov2685 = to_ov2685(sd); 511 512 return __ov2685_power_on(ov2685); 513 } 514 515 static int __maybe_unused ov2685_runtime_suspend(struct device *dev) 516 { 517 struct v4l2_subdev *sd = dev_get_drvdata(dev); 518 struct ov2685 *ov2685 = to_ov2685(sd); 519 520 __ov2685_power_off(ov2685); 521 522 return 0; 523 } 524 525 static const struct dev_pm_ops ov2685_pm_ops = { 526 SET_RUNTIME_PM_OPS(ov2685_runtime_suspend, 527 ov2685_runtime_resume, NULL) 528 }; 529 530 static int ov2685_set_ctrl(struct v4l2_ctrl *ctrl) 531 { 532 struct ov2685 *ov2685 = container_of(ctrl->handler, 533 struct ov2685, ctrl_handler); 534 struct i2c_client *client = ov2685->client; 535 s64 max_expo; 536 int ret; 537 538 /* Propagate change of current control to all related controls */ 539 switch (ctrl->id) { 540 case V4L2_CID_VBLANK: 541 /* Update max exposure while meeting expected vblanking */ 542 max_expo = ov2685->cur_mode->height + ctrl->val - 4; 543 __v4l2_ctrl_modify_range(ov2685->exposure, 544 ov2685->exposure->minimum, max_expo, 545 ov2685->exposure->step, 546 ov2685->exposure->default_value); 547 break; 548 } 549 550 if (!pm_runtime_get_if_in_use(&client->dev)) 551 return 0; 552 553 switch (ctrl->id) { 554 case V4L2_CID_EXPOSURE: 555 ret = ov2685_write_reg(ov2685->client, OV2685_REG_EXPOSURE, 556 OV2685_REG_VALUE_24BIT, ctrl->val << 4); 557 break; 558 case V4L2_CID_ANALOGUE_GAIN: 559 ret = ov2685_write_reg(ov2685->client, OV2685_REG_GAIN, 560 OV2685_REG_VALUE_16BIT, ctrl->val); 561 break; 562 case V4L2_CID_VBLANK: 563 ret = ov2685_write_reg(ov2685->client, OV2685_REG_VTS, 564 OV2685_REG_VALUE_16BIT, 565 ctrl->val + ov2685->cur_mode->height); 566 break; 567 case V4L2_CID_TEST_PATTERN: 568 ret = ov2685_write_reg(ov2685->client, OV2685_REG_TEST_PATTERN, 569 OV2685_REG_VALUE_08BIT, 570 ov2685_test_pattern_val[ctrl->val]); 571 break; 572 default: 573 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n", 574 __func__, ctrl->id, ctrl->val); 575 ret = -EINVAL; 576 break; 577 } 578 579 pm_runtime_put(&client->dev); 580 581 return ret; 582 } 583 584 static const struct v4l2_subdev_video_ops ov2685_video_ops = { 585 .s_stream = ov2685_s_stream, 586 }; 587 588 static const struct v4l2_subdev_pad_ops ov2685_pad_ops = { 589 .enum_mbus_code = ov2685_enum_mbus_code, 590 .enum_frame_size = ov2685_enum_frame_sizes, 591 .get_fmt = ov2685_get_fmt, 592 .set_fmt = ov2685_set_fmt, 593 }; 594 595 static const struct v4l2_subdev_ops ov2685_subdev_ops = { 596 .video = &ov2685_video_ops, 597 .pad = &ov2685_pad_ops, 598 }; 599 600 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 601 static const struct v4l2_subdev_internal_ops ov2685_internal_ops = { 602 .open = ov2685_open, 603 }; 604 #endif 605 606 static const struct v4l2_ctrl_ops ov2685_ctrl_ops = { 607 .s_ctrl = ov2685_set_ctrl, 608 }; 609 610 static int ov2685_initialize_controls(struct ov2685 *ov2685) 611 { 612 const struct ov2685_mode *mode; 613 struct v4l2_ctrl_handler *handler; 614 struct v4l2_ctrl *ctrl; 615 u64 exposure_max; 616 u32 pixel_rate, h_blank; 617 int ret; 618 619 handler = &ov2685->ctrl_handler; 620 mode = ov2685->cur_mode; 621 ret = v4l2_ctrl_handler_init(handler, 8); 622 if (ret) 623 return ret; 624 handler->lock = &ov2685->mutex; 625 626 ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ, 627 0, 0, link_freq_menu_items); 628 if (ctrl) 629 ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY; 630 631 pixel_rate = (link_freq_menu_items[0] * 2 * OV2685_LANES) / 632 OV2685_BITS_PER_SAMPLE; 633 v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE, 634 0, pixel_rate, 1, pixel_rate); 635 636 h_blank = mode->hts_def - mode->width; 637 ov2685->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK, 638 h_blank, h_blank, 1, h_blank); 639 if (ov2685->hblank) 640 ov2685->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; 641 642 ov2685->vblank = v4l2_ctrl_new_std(handler, &ov2685_ctrl_ops, 643 V4L2_CID_VBLANK, mode->vts_def - mode->height, 644 OV2685_VTS_MAX - mode->height, 1, 645 mode->vts_def - mode->height); 646 647 exposure_max = mode->vts_def - 4; 648 ov2685->exposure = v4l2_ctrl_new_std(handler, &ov2685_ctrl_ops, 649 V4L2_CID_EXPOSURE, OV2685_EXPOSURE_MIN, 650 exposure_max, OV2685_EXPOSURE_STEP, 651 mode->exp_def); 652 653 ov2685->anal_gain = v4l2_ctrl_new_std(handler, &ov2685_ctrl_ops, 654 V4L2_CID_ANALOGUE_GAIN, OV2685_GAIN_MIN, 655 OV2685_GAIN_MAX, OV2685_GAIN_STEP, 656 OV2685_GAIN_DEFAULT); 657 658 ov2685->test_pattern = v4l2_ctrl_new_std_menu_items(handler, 659 &ov2685_ctrl_ops, V4L2_CID_TEST_PATTERN, 660 ARRAY_SIZE(ov2685_test_pattern_menu) - 1, 661 0, 0, ov2685_test_pattern_menu); 662 663 if (handler->error) { 664 ret = handler->error; 665 dev_err(&ov2685->client->dev, 666 "Failed to init controls(%d)\n", ret); 667 goto err_free_handler; 668 } 669 670 ov2685->subdev.ctrl_handler = handler; 671 672 return 0; 673 674 err_free_handler: 675 v4l2_ctrl_handler_free(handler); 676 677 return ret; 678 } 679 680 static int ov2685_check_sensor_id(struct ov2685 *ov2685, 681 struct i2c_client *client) 682 { 683 struct device *dev = &ov2685->client->dev; 684 int ret; 685 u32 id = 0; 686 687 ret = ov2685_read_reg(client, OV2685_REG_CHIP_ID, 688 OV2685_REG_VALUE_16BIT, &id); 689 if (id != CHIP_ID) { 690 dev_err(dev, "Unexpected sensor id(%04x), ret(%d)\n", id, ret); 691 return ret; 692 } 693 694 dev_info(dev, "Detected OV%04x sensor\n", CHIP_ID); 695 696 return 0; 697 } 698 699 static int ov2685_configure_regulators(struct ov2685 *ov2685) 700 { 701 int i; 702 703 for (i = 0; i < OV2685_NUM_SUPPLIES; i++) 704 ov2685->supplies[i].supply = ov2685_supply_names[i]; 705 706 return devm_regulator_bulk_get(&ov2685->client->dev, 707 OV2685_NUM_SUPPLIES, 708 ov2685->supplies); 709 } 710 711 static int ov2685_probe(struct i2c_client *client, 712 const struct i2c_device_id *id) 713 { 714 struct device *dev = &client->dev; 715 struct ov2685 *ov2685; 716 int ret; 717 718 ov2685 = devm_kzalloc(dev, sizeof(*ov2685), GFP_KERNEL); 719 if (!ov2685) 720 return -ENOMEM; 721 722 ov2685->client = client; 723 ov2685->cur_mode = &supported_modes[0]; 724 725 ov2685->xvclk = devm_clk_get(dev, "xvclk"); 726 if (IS_ERR(ov2685->xvclk)) { 727 dev_err(dev, "Failed to get xvclk\n"); 728 return -EINVAL; 729 } 730 ret = clk_set_rate(ov2685->xvclk, OV2685_XVCLK_FREQ); 731 if (ret < 0) { 732 dev_err(dev, "Failed to set xvclk rate (24MHz)\n"); 733 return ret; 734 } 735 if (clk_get_rate(ov2685->xvclk) != OV2685_XVCLK_FREQ) 736 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n"); 737 738 ov2685->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); 739 if (IS_ERR(ov2685->reset_gpio)) { 740 dev_err(dev, "Failed to get reset-gpios\n"); 741 return -EINVAL; 742 } 743 744 ret = ov2685_configure_regulators(ov2685); 745 if (ret) { 746 dev_err(dev, "Failed to get power regulators\n"); 747 return ret; 748 } 749 750 mutex_init(&ov2685->mutex); 751 v4l2_i2c_subdev_init(&ov2685->subdev, client, &ov2685_subdev_ops); 752 ret = ov2685_initialize_controls(ov2685); 753 if (ret) 754 goto err_destroy_mutex; 755 756 ret = __ov2685_power_on(ov2685); 757 if (ret) 758 goto err_free_handler; 759 760 ret = ov2685_check_sensor_id(ov2685, client); 761 if (ret) 762 goto err_power_off; 763 764 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 765 ov2685->subdev.internal_ops = &ov2685_internal_ops; 766 ov2685->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 767 #endif 768 #if defined(CONFIG_MEDIA_CONTROLLER) 769 ov2685->pad.flags = MEDIA_PAD_FL_SOURCE; 770 ov2685->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR; 771 ret = media_entity_pads_init(&ov2685->subdev.entity, 1, &ov2685->pad); 772 if (ret < 0) 773 goto err_power_off; 774 #endif 775 776 ret = v4l2_async_register_subdev(&ov2685->subdev); 777 if (ret) { 778 dev_err(dev, "v4l2 async register subdev failed\n"); 779 goto err_clean_entity; 780 } 781 782 pm_runtime_set_active(dev); 783 pm_runtime_enable(dev); 784 pm_runtime_idle(dev); 785 786 return 0; 787 788 err_clean_entity: 789 #if defined(CONFIG_MEDIA_CONTROLLER) 790 media_entity_cleanup(&ov2685->subdev.entity); 791 #endif 792 err_power_off: 793 __ov2685_power_off(ov2685); 794 err_free_handler: 795 v4l2_ctrl_handler_free(&ov2685->ctrl_handler); 796 err_destroy_mutex: 797 mutex_destroy(&ov2685->mutex); 798 799 return ret; 800 } 801 802 static int ov2685_remove(struct i2c_client *client) 803 { 804 struct v4l2_subdev *sd = i2c_get_clientdata(client); 805 struct ov2685 *ov2685 = to_ov2685(sd); 806 807 v4l2_async_unregister_subdev(sd); 808 #if defined(CONFIG_MEDIA_CONTROLLER) 809 media_entity_cleanup(&sd->entity); 810 #endif 811 v4l2_ctrl_handler_free(&ov2685->ctrl_handler); 812 mutex_destroy(&ov2685->mutex); 813 814 pm_runtime_disable(&client->dev); 815 if (!pm_runtime_status_suspended(&client->dev)) 816 __ov2685_power_off(ov2685); 817 pm_runtime_set_suspended(&client->dev); 818 819 return 0; 820 } 821 822 #if IS_ENABLED(CONFIG_OF) 823 static const struct of_device_id ov2685_of_match[] = { 824 { .compatible = "ovti,ov2685" }, 825 {}, 826 }; 827 MODULE_DEVICE_TABLE(of, ov2685_of_match); 828 #endif 829 830 static struct i2c_driver ov2685_i2c_driver = { 831 .driver = { 832 .name = "ov2685", 833 .pm = &ov2685_pm_ops, 834 .of_match_table = of_match_ptr(ov2685_of_match), 835 }, 836 .probe = &ov2685_probe, 837 .remove = &ov2685_remove, 838 }; 839 840 module_i2c_driver(ov2685_i2c_driver); 841 842 MODULE_DESCRIPTION("OmniVision ov2685 sensor driver"); 843 MODULE_LICENSE("GPL v2"); 844