1 /* 2 * ov2640 Camera Driver 3 * 4 * Copyright (C) 2010 Alberto Panizzo <maramaopercheseimorto@gmail.com> 5 * 6 * Based on ov772x, ov9640 drivers and previous non merged implementations. 7 * 8 * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. 9 * Copyright (C) 2006, OmniVision 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16 #include <linux/init.h> 17 #include <linux/module.h> 18 #include <linux/i2c.h> 19 #include <linux/clk.h> 20 #include <linux/slab.h> 21 #include <linux/delay.h> 22 #include <linux/gpio.h> 23 #include <linux/gpio/consumer.h> 24 #include <linux/of_gpio.h> 25 #include <linux/v4l2-mediabus.h> 26 #include <linux/videodev2.h> 27 28 #include <media/v4l2-device.h> 29 #include <media/v4l2-event.h> 30 #include <media/v4l2-subdev.h> 31 #include <media/v4l2-ctrls.h> 32 #include <media/v4l2-image-sizes.h> 33 34 #define VAL_SET(x, mask, rshift, lshift) \ 35 ((((x) >> rshift) & mask) << lshift) 36 /* 37 * DSP registers 38 * register offset for BANK_SEL == BANK_SEL_DSP 39 */ 40 #define R_BYPASS 0x05 /* Bypass DSP */ 41 #define R_BYPASS_DSP_BYPAS 0x01 /* Bypass DSP, sensor out directly */ 42 #define R_BYPASS_USE_DSP 0x00 /* Use the internal DSP */ 43 #define QS 0x44 /* Quantization Scale Factor */ 44 #define CTRLI 0x50 45 #define CTRLI_LP_DP 0x80 46 #define CTRLI_ROUND 0x40 47 #define CTRLI_V_DIV_SET(x) VAL_SET(x, 0x3, 0, 3) 48 #define CTRLI_H_DIV_SET(x) VAL_SET(x, 0x3, 0, 0) 49 #define HSIZE 0x51 /* H_SIZE[7:0] (real/4) */ 50 #define HSIZE_SET(x) VAL_SET(x, 0xFF, 2, 0) 51 #define VSIZE 0x52 /* V_SIZE[7:0] (real/4) */ 52 #define VSIZE_SET(x) VAL_SET(x, 0xFF, 2, 0) 53 #define XOFFL 0x53 /* OFFSET_X[7:0] */ 54 #define XOFFL_SET(x) VAL_SET(x, 0xFF, 0, 0) 55 #define YOFFL 0x54 /* OFFSET_Y[7:0] */ 56 #define YOFFL_SET(x) VAL_SET(x, 0xFF, 0, 0) 57 #define VHYX 0x55 /* Offset and size completion */ 58 #define VHYX_VSIZE_SET(x) VAL_SET(x, 0x1, (8+2), 7) 59 #define VHYX_HSIZE_SET(x) VAL_SET(x, 0x1, (8+2), 3) 60 #define VHYX_YOFF_SET(x) VAL_SET(x, 0x3, 8, 4) 61 #define VHYX_XOFF_SET(x) VAL_SET(x, 0x3, 8, 0) 62 #define DPRP 0x56 63 #define TEST 0x57 /* Horizontal size completion */ 64 #define TEST_HSIZE_SET(x) VAL_SET(x, 0x1, (9+2), 7) 65 #define ZMOW 0x5A /* Zoom: Out Width OUTW[7:0] (real/4) */ 66 #define ZMOW_OUTW_SET(x) VAL_SET(x, 0xFF, 2, 0) 67 #define ZMOH 0x5B /* Zoom: Out Height OUTH[7:0] (real/4) */ 68 #define ZMOH_OUTH_SET(x) VAL_SET(x, 0xFF, 2, 0) 69 #define ZMHH 0x5C /* Zoom: Speed and H&W completion */ 70 #define ZMHH_ZSPEED_SET(x) VAL_SET(x, 0x0F, 0, 4) 71 #define ZMHH_OUTH_SET(x) VAL_SET(x, 0x1, (8+2), 2) 72 #define ZMHH_OUTW_SET(x) VAL_SET(x, 0x3, (8+2), 0) 73 #define BPADDR 0x7C /* SDE Indirect Register Access: Address */ 74 #define BPDATA 0x7D /* SDE Indirect Register Access: Data */ 75 #define CTRL2 0x86 /* DSP Module enable 2 */ 76 #define CTRL2_DCW_EN 0x20 77 #define CTRL2_SDE_EN 0x10 78 #define CTRL2_UV_ADJ_EN 0x08 79 #define CTRL2_UV_AVG_EN 0x04 80 #define CTRL2_CMX_EN 0x01 81 #define CTRL3 0x87 /* DSP Module enable 3 */ 82 #define CTRL3_BPC_EN 0x80 83 #define CTRL3_WPC_EN 0x40 84 #define SIZEL 0x8C /* Image Size Completion */ 85 #define SIZEL_HSIZE8_11_SET(x) VAL_SET(x, 0x1, 11, 6) 86 #define SIZEL_HSIZE8_SET(x) VAL_SET(x, 0x7, 0, 3) 87 #define SIZEL_VSIZE8_SET(x) VAL_SET(x, 0x7, 0, 0) 88 #define HSIZE8 0xC0 /* Image Horizontal Size HSIZE[10:3] */ 89 #define HSIZE8_SET(x) VAL_SET(x, 0xFF, 3, 0) 90 #define VSIZE8 0xC1 /* Image Vertical Size VSIZE[10:3] */ 91 #define VSIZE8_SET(x) VAL_SET(x, 0xFF, 3, 0) 92 #define CTRL0 0xC2 /* DSP Module enable 0 */ 93 #define CTRL0_AEC_EN 0x80 94 #define CTRL0_AEC_SEL 0x40 95 #define CTRL0_STAT_SEL 0x20 96 #define CTRL0_VFIRST 0x10 97 #define CTRL0_YUV422 0x08 98 #define CTRL0_YUV_EN 0x04 99 #define CTRL0_RGB_EN 0x02 100 #define CTRL0_RAW_EN 0x01 101 #define CTRL1 0xC3 /* DSP Module enable 1 */ 102 #define CTRL1_CIP 0x80 103 #define CTRL1_DMY 0x40 104 #define CTRL1_RAW_GMA 0x20 105 #define CTRL1_DG 0x10 106 #define CTRL1_AWB 0x08 107 #define CTRL1_AWB_GAIN 0x04 108 #define CTRL1_LENC 0x02 109 #define CTRL1_PRE 0x01 110 /* REG 0xC7 (unknown name): affects Auto White Balance (AWB) 111 * AWB_OFF 0x40 112 * AWB_SIMPLE 0x10 113 * AWB_ON 0x00 (Advanced AWB ?) */ 114 #define R_DVP_SP 0xD3 /* DVP output speed control */ 115 #define R_DVP_SP_AUTO_MODE 0x80 116 #define R_DVP_SP_DVP_MASK 0x3F /* DVP PCLK = sysclk (48)/[6:0] (YUV0); 117 * = sysclk (48)/(2*[6:0]) (RAW);*/ 118 #define IMAGE_MODE 0xDA /* Image Output Format Select */ 119 #define IMAGE_MODE_Y8_DVP_EN 0x40 120 #define IMAGE_MODE_JPEG_EN 0x10 121 #define IMAGE_MODE_YUV422 0x00 122 #define IMAGE_MODE_RAW10 0x04 /* (DVP) */ 123 #define IMAGE_MODE_RGB565 0x08 124 #define IMAGE_MODE_HREF_VSYNC 0x02 /* HREF timing select in DVP JPEG output 125 * mode (0 for HREF is same as sensor) */ 126 #define IMAGE_MODE_LBYTE_FIRST 0x01 /* Byte swap enable for DVP 127 * 1: Low byte first UYVY (C2[4] =0) 128 * VYUY (C2[4] =1) 129 * 0: High byte first YUYV (C2[4]=0) 130 * YVYU (C2[4] = 1) */ 131 #define RESET 0xE0 /* Reset */ 132 #define RESET_MICROC 0x40 133 #define RESET_SCCB 0x20 134 #define RESET_JPEG 0x10 135 #define RESET_DVP 0x04 136 #define RESET_IPU 0x02 137 #define RESET_CIF 0x01 138 #define REGED 0xED /* Register ED */ 139 #define REGED_CLK_OUT_DIS 0x10 140 #define MS_SP 0xF0 /* SCCB Master Speed */ 141 #define SS_ID 0xF7 /* SCCB Slave ID */ 142 #define SS_CTRL 0xF8 /* SCCB Slave Control */ 143 #define SS_CTRL_ADD_AUTO_INC 0x20 144 #define SS_CTRL_EN 0x08 145 #define SS_CTRL_DELAY_CLK 0x04 146 #define SS_CTRL_ACC_EN 0x02 147 #define SS_CTRL_SEN_PASS_THR 0x01 148 #define MC_BIST 0xF9 /* Microcontroller misc register */ 149 #define MC_BIST_RESET 0x80 /* Microcontroller Reset */ 150 #define MC_BIST_BOOT_ROM_SEL 0x40 151 #define MC_BIST_12KB_SEL 0x20 152 #define MC_BIST_12KB_MASK 0x30 153 #define MC_BIST_512KB_SEL 0x08 154 #define MC_BIST_512KB_MASK 0x0C 155 #define MC_BIST_BUSY_BIT_R 0x02 156 #define MC_BIST_MC_RES_ONE_SH_W 0x02 157 #define MC_BIST_LAUNCH 0x01 158 #define BANK_SEL 0xFF /* Register Bank Select */ 159 #define BANK_SEL_DSP 0x00 160 #define BANK_SEL_SENS 0x01 161 162 /* 163 * Sensor registers 164 * register offset for BANK_SEL == BANK_SEL_SENS 165 */ 166 #define GAIN 0x00 /* AGC - Gain control gain setting */ 167 #define COM1 0x03 /* Common control 1 */ 168 #define COM1_1_DUMMY_FR 0x40 169 #define COM1_3_DUMMY_FR 0x80 170 #define COM1_7_DUMMY_FR 0xC0 171 #define COM1_VWIN_LSB_UXGA 0x0F 172 #define COM1_VWIN_LSB_SVGA 0x0A 173 #define COM1_VWIN_LSB_CIF 0x06 174 #define REG04 0x04 /* Register 04 */ 175 #define REG04_DEF 0x20 /* Always set */ 176 #define REG04_HFLIP_IMG 0x80 /* Horizontal mirror image ON/OFF */ 177 #define REG04_VFLIP_IMG 0x40 /* Vertical flip image ON/OFF */ 178 #define REG04_VREF_EN 0x10 179 #define REG04_HREF_EN 0x08 180 #define REG04_AEC_SET(x) VAL_SET(x, 0x3, 0, 0) 181 #define REG08 0x08 /* Frame Exposure One-pin Control Pre-charge Row Num */ 182 #define COM2 0x09 /* Common control 2 */ 183 #define COM2_SOFT_SLEEP_MODE 0x10 /* Soft sleep mode */ 184 /* Output drive capability */ 185 #define COM2_OCAP_Nx_SET(N) (((N) - 1) & 0x03) /* N = [1x .. 4x] */ 186 #define PID 0x0A /* Product ID Number MSB */ 187 #define VER 0x0B /* Product ID Number LSB */ 188 #define COM3 0x0C /* Common control 3 */ 189 #define COM3_BAND_50H 0x04 /* 0 For Banding at 60H */ 190 #define COM3_BAND_AUTO 0x02 /* Auto Banding */ 191 #define COM3_SING_FR_SNAPSH 0x01 /* 0 For enable live video output after the 192 * snapshot sequence*/ 193 #define AEC 0x10 /* AEC[9:2] Exposure Value */ 194 #define CLKRC 0x11 /* Internal clock */ 195 #define CLKRC_EN 0x80 196 #define CLKRC_DIV_SET(x) (((x) - 1) & 0x1F) /* CLK = XVCLK/(x) */ 197 #define COM7 0x12 /* Common control 7 */ 198 #define COM7_SRST 0x80 /* Initiates system reset. All registers are 199 * set to factory default values after which 200 * the chip resumes normal operation */ 201 #define COM7_RES_UXGA 0x00 /* Resolution selectors for UXGA */ 202 #define COM7_RES_SVGA 0x40 /* SVGA */ 203 #define COM7_RES_CIF 0x20 /* CIF */ 204 #define COM7_ZOOM_EN 0x04 /* Enable Zoom mode */ 205 #define COM7_COLOR_BAR_TEST 0x02 /* Enable Color Bar Test Pattern */ 206 #define COM8 0x13 /* Common control 8 */ 207 #define COM8_DEF 0xC0 208 #define COM8_BNDF_EN 0x20 /* Banding filter ON/OFF */ 209 #define COM8_AGC_EN 0x04 /* AGC Auto/Manual control selection */ 210 #define COM8_AEC_EN 0x01 /* Auto/Manual Exposure control */ 211 #define COM9 0x14 /* Common control 9 212 * Automatic gain ceiling - maximum AGC value [7:5]*/ 213 #define COM9_AGC_GAIN_2x 0x00 /* 000 : 2x */ 214 #define COM9_AGC_GAIN_4x 0x20 /* 001 : 4x */ 215 #define COM9_AGC_GAIN_8x 0x40 /* 010 : 8x */ 216 #define COM9_AGC_GAIN_16x 0x60 /* 011 : 16x */ 217 #define COM9_AGC_GAIN_32x 0x80 /* 100 : 32x */ 218 #define COM9_AGC_GAIN_64x 0xA0 /* 101 : 64x */ 219 #define COM9_AGC_GAIN_128x 0xC0 /* 110 : 128x */ 220 #define COM10 0x15 /* Common control 10 */ 221 #define COM10_PCLK_HREF 0x20 /* PCLK output qualified by HREF */ 222 #define COM10_PCLK_RISE 0x10 /* Data is updated at the rising edge of 223 * PCLK (user can latch data at the next 224 * falling edge of PCLK). 225 * 0 otherwise. */ 226 #define COM10_HREF_INV 0x08 /* Invert HREF polarity: 227 * HREF negative for valid data*/ 228 #define COM10_VSINC_INV 0x02 /* Invert VSYNC polarity */ 229 #define HSTART 0x17 /* Horizontal Window start MSB 8 bit */ 230 #define HEND 0x18 /* Horizontal Window end MSB 8 bit */ 231 #define VSTART 0x19 /* Vertical Window start MSB 8 bit */ 232 #define VEND 0x1A /* Vertical Window end MSB 8 bit */ 233 #define MIDH 0x1C /* Manufacturer ID byte - high */ 234 #define MIDL 0x1D /* Manufacturer ID byte - low */ 235 #define AEW 0x24 /* AGC/AEC - Stable operating region (upper limit) */ 236 #define AEB 0x25 /* AGC/AEC - Stable operating region (lower limit) */ 237 #define VV 0x26 /* AGC/AEC Fast mode operating region */ 238 #define VV_HIGH_TH_SET(x) VAL_SET(x, 0xF, 0, 4) 239 #define VV_LOW_TH_SET(x) VAL_SET(x, 0xF, 0, 0) 240 #define REG2A 0x2A /* Dummy pixel insert MSB */ 241 #define FRARL 0x2B /* Dummy pixel insert LSB */ 242 #define ADDVFL 0x2D /* LSB of insert dummy lines in Vertical direction */ 243 #define ADDVFH 0x2E /* MSB of insert dummy lines in Vertical direction */ 244 #define YAVG 0x2F /* Y/G Channel Average value */ 245 #define REG32 0x32 /* Common Control 32 */ 246 #define REG32_PCLK_DIV_2 0x80 /* PCLK freq divided by 2 */ 247 #define REG32_PCLK_DIV_4 0xC0 /* PCLK freq divided by 4 */ 248 #define ARCOM2 0x34 /* Zoom: Horizontal start point */ 249 #define REG45 0x45 /* Register 45 */ 250 #define FLL 0x46 /* Frame Length Adjustment LSBs */ 251 #define FLH 0x47 /* Frame Length Adjustment MSBs */ 252 #define COM19 0x48 /* Zoom: Vertical start point */ 253 #define ZOOMS 0x49 /* Zoom: Vertical start point */ 254 #define COM22 0x4B /* Flash light control */ 255 #define COM25 0x4E /* For Banding operations */ 256 #define COM25_50HZ_BANDING_AEC_MSBS_MASK 0xC0 /* 50Hz Bd. AEC 2 MSBs */ 257 #define COM25_60HZ_BANDING_AEC_MSBS_MASK 0x30 /* 60Hz Bd. AEC 2 MSBs */ 258 #define COM25_50HZ_BANDING_AEC_MSBS_SET(x) VAL_SET(x, 0x3, 8, 6) 259 #define COM25_60HZ_BANDING_AEC_MSBS_SET(x) VAL_SET(x, 0x3, 8, 4) 260 #define BD50 0x4F /* 50Hz Banding AEC 8 LSBs */ 261 #define BD50_50HZ_BANDING_AEC_LSBS_SET(x) VAL_SET(x, 0xFF, 0, 0) 262 #define BD60 0x50 /* 60Hz Banding AEC 8 LSBs */ 263 #define BD60_60HZ_BANDING_AEC_LSBS_SET(x) VAL_SET(x, 0xFF, 0, 0) 264 #define REG5A 0x5A /* 50/60Hz Banding Maximum AEC Step */ 265 #define BD50_MAX_AEC_STEP_MASK 0xF0 /* 50Hz Banding Max. AEC Step */ 266 #define BD60_MAX_AEC_STEP_MASK 0x0F /* 60Hz Banding Max. AEC Step */ 267 #define BD50_MAX_AEC_STEP_SET(x) VAL_SET((x - 1), 0x0F, 0, 4) 268 #define BD60_MAX_AEC_STEP_SET(x) VAL_SET((x - 1), 0x0F, 0, 0) 269 #define REG5D 0x5D /* AVGsel[7:0], 16-zone average weight option */ 270 #define REG5E 0x5E /* AVGsel[15:8], 16-zone average weight option */ 271 #define REG5F 0x5F /* AVGsel[23:16], 16-zone average weight option */ 272 #define REG60 0x60 /* AVGsel[31:24], 16-zone average weight option */ 273 #define HISTO_LOW 0x61 /* Histogram Algorithm Low Level */ 274 #define HISTO_HIGH 0x62 /* Histogram Algorithm High Level */ 275 276 /* 277 * ID 278 */ 279 #define MANUFACTURER_ID 0x7FA2 280 #define PID_OV2640 0x2642 281 #define VERSION(pid, ver) ((pid << 8) | (ver & 0xFF)) 282 283 /* 284 * Struct 285 */ 286 struct regval_list { 287 u8 reg_num; 288 u8 value; 289 }; 290 291 struct ov2640_win_size { 292 char *name; 293 u32 width; 294 u32 height; 295 const struct regval_list *regs; 296 }; 297 298 299 struct ov2640_priv { 300 struct v4l2_subdev subdev; 301 #if defined(CONFIG_MEDIA_CONTROLLER) 302 struct media_pad pad; 303 #endif 304 struct v4l2_ctrl_handler hdl; 305 u32 cfmt_code; 306 struct clk *clk; 307 const struct ov2640_win_size *win; 308 309 struct gpio_desc *resetb_gpio; 310 struct gpio_desc *pwdn_gpio; 311 312 struct mutex lock; /* lock to protect streaming and power_count */ 313 bool streaming; 314 int power_count; 315 }; 316 317 /* 318 * Registers settings 319 */ 320 321 #define ENDMARKER { 0xff, 0xff } 322 323 static const struct regval_list ov2640_init_regs[] = { 324 { BANK_SEL, BANK_SEL_DSP }, 325 { 0x2c, 0xff }, 326 { 0x2e, 0xdf }, 327 { BANK_SEL, BANK_SEL_SENS }, 328 { 0x3c, 0x32 }, 329 { CLKRC, CLKRC_DIV_SET(1) }, 330 { COM2, COM2_OCAP_Nx_SET(3) }, 331 { REG04, REG04_DEF | REG04_HREF_EN }, 332 { COM8, COM8_DEF | COM8_BNDF_EN | COM8_AGC_EN | COM8_AEC_EN }, 333 { COM9, COM9_AGC_GAIN_8x | 0x08}, 334 { 0x2c, 0x0c }, 335 { 0x33, 0x78 }, 336 { 0x3a, 0x33 }, 337 { 0x3b, 0xfb }, 338 { 0x3e, 0x00 }, 339 { 0x43, 0x11 }, 340 { 0x16, 0x10 }, 341 { 0x39, 0x02 }, 342 { 0x35, 0x88 }, 343 { 0x22, 0x0a }, 344 { 0x37, 0x40 }, 345 { 0x23, 0x00 }, 346 { ARCOM2, 0xa0 }, 347 { 0x06, 0x02 }, 348 { 0x06, 0x88 }, 349 { 0x07, 0xc0 }, 350 { 0x0d, 0xb7 }, 351 { 0x0e, 0x01 }, 352 { 0x4c, 0x00 }, 353 { 0x4a, 0x81 }, 354 { 0x21, 0x99 }, 355 { AEW, 0x40 }, 356 { AEB, 0x38 }, 357 { VV, VV_HIGH_TH_SET(0x08) | VV_LOW_TH_SET(0x02) }, 358 { 0x5c, 0x00 }, 359 { 0x63, 0x00 }, 360 { FLL, 0x22 }, 361 { COM3, 0x38 | COM3_BAND_AUTO }, 362 { REG5D, 0x55 }, 363 { REG5E, 0x7d }, 364 { REG5F, 0x7d }, 365 { REG60, 0x55 }, 366 { HISTO_LOW, 0x70 }, 367 { HISTO_HIGH, 0x80 }, 368 { 0x7c, 0x05 }, 369 { 0x20, 0x80 }, 370 { 0x28, 0x30 }, 371 { 0x6c, 0x00 }, 372 { 0x6d, 0x80 }, 373 { 0x6e, 0x00 }, 374 { 0x70, 0x02 }, 375 { 0x71, 0x94 }, 376 { 0x73, 0xc1 }, 377 { 0x3d, 0x34 }, 378 { COM7, COM7_RES_UXGA | COM7_ZOOM_EN }, 379 { REG5A, BD50_MAX_AEC_STEP_SET(6) 380 | BD60_MAX_AEC_STEP_SET(8) }, /* 0x57 */ 381 { COM25, COM25_50HZ_BANDING_AEC_MSBS_SET(0x0bb) 382 | COM25_60HZ_BANDING_AEC_MSBS_SET(0x09c) }, /* 0x00 */ 383 { BD50, BD50_50HZ_BANDING_AEC_LSBS_SET(0x0bb) }, /* 0xbb */ 384 { BD60, BD60_60HZ_BANDING_AEC_LSBS_SET(0x09c) }, /* 0x9c */ 385 { BANK_SEL, BANK_SEL_DSP }, 386 { 0xe5, 0x7f }, 387 { MC_BIST, MC_BIST_RESET | MC_BIST_BOOT_ROM_SEL }, 388 { 0x41, 0x24 }, 389 { RESET, RESET_JPEG | RESET_DVP }, 390 { 0x76, 0xff }, 391 { 0x33, 0xa0 }, 392 { 0x42, 0x20 }, 393 { 0x43, 0x18 }, 394 { 0x4c, 0x00 }, 395 { CTRL3, CTRL3_BPC_EN | CTRL3_WPC_EN | 0x10 }, 396 { 0x88, 0x3f }, 397 { 0xd7, 0x03 }, 398 { 0xd9, 0x10 }, 399 { R_DVP_SP, R_DVP_SP_AUTO_MODE | 0x2 }, 400 { 0xc8, 0x08 }, 401 { 0xc9, 0x80 }, 402 { BPADDR, 0x00 }, 403 { BPDATA, 0x00 }, 404 { BPADDR, 0x03 }, 405 { BPDATA, 0x48 }, 406 { BPDATA, 0x48 }, 407 { BPADDR, 0x08 }, 408 { BPDATA, 0x20 }, 409 { BPDATA, 0x10 }, 410 { BPDATA, 0x0e }, 411 { 0x90, 0x00 }, 412 { 0x91, 0x0e }, 413 { 0x91, 0x1a }, 414 { 0x91, 0x31 }, 415 { 0x91, 0x5a }, 416 { 0x91, 0x69 }, 417 { 0x91, 0x75 }, 418 { 0x91, 0x7e }, 419 { 0x91, 0x88 }, 420 { 0x91, 0x8f }, 421 { 0x91, 0x96 }, 422 { 0x91, 0xa3 }, 423 { 0x91, 0xaf }, 424 { 0x91, 0xc4 }, 425 { 0x91, 0xd7 }, 426 { 0x91, 0xe8 }, 427 { 0x91, 0x20 }, 428 { 0x92, 0x00 }, 429 { 0x93, 0x06 }, 430 { 0x93, 0xe3 }, 431 { 0x93, 0x03 }, 432 { 0x93, 0x03 }, 433 { 0x93, 0x00 }, 434 { 0x93, 0x02 }, 435 { 0x93, 0x00 }, 436 { 0x93, 0x00 }, 437 { 0x93, 0x00 }, 438 { 0x93, 0x00 }, 439 { 0x93, 0x00 }, 440 { 0x93, 0x00 }, 441 { 0x93, 0x00 }, 442 { 0x96, 0x00 }, 443 { 0x97, 0x08 }, 444 { 0x97, 0x19 }, 445 { 0x97, 0x02 }, 446 { 0x97, 0x0c }, 447 { 0x97, 0x24 }, 448 { 0x97, 0x30 }, 449 { 0x97, 0x28 }, 450 { 0x97, 0x26 }, 451 { 0x97, 0x02 }, 452 { 0x97, 0x98 }, 453 { 0x97, 0x80 }, 454 { 0x97, 0x00 }, 455 { 0x97, 0x00 }, 456 { 0xa4, 0x00 }, 457 { 0xa8, 0x00 }, 458 { 0xc5, 0x11 }, 459 { 0xc6, 0x51 }, 460 { 0xbf, 0x80 }, 461 { 0xc7, 0x10 }, /* simple AWB */ 462 { 0xb6, 0x66 }, 463 { 0xb8, 0xA5 }, 464 { 0xb7, 0x64 }, 465 { 0xb9, 0x7C }, 466 { 0xb3, 0xaf }, 467 { 0xb4, 0x97 }, 468 { 0xb5, 0xFF }, 469 { 0xb0, 0xC5 }, 470 { 0xb1, 0x94 }, 471 { 0xb2, 0x0f }, 472 { 0xc4, 0x5c }, 473 { 0xa6, 0x00 }, 474 { 0xa7, 0x20 }, 475 { 0xa7, 0xd8 }, 476 { 0xa7, 0x1b }, 477 { 0xa7, 0x31 }, 478 { 0xa7, 0x00 }, 479 { 0xa7, 0x18 }, 480 { 0xa7, 0x20 }, 481 { 0xa7, 0xd8 }, 482 { 0xa7, 0x19 }, 483 { 0xa7, 0x31 }, 484 { 0xa7, 0x00 }, 485 { 0xa7, 0x18 }, 486 { 0xa7, 0x20 }, 487 { 0xa7, 0xd8 }, 488 { 0xa7, 0x19 }, 489 { 0xa7, 0x31 }, 490 { 0xa7, 0x00 }, 491 { 0xa7, 0x18 }, 492 { 0x7f, 0x00 }, 493 { 0xe5, 0x1f }, 494 { 0xe1, 0x77 }, 495 { 0xdd, 0x7f }, 496 { CTRL0, CTRL0_YUV422 | CTRL0_YUV_EN | CTRL0_RGB_EN }, 497 ENDMARKER, 498 }; 499 500 /* 501 * Register settings for window size 502 * The preamble, setup the internal DSP to input an UXGA (1600x1200) image. 503 * Then the different zooming configurations will setup the output image size. 504 */ 505 static const struct regval_list ov2640_size_change_preamble_regs[] = { 506 { BANK_SEL, BANK_SEL_DSP }, 507 { RESET, RESET_DVP }, 508 { SIZEL, SIZEL_HSIZE8_11_SET(UXGA_WIDTH) | 509 SIZEL_HSIZE8_SET(UXGA_WIDTH) | 510 SIZEL_VSIZE8_SET(UXGA_HEIGHT) }, 511 { HSIZE8, HSIZE8_SET(UXGA_WIDTH) }, 512 { VSIZE8, VSIZE8_SET(UXGA_HEIGHT) }, 513 { CTRL2, CTRL2_DCW_EN | CTRL2_SDE_EN | 514 CTRL2_UV_AVG_EN | CTRL2_CMX_EN | CTRL2_UV_ADJ_EN }, 515 { HSIZE, HSIZE_SET(UXGA_WIDTH) }, 516 { VSIZE, VSIZE_SET(UXGA_HEIGHT) }, 517 { XOFFL, XOFFL_SET(0) }, 518 { YOFFL, YOFFL_SET(0) }, 519 { VHYX, VHYX_HSIZE_SET(UXGA_WIDTH) | VHYX_VSIZE_SET(UXGA_HEIGHT) | 520 VHYX_XOFF_SET(0) | VHYX_YOFF_SET(0)}, 521 { TEST, TEST_HSIZE_SET(UXGA_WIDTH) }, 522 ENDMARKER, 523 }; 524 525 #define PER_SIZE_REG_SEQ(x, y, v_div, h_div, pclk_div) \ 526 { CTRLI, CTRLI_LP_DP | CTRLI_V_DIV_SET(v_div) | \ 527 CTRLI_H_DIV_SET(h_div)}, \ 528 { ZMOW, ZMOW_OUTW_SET(x) }, \ 529 { ZMOH, ZMOH_OUTH_SET(y) }, \ 530 { ZMHH, ZMHH_OUTW_SET(x) | ZMHH_OUTH_SET(y) }, \ 531 { R_DVP_SP, pclk_div }, \ 532 { RESET, 0x00} 533 534 static const struct regval_list ov2640_qcif_regs[] = { 535 PER_SIZE_REG_SEQ(QCIF_WIDTH, QCIF_HEIGHT, 3, 3, 4), 536 ENDMARKER, 537 }; 538 539 static const struct regval_list ov2640_qvga_regs[] = { 540 PER_SIZE_REG_SEQ(QVGA_WIDTH, QVGA_HEIGHT, 2, 2, 4), 541 ENDMARKER, 542 }; 543 544 static const struct regval_list ov2640_cif_regs[] = { 545 PER_SIZE_REG_SEQ(CIF_WIDTH, CIF_HEIGHT, 2, 2, 8), 546 ENDMARKER, 547 }; 548 549 static const struct regval_list ov2640_vga_regs[] = { 550 PER_SIZE_REG_SEQ(VGA_WIDTH, VGA_HEIGHT, 0, 0, 2), 551 ENDMARKER, 552 }; 553 554 static const struct regval_list ov2640_svga_regs[] = { 555 PER_SIZE_REG_SEQ(SVGA_WIDTH, SVGA_HEIGHT, 1, 1, 2), 556 ENDMARKER, 557 }; 558 559 static const struct regval_list ov2640_xga_regs[] = { 560 PER_SIZE_REG_SEQ(XGA_WIDTH, XGA_HEIGHT, 0, 0, 2), 561 { CTRLI, 0x00}, 562 ENDMARKER, 563 }; 564 565 static const struct regval_list ov2640_sxga_regs[] = { 566 PER_SIZE_REG_SEQ(SXGA_WIDTH, SXGA_HEIGHT, 0, 0, 2), 567 { CTRLI, 0x00}, 568 { R_DVP_SP, 2 | R_DVP_SP_AUTO_MODE }, 569 ENDMARKER, 570 }; 571 572 static const struct regval_list ov2640_uxga_regs[] = { 573 PER_SIZE_REG_SEQ(UXGA_WIDTH, UXGA_HEIGHT, 0, 0, 0), 574 { CTRLI, 0x00}, 575 { R_DVP_SP, 0 | R_DVP_SP_AUTO_MODE }, 576 ENDMARKER, 577 }; 578 579 #define OV2640_SIZE(n, w, h, r) \ 580 {.name = n, .width = w , .height = h, .regs = r } 581 582 static const struct ov2640_win_size ov2640_supported_win_sizes[] = { 583 OV2640_SIZE("QCIF", QCIF_WIDTH, QCIF_HEIGHT, ov2640_qcif_regs), 584 OV2640_SIZE("QVGA", QVGA_WIDTH, QVGA_HEIGHT, ov2640_qvga_regs), 585 OV2640_SIZE("CIF", CIF_WIDTH, CIF_HEIGHT, ov2640_cif_regs), 586 OV2640_SIZE("VGA", VGA_WIDTH, VGA_HEIGHT, ov2640_vga_regs), 587 OV2640_SIZE("SVGA", SVGA_WIDTH, SVGA_HEIGHT, ov2640_svga_regs), 588 OV2640_SIZE("XGA", XGA_WIDTH, XGA_HEIGHT, ov2640_xga_regs), 589 OV2640_SIZE("SXGA", SXGA_WIDTH, SXGA_HEIGHT, ov2640_sxga_regs), 590 OV2640_SIZE("UXGA", UXGA_WIDTH, UXGA_HEIGHT, ov2640_uxga_regs), 591 }; 592 593 /* 594 * Register settings for pixel formats 595 */ 596 static const struct regval_list ov2640_format_change_preamble_regs[] = { 597 { BANK_SEL, BANK_SEL_DSP }, 598 { R_BYPASS, R_BYPASS_USE_DSP }, 599 ENDMARKER, 600 }; 601 602 static const struct regval_list ov2640_yuyv_regs[] = { 603 { IMAGE_MODE, IMAGE_MODE_YUV422 }, 604 { 0xd7, 0x03 }, 605 { 0x33, 0xa0 }, 606 { 0xe5, 0x1f }, 607 { 0xe1, 0x67 }, 608 { RESET, 0x00 }, 609 { R_BYPASS, R_BYPASS_USE_DSP }, 610 ENDMARKER, 611 }; 612 613 static const struct regval_list ov2640_uyvy_regs[] = { 614 { IMAGE_MODE, IMAGE_MODE_LBYTE_FIRST | IMAGE_MODE_YUV422 }, 615 { 0xd7, 0x01 }, 616 { 0x33, 0xa0 }, 617 { 0xe1, 0x67 }, 618 { RESET, 0x00 }, 619 { R_BYPASS, R_BYPASS_USE_DSP }, 620 ENDMARKER, 621 }; 622 623 static const struct regval_list ov2640_rgb565_be_regs[] = { 624 { IMAGE_MODE, IMAGE_MODE_RGB565 }, 625 { 0xd7, 0x03 }, 626 { RESET, 0x00 }, 627 { R_BYPASS, R_BYPASS_USE_DSP }, 628 ENDMARKER, 629 }; 630 631 static const struct regval_list ov2640_rgb565_le_regs[] = { 632 { IMAGE_MODE, IMAGE_MODE_LBYTE_FIRST | IMAGE_MODE_RGB565 }, 633 { 0xd7, 0x03 }, 634 { RESET, 0x00 }, 635 { R_BYPASS, R_BYPASS_USE_DSP }, 636 ENDMARKER, 637 }; 638 639 static u32 ov2640_codes[] = { 640 MEDIA_BUS_FMT_YUYV8_2X8, 641 MEDIA_BUS_FMT_UYVY8_2X8, 642 MEDIA_BUS_FMT_YVYU8_2X8, 643 MEDIA_BUS_FMT_VYUY8_2X8, 644 MEDIA_BUS_FMT_RGB565_2X8_BE, 645 MEDIA_BUS_FMT_RGB565_2X8_LE, 646 }; 647 648 /* 649 * General functions 650 */ 651 static struct ov2640_priv *to_ov2640(const struct i2c_client *client) 652 { 653 return container_of(i2c_get_clientdata(client), struct ov2640_priv, 654 subdev); 655 } 656 657 static int ov2640_write_array(struct i2c_client *client, 658 const struct regval_list *vals) 659 { 660 int ret; 661 662 while ((vals->reg_num != 0xff) || (vals->value != 0xff)) { 663 ret = i2c_smbus_write_byte_data(client, 664 vals->reg_num, vals->value); 665 dev_vdbg(&client->dev, "array: 0x%02x, 0x%02x", 666 vals->reg_num, vals->value); 667 668 if (ret < 0) 669 return ret; 670 vals++; 671 } 672 return 0; 673 } 674 675 static int ov2640_mask_set(struct i2c_client *client, 676 u8 reg, u8 mask, u8 set) 677 { 678 s32 val = i2c_smbus_read_byte_data(client, reg); 679 if (val < 0) 680 return val; 681 682 val &= ~mask; 683 val |= set & mask; 684 685 dev_vdbg(&client->dev, "masks: 0x%02x, 0x%02x", reg, val); 686 687 return i2c_smbus_write_byte_data(client, reg, val); 688 } 689 690 static int ov2640_reset(struct i2c_client *client) 691 { 692 int ret; 693 static const struct regval_list reset_seq[] = { 694 {BANK_SEL, BANK_SEL_SENS}, 695 {COM7, COM7_SRST}, 696 ENDMARKER, 697 }; 698 699 ret = ov2640_write_array(client, reset_seq); 700 if (ret) 701 goto err; 702 703 msleep(5); 704 err: 705 dev_dbg(&client->dev, "%s: (ret %d)", __func__, ret); 706 return ret; 707 } 708 709 static const char * const ov2640_test_pattern_menu[] = { 710 "Disabled", 711 "Eight Vertical Colour Bars", 712 }; 713 714 /* 715 * functions 716 */ 717 static int ov2640_s_ctrl(struct v4l2_ctrl *ctrl) 718 { 719 struct v4l2_subdev *sd = 720 &container_of(ctrl->handler, struct ov2640_priv, hdl)->subdev; 721 struct i2c_client *client = v4l2_get_subdevdata(sd); 722 struct ov2640_priv *priv = to_ov2640(client); 723 u8 val; 724 int ret; 725 726 /* v4l2_ctrl_lock() locks our own mutex */ 727 728 /* 729 * If the device is not powered up by the host driver, do not apply any 730 * controls to H/W at this time. Instead the controls will be restored 731 * when the streaming is started. 732 */ 733 if (!priv->power_count) 734 return 0; 735 736 ret = i2c_smbus_write_byte_data(client, BANK_SEL, BANK_SEL_SENS); 737 if (ret < 0) 738 return ret; 739 740 switch (ctrl->id) { 741 case V4L2_CID_VFLIP: 742 val = ctrl->val ? REG04_VFLIP_IMG | REG04_VREF_EN : 0x00; 743 return ov2640_mask_set(client, REG04, 744 REG04_VFLIP_IMG | REG04_VREF_EN, val); 745 /* NOTE: REG04_VREF_EN: 1 line shift / even/odd line swap */ 746 case V4L2_CID_HFLIP: 747 val = ctrl->val ? REG04_HFLIP_IMG : 0x00; 748 return ov2640_mask_set(client, REG04, REG04_HFLIP_IMG, val); 749 case V4L2_CID_TEST_PATTERN: 750 val = ctrl->val ? COM7_COLOR_BAR_TEST : 0x00; 751 return ov2640_mask_set(client, COM7, COM7_COLOR_BAR_TEST, val); 752 } 753 754 return -EINVAL; 755 } 756 757 #ifdef CONFIG_VIDEO_ADV_DEBUG 758 static int ov2640_g_register(struct v4l2_subdev *sd, 759 struct v4l2_dbg_register *reg) 760 { 761 struct i2c_client *client = v4l2_get_subdevdata(sd); 762 int ret; 763 764 reg->size = 1; 765 if (reg->reg > 0xff) 766 return -EINVAL; 767 768 ret = i2c_smbus_read_byte_data(client, reg->reg); 769 if (ret < 0) 770 return ret; 771 772 reg->val = ret; 773 774 return 0; 775 } 776 777 static int ov2640_s_register(struct v4l2_subdev *sd, 778 const struct v4l2_dbg_register *reg) 779 { 780 struct i2c_client *client = v4l2_get_subdevdata(sd); 781 782 if (reg->reg > 0xff || 783 reg->val > 0xff) 784 return -EINVAL; 785 786 return i2c_smbus_write_byte_data(client, reg->reg, reg->val); 787 } 788 #endif 789 790 static void ov2640_set_power(struct ov2640_priv *priv, int on) 791 { 792 #ifdef CONFIG_GPIOLIB 793 if (priv->pwdn_gpio) 794 gpiod_direction_output(priv->pwdn_gpio, !on); 795 if (on && priv->resetb_gpio) { 796 /* Active the resetb pin to perform a reset pulse */ 797 gpiod_direction_output(priv->resetb_gpio, 1); 798 usleep_range(3000, 5000); 799 gpiod_set_value(priv->resetb_gpio, 0); 800 } 801 #endif 802 } 803 804 static int ov2640_s_power(struct v4l2_subdev *sd, int on) 805 { 806 struct i2c_client *client = v4l2_get_subdevdata(sd); 807 struct ov2640_priv *priv = to_ov2640(client); 808 809 mutex_lock(&priv->lock); 810 811 /* 812 * If the power count is modified from 0 to != 0 or from != 0 to 0, 813 * update the power state. 814 */ 815 if (priv->power_count == !on) 816 ov2640_set_power(priv, on); 817 priv->power_count += on ? 1 : -1; 818 WARN_ON(priv->power_count < 0); 819 mutex_unlock(&priv->lock); 820 821 return 0; 822 } 823 824 /* Select the nearest higher resolution for capture */ 825 static const struct ov2640_win_size *ov2640_select_win(u32 width, u32 height) 826 { 827 int i, default_size = ARRAY_SIZE(ov2640_supported_win_sizes) - 1; 828 829 for (i = 0; i < ARRAY_SIZE(ov2640_supported_win_sizes); i++) { 830 if (ov2640_supported_win_sizes[i].width >= width && 831 ov2640_supported_win_sizes[i].height >= height) 832 return &ov2640_supported_win_sizes[i]; 833 } 834 835 return &ov2640_supported_win_sizes[default_size]; 836 } 837 838 static int ov2640_set_params(struct i2c_client *client, 839 const struct ov2640_win_size *win, u32 code) 840 { 841 const struct regval_list *selected_cfmt_regs; 842 u8 val; 843 int ret; 844 845 switch (code) { 846 case MEDIA_BUS_FMT_RGB565_2X8_BE: 847 dev_dbg(&client->dev, "%s: Selected cfmt RGB565 BE", __func__); 848 selected_cfmt_regs = ov2640_rgb565_be_regs; 849 break; 850 case MEDIA_BUS_FMT_RGB565_2X8_LE: 851 dev_dbg(&client->dev, "%s: Selected cfmt RGB565 LE", __func__); 852 selected_cfmt_regs = ov2640_rgb565_le_regs; 853 break; 854 case MEDIA_BUS_FMT_YUYV8_2X8: 855 dev_dbg(&client->dev, "%s: Selected cfmt YUYV (YUV422)", __func__); 856 selected_cfmt_regs = ov2640_yuyv_regs; 857 break; 858 case MEDIA_BUS_FMT_UYVY8_2X8: 859 default: 860 dev_dbg(&client->dev, "%s: Selected cfmt UYVY", __func__); 861 selected_cfmt_regs = ov2640_uyvy_regs; 862 break; 863 case MEDIA_BUS_FMT_YVYU8_2X8: 864 dev_dbg(&client->dev, "%s: Selected cfmt YVYU", __func__); 865 selected_cfmt_regs = ov2640_yuyv_regs; 866 break; 867 case MEDIA_BUS_FMT_VYUY8_2X8: 868 dev_dbg(&client->dev, "%s: Selected cfmt VYUY", __func__); 869 selected_cfmt_regs = ov2640_uyvy_regs; 870 break; 871 } 872 873 /* reset hardware */ 874 ov2640_reset(client); 875 876 /* initialize the sensor with default data */ 877 dev_dbg(&client->dev, "%s: Init default", __func__); 878 ret = ov2640_write_array(client, ov2640_init_regs); 879 if (ret < 0) 880 goto err; 881 882 /* select preamble */ 883 dev_dbg(&client->dev, "%s: Set size to %s", __func__, win->name); 884 ret = ov2640_write_array(client, ov2640_size_change_preamble_regs); 885 if (ret < 0) 886 goto err; 887 888 /* set size win */ 889 ret = ov2640_write_array(client, win->regs); 890 if (ret < 0) 891 goto err; 892 893 /* cfmt preamble */ 894 dev_dbg(&client->dev, "%s: Set cfmt", __func__); 895 ret = ov2640_write_array(client, ov2640_format_change_preamble_regs); 896 if (ret < 0) 897 goto err; 898 899 /* set cfmt */ 900 ret = ov2640_write_array(client, selected_cfmt_regs); 901 if (ret < 0) 902 goto err; 903 val = (code == MEDIA_BUS_FMT_YVYU8_2X8) 904 || (code == MEDIA_BUS_FMT_VYUY8_2X8) ? CTRL0_VFIRST : 0x00; 905 ret = ov2640_mask_set(client, CTRL0, CTRL0_VFIRST, val); 906 if (ret < 0) 907 goto err; 908 909 return 0; 910 911 err: 912 dev_err(&client->dev, "%s: Error %d", __func__, ret); 913 ov2640_reset(client); 914 915 return ret; 916 } 917 918 static int ov2640_get_fmt(struct v4l2_subdev *sd, 919 struct v4l2_subdev_pad_config *cfg, 920 struct v4l2_subdev_format *format) 921 { 922 struct v4l2_mbus_framefmt *mf = &format->format; 923 struct i2c_client *client = v4l2_get_subdevdata(sd); 924 struct ov2640_priv *priv = to_ov2640(client); 925 926 if (format->pad) 927 return -EINVAL; 928 929 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 930 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 931 mf = v4l2_subdev_get_try_format(sd, cfg, 0); 932 format->format = *mf; 933 return 0; 934 #else 935 return -ENOTTY; 936 #endif 937 } 938 939 mf->width = priv->win->width; 940 mf->height = priv->win->height; 941 mf->code = priv->cfmt_code; 942 mf->colorspace = V4L2_COLORSPACE_SRGB; 943 mf->field = V4L2_FIELD_NONE; 944 mf->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; 945 mf->quantization = V4L2_QUANTIZATION_DEFAULT; 946 mf->xfer_func = V4L2_XFER_FUNC_DEFAULT; 947 948 return 0; 949 } 950 951 static int ov2640_set_fmt(struct v4l2_subdev *sd, 952 struct v4l2_subdev_pad_config *cfg, 953 struct v4l2_subdev_format *format) 954 { 955 struct v4l2_mbus_framefmt *mf = &format->format; 956 struct i2c_client *client = v4l2_get_subdevdata(sd); 957 struct ov2640_priv *priv = to_ov2640(client); 958 const struct ov2640_win_size *win; 959 int ret = 0; 960 961 if (format->pad) 962 return -EINVAL; 963 964 mutex_lock(&priv->lock); 965 966 /* select suitable win */ 967 win = ov2640_select_win(mf->width, mf->height); 968 mf->width = win->width; 969 mf->height = win->height; 970 971 mf->field = V4L2_FIELD_NONE; 972 mf->colorspace = V4L2_COLORSPACE_SRGB; 973 mf->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; 974 mf->quantization = V4L2_QUANTIZATION_DEFAULT; 975 mf->xfer_func = V4L2_XFER_FUNC_DEFAULT; 976 977 switch (mf->code) { 978 case MEDIA_BUS_FMT_RGB565_2X8_BE: 979 case MEDIA_BUS_FMT_RGB565_2X8_LE: 980 case MEDIA_BUS_FMT_YUYV8_2X8: 981 case MEDIA_BUS_FMT_UYVY8_2X8: 982 case MEDIA_BUS_FMT_YVYU8_2X8: 983 case MEDIA_BUS_FMT_VYUY8_2X8: 984 break; 985 default: 986 mf->code = MEDIA_BUS_FMT_UYVY8_2X8; 987 break; 988 } 989 990 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) { 991 struct ov2640_priv *priv = to_ov2640(client); 992 993 if (priv->streaming) { 994 ret = -EBUSY; 995 goto out; 996 } 997 /* select win */ 998 priv->win = win; 999 /* select format */ 1000 priv->cfmt_code = mf->code; 1001 } else { 1002 cfg->try_fmt = *mf; 1003 } 1004 out: 1005 mutex_unlock(&priv->lock); 1006 1007 return ret; 1008 } 1009 1010 static int ov2640_init_cfg(struct v4l2_subdev *sd, 1011 struct v4l2_subdev_pad_config *cfg) 1012 { 1013 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1014 struct v4l2_mbus_framefmt *try_fmt = 1015 v4l2_subdev_get_try_format(sd, cfg, 0); 1016 const struct ov2640_win_size *win = 1017 ov2640_select_win(SVGA_WIDTH, SVGA_HEIGHT); 1018 1019 try_fmt->width = win->width; 1020 try_fmt->height = win->height; 1021 try_fmt->code = MEDIA_BUS_FMT_UYVY8_2X8; 1022 try_fmt->colorspace = V4L2_COLORSPACE_SRGB; 1023 try_fmt->field = V4L2_FIELD_NONE; 1024 try_fmt->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; 1025 try_fmt->quantization = V4L2_QUANTIZATION_DEFAULT; 1026 try_fmt->xfer_func = V4L2_XFER_FUNC_DEFAULT; 1027 #endif 1028 return 0; 1029 } 1030 1031 static int ov2640_enum_mbus_code(struct v4l2_subdev *sd, 1032 struct v4l2_subdev_pad_config *cfg, 1033 struct v4l2_subdev_mbus_code_enum *code) 1034 { 1035 if (code->pad || code->index >= ARRAY_SIZE(ov2640_codes)) 1036 return -EINVAL; 1037 1038 code->code = ov2640_codes[code->index]; 1039 return 0; 1040 } 1041 1042 static int ov2640_get_selection(struct v4l2_subdev *sd, 1043 struct v4l2_subdev_pad_config *cfg, 1044 struct v4l2_subdev_selection *sel) 1045 { 1046 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE) 1047 return -EINVAL; 1048 1049 switch (sel->target) { 1050 case V4L2_SEL_TGT_CROP_BOUNDS: 1051 case V4L2_SEL_TGT_CROP: 1052 sel->r.left = 0; 1053 sel->r.top = 0; 1054 sel->r.width = UXGA_WIDTH; 1055 sel->r.height = UXGA_HEIGHT; 1056 return 0; 1057 default: 1058 return -EINVAL; 1059 } 1060 } 1061 1062 static int ov2640_s_stream(struct v4l2_subdev *sd, int on) 1063 { 1064 struct i2c_client *client = v4l2_get_subdevdata(sd); 1065 struct ov2640_priv *priv = to_ov2640(client); 1066 int ret = 0; 1067 1068 mutex_lock(&priv->lock); 1069 if (priv->streaming == !on) { 1070 if (on) { 1071 ret = ov2640_set_params(client, priv->win, 1072 priv->cfmt_code); 1073 if (!ret) 1074 ret = __v4l2_ctrl_handler_setup(&priv->hdl); 1075 } 1076 } 1077 if (!ret) 1078 priv->streaming = on; 1079 mutex_unlock(&priv->lock); 1080 1081 return ret; 1082 } 1083 1084 static int ov2640_video_probe(struct i2c_client *client) 1085 { 1086 struct ov2640_priv *priv = to_ov2640(client); 1087 u8 pid, ver, midh, midl; 1088 const char *devname; 1089 int ret; 1090 1091 ret = ov2640_s_power(&priv->subdev, 1); 1092 if (ret < 0) 1093 return ret; 1094 1095 /* 1096 * check and show product ID and manufacturer ID 1097 */ 1098 i2c_smbus_write_byte_data(client, BANK_SEL, BANK_SEL_SENS); 1099 pid = i2c_smbus_read_byte_data(client, PID); 1100 ver = i2c_smbus_read_byte_data(client, VER); 1101 midh = i2c_smbus_read_byte_data(client, MIDH); 1102 midl = i2c_smbus_read_byte_data(client, MIDL); 1103 1104 switch (VERSION(pid, ver)) { 1105 case PID_OV2640: 1106 devname = "ov2640"; 1107 break; 1108 default: 1109 dev_err(&client->dev, 1110 "Product ID error %x:%x\n", pid, ver); 1111 ret = -ENODEV; 1112 goto done; 1113 } 1114 1115 dev_info(&client->dev, 1116 "%s Product ID %0x:%0x Manufacturer ID %x:%x\n", 1117 devname, pid, ver, midh, midl); 1118 1119 done: 1120 ov2640_s_power(&priv->subdev, 0); 1121 return ret; 1122 } 1123 1124 static const struct v4l2_ctrl_ops ov2640_ctrl_ops = { 1125 .s_ctrl = ov2640_s_ctrl, 1126 }; 1127 1128 static const struct v4l2_subdev_core_ops ov2640_subdev_core_ops = { 1129 .log_status = v4l2_ctrl_subdev_log_status, 1130 .subscribe_event = v4l2_ctrl_subdev_subscribe_event, 1131 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 1132 #ifdef CONFIG_VIDEO_ADV_DEBUG 1133 .g_register = ov2640_g_register, 1134 .s_register = ov2640_s_register, 1135 #endif 1136 .s_power = ov2640_s_power, 1137 }; 1138 1139 static const struct v4l2_subdev_pad_ops ov2640_subdev_pad_ops = { 1140 .init_cfg = ov2640_init_cfg, 1141 .enum_mbus_code = ov2640_enum_mbus_code, 1142 .get_selection = ov2640_get_selection, 1143 .get_fmt = ov2640_get_fmt, 1144 .set_fmt = ov2640_set_fmt, 1145 }; 1146 1147 static const struct v4l2_subdev_video_ops ov2640_subdev_video_ops = { 1148 .s_stream = ov2640_s_stream, 1149 }; 1150 1151 static const struct v4l2_subdev_ops ov2640_subdev_ops = { 1152 .core = &ov2640_subdev_core_ops, 1153 .pad = &ov2640_subdev_pad_ops, 1154 .video = &ov2640_subdev_video_ops, 1155 }; 1156 1157 static int ov2640_probe_dt(struct i2c_client *client, 1158 struct ov2640_priv *priv) 1159 { 1160 int ret; 1161 1162 /* Request the reset GPIO deasserted */ 1163 priv->resetb_gpio = devm_gpiod_get_optional(&client->dev, "resetb", 1164 GPIOD_OUT_LOW); 1165 1166 if (!priv->resetb_gpio) 1167 dev_dbg(&client->dev, "resetb gpio is not assigned!\n"); 1168 1169 ret = PTR_ERR_OR_ZERO(priv->resetb_gpio); 1170 if (ret && ret != -ENOSYS) { 1171 dev_dbg(&client->dev, 1172 "Error %d while getting resetb gpio\n", ret); 1173 return ret; 1174 } 1175 1176 /* Request the power down GPIO asserted */ 1177 priv->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "pwdn", 1178 GPIOD_OUT_HIGH); 1179 1180 if (!priv->pwdn_gpio) 1181 dev_dbg(&client->dev, "pwdn gpio is not assigned!\n"); 1182 1183 ret = PTR_ERR_OR_ZERO(priv->pwdn_gpio); 1184 if (ret && ret != -ENOSYS) { 1185 dev_dbg(&client->dev, 1186 "Error %d while getting pwdn gpio\n", ret); 1187 return ret; 1188 } 1189 1190 return 0; 1191 } 1192 1193 /* 1194 * i2c_driver functions 1195 */ 1196 static int ov2640_probe(struct i2c_client *client, 1197 const struct i2c_device_id *did) 1198 { 1199 struct ov2640_priv *priv; 1200 struct i2c_adapter *adapter = client->adapter; 1201 int ret; 1202 1203 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) { 1204 dev_err(&adapter->dev, 1205 "OV2640: I2C-Adapter doesn't support SMBUS\n"); 1206 return -EIO; 1207 } 1208 1209 priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL); 1210 if (!priv) 1211 return -ENOMEM; 1212 1213 if (client->dev.of_node) { 1214 priv->clk = devm_clk_get(&client->dev, "xvclk"); 1215 if (IS_ERR(priv->clk)) 1216 return PTR_ERR(priv->clk); 1217 ret = clk_prepare_enable(priv->clk); 1218 if (ret) 1219 return ret; 1220 } 1221 1222 ret = ov2640_probe_dt(client, priv); 1223 if (ret) 1224 goto err_clk; 1225 1226 priv->win = ov2640_select_win(SVGA_WIDTH, SVGA_HEIGHT); 1227 priv->cfmt_code = MEDIA_BUS_FMT_UYVY8_2X8; 1228 1229 v4l2_i2c_subdev_init(&priv->subdev, client, &ov2640_subdev_ops); 1230 priv->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | 1231 V4L2_SUBDEV_FL_HAS_EVENTS; 1232 mutex_init(&priv->lock); 1233 v4l2_ctrl_handler_init(&priv->hdl, 3); 1234 priv->hdl.lock = &priv->lock; 1235 v4l2_ctrl_new_std(&priv->hdl, &ov2640_ctrl_ops, 1236 V4L2_CID_VFLIP, 0, 1, 1, 0); 1237 v4l2_ctrl_new_std(&priv->hdl, &ov2640_ctrl_ops, 1238 V4L2_CID_HFLIP, 0, 1, 1, 0); 1239 v4l2_ctrl_new_std_menu_items(&priv->hdl, &ov2640_ctrl_ops, 1240 V4L2_CID_TEST_PATTERN, 1241 ARRAY_SIZE(ov2640_test_pattern_menu) - 1, 0, 0, 1242 ov2640_test_pattern_menu); 1243 priv->subdev.ctrl_handler = &priv->hdl; 1244 if (priv->hdl.error) { 1245 ret = priv->hdl.error; 1246 goto err_hdl; 1247 } 1248 #if defined(CONFIG_MEDIA_CONTROLLER) 1249 priv->pad.flags = MEDIA_PAD_FL_SOURCE; 1250 priv->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1251 ret = media_entity_pads_init(&priv->subdev.entity, 1, &priv->pad); 1252 if (ret < 0) 1253 goto err_hdl; 1254 #endif 1255 1256 ret = ov2640_video_probe(client); 1257 if (ret < 0) 1258 goto err_videoprobe; 1259 1260 ret = v4l2_async_register_subdev(&priv->subdev); 1261 if (ret < 0) 1262 goto err_videoprobe; 1263 1264 dev_info(&adapter->dev, "OV2640 Probed\n"); 1265 1266 return 0; 1267 1268 err_videoprobe: 1269 media_entity_cleanup(&priv->subdev.entity); 1270 err_hdl: 1271 v4l2_ctrl_handler_free(&priv->hdl); 1272 mutex_destroy(&priv->lock); 1273 err_clk: 1274 clk_disable_unprepare(priv->clk); 1275 return ret; 1276 } 1277 1278 static int ov2640_remove(struct i2c_client *client) 1279 { 1280 struct ov2640_priv *priv = to_ov2640(client); 1281 1282 v4l2_async_unregister_subdev(&priv->subdev); 1283 v4l2_ctrl_handler_free(&priv->hdl); 1284 mutex_destroy(&priv->lock); 1285 media_entity_cleanup(&priv->subdev.entity); 1286 v4l2_device_unregister_subdev(&priv->subdev); 1287 clk_disable_unprepare(priv->clk); 1288 return 0; 1289 } 1290 1291 static const struct i2c_device_id ov2640_id[] = { 1292 { "ov2640", 0 }, 1293 { } 1294 }; 1295 MODULE_DEVICE_TABLE(i2c, ov2640_id); 1296 1297 static const struct of_device_id ov2640_of_match[] = { 1298 {.compatible = "ovti,ov2640", }, 1299 {}, 1300 }; 1301 MODULE_DEVICE_TABLE(of, ov2640_of_match); 1302 1303 static struct i2c_driver ov2640_i2c_driver = { 1304 .driver = { 1305 .name = "ov2640", 1306 .of_match_table = of_match_ptr(ov2640_of_match), 1307 }, 1308 .probe = ov2640_probe, 1309 .remove = ov2640_remove, 1310 .id_table = ov2640_id, 1311 }; 1312 1313 module_i2c_driver(ov2640_i2c_driver); 1314 1315 MODULE_DESCRIPTION("Driver for Omni Vision 2640 sensor"); 1316 MODULE_AUTHOR("Alberto Panizzo"); 1317 MODULE_LICENSE("GPL v2"); 1318