xref: /linux/drivers/media/i2c/ov13b10.c (revision c5dbf04160005e07e8ca7232a7faa77ab1547ae0)
1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2021 Intel Corporation.
3 
4 #include <linux/acpi.h>
5 #include <linux/clk.h>
6 #include <linux/delay.h>
7 #include <linux/gpio/consumer.h>
8 #include <linux/i2c.h>
9 #include <linux/module.h>
10 #include <linux/pm_runtime.h>
11 #include <media/v4l2-ctrls.h>
12 #include <media/v4l2-device.h>
13 #include <media/v4l2-fwnode.h>
14 
15 #define OV13B10_REG_VALUE_08BIT		1
16 #define OV13B10_REG_VALUE_16BIT		2
17 #define OV13B10_REG_VALUE_24BIT		3
18 
19 #define OV13B10_REG_MODE_SELECT		0x0100
20 #define OV13B10_MODE_STANDBY		0x00
21 #define OV13B10_MODE_STREAMING		0x01
22 
23 #define OV13B10_REG_SOFTWARE_RST	0x0103
24 #define OV13B10_SOFTWARE_RST		0x01
25 
26 /* Chip ID */
27 #define OV13B10_REG_CHIP_ID		0x300a
28 #define OV13B10_CHIP_ID			0x560d42
29 
30 /* V_TIMING internal */
31 #define OV13B10_REG_VTS			0x380e
32 #define OV13B10_VTS_30FPS		0x0c7c
33 #define OV13B10_VTS_60FPS		0x063e
34 #define OV13B10_VTS_120FPS		0x0320
35 #define OV13B10_VTS_MAX			0x7fff
36 
37 /* HBLANK control - read only */
38 #define OV13B10_PPL_560MHZ		4704
39 
40 /* Exposure control */
41 #define OV13B10_REG_EXPOSURE		0x3500
42 #define OV13B10_EXPOSURE_MIN		4
43 #define OV13B10_EXPOSURE_STEP		1
44 #define OV13B10_EXPOSURE_DEFAULT	0x40
45 
46 /* Analog gain control */
47 #define OV13B10_REG_ANALOG_GAIN		0x3508
48 #define OV13B10_ANA_GAIN_MIN		0x80
49 #define OV13B10_ANA_GAIN_MAX		0x07c0
50 #define OV13B10_ANA_GAIN_STEP		1
51 #define OV13B10_ANA_GAIN_DEFAULT	0x80
52 
53 /* Digital gain control */
54 #define OV13B10_REG_DGTL_GAIN_H		0x350a
55 #define OV13B10_REG_DGTL_GAIN_M		0x350b
56 #define OV13B10_REG_DGTL_GAIN_L		0x350c
57 
58 #define OV13B10_DGTL_GAIN_MIN		1024	     /* Min = 1 X */
59 #define OV13B10_DGTL_GAIN_MAX		(4096 - 1)   /* Max = 4 X */
60 #define OV13B10_DGTL_GAIN_DEFAULT	2560	     /* Default gain = 2.5 X */
61 #define OV13B10_DGTL_GAIN_STEP		1	     /* Each step = 1/1024 */
62 
63 #define OV13B10_DGTL_GAIN_L_SHIFT	6
64 #define OV13B10_DGTL_GAIN_L_MASK	0x3
65 #define OV13B10_DGTL_GAIN_M_SHIFT	2
66 #define OV13B10_DGTL_GAIN_M_MASK	0xff
67 #define OV13B10_DGTL_GAIN_H_SHIFT	10
68 #define OV13B10_DGTL_GAIN_H_MASK	0x3
69 
70 /* Test Pattern Control */
71 #define OV13B10_REG_TEST_PATTERN	0x5080
72 #define OV13B10_TEST_PATTERN_ENABLE	BIT(7)
73 #define OV13B10_TEST_PATTERN_MASK	0xf3
74 #define OV13B10_TEST_PATTERN_BAR_SHIFT	2
75 
76 /* Flip Control */
77 #define OV13B10_REG_FORMAT1		0x3820
78 #define OV13B10_REG_FORMAT2		0x3821
79 
80 /* Horizontal Window Offset */
81 #define OV13B10_REG_H_WIN_OFFSET	0x3811
82 
83 /* Vertical Window Offset */
84 #define OV13B10_REG_V_WIN_OFFSET	0x3813
85 
86 struct ov13b10_reg {
87 	u16 address;
88 	u8 val;
89 };
90 
91 struct ov13b10_reg_list {
92 	u32 num_of_regs;
93 	const struct ov13b10_reg *regs;
94 };
95 
96 /* Link frequency config */
97 struct ov13b10_link_freq_config {
98 	u32 pixels_per_line;
99 
100 	/* registers for this link frequency */
101 	struct ov13b10_reg_list reg_list;
102 };
103 
104 /* Mode : resolution and related config&values */
105 struct ov13b10_mode {
106 	/* Frame width */
107 	u32 width;
108 	/* Frame height */
109 	u32 height;
110 
111 	/* V-timing */
112 	u32 vts_def;
113 	u32 vts_min;
114 
115 	/* Index of Link frequency config to be used */
116 	u32 link_freq_index;
117 	/* Default register values */
118 	struct ov13b10_reg_list reg_list;
119 };
120 
121 /* 4208x3120 needs 1120Mbps/lane, 4 lanes */
122 static const struct ov13b10_reg mipi_data_rate_1120mbps[] = {
123 	{0x0103, 0x01},
124 	{0x0303, 0x04},
125 	{0x0305, 0xaf},
126 	{0x0321, 0x00},
127 	{0x0323, 0x04},
128 	{0x0324, 0x01},
129 	{0x0325, 0xa4},
130 	{0x0326, 0x81},
131 	{0x0327, 0x04},
132 	{0x3012, 0x07},
133 	{0x3013, 0x32},
134 	{0x3107, 0x23},
135 	{0x3501, 0x0c},
136 	{0x3502, 0x10},
137 	{0x3504, 0x08},
138 	{0x3508, 0x07},
139 	{0x3509, 0xc0},
140 	{0x3600, 0x16},
141 	{0x3601, 0x54},
142 	{0x3612, 0x4e},
143 	{0x3620, 0x00},
144 	{0x3621, 0x68},
145 	{0x3622, 0x66},
146 	{0x3623, 0x03},
147 	{0x3662, 0x92},
148 	{0x3666, 0xbb},
149 	{0x3667, 0x44},
150 	{0x366e, 0xff},
151 	{0x366f, 0xf3},
152 	{0x3675, 0x44},
153 	{0x3676, 0x00},
154 	{0x367f, 0xe9},
155 	{0x3681, 0x32},
156 	{0x3682, 0x1f},
157 	{0x3683, 0x0b},
158 	{0x3684, 0x0b},
159 	{0x3704, 0x0f},
160 	{0x3706, 0x40},
161 	{0x3708, 0x3b},
162 	{0x3709, 0x72},
163 	{0x370b, 0xa2},
164 	{0x3714, 0x24},
165 	{0x371a, 0x3e},
166 	{0x3725, 0x42},
167 	{0x3739, 0x12},
168 	{0x3767, 0x00},
169 	{0x377a, 0x0d},
170 	{0x3789, 0x18},
171 	{0x3790, 0x40},
172 	{0x3791, 0xa2},
173 	{0x37c2, 0x04},
174 	{0x37c3, 0xf1},
175 	{0x37d9, 0x0c},
176 	{0x37da, 0x02},
177 	{0x37dc, 0x02},
178 	{0x37e1, 0x04},
179 	{0x37e2, 0x0a},
180 	{0x3800, 0x00},
181 	{0x3801, 0x00},
182 	{0x3802, 0x00},
183 	{0x3803, 0x08},
184 	{0x3804, 0x10},
185 	{0x3805, 0x8f},
186 	{0x3806, 0x0c},
187 	{0x3807, 0x47},
188 	{0x3808, 0x10},
189 	{0x3809, 0x70},
190 	{0x380a, 0x0c},
191 	{0x380b, 0x30},
192 	{0x380c, 0x04},
193 	{0x380d, 0x98},
194 	{0x380e, 0x0c},
195 	{0x380f, 0x7c},
196 	{0x3811, 0x0f},
197 	{0x3813, 0x09},
198 	{0x3814, 0x01},
199 	{0x3815, 0x01},
200 	{0x3816, 0x01},
201 	{0x3817, 0x01},
202 	{0x381f, 0x08},
203 	{0x3820, 0x88},
204 	{0x3821, 0x00},
205 	{0x3822, 0x14},
206 	{0x382e, 0xe6},
207 	{0x3c80, 0x00},
208 	{0x3c87, 0x01},
209 	{0x3c8c, 0x19},
210 	{0x3c8d, 0x1c},
211 	{0x3ca0, 0x00},
212 	{0x3ca1, 0x00},
213 	{0x3ca2, 0x00},
214 	{0x3ca3, 0x00},
215 	{0x3ca4, 0x50},
216 	{0x3ca5, 0x11},
217 	{0x3ca6, 0x01},
218 	{0x3ca7, 0x00},
219 	{0x3ca8, 0x00},
220 	{0x4008, 0x02},
221 	{0x4009, 0x0f},
222 	{0x400a, 0x01},
223 	{0x400b, 0x19},
224 	{0x4011, 0x21},
225 	{0x4017, 0x08},
226 	{0x4019, 0x04},
227 	{0x401a, 0x58},
228 	{0x4032, 0x1e},
229 	{0x4050, 0x02},
230 	{0x4051, 0x09},
231 	{0x405e, 0x00},
232 	{0x4066, 0x02},
233 	{0x4501, 0x00},
234 	{0x4502, 0x10},
235 	{0x4505, 0x00},
236 	{0x4800, 0x64},
237 	{0x481b, 0x3e},
238 	{0x481f, 0x30},
239 	{0x4825, 0x34},
240 	{0x4837, 0x0e},
241 	{0x484b, 0x01},
242 	{0x4883, 0x02},
243 	{0x5000, 0xff},
244 	{0x5001, 0x0f},
245 	{0x5045, 0x20},
246 	{0x5046, 0x20},
247 	{0x5047, 0xa4},
248 	{0x5048, 0x20},
249 	{0x5049, 0xa4},
250 };
251 
252 static const struct ov13b10_reg mode_4208x3120_regs[] = {
253 	{0x0305, 0xaf},
254 	{0x3501, 0x0c},
255 	{0x3662, 0x92},
256 	{0x3714, 0x24},
257 	{0x3739, 0x12},
258 	{0x37c2, 0x04},
259 	{0x37d9, 0x0c},
260 	{0x37e2, 0x0a},
261 	{0x3800, 0x00},
262 	{0x3801, 0x00},
263 	{0x3802, 0x00},
264 	{0x3803, 0x08},
265 	{0x3804, 0x10},
266 	{0x3805, 0x8f},
267 	{0x3806, 0x0c},
268 	{0x3807, 0x47},
269 	{0x3808, 0x10},
270 	{0x3809, 0x70},
271 	{0x380a, 0x0c},
272 	{0x380b, 0x30},
273 	{0x380c, 0x04},
274 	{0x380d, 0x98},
275 	{0x380e, 0x0c},
276 	{0x380f, 0x7c},
277 	{0x3810, 0x00},
278 	{0x3811, 0x0f},
279 	{0x3812, 0x00},
280 	{0x3813, 0x09},
281 	{0x3814, 0x01},
282 	{0x3816, 0x01},
283 	{0x3820, 0x88},
284 	{0x3c8c, 0x19},
285 	{0x4008, 0x02},
286 	{0x4009, 0x0f},
287 	{0x4050, 0x02},
288 	{0x4051, 0x09},
289 	{0x4501, 0x00},
290 	{0x4505, 0x00},
291 	{0x4837, 0x0e},
292 	{0x5000, 0xff},
293 	{0x5001, 0x0f},
294 };
295 
296 static const struct ov13b10_reg mode_4160x3120_regs[] = {
297 	{0x0305, 0xaf},
298 	{0x3501, 0x0c},
299 	{0x3662, 0x92},
300 	{0x3714, 0x24},
301 	{0x3739, 0x12},
302 	{0x37c2, 0x04},
303 	{0x37d9, 0x0c},
304 	{0x37e2, 0x0a},
305 	{0x3800, 0x00},
306 	{0x3801, 0x00},
307 	{0x3802, 0x00},
308 	{0x3803, 0x08},
309 	{0x3804, 0x10},
310 	{0x3805, 0x8f},
311 	{0x3806, 0x0c},
312 	{0x3807, 0x47},
313 	{0x3808, 0x10},
314 	{0x3809, 0x40},
315 	{0x380a, 0x0c},
316 	{0x380b, 0x30},
317 	{0x380c, 0x04},
318 	{0x380d, 0x98},
319 	{0x380e, 0x0c},
320 	{0x380f, 0x7c},
321 	{0x3810, 0x00},
322 	{0x3811, 0x27},
323 	{0x3812, 0x00},
324 	{0x3813, 0x09},
325 	{0x3814, 0x01},
326 	{0x3816, 0x01},
327 	{0x3820, 0x88},
328 	{0x3c8c, 0x19},
329 	{0x4008, 0x02},
330 	{0x4009, 0x0f},
331 	{0x4050, 0x02},
332 	{0x4051, 0x09},
333 	{0x4501, 0x00},
334 	{0x4505, 0x00},
335 	{0x4837, 0x0e},
336 	{0x5000, 0xff},
337 	{0x5001, 0x0f},
338 };
339 
340 static const struct ov13b10_reg mode_4160x2340_regs[] = {
341 	{0x0305, 0xaf},
342 	{0x3501, 0x0c},
343 	{0x3662, 0x92},
344 	{0x3714, 0x24},
345 	{0x3739, 0x12},
346 	{0x37c2, 0x04},
347 	{0x37d9, 0x0c},
348 	{0x37e2, 0x0a},
349 	{0x3800, 0x00},
350 	{0x3801, 0x00},
351 	{0x3802, 0x00},
352 	{0x3803, 0x08},
353 	{0x3804, 0x10},
354 	{0x3805, 0x8f},
355 	{0x3806, 0x0c},
356 	{0x3807, 0x47},
357 	{0x3808, 0x10},
358 	{0x3809, 0x40},
359 	{0x380a, 0x09},
360 	{0x380b, 0x24},
361 	{0x380c, 0x04},
362 	{0x380d, 0x98},
363 	{0x380e, 0x0c},
364 	{0x380f, 0x7c},
365 	{0x3810, 0x00},
366 	{0x3811, 0x27},
367 	{0x3812, 0x01},
368 	{0x3813, 0x8f},
369 	{0x3814, 0x01},
370 	{0x3816, 0x01},
371 	{0x3820, 0x88},
372 	{0x3c8c, 0x19},
373 	{0x4008, 0x02},
374 	{0x4009, 0x0f},
375 	{0x4050, 0x02},
376 	{0x4051, 0x09},
377 	{0x4501, 0x00},
378 	{0x4505, 0x00},
379 	{0x4837, 0x0e},
380 	{0x5000, 0xff},
381 	{0x5001, 0x0f},
382 };
383 
384 static const struct ov13b10_reg mode_2104x1560_regs[] = {
385 	{0x0305, 0xaf},
386 	{0x3501, 0x06},
387 	{0x3662, 0x88},
388 	{0x3714, 0x28},
389 	{0x3739, 0x10},
390 	{0x37c2, 0x14},
391 	{0x37d9, 0x06},
392 	{0x37e2, 0x0c},
393 	{0x3800, 0x00},
394 	{0x3801, 0x00},
395 	{0x3802, 0x00},
396 	{0x3803, 0x08},
397 	{0x3804, 0x10},
398 	{0x3805, 0x8f},
399 	{0x3806, 0x0c},
400 	{0x3807, 0x47},
401 	{0x3808, 0x08},
402 	{0x3809, 0x38},
403 	{0x380a, 0x06},
404 	{0x380b, 0x18},
405 	{0x380c, 0x04},
406 	{0x380d, 0x98},
407 	{0x380e, 0x06},
408 	{0x380f, 0x3e},
409 	{0x3810, 0x00},
410 	{0x3811, 0x07},
411 	{0x3812, 0x00},
412 	{0x3813, 0x05},
413 	{0x3814, 0x03},
414 	{0x3816, 0x03},
415 	{0x3820, 0x8b},
416 	{0x3c8c, 0x18},
417 	{0x4008, 0x00},
418 	{0x4009, 0x05},
419 	{0x4050, 0x00},
420 	{0x4051, 0x05},
421 	{0x4501, 0x08},
422 	{0x4505, 0x00},
423 	{0x4837, 0x0e},
424 	{0x5000, 0xfd},
425 	{0x5001, 0x0d},
426 };
427 
428 static const struct ov13b10_reg mode_2080x1170_regs[] = {
429 	{0x0305, 0xaf},
430 	{0x3501, 0x06},
431 	{0x3662, 0x88},
432 	{0x3714, 0x28},
433 	{0x3739, 0x10},
434 	{0x37c2, 0x14},
435 	{0x37d9, 0x06},
436 	{0x37e2, 0x0c},
437 	{0x3800, 0x00},
438 	{0x3801, 0x00},
439 	{0x3802, 0x00},
440 	{0x3803, 0x08},
441 	{0x3804, 0x10},
442 	{0x3805, 0x8f},
443 	{0x3806, 0x0c},
444 	{0x3807, 0x47},
445 	{0x3808, 0x08},
446 	{0x3809, 0x20},
447 	{0x380a, 0x04},
448 	{0x380b, 0x92},
449 	{0x380c, 0x04},
450 	{0x380d, 0x98},
451 	{0x380e, 0x06},
452 	{0x380f, 0x3e},
453 	{0x3810, 0x00},
454 	{0x3811, 0x13},
455 	{0x3812, 0x00},
456 	{0x3813, 0xc9},
457 	{0x3814, 0x03},
458 	{0x3816, 0x03},
459 	{0x3820, 0x8b},
460 	{0x3c8c, 0x18},
461 	{0x4008, 0x00},
462 	{0x4009, 0x05},
463 	{0x4050, 0x00},
464 	{0x4051, 0x05},
465 	{0x4501, 0x08},
466 	{0x4505, 0x00},
467 	{0x4837, 0x0e},
468 	{0x5000, 0xfd},
469 	{0x5001, 0x0d},
470 };
471 
472 static const struct ov13b10_reg mode_1364x768_120fps_regs[] = {
473 	{0x0305, 0xaf},
474 	{0x3011, 0x7c},
475 	{0x3501, 0x03},
476 	{0x3502, 0x00},
477 	{0x3662, 0x88},
478 	{0x3714, 0x28},
479 	{0x3739, 0x10},
480 	{0x37c2, 0x14},
481 	{0x37d9, 0x06},
482 	{0x37e2, 0x0c},
483 	{0x37e4, 0x00},
484 	{0x3800, 0x02},
485 	{0x3801, 0xe4},
486 	{0x3802, 0x03},
487 	{0x3803, 0x48},
488 	{0x3804, 0x0d},
489 	{0x3805, 0xab},
490 	{0x3806, 0x09},
491 	{0x3807, 0x60},
492 	{0x3808, 0x05},
493 	{0x3809, 0x54},
494 	{0x380a, 0x03},
495 	{0x380b, 0x00},
496 	{0x380c, 0x04},
497 	{0x380d, 0x8e},
498 	{0x380e, 0x03},
499 	{0x380f, 0x20},
500 	{0x3811, 0x07},
501 	{0x3813, 0x07},
502 	{0x3814, 0x03},
503 	{0x3816, 0x03},
504 	{0x3820, 0x8b},
505 	{0x3c8c, 0x18},
506 	{0x4008, 0x00},
507 	{0x4009, 0x05},
508 	{0x4050, 0x00},
509 	{0x4051, 0x05},
510 	{0x4501, 0x08},
511 	{0x4505, 0x04},
512 	{0x5000, 0xfd},
513 	{0x5001, 0x0d},
514 };
515 
516 static const char * const ov13b10_test_pattern_menu[] = {
517 	"Disabled",
518 	"Vertical Color Bar Type 1",
519 	"Vertical Color Bar Type 2",
520 	"Vertical Color Bar Type 3",
521 	"Vertical Color Bar Type 4"
522 };
523 
524 /* Configurations for supported link frequencies */
525 #define OV13B10_LINK_FREQ_560MHZ	560000000ULL
526 #define OV13B10_LINK_FREQ_INDEX_0	0
527 
528 #define OV13B10_EXT_CLK			19200000
529 #define OV13B10_DATA_LANES		4
530 
531 /*
532  * pixel_rate = link_freq * data-rate * nr_of_lanes / bits_per_sample
533  * data rate => double data rate; number of lanes => 4; bits per pixel => 10
534  */
535 static u64 link_freq_to_pixel_rate(u64 f)
536 {
537 	f *= 2 * OV13B10_DATA_LANES;
538 	do_div(f, 10);
539 
540 	return f;
541 }
542 
543 /* Menu items for LINK_FREQ V4L2 control */
544 static const s64 link_freq_menu_items[] = {
545 	OV13B10_LINK_FREQ_560MHZ
546 };
547 
548 /* Link frequency configs */
549 static const struct ov13b10_link_freq_config
550 			link_freq_configs[] = {
551 	{
552 		.pixels_per_line = OV13B10_PPL_560MHZ,
553 		.reg_list = {
554 			.num_of_regs = ARRAY_SIZE(mipi_data_rate_1120mbps),
555 			.regs = mipi_data_rate_1120mbps,
556 		}
557 	}
558 };
559 
560 /* Mode configs */
561 static const struct ov13b10_mode supported_modes[] = {
562 	{
563 		.width = 4208,
564 		.height = 3120,
565 		.vts_def = OV13B10_VTS_30FPS,
566 		.vts_min = OV13B10_VTS_30FPS,
567 		.reg_list = {
568 			.num_of_regs = ARRAY_SIZE(mode_4208x3120_regs),
569 			.regs = mode_4208x3120_regs,
570 		},
571 		.link_freq_index = OV13B10_LINK_FREQ_INDEX_0,
572 	},
573 	{
574 		.width = 4160,
575 		.height = 3120,
576 		.vts_def = OV13B10_VTS_30FPS,
577 		.vts_min = OV13B10_VTS_30FPS,
578 		.reg_list = {
579 			.num_of_regs = ARRAY_SIZE(mode_4160x3120_regs),
580 			.regs = mode_4160x3120_regs,
581 		},
582 		.link_freq_index = OV13B10_LINK_FREQ_INDEX_0,
583 	},
584 	{
585 		.width = 4160,
586 		.height = 2340,
587 		.vts_def = OV13B10_VTS_30FPS,
588 		.vts_min = OV13B10_VTS_30FPS,
589 		.reg_list = {
590 			.num_of_regs = ARRAY_SIZE(mode_4160x2340_regs),
591 			.regs = mode_4160x2340_regs,
592 		},
593 		.link_freq_index = OV13B10_LINK_FREQ_INDEX_0,
594 	},
595 	{
596 		.width = 2104,
597 		.height = 1560,
598 		.vts_def = OV13B10_VTS_60FPS,
599 		.vts_min = OV13B10_VTS_60FPS,
600 		.reg_list = {
601 			.num_of_regs = ARRAY_SIZE(mode_2104x1560_regs),
602 			.regs = mode_2104x1560_regs,
603 		},
604 		.link_freq_index = OV13B10_LINK_FREQ_INDEX_0,
605 	},
606 	{
607 		.width = 2080,
608 		.height = 1170,
609 		.vts_def = OV13B10_VTS_60FPS,
610 		.vts_min = OV13B10_VTS_60FPS,
611 		.reg_list = {
612 			.num_of_regs = ARRAY_SIZE(mode_2080x1170_regs),
613 			.regs = mode_2080x1170_regs,
614 		},
615 		.link_freq_index = OV13B10_LINK_FREQ_INDEX_0,
616 	},
617 	{
618 		.width = 1364,
619 		.height = 768,
620 		.vts_def = OV13B10_VTS_120FPS,
621 		.vts_min = OV13B10_VTS_120FPS,
622 		.link_freq_index = OV13B10_LINK_FREQ_INDEX_0,
623 		.reg_list = {
624 			.num_of_regs = ARRAY_SIZE(mode_1364x768_120fps_regs),
625 			.regs = mode_1364x768_120fps_regs,
626 		},
627 	},
628 };
629 
630 struct ov13b10 {
631 	struct v4l2_subdev sd;
632 	struct media_pad pad;
633 
634 	struct v4l2_ctrl_handler ctrl_handler;
635 
636 	struct clk *img_clk;
637 	struct regulator *avdd;
638 	struct gpio_desc *reset;
639 
640 	/* V4L2 Controls */
641 	struct v4l2_ctrl *link_freq;
642 	struct v4l2_ctrl *pixel_rate;
643 	struct v4l2_ctrl *vblank;
644 	struct v4l2_ctrl *hblank;
645 	struct v4l2_ctrl *exposure;
646 
647 	/* Current mode */
648 	const struct ov13b10_mode *cur_mode;
649 
650 	/* Mutex for serialized access */
651 	struct mutex mutex;
652 
653 	/* True if the device has been identified */
654 	bool identified;
655 };
656 
657 #define to_ov13b10(_sd)	container_of(_sd, struct ov13b10, sd)
658 
659 /* Read registers up to 4 at a time */
660 static int ov13b10_read_reg(struct ov13b10 *ov13b,
661 			    u16 reg, u32 len, u32 *val)
662 {
663 	struct i2c_client *client = v4l2_get_subdevdata(&ov13b->sd);
664 	struct i2c_msg msgs[2];
665 	u8 *data_be_p;
666 	int ret;
667 	__be32 data_be = 0;
668 	__be16 reg_addr_be = cpu_to_be16(reg);
669 
670 	if (len > 4)
671 		return -EINVAL;
672 
673 	data_be_p = (u8 *)&data_be;
674 	/* Write register address */
675 	msgs[0].addr = client->addr;
676 	msgs[0].flags = 0;
677 	msgs[0].len = 2;
678 	msgs[0].buf = (u8 *)&reg_addr_be;
679 
680 	/* Read data from register */
681 	msgs[1].addr = client->addr;
682 	msgs[1].flags = I2C_M_RD;
683 	msgs[1].len = len;
684 	msgs[1].buf = &data_be_p[4 - len];
685 
686 	ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
687 	if (ret != ARRAY_SIZE(msgs))
688 		return -EIO;
689 
690 	*val = be32_to_cpu(data_be);
691 
692 	return 0;
693 }
694 
695 /* Write registers up to 4 at a time */
696 static int ov13b10_write_reg(struct ov13b10 *ov13b,
697 			     u16 reg, u32 len, u32 __val)
698 {
699 	struct i2c_client *client = v4l2_get_subdevdata(&ov13b->sd);
700 	int buf_i, val_i;
701 	u8 buf[6], *val_p;
702 	__be32 val;
703 
704 	if (len > 4)
705 		return -EINVAL;
706 
707 	buf[0] = reg >> 8;
708 	buf[1] = reg & 0xff;
709 
710 	val = cpu_to_be32(__val);
711 	val_p = (u8 *)&val;
712 	buf_i = 2;
713 	val_i = 4 - len;
714 
715 	while (val_i < 4)
716 		buf[buf_i++] = val_p[val_i++];
717 
718 	if (i2c_master_send(client, buf, len + 2) != len + 2)
719 		return -EIO;
720 
721 	return 0;
722 }
723 
724 /* Write a list of registers */
725 static int ov13b10_write_regs(struct ov13b10 *ov13b,
726 			      const struct ov13b10_reg *regs, u32 len)
727 {
728 	struct i2c_client *client = v4l2_get_subdevdata(&ov13b->sd);
729 	int ret;
730 	u32 i;
731 
732 	for (i = 0; i < len; i++) {
733 		ret = ov13b10_write_reg(ov13b, regs[i].address, 1,
734 					regs[i].val);
735 		if (ret) {
736 			dev_err_ratelimited(&client->dev,
737 					    "Failed to write reg 0x%4.4x. error = %d\n",
738 					    regs[i].address, ret);
739 
740 			return ret;
741 		}
742 	}
743 
744 	return 0;
745 }
746 
747 static int ov13b10_write_reg_list(struct ov13b10 *ov13b,
748 				  const struct ov13b10_reg_list *r_list)
749 {
750 	return ov13b10_write_regs(ov13b, r_list->regs, r_list->num_of_regs);
751 }
752 
753 /* Open sub-device */
754 static int ov13b10_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
755 {
756 	const struct ov13b10_mode *default_mode = &supported_modes[0];
757 	struct ov13b10 *ov13b = to_ov13b10(sd);
758 	struct v4l2_mbus_framefmt *try_fmt = v4l2_subdev_get_try_format(sd,
759 									fh->state,
760 									0);
761 
762 	mutex_lock(&ov13b->mutex);
763 
764 	/* Initialize try_fmt */
765 	try_fmt->width = default_mode->width;
766 	try_fmt->height = default_mode->height;
767 	try_fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
768 	try_fmt->field = V4L2_FIELD_NONE;
769 
770 	/* No crop or compose */
771 	mutex_unlock(&ov13b->mutex);
772 
773 	return 0;
774 }
775 
776 static int ov13b10_update_digital_gain(struct ov13b10 *ov13b, u32 d_gain)
777 {
778 	int ret;
779 	u32 val;
780 
781 	/*
782 	 * 0x350C[7:6], 0x350B[7:0], 0x350A[1:0]
783 	 */
784 
785 	val = (d_gain & OV13B10_DGTL_GAIN_L_MASK) << OV13B10_DGTL_GAIN_L_SHIFT;
786 	ret = ov13b10_write_reg(ov13b, OV13B10_REG_DGTL_GAIN_L,
787 				OV13B10_REG_VALUE_08BIT, val);
788 	if (ret)
789 		return ret;
790 
791 	val = (d_gain >> OV13B10_DGTL_GAIN_M_SHIFT) & OV13B10_DGTL_GAIN_M_MASK;
792 	ret = ov13b10_write_reg(ov13b, OV13B10_REG_DGTL_GAIN_M,
793 				OV13B10_REG_VALUE_08BIT, val);
794 	if (ret)
795 		return ret;
796 
797 	val = (d_gain >> OV13B10_DGTL_GAIN_H_SHIFT) & OV13B10_DGTL_GAIN_H_MASK;
798 	ret = ov13b10_write_reg(ov13b, OV13B10_REG_DGTL_GAIN_H,
799 				OV13B10_REG_VALUE_08BIT, val);
800 
801 	return ret;
802 }
803 
804 static int ov13b10_enable_test_pattern(struct ov13b10 *ov13b, u32 pattern)
805 {
806 	int ret;
807 	u32 val;
808 
809 	ret = ov13b10_read_reg(ov13b, OV13B10_REG_TEST_PATTERN,
810 			       OV13B10_REG_VALUE_08BIT, &val);
811 	if (ret)
812 		return ret;
813 
814 	if (pattern) {
815 		val &= OV13B10_TEST_PATTERN_MASK;
816 		val |= ((pattern - 1) << OV13B10_TEST_PATTERN_BAR_SHIFT) |
817 		     OV13B10_TEST_PATTERN_ENABLE;
818 	} else {
819 		val &= ~OV13B10_TEST_PATTERN_ENABLE;
820 	}
821 
822 	return ov13b10_write_reg(ov13b, OV13B10_REG_TEST_PATTERN,
823 				 OV13B10_REG_VALUE_08BIT, val);
824 }
825 
826 static int ov13b10_set_ctrl_hflip(struct ov13b10 *ov13b, u32 ctrl_val)
827 {
828 	int ret;
829 	u32 val;
830 
831 	ret = ov13b10_read_reg(ov13b, OV13B10_REG_FORMAT1,
832 			       OV13B10_REG_VALUE_08BIT, &val);
833 	if (ret)
834 		return ret;
835 
836 	ret = ov13b10_write_reg(ov13b, OV13B10_REG_FORMAT1,
837 				OV13B10_REG_VALUE_08BIT,
838 				ctrl_val ? val & ~BIT(3) : val);
839 
840 	if (ret)
841 		return ret;
842 
843 	ret = ov13b10_read_reg(ov13b, OV13B10_REG_H_WIN_OFFSET,
844 			       OV13B10_REG_VALUE_08BIT, &val);
845 	if (ret)
846 		return ret;
847 
848 	/*
849 	 * Applying cropping offset to reverse the change of Bayer order
850 	 * after mirroring image
851 	 */
852 	return ov13b10_write_reg(ov13b, OV13B10_REG_H_WIN_OFFSET,
853 				 OV13B10_REG_VALUE_08BIT,
854 				 ctrl_val ? ++val : val);
855 }
856 
857 static int ov13b10_set_ctrl_vflip(struct ov13b10 *ov13b, u32 ctrl_val)
858 {
859 	int ret;
860 	u32 val;
861 
862 	ret = ov13b10_read_reg(ov13b, OV13B10_REG_FORMAT1,
863 			       OV13B10_REG_VALUE_08BIT, &val);
864 	if (ret)
865 		return ret;
866 
867 	ret = ov13b10_write_reg(ov13b, OV13B10_REG_FORMAT1,
868 				OV13B10_REG_VALUE_08BIT,
869 				ctrl_val ? val | BIT(4) | BIT(5)  : val);
870 
871 	if (ret)
872 		return ret;
873 
874 	ret = ov13b10_read_reg(ov13b, OV13B10_REG_V_WIN_OFFSET,
875 			       OV13B10_REG_VALUE_08BIT, &val);
876 	if (ret)
877 		return ret;
878 
879 	/*
880 	 * Applying cropping offset to reverse the change of Bayer order
881 	 * after flipping image
882 	 */
883 	return ov13b10_write_reg(ov13b, OV13B10_REG_V_WIN_OFFSET,
884 				 OV13B10_REG_VALUE_08BIT,
885 				 ctrl_val ? --val : val);
886 }
887 
888 static int ov13b10_set_ctrl(struct v4l2_ctrl *ctrl)
889 {
890 	struct ov13b10 *ov13b = container_of(ctrl->handler,
891 					     struct ov13b10, ctrl_handler);
892 	struct i2c_client *client = v4l2_get_subdevdata(&ov13b->sd);
893 	s64 max;
894 	int ret;
895 
896 	/* Propagate change of current control to all related controls */
897 	switch (ctrl->id) {
898 	case V4L2_CID_VBLANK:
899 		/* Update max exposure while meeting expected vblanking */
900 		max = ov13b->cur_mode->height + ctrl->val - 8;
901 		__v4l2_ctrl_modify_range(ov13b->exposure,
902 					 ov13b->exposure->minimum,
903 					 max, ov13b->exposure->step, max);
904 		break;
905 	}
906 
907 	/*
908 	 * Applying V4L2 control value only happens
909 	 * when power is up for streaming
910 	 */
911 	if (!pm_runtime_get_if_in_use(&client->dev))
912 		return 0;
913 
914 	ret = 0;
915 	switch (ctrl->id) {
916 	case V4L2_CID_ANALOGUE_GAIN:
917 		ret = ov13b10_write_reg(ov13b, OV13B10_REG_ANALOG_GAIN,
918 					OV13B10_REG_VALUE_16BIT,
919 					ctrl->val << 1);
920 		break;
921 	case V4L2_CID_DIGITAL_GAIN:
922 		ret = ov13b10_update_digital_gain(ov13b, ctrl->val);
923 		break;
924 	case V4L2_CID_EXPOSURE:
925 		ret = ov13b10_write_reg(ov13b, OV13B10_REG_EXPOSURE,
926 					OV13B10_REG_VALUE_24BIT,
927 					ctrl->val);
928 		break;
929 	case V4L2_CID_VBLANK:
930 		ret = ov13b10_write_reg(ov13b, OV13B10_REG_VTS,
931 					OV13B10_REG_VALUE_16BIT,
932 					ov13b->cur_mode->height
933 					+ ctrl->val);
934 		break;
935 	case V4L2_CID_TEST_PATTERN:
936 		ret = ov13b10_enable_test_pattern(ov13b, ctrl->val);
937 		break;
938 	case V4L2_CID_HFLIP:
939 		ov13b10_set_ctrl_hflip(ov13b, ctrl->val);
940 		break;
941 	case V4L2_CID_VFLIP:
942 		ov13b10_set_ctrl_vflip(ov13b, ctrl->val);
943 		break;
944 	default:
945 		dev_info(&client->dev,
946 			 "ctrl(id:0x%x,val:0x%x) is not handled\n",
947 			 ctrl->id, ctrl->val);
948 		break;
949 	}
950 
951 	pm_runtime_put(&client->dev);
952 
953 	return ret;
954 }
955 
956 static const struct v4l2_ctrl_ops ov13b10_ctrl_ops = {
957 	.s_ctrl = ov13b10_set_ctrl,
958 };
959 
960 static int ov13b10_enum_mbus_code(struct v4l2_subdev *sd,
961 				  struct v4l2_subdev_state *sd_state,
962 				  struct v4l2_subdev_mbus_code_enum *code)
963 {
964 	/* Only one bayer order(GRBG) is supported */
965 	if (code->index > 0)
966 		return -EINVAL;
967 
968 	code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
969 
970 	return 0;
971 }
972 
973 static int ov13b10_enum_frame_size(struct v4l2_subdev *sd,
974 				   struct v4l2_subdev_state *sd_state,
975 				   struct v4l2_subdev_frame_size_enum *fse)
976 {
977 	if (fse->index >= ARRAY_SIZE(supported_modes))
978 		return -EINVAL;
979 
980 	if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
981 		return -EINVAL;
982 
983 	fse->min_width = supported_modes[fse->index].width;
984 	fse->max_width = fse->min_width;
985 	fse->min_height = supported_modes[fse->index].height;
986 	fse->max_height = fse->min_height;
987 
988 	return 0;
989 }
990 
991 static void ov13b10_update_pad_format(const struct ov13b10_mode *mode,
992 				      struct v4l2_subdev_format *fmt)
993 {
994 	fmt->format.width = mode->width;
995 	fmt->format.height = mode->height;
996 	fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
997 	fmt->format.field = V4L2_FIELD_NONE;
998 }
999 
1000 static int ov13b10_do_get_pad_format(struct ov13b10 *ov13b,
1001 				     struct v4l2_subdev_state *sd_state,
1002 				     struct v4l2_subdev_format *fmt)
1003 {
1004 	struct v4l2_mbus_framefmt *framefmt;
1005 	struct v4l2_subdev *sd = &ov13b->sd;
1006 
1007 	if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1008 		framefmt = v4l2_subdev_get_try_format(sd, sd_state, fmt->pad);
1009 		fmt->format = *framefmt;
1010 	} else {
1011 		ov13b10_update_pad_format(ov13b->cur_mode, fmt);
1012 	}
1013 
1014 	return 0;
1015 }
1016 
1017 static int ov13b10_get_pad_format(struct v4l2_subdev *sd,
1018 				  struct v4l2_subdev_state *sd_state,
1019 				  struct v4l2_subdev_format *fmt)
1020 {
1021 	struct ov13b10 *ov13b = to_ov13b10(sd);
1022 	int ret;
1023 
1024 	mutex_lock(&ov13b->mutex);
1025 	ret = ov13b10_do_get_pad_format(ov13b, sd_state, fmt);
1026 	mutex_unlock(&ov13b->mutex);
1027 
1028 	return ret;
1029 }
1030 
1031 static int
1032 ov13b10_set_pad_format(struct v4l2_subdev *sd,
1033 		       struct v4l2_subdev_state *sd_state,
1034 		       struct v4l2_subdev_format *fmt)
1035 {
1036 	struct ov13b10 *ov13b = to_ov13b10(sd);
1037 	const struct ov13b10_mode *mode;
1038 	struct v4l2_mbus_framefmt *framefmt;
1039 	s32 vblank_def;
1040 	s32 vblank_min;
1041 	s64 h_blank;
1042 	s64 pixel_rate;
1043 	s64 link_freq;
1044 
1045 	mutex_lock(&ov13b->mutex);
1046 
1047 	/* Only one raw bayer(GRBG) order is supported */
1048 	if (fmt->format.code != MEDIA_BUS_FMT_SGRBG10_1X10)
1049 		fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
1050 
1051 	mode = v4l2_find_nearest_size(supported_modes,
1052 				      ARRAY_SIZE(supported_modes),
1053 				      width, height,
1054 				      fmt->format.width, fmt->format.height);
1055 	ov13b10_update_pad_format(mode, fmt);
1056 	if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1057 		framefmt = v4l2_subdev_get_try_format(sd, sd_state, fmt->pad);
1058 		*framefmt = fmt->format;
1059 	} else {
1060 		ov13b->cur_mode = mode;
1061 		__v4l2_ctrl_s_ctrl(ov13b->link_freq, mode->link_freq_index);
1062 		link_freq = link_freq_menu_items[mode->link_freq_index];
1063 		pixel_rate = link_freq_to_pixel_rate(link_freq);
1064 		__v4l2_ctrl_s_ctrl_int64(ov13b->pixel_rate, pixel_rate);
1065 
1066 		/* Update limits and set FPS to default */
1067 		vblank_def = ov13b->cur_mode->vts_def -
1068 			     ov13b->cur_mode->height;
1069 		vblank_min = ov13b->cur_mode->vts_min -
1070 			     ov13b->cur_mode->height;
1071 		__v4l2_ctrl_modify_range(ov13b->vblank, vblank_min,
1072 					 OV13B10_VTS_MAX
1073 					 - ov13b->cur_mode->height,
1074 					 1,
1075 					 vblank_def);
1076 		__v4l2_ctrl_s_ctrl(ov13b->vblank, vblank_def);
1077 		h_blank =
1078 			link_freq_configs[mode->link_freq_index].pixels_per_line
1079 			 - ov13b->cur_mode->width;
1080 		__v4l2_ctrl_modify_range(ov13b->hblank, h_blank,
1081 					 h_blank, 1, h_blank);
1082 	}
1083 
1084 	mutex_unlock(&ov13b->mutex);
1085 
1086 	return 0;
1087 }
1088 
1089 /* Verify chip ID */
1090 static int ov13b10_identify_module(struct ov13b10 *ov13b)
1091 {
1092 	struct i2c_client *client = v4l2_get_subdevdata(&ov13b->sd);
1093 	int ret;
1094 	u32 val;
1095 
1096 	if (ov13b->identified)
1097 		return 0;
1098 
1099 	ret = ov13b10_read_reg(ov13b, OV13B10_REG_CHIP_ID,
1100 			       OV13B10_REG_VALUE_24BIT, &val);
1101 	if (ret)
1102 		return ret;
1103 
1104 	if (val != OV13B10_CHIP_ID) {
1105 		dev_err(&client->dev, "chip id mismatch: %x!=%x\n",
1106 			OV13B10_CHIP_ID, val);
1107 		return -EIO;
1108 	}
1109 
1110 	ov13b->identified = true;
1111 
1112 	return 0;
1113 }
1114 
1115 static int ov13b10_power_off(struct device *dev)
1116 {
1117 	struct v4l2_subdev *sd = dev_get_drvdata(dev);
1118 	struct ov13b10 *ov13b10 = to_ov13b10(sd);
1119 
1120 	gpiod_set_value_cansleep(ov13b10->reset, 1);
1121 
1122 	if (ov13b10->avdd)
1123 		regulator_disable(ov13b10->avdd);
1124 
1125 	clk_disable_unprepare(ov13b10->img_clk);
1126 
1127 	return 0;
1128 }
1129 
1130 static int ov13b10_power_on(struct device *dev)
1131 {
1132 	struct v4l2_subdev *sd = dev_get_drvdata(dev);
1133 	struct ov13b10 *ov13b10 = to_ov13b10(sd);
1134 	int ret;
1135 
1136 	ret = clk_prepare_enable(ov13b10->img_clk);
1137 	if (ret < 0) {
1138 		dev_err(dev, "failed to enable imaging clock: %d", ret);
1139 		return ret;
1140 	}
1141 
1142 	if (ov13b10->avdd) {
1143 		ret = regulator_enable(ov13b10->avdd);
1144 		if (ret < 0) {
1145 			dev_err(dev, "failed to enable avdd: %d", ret);
1146 			clk_disable_unprepare(ov13b10->img_clk);
1147 			return ret;
1148 		}
1149 	}
1150 
1151 	gpiod_set_value_cansleep(ov13b10->reset, 0);
1152 	/* 5ms to wait ready after XSHUTDN assert */
1153 	usleep_range(5000, 5500);
1154 
1155 	return 0;
1156 }
1157 
1158 static int ov13b10_start_streaming(struct ov13b10 *ov13b)
1159 {
1160 	struct i2c_client *client = v4l2_get_subdevdata(&ov13b->sd);
1161 	const struct ov13b10_reg_list *reg_list;
1162 	int ret, link_freq_index;
1163 
1164 	ret = ov13b10_identify_module(ov13b);
1165 	if (ret)
1166 		return ret;
1167 
1168 	/* Get out of from software reset */
1169 	ret = ov13b10_write_reg(ov13b, OV13B10_REG_SOFTWARE_RST,
1170 				OV13B10_REG_VALUE_08BIT, OV13B10_SOFTWARE_RST);
1171 	if (ret) {
1172 		dev_err(&client->dev, "%s failed to set powerup registers\n",
1173 			__func__);
1174 		return ret;
1175 	}
1176 
1177 	link_freq_index = ov13b->cur_mode->link_freq_index;
1178 	reg_list = &link_freq_configs[link_freq_index].reg_list;
1179 	ret = ov13b10_write_reg_list(ov13b, reg_list);
1180 	if (ret) {
1181 		dev_err(&client->dev, "%s failed to set plls\n", __func__);
1182 		return ret;
1183 	}
1184 
1185 	/* Apply default values of current mode */
1186 	reg_list = &ov13b->cur_mode->reg_list;
1187 	ret = ov13b10_write_reg_list(ov13b, reg_list);
1188 	if (ret) {
1189 		dev_err(&client->dev, "%s failed to set mode\n", __func__);
1190 		return ret;
1191 	}
1192 
1193 	/* Apply customized values from user */
1194 	ret =  __v4l2_ctrl_handler_setup(ov13b->sd.ctrl_handler);
1195 	if (ret)
1196 		return ret;
1197 
1198 	return ov13b10_write_reg(ov13b, OV13B10_REG_MODE_SELECT,
1199 				 OV13B10_REG_VALUE_08BIT,
1200 				 OV13B10_MODE_STREAMING);
1201 }
1202 
1203 /* Stop streaming */
1204 static int ov13b10_stop_streaming(struct ov13b10 *ov13b)
1205 {
1206 	return ov13b10_write_reg(ov13b, OV13B10_REG_MODE_SELECT,
1207 				 OV13B10_REG_VALUE_08BIT, OV13B10_MODE_STANDBY);
1208 }
1209 
1210 static int ov13b10_set_stream(struct v4l2_subdev *sd, int enable)
1211 {
1212 	struct ov13b10 *ov13b = to_ov13b10(sd);
1213 	struct i2c_client *client = v4l2_get_subdevdata(sd);
1214 	int ret = 0;
1215 
1216 	mutex_lock(&ov13b->mutex);
1217 
1218 	if (enable) {
1219 		ret = pm_runtime_resume_and_get(&client->dev);
1220 		if (ret < 0)
1221 			goto err_unlock;
1222 
1223 		/*
1224 		 * Apply default & customized values
1225 		 * and then start streaming.
1226 		 */
1227 		ret = ov13b10_start_streaming(ov13b);
1228 		if (ret)
1229 			goto err_rpm_put;
1230 	} else {
1231 		ov13b10_stop_streaming(ov13b);
1232 		pm_runtime_put(&client->dev);
1233 	}
1234 
1235 	mutex_unlock(&ov13b->mutex);
1236 
1237 	return ret;
1238 
1239 err_rpm_put:
1240 	pm_runtime_put(&client->dev);
1241 err_unlock:
1242 	mutex_unlock(&ov13b->mutex);
1243 
1244 	return ret;
1245 }
1246 
1247 static int ov13b10_suspend(struct device *dev)
1248 {
1249 	ov13b10_power_off(dev);
1250 
1251 	return 0;
1252 }
1253 
1254 static int ov13b10_resume(struct device *dev)
1255 {
1256 	return ov13b10_power_on(dev);
1257 }
1258 
1259 static const struct v4l2_subdev_video_ops ov13b10_video_ops = {
1260 	.s_stream = ov13b10_set_stream,
1261 };
1262 
1263 static const struct v4l2_subdev_pad_ops ov13b10_pad_ops = {
1264 	.enum_mbus_code = ov13b10_enum_mbus_code,
1265 	.get_fmt = ov13b10_get_pad_format,
1266 	.set_fmt = ov13b10_set_pad_format,
1267 	.enum_frame_size = ov13b10_enum_frame_size,
1268 };
1269 
1270 static const struct v4l2_subdev_ops ov13b10_subdev_ops = {
1271 	.video = &ov13b10_video_ops,
1272 	.pad = &ov13b10_pad_ops,
1273 };
1274 
1275 static const struct media_entity_operations ov13b10_subdev_entity_ops = {
1276 	.link_validate = v4l2_subdev_link_validate,
1277 };
1278 
1279 static const struct v4l2_subdev_internal_ops ov13b10_internal_ops = {
1280 	.open = ov13b10_open,
1281 };
1282 
1283 /* Initialize control handlers */
1284 static int ov13b10_init_controls(struct ov13b10 *ov13b)
1285 {
1286 	struct i2c_client *client = v4l2_get_subdevdata(&ov13b->sd);
1287 	struct v4l2_fwnode_device_properties props;
1288 	struct v4l2_ctrl_handler *ctrl_hdlr;
1289 	s64 exposure_max;
1290 	s64 vblank_def;
1291 	s64 vblank_min;
1292 	s64 hblank;
1293 	s64 pixel_rate_min;
1294 	s64 pixel_rate_max;
1295 	const struct ov13b10_mode *mode;
1296 	u32 max;
1297 	int ret;
1298 
1299 	ctrl_hdlr = &ov13b->ctrl_handler;
1300 	ret = v4l2_ctrl_handler_init(ctrl_hdlr, 10);
1301 	if (ret)
1302 		return ret;
1303 
1304 	mutex_init(&ov13b->mutex);
1305 	ctrl_hdlr->lock = &ov13b->mutex;
1306 	max = ARRAY_SIZE(link_freq_menu_items) - 1;
1307 	ov13b->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr,
1308 						  &ov13b10_ctrl_ops,
1309 						  V4L2_CID_LINK_FREQ,
1310 						  max,
1311 						  0,
1312 						  link_freq_menu_items);
1313 	if (ov13b->link_freq)
1314 		ov13b->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1315 
1316 	pixel_rate_max = link_freq_to_pixel_rate(link_freq_menu_items[0]);
1317 	pixel_rate_min = 0;
1318 	/* By default, PIXEL_RATE is read only */
1319 	ov13b->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops,
1320 					      V4L2_CID_PIXEL_RATE,
1321 					      pixel_rate_min, pixel_rate_max,
1322 					      1, pixel_rate_max);
1323 
1324 	mode = ov13b->cur_mode;
1325 	vblank_def = mode->vts_def - mode->height;
1326 	vblank_min = mode->vts_min - mode->height;
1327 	ov13b->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops,
1328 					  V4L2_CID_VBLANK,
1329 					  vblank_min,
1330 					  OV13B10_VTS_MAX - mode->height, 1,
1331 					  vblank_def);
1332 
1333 	hblank = link_freq_configs[mode->link_freq_index].pixels_per_line -
1334 		 mode->width;
1335 	ov13b->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops,
1336 					  V4L2_CID_HBLANK,
1337 					  hblank, hblank, 1, hblank);
1338 	if (ov13b->hblank)
1339 		ov13b->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1340 
1341 	exposure_max = mode->vts_def - 8;
1342 	ov13b->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops,
1343 					    V4L2_CID_EXPOSURE,
1344 					    OV13B10_EXPOSURE_MIN,
1345 					    exposure_max, OV13B10_EXPOSURE_STEP,
1346 					    exposure_max);
1347 
1348 	v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
1349 			  OV13B10_ANA_GAIN_MIN, OV13B10_ANA_GAIN_MAX,
1350 			  OV13B10_ANA_GAIN_STEP, OV13B10_ANA_GAIN_DEFAULT);
1351 
1352 	/* Digital gain */
1353 	v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
1354 			  OV13B10_DGTL_GAIN_MIN, OV13B10_DGTL_GAIN_MAX,
1355 			  OV13B10_DGTL_GAIN_STEP, OV13B10_DGTL_GAIN_DEFAULT);
1356 
1357 	v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov13b10_ctrl_ops,
1358 				     V4L2_CID_TEST_PATTERN,
1359 				     ARRAY_SIZE(ov13b10_test_pattern_menu) - 1,
1360 				     0, 0, ov13b10_test_pattern_menu);
1361 
1362 	v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops,
1363 			  V4L2_CID_HFLIP, 0, 1, 1, 0);
1364 	v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops,
1365 			  V4L2_CID_VFLIP, 0, 1, 1, 0);
1366 
1367 	if (ctrl_hdlr->error) {
1368 		ret = ctrl_hdlr->error;
1369 		dev_err(&client->dev, "%s control init failed (%d)\n",
1370 			__func__, ret);
1371 		goto error;
1372 	}
1373 
1374 	ret = v4l2_fwnode_device_parse(&client->dev, &props);
1375 	if (ret)
1376 		goto error;
1377 
1378 	ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &ov13b10_ctrl_ops,
1379 					      &props);
1380 	if (ret)
1381 		goto error;
1382 
1383 	ov13b->sd.ctrl_handler = ctrl_hdlr;
1384 
1385 	return 0;
1386 
1387 error:
1388 	v4l2_ctrl_handler_free(ctrl_hdlr);
1389 	mutex_destroy(&ov13b->mutex);
1390 
1391 	return ret;
1392 }
1393 
1394 static void ov13b10_free_controls(struct ov13b10 *ov13b)
1395 {
1396 	v4l2_ctrl_handler_free(ov13b->sd.ctrl_handler);
1397 	mutex_destroy(&ov13b->mutex);
1398 }
1399 
1400 static int ov13b10_get_pm_resources(struct device *dev)
1401 {
1402 	struct v4l2_subdev *sd = dev_get_drvdata(dev);
1403 	struct ov13b10 *ov13b = to_ov13b10(sd);
1404 	int ret;
1405 
1406 	ov13b->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
1407 	if (IS_ERR(ov13b->reset))
1408 		return dev_err_probe(dev, PTR_ERR(ov13b->reset),
1409 				     "failed to get reset gpio\n");
1410 
1411 	ov13b->img_clk = devm_clk_get_optional(dev, NULL);
1412 	if (IS_ERR(ov13b->img_clk))
1413 		return dev_err_probe(dev, PTR_ERR(ov13b->img_clk),
1414 				     "failed to get imaging clock\n");
1415 
1416 	ov13b->avdd = devm_regulator_get_optional(dev, "avdd");
1417 	if (IS_ERR(ov13b->avdd)) {
1418 		ret = PTR_ERR(ov13b->avdd);
1419 		ov13b->avdd = NULL;
1420 		if (ret != -ENODEV)
1421 			return dev_err_probe(dev, ret,
1422 					     "failed to get avdd regulator\n");
1423 	}
1424 
1425 	return 0;
1426 }
1427 
1428 static int ov13b10_check_hwcfg(struct device *dev)
1429 {
1430 	struct v4l2_fwnode_endpoint bus_cfg = {
1431 		.bus_type = V4L2_MBUS_CSI2_DPHY
1432 	};
1433 	struct fwnode_handle *ep;
1434 	struct fwnode_handle *fwnode = dev_fwnode(dev);
1435 	unsigned int i, j;
1436 	int ret;
1437 	u32 ext_clk;
1438 
1439 	if (!fwnode)
1440 		return -ENXIO;
1441 
1442 	ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
1443 	if (!ep)
1444 		return -EPROBE_DEFER;
1445 
1446 	ret = fwnode_property_read_u32(dev_fwnode(dev), "clock-frequency",
1447 				       &ext_clk);
1448 	if (ret) {
1449 		dev_err(dev, "can't get clock frequency");
1450 		return ret;
1451 	}
1452 
1453 	if (ext_clk != OV13B10_EXT_CLK) {
1454 		dev_err(dev, "external clock %d is not supported",
1455 			ext_clk);
1456 		return -EINVAL;
1457 	}
1458 
1459 	ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
1460 	fwnode_handle_put(ep);
1461 	if (ret)
1462 		return ret;
1463 
1464 	if (bus_cfg.bus.mipi_csi2.num_data_lanes != OV13B10_DATA_LANES) {
1465 		dev_err(dev, "number of CSI2 data lanes %d is not supported",
1466 			bus_cfg.bus.mipi_csi2.num_data_lanes);
1467 		ret = -EINVAL;
1468 		goto out_err;
1469 	}
1470 
1471 	if (!bus_cfg.nr_of_link_frequencies) {
1472 		dev_err(dev, "no link frequencies defined");
1473 		ret = -EINVAL;
1474 		goto out_err;
1475 	}
1476 
1477 	for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) {
1478 		for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) {
1479 			if (link_freq_menu_items[i] ==
1480 				bus_cfg.link_frequencies[j])
1481 				break;
1482 		}
1483 
1484 		if (j == bus_cfg.nr_of_link_frequencies) {
1485 			dev_err(dev, "no link frequency %lld supported",
1486 				link_freq_menu_items[i]);
1487 			ret = -EINVAL;
1488 			goto out_err;
1489 		}
1490 	}
1491 
1492 out_err:
1493 	v4l2_fwnode_endpoint_free(&bus_cfg);
1494 
1495 	return ret;
1496 }
1497 
1498 static int ov13b10_probe(struct i2c_client *client)
1499 {
1500 	struct ov13b10 *ov13b;
1501 	bool full_power;
1502 	int ret;
1503 
1504 	/* Check HW config */
1505 	ret = ov13b10_check_hwcfg(&client->dev);
1506 	if (ret) {
1507 		dev_err(&client->dev, "failed to check hwcfg: %d", ret);
1508 		return ret;
1509 	}
1510 
1511 	ov13b = devm_kzalloc(&client->dev, sizeof(*ov13b), GFP_KERNEL);
1512 	if (!ov13b)
1513 		return -ENOMEM;
1514 
1515 	/* Initialize subdev */
1516 	v4l2_i2c_subdev_init(&ov13b->sd, client, &ov13b10_subdev_ops);
1517 
1518 	ret = ov13b10_get_pm_resources(&client->dev);
1519 	if (ret)
1520 		return ret;
1521 
1522 	full_power = acpi_dev_state_d0(&client->dev);
1523 	if (full_power) {
1524 		ret = ov13b10_power_on(&client->dev);
1525 		if (ret) {
1526 			dev_err(&client->dev, "failed to power on\n");
1527 			return ret;
1528 		}
1529 
1530 		/* Check module identity */
1531 		ret = ov13b10_identify_module(ov13b);
1532 		if (ret) {
1533 			dev_err(&client->dev, "failed to find sensor: %d\n", ret);
1534 			goto error_power_off;
1535 		}
1536 	}
1537 
1538 	/* Set default mode to max resolution */
1539 	ov13b->cur_mode = &supported_modes[0];
1540 
1541 	ret = ov13b10_init_controls(ov13b);
1542 	if (ret)
1543 		goto error_power_off;
1544 
1545 	/* Initialize subdev */
1546 	ov13b->sd.internal_ops = &ov13b10_internal_ops;
1547 	ov13b->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1548 	ov13b->sd.entity.ops = &ov13b10_subdev_entity_ops;
1549 	ov13b->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1550 
1551 	/* Initialize source pad */
1552 	ov13b->pad.flags = MEDIA_PAD_FL_SOURCE;
1553 	ret = media_entity_pads_init(&ov13b->sd.entity, 1, &ov13b->pad);
1554 	if (ret) {
1555 		dev_err(&client->dev, "%s failed:%d\n", __func__, ret);
1556 		goto error_handler_free;
1557 	}
1558 
1559 	ret = v4l2_async_register_subdev_sensor(&ov13b->sd);
1560 	if (ret < 0)
1561 		goto error_media_entity;
1562 
1563 	/*
1564 	 * Device is already turned on by i2c-core with ACPI domain PM.
1565 	 * Enable runtime PM and turn off the device.
1566 	 */
1567 
1568 	/* Set the device's state to active if it's in D0 state. */
1569 	if (full_power)
1570 		pm_runtime_set_active(&client->dev);
1571 	pm_runtime_enable(&client->dev);
1572 	pm_runtime_idle(&client->dev);
1573 
1574 	return 0;
1575 
1576 error_media_entity:
1577 	media_entity_cleanup(&ov13b->sd.entity);
1578 
1579 error_handler_free:
1580 	ov13b10_free_controls(ov13b);
1581 	dev_err(&client->dev, "%s failed:%d\n", __func__, ret);
1582 
1583 error_power_off:
1584 	ov13b10_power_off(&client->dev);
1585 
1586 	return ret;
1587 }
1588 
1589 static void ov13b10_remove(struct i2c_client *client)
1590 {
1591 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
1592 	struct ov13b10 *ov13b = to_ov13b10(sd);
1593 
1594 	v4l2_async_unregister_subdev(sd);
1595 	media_entity_cleanup(&sd->entity);
1596 	ov13b10_free_controls(ov13b);
1597 
1598 	pm_runtime_disable(&client->dev);
1599 }
1600 
1601 static DEFINE_RUNTIME_DEV_PM_OPS(ov13b10_pm_ops, ov13b10_suspend,
1602 				 ov13b10_resume, NULL);
1603 
1604 #ifdef CONFIG_ACPI
1605 static const struct acpi_device_id ov13b10_acpi_ids[] = {
1606 	{"OVTIDB10"},
1607 	{"OVTI13B1"},
1608 	{ /* sentinel */ }
1609 };
1610 
1611 MODULE_DEVICE_TABLE(acpi, ov13b10_acpi_ids);
1612 #endif
1613 
1614 static struct i2c_driver ov13b10_i2c_driver = {
1615 	.driver = {
1616 		.name = "ov13b10",
1617 		.pm = pm_ptr(&ov13b10_pm_ops),
1618 		.acpi_match_table = ACPI_PTR(ov13b10_acpi_ids),
1619 	},
1620 	.probe = ov13b10_probe,
1621 	.remove = ov13b10_remove,
1622 	.flags = I2C_DRV_ACPI_WAIVE_D0_PROBE,
1623 };
1624 
1625 module_i2c_driver(ov13b10_i2c_driver);
1626 
1627 MODULE_AUTHOR("Kao, Arec <arec.kao@intel.com>");
1628 MODULE_DESCRIPTION("Omnivision ov13b10 sensor driver");
1629 MODULE_LICENSE("GPL v2");
1630