1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2021 Intel Corporation. 3 4 #include <linux/acpi.h> 5 #include <linux/clk.h> 6 #include <linux/delay.h> 7 #include <linux/gpio/consumer.h> 8 #include <linux/i2c.h> 9 #include <linux/module.h> 10 #include <linux/pm_runtime.h> 11 #include <media/v4l2-ctrls.h> 12 #include <media/v4l2-device.h> 13 #include <media/v4l2-fwnode.h> 14 15 #define OV13B10_REG_VALUE_08BIT 1 16 #define OV13B10_REG_VALUE_16BIT 2 17 #define OV13B10_REG_VALUE_24BIT 3 18 19 #define OV13B10_REG_MODE_SELECT 0x0100 20 #define OV13B10_MODE_STANDBY 0x00 21 #define OV13B10_MODE_STREAMING 0x01 22 23 #define OV13B10_REG_SOFTWARE_RST 0x0103 24 #define OV13B10_SOFTWARE_RST 0x01 25 26 /* Chip ID */ 27 #define OV13B10_REG_CHIP_ID 0x300a 28 #define OV13B10_CHIP_ID 0x560d42 29 30 /* V_TIMING internal */ 31 #define OV13B10_REG_VTS 0x380e 32 #define OV13B10_VTS_30FPS 0x0c7c 33 #define OV13B10_VTS_60FPS 0x063e 34 #define OV13B10_VTS_120FPS 0x0320 35 #define OV13B10_VTS_MAX 0x7fff 36 37 /* Exposure control */ 38 #define OV13B10_REG_EXPOSURE 0x3500 39 #define OV13B10_EXPOSURE_MIN 4 40 #define OV13B10_EXPOSURE_STEP 1 41 #define OV13B10_EXPOSURE_DEFAULT 0x40 42 43 /* Analog gain control */ 44 #define OV13B10_REG_ANALOG_GAIN 0x3508 45 #define OV13B10_ANA_GAIN_MIN 0x80 46 #define OV13B10_ANA_GAIN_MAX 0x07c0 47 #define OV13B10_ANA_GAIN_STEP 1 48 #define OV13B10_ANA_GAIN_DEFAULT 0x80 49 50 /* Digital gain control */ 51 #define OV13B10_REG_DGTL_GAIN_H 0x350a 52 #define OV13B10_REG_DGTL_GAIN_M 0x350b 53 #define OV13B10_REG_DGTL_GAIN_L 0x350c 54 55 #define OV13B10_DGTL_GAIN_MIN 1024 /* Min = 1 X */ 56 #define OV13B10_DGTL_GAIN_MAX (4096 - 1) /* Max = 4 X */ 57 #define OV13B10_DGTL_GAIN_DEFAULT 2560 /* Default gain = 2.5 X */ 58 #define OV13B10_DGTL_GAIN_STEP 1 /* Each step = 1/1024 */ 59 60 #define OV13B10_DGTL_GAIN_L_SHIFT 6 61 #define OV13B10_DGTL_GAIN_L_MASK 0x3 62 #define OV13B10_DGTL_GAIN_M_SHIFT 2 63 #define OV13B10_DGTL_GAIN_M_MASK 0xff 64 #define OV13B10_DGTL_GAIN_H_SHIFT 10 65 #define OV13B10_DGTL_GAIN_H_MASK 0x3 66 67 /* Test Pattern Control */ 68 #define OV13B10_REG_TEST_PATTERN 0x5080 69 #define OV13B10_TEST_PATTERN_ENABLE BIT(7) 70 #define OV13B10_TEST_PATTERN_MASK 0xf3 71 #define OV13B10_TEST_PATTERN_BAR_SHIFT 2 72 73 /* Flip Control */ 74 #define OV13B10_REG_FORMAT1 0x3820 75 #define OV13B10_REG_FORMAT2 0x3821 76 77 /* Horizontal Window Offset */ 78 #define OV13B10_REG_H_WIN_OFFSET 0x3811 79 80 /* Vertical Window Offset */ 81 #define OV13B10_REG_V_WIN_OFFSET 0x3813 82 83 struct ov13b10_reg { 84 u16 address; 85 u8 val; 86 }; 87 88 struct ov13b10_reg_list { 89 u32 num_of_regs; 90 const struct ov13b10_reg *regs; 91 }; 92 93 /* Link frequency config */ 94 struct ov13b10_link_freq_config { 95 u64 link_freq; 96 97 /* registers for this link frequency */ 98 struct ov13b10_reg_list reg_list; 99 }; 100 101 /* Mode : resolution and related config&values */ 102 struct ov13b10_mode { 103 /* Frame width */ 104 u32 width; 105 /* Frame height */ 106 u32 height; 107 108 /* V-timing */ 109 u32 vts_def; 110 u32 vts_min; 111 112 /* Index of Link frequency config to be used */ 113 u32 link_freq_index; 114 115 /* Pixels per line in current mode */ 116 u32 ppl; 117 118 /* Default register values */ 119 struct ov13b10_reg_list reg_list; 120 }; 121 122 /* 4208x3120 needs 1120Mbps/lane, 4 lanes */ 123 static const struct ov13b10_reg mipi_data_rate_1120mbps[] = { 124 {0x0103, 0x01}, 125 {0x0303, 0x04}, 126 {0x0305, 0xaf}, 127 {0x0321, 0x00}, 128 {0x0323, 0x04}, 129 {0x0324, 0x01}, 130 {0x0325, 0xa4}, 131 {0x0326, 0x81}, 132 {0x0327, 0x04}, 133 {0x3012, 0x07}, 134 {0x3013, 0x32}, 135 {0x3107, 0x23}, 136 {0x3501, 0x0c}, 137 {0x3502, 0x10}, 138 {0x3504, 0x08}, 139 {0x3508, 0x07}, 140 {0x3509, 0xc0}, 141 {0x3600, 0x16}, 142 {0x3601, 0x54}, 143 {0x3612, 0x4e}, 144 {0x3620, 0x00}, 145 {0x3621, 0x68}, 146 {0x3622, 0x66}, 147 {0x3623, 0x03}, 148 {0x3662, 0x92}, 149 {0x3666, 0xbb}, 150 {0x3667, 0x44}, 151 {0x366e, 0xff}, 152 {0x366f, 0xf3}, 153 {0x3675, 0x44}, 154 {0x3676, 0x00}, 155 {0x367f, 0xe9}, 156 {0x3681, 0x32}, 157 {0x3682, 0x1f}, 158 {0x3683, 0x0b}, 159 {0x3684, 0x0b}, 160 {0x3704, 0x0f}, 161 {0x3706, 0x40}, 162 {0x3708, 0x3b}, 163 {0x3709, 0x72}, 164 {0x370b, 0xa2}, 165 {0x3714, 0x24}, 166 {0x371a, 0x3e}, 167 {0x3725, 0x42}, 168 {0x3739, 0x12}, 169 {0x3767, 0x00}, 170 {0x377a, 0x0d}, 171 {0x3789, 0x18}, 172 {0x3790, 0x40}, 173 {0x3791, 0xa2}, 174 {0x37c2, 0x04}, 175 {0x37c3, 0xf1}, 176 {0x37d9, 0x0c}, 177 {0x37da, 0x02}, 178 {0x37dc, 0x02}, 179 {0x37e1, 0x04}, 180 {0x37e2, 0x0a}, 181 {0x3800, 0x00}, 182 {0x3801, 0x00}, 183 {0x3802, 0x00}, 184 {0x3803, 0x08}, 185 {0x3804, 0x10}, 186 {0x3805, 0x8f}, 187 {0x3806, 0x0c}, 188 {0x3807, 0x47}, 189 {0x3808, 0x10}, 190 {0x3809, 0x70}, 191 {0x380a, 0x0c}, 192 {0x380b, 0x30}, 193 {0x380c, 0x04}, 194 {0x380d, 0x98}, 195 {0x380e, 0x0c}, 196 {0x380f, 0x7c}, 197 {0x3811, 0x0f}, 198 {0x3813, 0x09}, 199 {0x3814, 0x01}, 200 {0x3815, 0x01}, 201 {0x3816, 0x01}, 202 {0x3817, 0x01}, 203 {0x381f, 0x08}, 204 {0x3820, 0x88}, 205 {0x3821, 0x00}, 206 {0x3822, 0x14}, 207 {0x382e, 0xe6}, 208 {0x3c80, 0x00}, 209 {0x3c87, 0x01}, 210 {0x3c8c, 0x19}, 211 {0x3c8d, 0x1c}, 212 {0x3ca0, 0x00}, 213 {0x3ca1, 0x00}, 214 {0x3ca2, 0x00}, 215 {0x3ca3, 0x00}, 216 {0x3ca4, 0x50}, 217 {0x3ca5, 0x11}, 218 {0x3ca6, 0x01}, 219 {0x3ca7, 0x00}, 220 {0x3ca8, 0x00}, 221 {0x4008, 0x02}, 222 {0x4009, 0x0f}, 223 {0x400a, 0x01}, 224 {0x400b, 0x19}, 225 {0x4011, 0x21}, 226 {0x4017, 0x08}, 227 {0x4019, 0x04}, 228 {0x401a, 0x58}, 229 {0x4032, 0x1e}, 230 {0x4050, 0x02}, 231 {0x4051, 0x09}, 232 {0x405e, 0x00}, 233 {0x4066, 0x02}, 234 {0x4501, 0x00}, 235 {0x4502, 0x10}, 236 {0x4505, 0x00}, 237 {0x4800, 0x64}, 238 {0x481b, 0x3e}, 239 {0x481f, 0x30}, 240 {0x4825, 0x34}, 241 {0x4837, 0x0e}, 242 {0x484b, 0x01}, 243 {0x4883, 0x02}, 244 {0x5000, 0xff}, 245 {0x5001, 0x0f}, 246 {0x5045, 0x20}, 247 {0x5046, 0x20}, 248 {0x5047, 0xa4}, 249 {0x5048, 0x20}, 250 {0x5049, 0xa4}, 251 }; 252 253 static const struct ov13b10_reg mode_4208x3120_regs[] = { 254 {0x0305, 0xaf}, 255 {0x3501, 0x0c}, 256 {0x3662, 0x92}, 257 {0x3714, 0x24}, 258 {0x3739, 0x12}, 259 {0x37c2, 0x04}, 260 {0x37d9, 0x0c}, 261 {0x37e2, 0x0a}, 262 {0x3800, 0x00}, 263 {0x3801, 0x00}, 264 {0x3802, 0x00}, 265 {0x3803, 0x08}, 266 {0x3804, 0x10}, 267 {0x3805, 0x8f}, 268 {0x3806, 0x0c}, 269 {0x3807, 0x47}, 270 {0x3808, 0x10}, 271 {0x3809, 0x70}, 272 {0x380a, 0x0c}, 273 {0x380b, 0x30}, 274 {0x380c, 0x04}, 275 {0x380d, 0x98}, 276 {0x380e, 0x0c}, 277 {0x380f, 0x7c}, 278 {0x3810, 0x00}, 279 {0x3811, 0x0f}, 280 {0x3812, 0x00}, 281 {0x3813, 0x09}, 282 {0x3814, 0x01}, 283 {0x3816, 0x01}, 284 {0x3820, 0x88}, 285 {0x3c8c, 0x19}, 286 {0x4008, 0x02}, 287 {0x4009, 0x0f}, 288 {0x4050, 0x02}, 289 {0x4051, 0x09}, 290 {0x4501, 0x00}, 291 {0x4505, 0x00}, 292 {0x4837, 0x0e}, 293 {0x5000, 0xff}, 294 {0x5001, 0x0f}, 295 }; 296 297 static const struct ov13b10_reg mode_4160x3120_regs[] = { 298 {0x0305, 0xaf}, 299 {0x3501, 0x0c}, 300 {0x3662, 0x92}, 301 {0x3714, 0x24}, 302 {0x3739, 0x12}, 303 {0x37c2, 0x04}, 304 {0x37d9, 0x0c}, 305 {0x37e2, 0x0a}, 306 {0x3800, 0x00}, 307 {0x3801, 0x00}, 308 {0x3802, 0x00}, 309 {0x3803, 0x08}, 310 {0x3804, 0x10}, 311 {0x3805, 0x8f}, 312 {0x3806, 0x0c}, 313 {0x3807, 0x47}, 314 {0x3808, 0x10}, 315 {0x3809, 0x40}, 316 {0x380a, 0x0c}, 317 {0x380b, 0x30}, 318 {0x380c, 0x04}, 319 {0x380d, 0x98}, 320 {0x380e, 0x0c}, 321 {0x380f, 0x7c}, 322 {0x3810, 0x00}, 323 {0x3811, 0x27}, 324 {0x3812, 0x00}, 325 {0x3813, 0x09}, 326 {0x3814, 0x01}, 327 {0x3816, 0x01}, 328 {0x3820, 0x88}, 329 {0x3c8c, 0x19}, 330 {0x4008, 0x02}, 331 {0x4009, 0x0f}, 332 {0x4050, 0x02}, 333 {0x4051, 0x09}, 334 {0x4501, 0x00}, 335 {0x4505, 0x00}, 336 {0x4837, 0x0e}, 337 {0x5000, 0xff}, 338 {0x5001, 0x0f}, 339 }; 340 341 static const struct ov13b10_reg mode_4160x2340_regs[] = { 342 {0x0305, 0xaf}, 343 {0x3501, 0x0c}, 344 {0x3662, 0x92}, 345 {0x3714, 0x24}, 346 {0x3739, 0x12}, 347 {0x37c2, 0x04}, 348 {0x37d9, 0x0c}, 349 {0x37e2, 0x0a}, 350 {0x3800, 0x00}, 351 {0x3801, 0x00}, 352 {0x3802, 0x00}, 353 {0x3803, 0x08}, 354 {0x3804, 0x10}, 355 {0x3805, 0x8f}, 356 {0x3806, 0x0c}, 357 {0x3807, 0x47}, 358 {0x3808, 0x10}, 359 {0x3809, 0x40}, 360 {0x380a, 0x09}, 361 {0x380b, 0x24}, 362 {0x380c, 0x04}, 363 {0x380d, 0x98}, 364 {0x380e, 0x0c}, 365 {0x380f, 0x7c}, 366 {0x3810, 0x00}, 367 {0x3811, 0x27}, 368 {0x3812, 0x01}, 369 {0x3813, 0x8f}, 370 {0x3814, 0x01}, 371 {0x3816, 0x01}, 372 {0x3820, 0x88}, 373 {0x3c8c, 0x19}, 374 {0x4008, 0x02}, 375 {0x4009, 0x0f}, 376 {0x4050, 0x02}, 377 {0x4051, 0x09}, 378 {0x4501, 0x00}, 379 {0x4505, 0x00}, 380 {0x4837, 0x0e}, 381 {0x5000, 0xff}, 382 {0x5001, 0x0f}, 383 }; 384 385 static const struct ov13b10_reg mode_2104x1560_regs[] = { 386 {0x0305, 0xaf}, 387 {0x3501, 0x06}, 388 {0x3662, 0x88}, 389 {0x3714, 0x28}, 390 {0x3739, 0x10}, 391 {0x37c2, 0x14}, 392 {0x37d9, 0x06}, 393 {0x37e2, 0x0c}, 394 {0x3800, 0x00}, 395 {0x3801, 0x00}, 396 {0x3802, 0x00}, 397 {0x3803, 0x08}, 398 {0x3804, 0x10}, 399 {0x3805, 0x8f}, 400 {0x3806, 0x0c}, 401 {0x3807, 0x47}, 402 {0x3808, 0x08}, 403 {0x3809, 0x38}, 404 {0x380a, 0x06}, 405 {0x380b, 0x18}, 406 {0x380c, 0x04}, 407 {0x380d, 0x98}, 408 {0x380e, 0x06}, 409 {0x380f, 0x3e}, 410 {0x3810, 0x00}, 411 {0x3811, 0x07}, 412 {0x3812, 0x00}, 413 {0x3813, 0x05}, 414 {0x3814, 0x03}, 415 {0x3816, 0x03}, 416 {0x3820, 0x8b}, 417 {0x3c8c, 0x18}, 418 {0x4008, 0x00}, 419 {0x4009, 0x05}, 420 {0x4050, 0x00}, 421 {0x4051, 0x05}, 422 {0x4501, 0x08}, 423 {0x4505, 0x00}, 424 {0x4837, 0x0e}, 425 {0x5000, 0xfd}, 426 {0x5001, 0x0d}, 427 }; 428 429 static const struct ov13b10_reg mode_2080x1170_regs[] = { 430 {0x0305, 0xaf}, 431 {0x3501, 0x06}, 432 {0x3662, 0x88}, 433 {0x3714, 0x28}, 434 {0x3739, 0x10}, 435 {0x37c2, 0x14}, 436 {0x37d9, 0x06}, 437 {0x37e2, 0x0c}, 438 {0x3800, 0x00}, 439 {0x3801, 0x00}, 440 {0x3802, 0x00}, 441 {0x3803, 0x08}, 442 {0x3804, 0x10}, 443 {0x3805, 0x8f}, 444 {0x3806, 0x0c}, 445 {0x3807, 0x47}, 446 {0x3808, 0x08}, 447 {0x3809, 0x20}, 448 {0x380a, 0x04}, 449 {0x380b, 0x92}, 450 {0x380c, 0x04}, 451 {0x380d, 0x98}, 452 {0x380e, 0x06}, 453 {0x380f, 0x3e}, 454 {0x3810, 0x00}, 455 {0x3811, 0x13}, 456 {0x3812, 0x00}, 457 {0x3813, 0xc9}, 458 {0x3814, 0x03}, 459 {0x3816, 0x03}, 460 {0x3820, 0x8b}, 461 {0x3c8c, 0x18}, 462 {0x4008, 0x00}, 463 {0x4009, 0x05}, 464 {0x4050, 0x00}, 465 {0x4051, 0x05}, 466 {0x4501, 0x08}, 467 {0x4505, 0x00}, 468 {0x4837, 0x0e}, 469 {0x5000, 0xfd}, 470 {0x5001, 0x0d}, 471 }; 472 473 static const struct ov13b10_reg mode_1364x768_120fps_regs[] = { 474 {0x0305, 0xaf}, 475 {0x3011, 0x7c}, 476 {0x3501, 0x03}, 477 {0x3502, 0x00}, 478 {0x3662, 0x88}, 479 {0x3714, 0x28}, 480 {0x3739, 0x10}, 481 {0x37c2, 0x14}, 482 {0x37d9, 0x06}, 483 {0x37e2, 0x0c}, 484 {0x37e4, 0x00}, 485 {0x3800, 0x02}, 486 {0x3801, 0xe4}, 487 {0x3802, 0x03}, 488 {0x3803, 0x48}, 489 {0x3804, 0x0d}, 490 {0x3805, 0xab}, 491 {0x3806, 0x09}, 492 {0x3807, 0x60}, 493 {0x3808, 0x05}, 494 {0x3809, 0x54}, 495 {0x380a, 0x03}, 496 {0x380b, 0x00}, 497 {0x380c, 0x04}, 498 {0x380d, 0x8e}, 499 {0x380e, 0x03}, 500 {0x380f, 0x20}, 501 {0x3811, 0x07}, 502 {0x3813, 0x07}, 503 {0x3814, 0x03}, 504 {0x3816, 0x03}, 505 {0x3820, 0x8b}, 506 {0x3c8c, 0x18}, 507 {0x4008, 0x00}, 508 {0x4009, 0x05}, 509 {0x4050, 0x00}, 510 {0x4051, 0x05}, 511 {0x4501, 0x08}, 512 {0x4505, 0x04}, 513 {0x5000, 0xfd}, 514 {0x5001, 0x0d}, 515 }; 516 517 static const struct ov13b10_reg mode_2lanes_2104x1560_60fps_regs[] = { 518 {0x3016, 0x32}, 519 {0x3106, 0x29}, 520 {0x0305, 0xaf}, 521 {0x3501, 0x06}, 522 {0x3662, 0x88}, 523 {0x3714, 0x28}, 524 {0x3739, 0x10}, 525 {0x37c2, 0x14}, 526 {0x37d9, 0x06}, 527 {0x37e2, 0x0c}, 528 {0x3800, 0x00}, 529 {0x3801, 0x00}, 530 {0x3802, 0x00}, 531 {0x3803, 0x08}, 532 {0x3804, 0x10}, 533 {0x3805, 0x8f}, 534 {0x3806, 0x0c}, 535 {0x3807, 0x47}, 536 {0x3808, 0x08}, 537 {0x3809, 0x38}, 538 {0x380a, 0x06}, 539 {0x380b, 0x18}, 540 {0x380c, 0x04}, 541 {0x380d, 0x98}, 542 {0x380e, 0x06}, 543 {0x380f, 0x3e}, 544 {0x3810, 0x00}, 545 {0x3811, 0x07}, 546 {0x3812, 0x00}, 547 {0x3813, 0x05}, 548 {0x3814, 0x03}, 549 {0x3816, 0x03}, 550 {0x3820, 0x8b}, 551 {0x3c8c, 0x18}, 552 {0x4008, 0x00}, 553 {0x4009, 0x05}, 554 {0x4050, 0x00}, 555 {0x4051, 0x05}, 556 {0x4501, 0x08}, 557 {0x4505, 0x00}, 558 {0x4837, 0x0e}, 559 {0x5000, 0xfd}, 560 {0x5001, 0x0d}, 561 }; 562 563 static const char * const ov13b10_test_pattern_menu[] = { 564 "Disabled", 565 "Vertical Color Bar Type 1", 566 "Vertical Color Bar Type 2", 567 "Vertical Color Bar Type 3", 568 "Vertical Color Bar Type 4" 569 }; 570 571 /* Configurations for supported link frequencies */ 572 #define OV13B10_LINK_FREQ_560MHZ 560000000ULL 573 #define OV13B10_LINK_FREQ_INDEX_0 0 574 575 #define OV13B10_EXT_CLK 19200000 576 #define OV13B10_4_DATA_LANES 4 577 #define OV13B10_2_DATA_LANES 2 578 579 /* 580 * pixel_rate = data_rate * nr_of_lanes / bits_per_pixel 581 * data_rate => link_freq * 2; number of lanes => 4 or 2; bits per pixel => 10 582 */ 583 static u64 link_freq_to_pixel_rate(u64 f, u8 lanes) 584 { 585 f *= 2 * lanes; 586 do_div(f, 10); 587 588 return f; 589 } 590 591 /* Menu items for LINK_FREQ V4L2 control */ 592 static const s64 link_freq_menu_items[] = { 593 OV13B10_LINK_FREQ_560MHZ 594 }; 595 596 /* Link frequency configs */ 597 static const struct ov13b10_link_freq_config 598 link_freq_configs[] = { 599 { 600 .link_freq = OV13B10_LINK_FREQ_560MHZ, 601 .reg_list = { 602 .num_of_regs = ARRAY_SIZE(mipi_data_rate_1120mbps), 603 .regs = mipi_data_rate_1120mbps, 604 } 605 } 606 }; 607 608 /* Mode configs */ 609 static const struct ov13b10_mode supported_4_lanes_modes[] = { 610 /* 4 data lanes */ 611 { 612 .width = 4208, 613 .height = 3120, 614 .vts_def = OV13B10_VTS_30FPS, 615 .vts_min = OV13B10_VTS_30FPS, 616 .ppl = 4704, 617 .reg_list = { 618 .num_of_regs = ARRAY_SIZE(mode_4208x3120_regs), 619 .regs = mode_4208x3120_regs, 620 }, 621 .link_freq_index = OV13B10_LINK_FREQ_INDEX_0, 622 }, 623 { 624 .width = 4160, 625 .height = 3120, 626 .vts_def = OV13B10_VTS_30FPS, 627 .vts_min = OV13B10_VTS_30FPS, 628 .ppl = 4704, 629 .reg_list = { 630 .num_of_regs = ARRAY_SIZE(mode_4160x3120_regs), 631 .regs = mode_4160x3120_regs, 632 }, 633 .link_freq_index = OV13B10_LINK_FREQ_INDEX_0, 634 }, 635 { 636 .width = 4160, 637 .height = 2340, 638 .vts_def = OV13B10_VTS_30FPS, 639 .vts_min = OV13B10_VTS_30FPS, 640 .ppl = 4704, 641 .reg_list = { 642 .num_of_regs = ARRAY_SIZE(mode_4160x2340_regs), 643 .regs = mode_4160x2340_regs, 644 }, 645 .link_freq_index = OV13B10_LINK_FREQ_INDEX_0, 646 }, 647 { 648 .width = 2104, 649 .height = 1560, 650 .vts_def = OV13B10_VTS_60FPS, 651 .vts_min = OV13B10_VTS_60FPS, 652 .ppl = 4704, 653 .reg_list = { 654 .num_of_regs = ARRAY_SIZE(mode_2104x1560_regs), 655 .regs = mode_2104x1560_regs, 656 }, 657 .link_freq_index = OV13B10_LINK_FREQ_INDEX_0, 658 }, 659 { 660 .width = 2080, 661 .height = 1170, 662 .vts_def = OV13B10_VTS_60FPS, 663 .vts_min = OV13B10_VTS_60FPS, 664 .ppl = 4704, 665 .reg_list = { 666 .num_of_regs = ARRAY_SIZE(mode_2080x1170_regs), 667 .regs = mode_2080x1170_regs, 668 }, 669 .link_freq_index = OV13B10_LINK_FREQ_INDEX_0, 670 }, 671 { 672 .width = 1364, 673 .height = 768, 674 .vts_def = OV13B10_VTS_120FPS, 675 .vts_min = OV13B10_VTS_120FPS, 676 .link_freq_index = OV13B10_LINK_FREQ_INDEX_0, 677 .ppl = 4664, 678 .reg_list = { 679 .num_of_regs = ARRAY_SIZE(mode_1364x768_120fps_regs), 680 .regs = mode_1364x768_120fps_regs, 681 }, 682 }, 683 }; 684 685 static const struct ov13b10_mode supported_2_lanes_modes[] = { 686 /* 2 data lanes */ 687 { 688 .width = 2104, 689 .height = 1560, 690 .vts_def = OV13B10_VTS_60FPS, 691 .vts_min = OV13B10_VTS_60FPS, 692 .link_freq_index = OV13B10_LINK_FREQ_INDEX_0, 693 .ppl = 2352, 694 .reg_list = { 695 .num_of_regs = 696 ARRAY_SIZE(mode_2lanes_2104x1560_60fps_regs), 697 .regs = mode_2lanes_2104x1560_60fps_regs, 698 }, 699 }, 700 }; 701 702 struct ov13b10 { 703 struct device *dev; 704 705 struct v4l2_subdev sd; 706 struct media_pad pad; 707 708 struct v4l2_ctrl_handler ctrl_handler; 709 710 struct clk *img_clk; 711 struct regulator *avdd; 712 struct gpio_desc *reset; 713 714 /* V4L2 Controls */ 715 struct v4l2_ctrl *link_freq; 716 struct v4l2_ctrl *pixel_rate; 717 struct v4l2_ctrl *vblank; 718 struct v4l2_ctrl *hblank; 719 struct v4l2_ctrl *exposure; 720 721 /* Supported modes */ 722 const struct ov13b10_mode *supported_modes; 723 724 /* Current mode */ 725 const struct ov13b10_mode *cur_mode; 726 727 /* Mutex for serialized access */ 728 struct mutex mutex; 729 730 u8 supported_modes_num; 731 732 /* Data lanes used */ 733 u8 data_lanes; 734 735 /* True if the device has been identified */ 736 bool identified; 737 }; 738 739 #define to_ov13b10(_sd) container_of(_sd, struct ov13b10, sd) 740 741 /* Read registers up to 4 at a time */ 742 static int ov13b10_read_reg(struct ov13b10 *ov13b, 743 u16 reg, u32 len, u32 *val) 744 { 745 struct i2c_client *client = v4l2_get_subdevdata(&ov13b->sd); 746 struct i2c_msg msgs[2]; 747 u8 *data_be_p; 748 int ret; 749 __be32 data_be = 0; 750 __be16 reg_addr_be = cpu_to_be16(reg); 751 752 if (len > 4) 753 return -EINVAL; 754 755 data_be_p = (u8 *)&data_be; 756 /* Write register address */ 757 msgs[0].addr = client->addr; 758 msgs[0].flags = 0; 759 msgs[0].len = 2; 760 msgs[0].buf = (u8 *)®_addr_be; 761 762 /* Read data from register */ 763 msgs[1].addr = client->addr; 764 msgs[1].flags = I2C_M_RD; 765 msgs[1].len = len; 766 msgs[1].buf = &data_be_p[4 - len]; 767 768 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); 769 if (ret != ARRAY_SIZE(msgs)) 770 return -EIO; 771 772 *val = be32_to_cpu(data_be); 773 774 return 0; 775 } 776 777 /* Write registers up to 4 at a time */ 778 static int ov13b10_write_reg(struct ov13b10 *ov13b, 779 u16 reg, u32 len, u32 __val) 780 { 781 struct i2c_client *client = v4l2_get_subdevdata(&ov13b->sd); 782 int buf_i, val_i; 783 u8 buf[6], *val_p; 784 __be32 val; 785 786 if (len > 4) 787 return -EINVAL; 788 789 buf[0] = reg >> 8; 790 buf[1] = reg & 0xff; 791 792 val = cpu_to_be32(__val); 793 val_p = (u8 *)&val; 794 buf_i = 2; 795 val_i = 4 - len; 796 797 while (val_i < 4) 798 buf[buf_i++] = val_p[val_i++]; 799 800 if (i2c_master_send(client, buf, len + 2) != len + 2) 801 return -EIO; 802 803 return 0; 804 } 805 806 /* Write a list of registers */ 807 static int ov13b10_write_regs(struct ov13b10 *ov13b, 808 const struct ov13b10_reg *regs, u32 len) 809 { 810 int ret; 811 u32 i; 812 813 for (i = 0; i < len; i++) { 814 ret = ov13b10_write_reg(ov13b, regs[i].address, 1, 815 regs[i].val); 816 if (ret) { 817 dev_err_ratelimited(ov13b->dev, 818 "Failed to write reg 0x%4.4x. error = %d\n", 819 regs[i].address, ret); 820 821 return ret; 822 } 823 } 824 825 return 0; 826 } 827 828 static int ov13b10_write_reg_list(struct ov13b10 *ov13b, 829 const struct ov13b10_reg_list *r_list) 830 { 831 return ov13b10_write_regs(ov13b, r_list->regs, r_list->num_of_regs); 832 } 833 834 /* Open sub-device */ 835 static int ov13b10_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) 836 { 837 struct ov13b10 *ov13b = to_ov13b10(sd); 838 const struct ov13b10_mode *default_mode = ov13b->supported_modes; 839 struct v4l2_mbus_framefmt *try_fmt = v4l2_subdev_state_get_format(fh->state, 840 0); 841 842 mutex_lock(&ov13b->mutex); 843 844 /* Initialize try_fmt */ 845 try_fmt->width = default_mode->width; 846 try_fmt->height = default_mode->height; 847 try_fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10; 848 try_fmt->field = V4L2_FIELD_NONE; 849 850 /* No crop or compose */ 851 mutex_unlock(&ov13b->mutex); 852 853 return 0; 854 } 855 856 static int ov13b10_update_digital_gain(struct ov13b10 *ov13b, u32 d_gain) 857 { 858 int ret; 859 u32 val; 860 861 /* 862 * 0x350C[7:6], 0x350B[7:0], 0x350A[1:0] 863 */ 864 865 val = (d_gain & OV13B10_DGTL_GAIN_L_MASK) << OV13B10_DGTL_GAIN_L_SHIFT; 866 ret = ov13b10_write_reg(ov13b, OV13B10_REG_DGTL_GAIN_L, 867 OV13B10_REG_VALUE_08BIT, val); 868 if (ret) 869 return ret; 870 871 val = (d_gain >> OV13B10_DGTL_GAIN_M_SHIFT) & OV13B10_DGTL_GAIN_M_MASK; 872 ret = ov13b10_write_reg(ov13b, OV13B10_REG_DGTL_GAIN_M, 873 OV13B10_REG_VALUE_08BIT, val); 874 if (ret) 875 return ret; 876 877 val = (d_gain >> OV13B10_DGTL_GAIN_H_SHIFT) & OV13B10_DGTL_GAIN_H_MASK; 878 ret = ov13b10_write_reg(ov13b, OV13B10_REG_DGTL_GAIN_H, 879 OV13B10_REG_VALUE_08BIT, val); 880 881 return ret; 882 } 883 884 static int ov13b10_enable_test_pattern(struct ov13b10 *ov13b, u32 pattern) 885 { 886 int ret; 887 u32 val; 888 889 ret = ov13b10_read_reg(ov13b, OV13B10_REG_TEST_PATTERN, 890 OV13B10_REG_VALUE_08BIT, &val); 891 if (ret) 892 return ret; 893 894 if (pattern) { 895 val &= OV13B10_TEST_PATTERN_MASK; 896 val |= ((pattern - 1) << OV13B10_TEST_PATTERN_BAR_SHIFT) | 897 OV13B10_TEST_PATTERN_ENABLE; 898 } else { 899 val &= ~OV13B10_TEST_PATTERN_ENABLE; 900 } 901 902 return ov13b10_write_reg(ov13b, OV13B10_REG_TEST_PATTERN, 903 OV13B10_REG_VALUE_08BIT, val); 904 } 905 906 static int ov13b10_set_ctrl_hflip(struct ov13b10 *ov13b, u32 ctrl_val) 907 { 908 int ret; 909 u32 val; 910 911 ret = ov13b10_read_reg(ov13b, OV13B10_REG_FORMAT1, 912 OV13B10_REG_VALUE_08BIT, &val); 913 if (ret) 914 return ret; 915 916 ret = ov13b10_write_reg(ov13b, OV13B10_REG_FORMAT1, 917 OV13B10_REG_VALUE_08BIT, 918 ctrl_val ? val & ~BIT(3) : val); 919 920 if (ret) 921 return ret; 922 923 ret = ov13b10_read_reg(ov13b, OV13B10_REG_H_WIN_OFFSET, 924 OV13B10_REG_VALUE_08BIT, &val); 925 if (ret) 926 return ret; 927 928 /* 929 * Applying cropping offset to reverse the change of Bayer order 930 * after mirroring image 931 */ 932 return ov13b10_write_reg(ov13b, OV13B10_REG_H_WIN_OFFSET, 933 OV13B10_REG_VALUE_08BIT, 934 ctrl_val ? ++val : val); 935 } 936 937 static int ov13b10_set_ctrl_vflip(struct ov13b10 *ov13b, u32 ctrl_val) 938 { 939 int ret; 940 u32 val; 941 942 ret = ov13b10_read_reg(ov13b, OV13B10_REG_FORMAT1, 943 OV13B10_REG_VALUE_08BIT, &val); 944 if (ret) 945 return ret; 946 947 ret = ov13b10_write_reg(ov13b, OV13B10_REG_FORMAT1, 948 OV13B10_REG_VALUE_08BIT, 949 ctrl_val ? val | BIT(4) | BIT(5) : val); 950 951 if (ret) 952 return ret; 953 954 ret = ov13b10_read_reg(ov13b, OV13B10_REG_V_WIN_OFFSET, 955 OV13B10_REG_VALUE_08BIT, &val); 956 if (ret) 957 return ret; 958 959 /* 960 * Applying cropping offset to reverse the change of Bayer order 961 * after flipping image 962 */ 963 return ov13b10_write_reg(ov13b, OV13B10_REG_V_WIN_OFFSET, 964 OV13B10_REG_VALUE_08BIT, 965 ctrl_val ? --val : val); 966 } 967 968 static int ov13b10_set_ctrl(struct v4l2_ctrl *ctrl) 969 { 970 struct ov13b10 *ov13b = container_of(ctrl->handler, 971 struct ov13b10, ctrl_handler); 972 s64 max; 973 int ret; 974 975 /* Propagate change of current control to all related controls */ 976 switch (ctrl->id) { 977 case V4L2_CID_VBLANK: 978 /* Update max exposure while meeting expected vblanking */ 979 max = ov13b->cur_mode->height + ctrl->val - 8; 980 __v4l2_ctrl_modify_range(ov13b->exposure, 981 ov13b->exposure->minimum, 982 max, ov13b->exposure->step, max); 983 break; 984 } 985 986 /* 987 * Applying V4L2 control value only happens 988 * when power is up for streaming 989 */ 990 if (!pm_runtime_get_if_in_use(ov13b->dev)) 991 return 0; 992 993 ret = 0; 994 switch (ctrl->id) { 995 case V4L2_CID_ANALOGUE_GAIN: 996 ret = ov13b10_write_reg(ov13b, OV13B10_REG_ANALOG_GAIN, 997 OV13B10_REG_VALUE_16BIT, 998 ctrl->val << 1); 999 break; 1000 case V4L2_CID_DIGITAL_GAIN: 1001 ret = ov13b10_update_digital_gain(ov13b, ctrl->val); 1002 break; 1003 case V4L2_CID_EXPOSURE: 1004 ret = ov13b10_write_reg(ov13b, OV13B10_REG_EXPOSURE, 1005 OV13B10_REG_VALUE_24BIT, 1006 ctrl->val); 1007 break; 1008 case V4L2_CID_VBLANK: 1009 ret = ov13b10_write_reg(ov13b, OV13B10_REG_VTS, 1010 OV13B10_REG_VALUE_16BIT, 1011 ov13b->cur_mode->height 1012 + ctrl->val); 1013 break; 1014 case V4L2_CID_TEST_PATTERN: 1015 ret = ov13b10_enable_test_pattern(ov13b, ctrl->val); 1016 break; 1017 case V4L2_CID_HFLIP: 1018 ov13b10_set_ctrl_hflip(ov13b, ctrl->val); 1019 break; 1020 case V4L2_CID_VFLIP: 1021 ov13b10_set_ctrl_vflip(ov13b, ctrl->val); 1022 break; 1023 default: 1024 dev_info(ov13b->dev, 1025 "ctrl(id:0x%x,val:0x%x) is not handled\n", 1026 ctrl->id, ctrl->val); 1027 break; 1028 } 1029 1030 pm_runtime_put(ov13b->dev); 1031 1032 return ret; 1033 } 1034 1035 static const struct v4l2_ctrl_ops ov13b10_ctrl_ops = { 1036 .s_ctrl = ov13b10_set_ctrl, 1037 }; 1038 1039 static int ov13b10_enum_mbus_code(struct v4l2_subdev *sd, 1040 struct v4l2_subdev_state *sd_state, 1041 struct v4l2_subdev_mbus_code_enum *code) 1042 { 1043 /* Only one bayer order(GRBG) is supported */ 1044 if (code->index > 0) 1045 return -EINVAL; 1046 1047 code->code = MEDIA_BUS_FMT_SGRBG10_1X10; 1048 1049 return 0; 1050 } 1051 1052 static int ov13b10_enum_frame_size(struct v4l2_subdev *sd, 1053 struct v4l2_subdev_state *sd_state, 1054 struct v4l2_subdev_frame_size_enum *fse) 1055 { 1056 struct ov13b10 *ov13b = to_ov13b10(sd); 1057 const struct ov13b10_mode *supported_modes = ov13b->supported_modes; 1058 1059 if (fse->index >= ov13b->supported_modes_num) 1060 return -EINVAL; 1061 1062 if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10) 1063 return -EINVAL; 1064 1065 fse->min_width = supported_modes[fse->index].width; 1066 fse->max_width = fse->min_width; 1067 fse->min_height = supported_modes[fse->index].height; 1068 fse->max_height = fse->min_height; 1069 1070 return 0; 1071 } 1072 1073 static void ov13b10_update_pad_format(const struct ov13b10_mode *mode, 1074 struct v4l2_subdev_format *fmt) 1075 { 1076 fmt->format.width = mode->width; 1077 fmt->format.height = mode->height; 1078 fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10; 1079 fmt->format.field = V4L2_FIELD_NONE; 1080 } 1081 1082 static int ov13b10_do_get_pad_format(struct ov13b10 *ov13b, 1083 struct v4l2_subdev_state *sd_state, 1084 struct v4l2_subdev_format *fmt) 1085 { 1086 struct v4l2_mbus_framefmt *framefmt; 1087 1088 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { 1089 framefmt = v4l2_subdev_state_get_format(sd_state, fmt->pad); 1090 fmt->format = *framefmt; 1091 } else { 1092 ov13b10_update_pad_format(ov13b->cur_mode, fmt); 1093 } 1094 1095 return 0; 1096 } 1097 1098 static int ov13b10_get_pad_format(struct v4l2_subdev *sd, 1099 struct v4l2_subdev_state *sd_state, 1100 struct v4l2_subdev_format *fmt) 1101 { 1102 struct ov13b10 *ov13b = to_ov13b10(sd); 1103 int ret; 1104 1105 mutex_lock(&ov13b->mutex); 1106 ret = ov13b10_do_get_pad_format(ov13b, sd_state, fmt); 1107 mutex_unlock(&ov13b->mutex); 1108 1109 return ret; 1110 } 1111 1112 static int 1113 ov13b10_set_pad_format(struct v4l2_subdev *sd, 1114 struct v4l2_subdev_state *sd_state, 1115 struct v4l2_subdev_format *fmt) 1116 { 1117 struct ov13b10 *ov13b = to_ov13b10(sd); 1118 const struct ov13b10_mode *mode; 1119 const struct ov13b10_mode *supported_modes = ov13b->supported_modes; 1120 struct v4l2_mbus_framefmt *framefmt; 1121 s32 vblank_def; 1122 s32 vblank_min; 1123 s64 h_blank; 1124 s64 pixel_rate; 1125 s64 link_freq; 1126 1127 mutex_lock(&ov13b->mutex); 1128 1129 /* Only one raw bayer(GRBG) order is supported */ 1130 if (fmt->format.code != MEDIA_BUS_FMT_SGRBG10_1X10) 1131 fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10; 1132 1133 mode = v4l2_find_nearest_size(supported_modes, 1134 ov13b->supported_modes_num, 1135 width, height, 1136 fmt->format.width, fmt->format.height); 1137 ov13b10_update_pad_format(mode, fmt); 1138 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { 1139 framefmt = v4l2_subdev_state_get_format(sd_state, fmt->pad); 1140 *framefmt = fmt->format; 1141 } else { 1142 ov13b->cur_mode = mode; 1143 __v4l2_ctrl_s_ctrl(ov13b->link_freq, mode->link_freq_index); 1144 link_freq = link_freq_menu_items[mode->link_freq_index]; 1145 pixel_rate = link_freq_to_pixel_rate(link_freq, 1146 ov13b->data_lanes); 1147 __v4l2_ctrl_s_ctrl_int64(ov13b->pixel_rate, pixel_rate); 1148 1149 /* Update limits and set FPS to default */ 1150 vblank_def = mode->vts_def - mode->height; 1151 vblank_min = mode->vts_min - mode->height; 1152 __v4l2_ctrl_modify_range(ov13b->vblank, vblank_min, 1153 OV13B10_VTS_MAX - mode->height, 1154 1, vblank_def); 1155 __v4l2_ctrl_s_ctrl(ov13b->vblank, vblank_def); 1156 h_blank = mode->ppl - mode->width; 1157 __v4l2_ctrl_modify_range(ov13b->hblank, h_blank, 1158 h_blank, 1, h_blank); 1159 } 1160 1161 mutex_unlock(&ov13b->mutex); 1162 1163 return 0; 1164 } 1165 1166 /* Verify chip ID */ 1167 static int ov13b10_identify_module(struct ov13b10 *ov13b) 1168 { 1169 int ret; 1170 u32 val; 1171 1172 if (ov13b->identified) 1173 return 0; 1174 1175 ret = ov13b10_read_reg(ov13b, OV13B10_REG_CHIP_ID, 1176 OV13B10_REG_VALUE_24BIT, &val); 1177 if (ret) 1178 return ret; 1179 1180 if (val != OV13B10_CHIP_ID) { 1181 dev_err(ov13b->dev, "chip id mismatch: %x!=%x\n", 1182 OV13B10_CHIP_ID, val); 1183 return -EIO; 1184 } 1185 1186 ov13b->identified = true; 1187 1188 return 0; 1189 } 1190 1191 static int ov13b10_power_off(struct device *dev) 1192 { 1193 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1194 struct ov13b10 *ov13b10 = to_ov13b10(sd); 1195 1196 gpiod_set_value_cansleep(ov13b10->reset, 1); 1197 1198 if (ov13b10->avdd) 1199 regulator_disable(ov13b10->avdd); 1200 1201 clk_disable_unprepare(ov13b10->img_clk); 1202 1203 return 0; 1204 } 1205 1206 static int ov13b10_power_on(struct device *dev) 1207 { 1208 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1209 struct ov13b10 *ov13b10 = to_ov13b10(sd); 1210 int ret; 1211 1212 ret = clk_prepare_enable(ov13b10->img_clk); 1213 if (ret < 0) { 1214 dev_err(dev, "failed to enable imaging clock: %d", ret); 1215 return ret; 1216 } 1217 1218 if (ov13b10->avdd) { 1219 ret = regulator_enable(ov13b10->avdd); 1220 if (ret < 0) { 1221 dev_err(dev, "failed to enable avdd: %d", ret); 1222 clk_disable_unprepare(ov13b10->img_clk); 1223 return ret; 1224 } 1225 } 1226 1227 gpiod_set_value_cansleep(ov13b10->reset, 0); 1228 /* 5ms to wait ready after XSHUTDN assert */ 1229 usleep_range(5000, 5500); 1230 1231 return 0; 1232 } 1233 1234 static int ov13b10_start_streaming(struct ov13b10 *ov13b) 1235 { 1236 const struct ov13b10_reg_list *reg_list; 1237 int ret, link_freq_index; 1238 1239 ret = ov13b10_identify_module(ov13b); 1240 if (ret) 1241 return ret; 1242 1243 /* Get out of from software reset */ 1244 ret = ov13b10_write_reg(ov13b, OV13B10_REG_SOFTWARE_RST, 1245 OV13B10_REG_VALUE_08BIT, OV13B10_SOFTWARE_RST); 1246 if (ret) { 1247 dev_err(ov13b->dev, "%s failed to set powerup registers\n", 1248 __func__); 1249 return ret; 1250 } 1251 1252 link_freq_index = ov13b->cur_mode->link_freq_index; 1253 reg_list = &link_freq_configs[link_freq_index].reg_list; 1254 ret = ov13b10_write_reg_list(ov13b, reg_list); 1255 if (ret) { 1256 dev_err(ov13b->dev, "%s failed to set plls\n", __func__); 1257 return ret; 1258 } 1259 1260 /* Apply default values of current mode */ 1261 reg_list = &ov13b->cur_mode->reg_list; 1262 ret = ov13b10_write_reg_list(ov13b, reg_list); 1263 if (ret) { 1264 dev_err(ov13b->dev, "%s failed to set mode\n", __func__); 1265 return ret; 1266 } 1267 1268 /* Apply customized values from user */ 1269 ret = __v4l2_ctrl_handler_setup(ov13b->sd.ctrl_handler); 1270 if (ret) 1271 return ret; 1272 1273 return ov13b10_write_reg(ov13b, OV13B10_REG_MODE_SELECT, 1274 OV13B10_REG_VALUE_08BIT, 1275 OV13B10_MODE_STREAMING); 1276 } 1277 1278 /* Stop streaming */ 1279 static int ov13b10_stop_streaming(struct ov13b10 *ov13b) 1280 { 1281 return ov13b10_write_reg(ov13b, OV13B10_REG_MODE_SELECT, 1282 OV13B10_REG_VALUE_08BIT, OV13B10_MODE_STANDBY); 1283 } 1284 1285 static int ov13b10_set_stream(struct v4l2_subdev *sd, int enable) 1286 { 1287 struct ov13b10 *ov13b = to_ov13b10(sd); 1288 int ret = 0; 1289 1290 mutex_lock(&ov13b->mutex); 1291 1292 if (enable) { 1293 ret = pm_runtime_resume_and_get(ov13b->dev); 1294 if (ret < 0) 1295 goto err_unlock; 1296 1297 /* 1298 * Apply default & customized values 1299 * and then start streaming. 1300 */ 1301 ret = ov13b10_start_streaming(ov13b); 1302 if (ret) 1303 goto err_rpm_put; 1304 } else { 1305 ov13b10_stop_streaming(ov13b); 1306 pm_runtime_put(ov13b->dev); 1307 } 1308 1309 mutex_unlock(&ov13b->mutex); 1310 1311 return ret; 1312 1313 err_rpm_put: 1314 pm_runtime_put(ov13b->dev); 1315 err_unlock: 1316 mutex_unlock(&ov13b->mutex); 1317 1318 return ret; 1319 } 1320 1321 static int ov13b10_suspend(struct device *dev) 1322 { 1323 ov13b10_power_off(dev); 1324 1325 return 0; 1326 } 1327 1328 static int ov13b10_resume(struct device *dev) 1329 { 1330 return ov13b10_power_on(dev); 1331 } 1332 1333 static const struct v4l2_subdev_video_ops ov13b10_video_ops = { 1334 .s_stream = ov13b10_set_stream, 1335 }; 1336 1337 static const struct v4l2_subdev_pad_ops ov13b10_pad_ops = { 1338 .enum_mbus_code = ov13b10_enum_mbus_code, 1339 .get_fmt = ov13b10_get_pad_format, 1340 .set_fmt = ov13b10_set_pad_format, 1341 .enum_frame_size = ov13b10_enum_frame_size, 1342 }; 1343 1344 static const struct v4l2_subdev_ops ov13b10_subdev_ops = { 1345 .video = &ov13b10_video_ops, 1346 .pad = &ov13b10_pad_ops, 1347 }; 1348 1349 static const struct media_entity_operations ov13b10_subdev_entity_ops = { 1350 .link_validate = v4l2_subdev_link_validate, 1351 }; 1352 1353 static const struct v4l2_subdev_internal_ops ov13b10_internal_ops = { 1354 .open = ov13b10_open, 1355 }; 1356 1357 /* Initialize control handlers */ 1358 static int ov13b10_init_controls(struct ov13b10 *ov13b) 1359 { 1360 struct v4l2_fwnode_device_properties props; 1361 struct v4l2_ctrl_handler *ctrl_hdlr; 1362 s64 exposure_max; 1363 s64 vblank_def; 1364 s64 vblank_min; 1365 s64 hblank; 1366 s64 pixel_rate_min; 1367 s64 pixel_rate_max; 1368 const struct ov13b10_mode *mode; 1369 u32 max; 1370 int ret; 1371 1372 ctrl_hdlr = &ov13b->ctrl_handler; 1373 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 10); 1374 if (ret) 1375 return ret; 1376 1377 mutex_init(&ov13b->mutex); 1378 ctrl_hdlr->lock = &ov13b->mutex; 1379 max = ARRAY_SIZE(link_freq_menu_items) - 1; 1380 ov13b->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, 1381 &ov13b10_ctrl_ops, 1382 V4L2_CID_LINK_FREQ, 1383 max, 1384 0, 1385 link_freq_menu_items); 1386 if (ov13b->link_freq) 1387 ov13b->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; 1388 1389 pixel_rate_max = link_freq_to_pixel_rate(link_freq_menu_items[0], 1390 ov13b->data_lanes); 1391 pixel_rate_min = 0; 1392 /* By default, PIXEL_RATE is read only */ 1393 ov13b->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops, 1394 V4L2_CID_PIXEL_RATE, 1395 pixel_rate_min, pixel_rate_max, 1396 1, pixel_rate_max); 1397 1398 mode = ov13b->cur_mode; 1399 vblank_def = mode->vts_def - mode->height; 1400 vblank_min = mode->vts_min - mode->height; 1401 ov13b->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops, 1402 V4L2_CID_VBLANK, 1403 vblank_min, 1404 OV13B10_VTS_MAX - mode->height, 1, 1405 vblank_def); 1406 1407 hblank = mode->ppl - mode->width; 1408 ov13b->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops, 1409 V4L2_CID_HBLANK, 1410 hblank, hblank, 1, hblank); 1411 if (ov13b->hblank) 1412 ov13b->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; 1413 1414 exposure_max = mode->vts_def - 8; 1415 ov13b->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops, 1416 V4L2_CID_EXPOSURE, 1417 OV13B10_EXPOSURE_MIN, 1418 exposure_max, OV13B10_EXPOSURE_STEP, 1419 exposure_max); 1420 1421 v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, 1422 OV13B10_ANA_GAIN_MIN, OV13B10_ANA_GAIN_MAX, 1423 OV13B10_ANA_GAIN_STEP, OV13B10_ANA_GAIN_DEFAULT); 1424 1425 /* Digital gain */ 1426 v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops, V4L2_CID_DIGITAL_GAIN, 1427 OV13B10_DGTL_GAIN_MIN, OV13B10_DGTL_GAIN_MAX, 1428 OV13B10_DGTL_GAIN_STEP, OV13B10_DGTL_GAIN_DEFAULT); 1429 1430 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov13b10_ctrl_ops, 1431 V4L2_CID_TEST_PATTERN, 1432 ARRAY_SIZE(ov13b10_test_pattern_menu) - 1, 1433 0, 0, ov13b10_test_pattern_menu); 1434 1435 v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops, 1436 V4L2_CID_HFLIP, 0, 1, 1, 0); 1437 v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops, 1438 V4L2_CID_VFLIP, 0, 1, 1, 0); 1439 1440 if (ctrl_hdlr->error) { 1441 ret = ctrl_hdlr->error; 1442 dev_err(ov13b->dev, "%s control init failed (%d)\n", 1443 __func__, ret); 1444 goto error; 1445 } 1446 1447 ret = v4l2_fwnode_device_parse(ov13b->dev, &props); 1448 if (ret) 1449 goto error; 1450 1451 ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &ov13b10_ctrl_ops, 1452 &props); 1453 if (ret) 1454 goto error; 1455 1456 ov13b->sd.ctrl_handler = ctrl_hdlr; 1457 1458 return 0; 1459 1460 error: 1461 v4l2_ctrl_handler_free(ctrl_hdlr); 1462 mutex_destroy(&ov13b->mutex); 1463 1464 return ret; 1465 } 1466 1467 static void ov13b10_free_controls(struct ov13b10 *ov13b) 1468 { 1469 v4l2_ctrl_handler_free(ov13b->sd.ctrl_handler); 1470 mutex_destroy(&ov13b->mutex); 1471 } 1472 1473 static int ov13b10_get_pm_resources(struct ov13b10 *ov13b) 1474 { 1475 unsigned long freq; 1476 int ret; 1477 1478 ov13b->reset = devm_gpiod_get_optional(ov13b->dev, "reset", GPIOD_OUT_LOW); 1479 if (IS_ERR(ov13b->reset)) 1480 return dev_err_probe(ov13b->dev, PTR_ERR(ov13b->reset), 1481 "failed to get reset gpio\n"); 1482 1483 ov13b->img_clk = devm_v4l2_sensor_clk_get(ov13b->dev, NULL); 1484 if (IS_ERR(ov13b->img_clk)) 1485 return dev_err_probe(ov13b->dev, PTR_ERR(ov13b->img_clk), 1486 "failed to get imaging clock\n"); 1487 1488 freq = clk_get_rate(ov13b->img_clk); 1489 if (freq != OV13B10_EXT_CLK) 1490 return dev_err_probe(ov13b->dev, -EINVAL, 1491 "external clock %lu is not supported\n", 1492 freq); 1493 1494 ov13b->avdd = devm_regulator_get_optional(ov13b->dev, "avdd"); 1495 if (IS_ERR(ov13b->avdd)) { 1496 ret = PTR_ERR(ov13b->avdd); 1497 ov13b->avdd = NULL; 1498 if (ret != -ENODEV) 1499 return dev_err_probe(ov13b->dev, ret, 1500 "failed to get avdd regulator\n"); 1501 } 1502 1503 return 0; 1504 } 1505 1506 static int ov13b10_check_hwcfg(struct ov13b10 *ov13b) 1507 { 1508 struct v4l2_fwnode_endpoint bus_cfg = { 1509 .bus_type = V4L2_MBUS_CSI2_DPHY 1510 }; 1511 struct device *dev = ov13b->dev; 1512 struct fwnode_handle *ep; 1513 struct fwnode_handle *fwnode = dev_fwnode(dev); 1514 unsigned int i, j; 1515 int ret; 1516 u8 dlane; 1517 1518 if (!fwnode) 1519 return -ENXIO; 1520 1521 ep = fwnode_graph_get_next_endpoint(fwnode, NULL); 1522 if (!ep) 1523 return -EPROBE_DEFER; 1524 1525 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg); 1526 fwnode_handle_put(ep); 1527 if (ret) 1528 return ret; 1529 1530 dlane = bus_cfg.bus.mipi_csi2.num_data_lanes; 1531 switch (dlane) { 1532 case OV13B10_4_DATA_LANES: 1533 ov13b->supported_modes = supported_4_lanes_modes; 1534 ov13b->supported_modes_num = 1535 ARRAY_SIZE(supported_4_lanes_modes); 1536 break; 1537 1538 case OV13B10_2_DATA_LANES: 1539 ov13b->supported_modes = supported_2_lanes_modes; 1540 ov13b->supported_modes_num = 1541 ARRAY_SIZE(supported_2_lanes_modes); 1542 break; 1543 1544 default: 1545 dev_err(dev, "number of CSI2 data lanes %d is not supported", 1546 dlane); 1547 ret = -EINVAL; 1548 goto out_err; 1549 } 1550 1551 ov13b->data_lanes = dlane; 1552 ov13b->cur_mode = ov13b->supported_modes; 1553 dev_dbg(dev, "%u lanes with %u modes selected\n", 1554 ov13b->data_lanes, ov13b->supported_modes_num); 1555 1556 if (!bus_cfg.nr_of_link_frequencies) { 1557 dev_err(dev, "no link frequencies defined"); 1558 ret = -EINVAL; 1559 goto out_err; 1560 } 1561 1562 for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) { 1563 for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) { 1564 if (link_freq_menu_items[i] == 1565 bus_cfg.link_frequencies[j]) 1566 break; 1567 } 1568 1569 if (j == bus_cfg.nr_of_link_frequencies) { 1570 dev_err(dev, "no link frequency %lld supported", 1571 link_freq_menu_items[i]); 1572 ret = -EINVAL; 1573 goto out_err; 1574 } 1575 } 1576 1577 out_err: 1578 v4l2_fwnode_endpoint_free(&bus_cfg); 1579 1580 return ret; 1581 } 1582 1583 static int ov13b10_probe(struct i2c_client *client) 1584 { 1585 struct ov13b10 *ov13b; 1586 bool full_power; 1587 int ret; 1588 1589 ov13b = devm_kzalloc(&client->dev, sizeof(*ov13b), GFP_KERNEL); 1590 if (!ov13b) 1591 return -ENOMEM; 1592 1593 ov13b->dev = &client->dev; 1594 1595 /* Check HW config */ 1596 ret = ov13b10_check_hwcfg(ov13b); 1597 if (ret) { 1598 dev_err(ov13b->dev, "failed to check hwcfg: %d", ret); 1599 return ret; 1600 } 1601 1602 /* Initialize subdev */ 1603 v4l2_i2c_subdev_init(&ov13b->sd, client, &ov13b10_subdev_ops); 1604 1605 ret = ov13b10_get_pm_resources(ov13b); 1606 if (ret) 1607 return ret; 1608 1609 full_power = acpi_dev_state_d0(ov13b->dev); 1610 if (full_power) { 1611 ret = ov13b10_power_on(ov13b->dev); 1612 if (ret) { 1613 dev_err(ov13b->dev, "failed to power on\n"); 1614 return ret; 1615 } 1616 1617 /* Check module identity */ 1618 ret = ov13b10_identify_module(ov13b); 1619 if (ret) { 1620 dev_err(ov13b->dev, "failed to find sensor: %d\n", ret); 1621 goto error_power_off; 1622 } 1623 } 1624 1625 ret = ov13b10_init_controls(ov13b); 1626 if (ret) 1627 goto error_power_off; 1628 1629 /* Initialize subdev */ 1630 ov13b->sd.internal_ops = &ov13b10_internal_ops; 1631 ov13b->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1632 ov13b->sd.entity.ops = &ov13b10_subdev_entity_ops; 1633 ov13b->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1634 1635 /* Initialize source pad */ 1636 ov13b->pad.flags = MEDIA_PAD_FL_SOURCE; 1637 ret = media_entity_pads_init(&ov13b->sd.entity, 1, &ov13b->pad); 1638 if (ret) { 1639 dev_err(ov13b->dev, "%s failed:%d\n", __func__, ret); 1640 goto error_handler_free; 1641 } 1642 1643 1644 /* 1645 * Device is already turned on by i2c-core with ACPI domain PM. 1646 * Enable runtime PM and turn off the device. 1647 */ 1648 /* Set the device's state to active if it's in D0 state. */ 1649 if (full_power) 1650 pm_runtime_set_active(ov13b->dev); 1651 pm_runtime_enable(ov13b->dev); 1652 pm_runtime_idle(ov13b->dev); 1653 1654 ret = v4l2_async_register_subdev_sensor(&ov13b->sd); 1655 if (ret < 0) 1656 goto error_media_entity_runtime_pm; 1657 1658 return 0; 1659 1660 error_media_entity_runtime_pm: 1661 pm_runtime_disable(ov13b->dev); 1662 if (full_power) 1663 pm_runtime_set_suspended(ov13b->dev); 1664 media_entity_cleanup(&ov13b->sd.entity); 1665 1666 error_handler_free: 1667 ov13b10_free_controls(ov13b); 1668 dev_err(ov13b->dev, "%s failed:%d\n", __func__, ret); 1669 1670 error_power_off: 1671 ov13b10_power_off(ov13b->dev); 1672 1673 return ret; 1674 } 1675 1676 static void ov13b10_remove(struct i2c_client *client) 1677 { 1678 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1679 struct ov13b10 *ov13b = to_ov13b10(sd); 1680 1681 v4l2_async_unregister_subdev(sd); 1682 media_entity_cleanup(&sd->entity); 1683 ov13b10_free_controls(ov13b); 1684 1685 pm_runtime_disable(ov13b->dev); 1686 pm_runtime_set_suspended(ov13b->dev); 1687 } 1688 1689 static DEFINE_RUNTIME_DEV_PM_OPS(ov13b10_pm_ops, ov13b10_suspend, 1690 ov13b10_resume, NULL); 1691 1692 #ifdef CONFIG_ACPI 1693 static const struct acpi_device_id ov13b10_acpi_ids[] = { 1694 {"OVTIDB10"}, 1695 {"OVTI13B1"}, 1696 { /* sentinel */ } 1697 }; 1698 1699 MODULE_DEVICE_TABLE(acpi, ov13b10_acpi_ids); 1700 #endif 1701 1702 static struct i2c_driver ov13b10_i2c_driver = { 1703 .driver = { 1704 .name = "ov13b10", 1705 .pm = pm_ptr(&ov13b10_pm_ops), 1706 .acpi_match_table = ACPI_PTR(ov13b10_acpi_ids), 1707 }, 1708 .probe = ov13b10_probe, 1709 .remove = ov13b10_remove, 1710 .flags = I2C_DRV_ACPI_WAIVE_D0_PROBE, 1711 }; 1712 1713 module_i2c_driver(ov13b10_i2c_driver); 1714 1715 MODULE_AUTHOR("Kao, Arec <arec.kao@intel.com>"); 1716 MODULE_DESCRIPTION("Omnivision ov13b10 sensor driver"); 1717 MODULE_LICENSE("GPL v2"); 1718