1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2017 Intel Corporation. 3 4 #include <linux/acpi.h> 5 #include <linux/i2c.h> 6 #include <linux/module.h> 7 #include <linux/pm_runtime.h> 8 #include <media/v4l2-ctrls.h> 9 #include <media/v4l2-device.h> 10 #include <media/v4l2-event.h> 11 #include <media/v4l2-fwnode.h> 12 13 #define OV13858_REG_VALUE_08BIT 1 14 #define OV13858_REG_VALUE_16BIT 2 15 #define OV13858_REG_VALUE_24BIT 3 16 17 #define OV13858_REG_MODE_SELECT 0x0100 18 #define OV13858_MODE_STANDBY 0x00 19 #define OV13858_MODE_STREAMING 0x01 20 21 #define OV13858_REG_SOFTWARE_RST 0x0103 22 #define OV13858_SOFTWARE_RST 0x01 23 24 /* PLL1 generates PCLK and MIPI_PHY_CLK */ 25 #define OV13858_REG_PLL1_CTRL_0 0x0300 26 #define OV13858_REG_PLL1_CTRL_1 0x0301 27 #define OV13858_REG_PLL1_CTRL_2 0x0302 28 #define OV13858_REG_PLL1_CTRL_3 0x0303 29 #define OV13858_REG_PLL1_CTRL_4 0x0304 30 #define OV13858_REG_PLL1_CTRL_5 0x0305 31 32 /* PLL2 generates DAC_CLK, SCLK and SRAM_CLK */ 33 #define OV13858_REG_PLL2_CTRL_B 0x030b 34 #define OV13858_REG_PLL2_CTRL_C 0x030c 35 #define OV13858_REG_PLL2_CTRL_D 0x030d 36 #define OV13858_REG_PLL2_CTRL_E 0x030e 37 #define OV13858_REG_PLL2_CTRL_F 0x030f 38 #define OV13858_REG_PLL2_CTRL_12 0x0312 39 #define OV13858_REG_MIPI_SC_CTRL0 0x3016 40 #define OV13858_REG_MIPI_SC_CTRL1 0x3022 41 42 /* Chip ID */ 43 #define OV13858_REG_CHIP_ID 0x300a 44 #define OV13858_CHIP_ID 0x00d855 45 46 /* V_TIMING internal */ 47 #define OV13858_REG_VTS 0x380e 48 #define OV13858_VTS_30FPS 0x0c8e /* 30 fps */ 49 #define OV13858_VTS_60FPS 0x0648 /* 60 fps */ 50 #define OV13858_VTS_MAX 0x7fff 51 52 /* HBLANK control - read only */ 53 #define OV13858_PPL_270MHZ 2244 54 #define OV13858_PPL_540MHZ 4488 55 56 /* Exposure control */ 57 #define OV13858_REG_EXPOSURE 0x3500 58 #define OV13858_EXPOSURE_MIN 4 59 #define OV13858_EXPOSURE_STEP 1 60 #define OV13858_EXPOSURE_DEFAULT 0x640 61 62 /* Analog gain control */ 63 #define OV13858_REG_ANALOG_GAIN 0x3508 64 #define OV13858_ANA_GAIN_MIN 0 65 #define OV13858_ANA_GAIN_MAX 0x1fff 66 #define OV13858_ANA_GAIN_STEP 1 67 #define OV13858_ANA_GAIN_DEFAULT 0x80 68 69 /* Digital gain control */ 70 #define OV13858_REG_B_MWB_GAIN 0x5100 71 #define OV13858_REG_G_MWB_GAIN 0x5102 72 #define OV13858_REG_R_MWB_GAIN 0x5104 73 #define OV13858_DGTL_GAIN_MIN 0 74 #define OV13858_DGTL_GAIN_MAX 16384 /* Max = 16 X */ 75 #define OV13858_DGTL_GAIN_DEFAULT 1024 /* Default gain = 1 X */ 76 #define OV13858_DGTL_GAIN_STEP 1 /* Each step = 1/1024 */ 77 78 /* Test Pattern Control */ 79 #define OV13858_REG_TEST_PATTERN 0x4503 80 #define OV13858_TEST_PATTERN_ENABLE BIT(7) 81 #define OV13858_TEST_PATTERN_MASK 0xfc 82 83 /* Number of frames to skip */ 84 #define OV13858_NUM_OF_SKIP_FRAMES 2 85 86 struct ov13858_reg { 87 u16 address; 88 u8 val; 89 }; 90 91 struct ov13858_reg_list { 92 u32 num_of_regs; 93 const struct ov13858_reg *regs; 94 }; 95 96 /* Link frequency config */ 97 struct ov13858_link_freq_config { 98 u32 pixels_per_line; 99 100 /* PLL registers for this link frequency */ 101 struct ov13858_reg_list reg_list; 102 }; 103 104 /* Mode : resolution and related config&values */ 105 struct ov13858_mode { 106 /* Frame width */ 107 u32 width; 108 /* Frame height */ 109 u32 height; 110 111 /* V-timing */ 112 u32 vts_def; 113 u32 vts_min; 114 115 /* Index of Link frequency config to be used */ 116 u32 link_freq_index; 117 /* Default register values */ 118 struct ov13858_reg_list reg_list; 119 }; 120 121 /* 4224x3136 needs 1080Mbps/lane, 4 lanes */ 122 static const struct ov13858_reg mipi_data_rate_1080mbps[] = { 123 /* PLL1 registers */ 124 {OV13858_REG_PLL1_CTRL_0, 0x07}, 125 {OV13858_REG_PLL1_CTRL_1, 0x01}, 126 {OV13858_REG_PLL1_CTRL_2, 0xc2}, 127 {OV13858_REG_PLL1_CTRL_3, 0x00}, 128 {OV13858_REG_PLL1_CTRL_4, 0x00}, 129 {OV13858_REG_PLL1_CTRL_5, 0x01}, 130 131 /* PLL2 registers */ 132 {OV13858_REG_PLL2_CTRL_B, 0x05}, 133 {OV13858_REG_PLL2_CTRL_C, 0x01}, 134 {OV13858_REG_PLL2_CTRL_D, 0x0e}, 135 {OV13858_REG_PLL2_CTRL_E, 0x05}, 136 {OV13858_REG_PLL2_CTRL_F, 0x01}, 137 {OV13858_REG_PLL2_CTRL_12, 0x01}, 138 {OV13858_REG_MIPI_SC_CTRL0, 0x72}, 139 {OV13858_REG_MIPI_SC_CTRL1, 0x01}, 140 }; 141 142 /* 143 * 2112x1568, 2112x1188, 1056x784 need 540Mbps/lane, 144 * 4 lanes 145 */ 146 static const struct ov13858_reg mipi_data_rate_540mbps[] = { 147 /* PLL1 registers */ 148 {OV13858_REG_PLL1_CTRL_0, 0x07}, 149 {OV13858_REG_PLL1_CTRL_1, 0x01}, 150 {OV13858_REG_PLL1_CTRL_2, 0xc2}, 151 {OV13858_REG_PLL1_CTRL_3, 0x01}, 152 {OV13858_REG_PLL1_CTRL_4, 0x00}, 153 {OV13858_REG_PLL1_CTRL_5, 0x01}, 154 155 /* PLL2 registers */ 156 {OV13858_REG_PLL2_CTRL_B, 0x05}, 157 {OV13858_REG_PLL2_CTRL_C, 0x01}, 158 {OV13858_REG_PLL2_CTRL_D, 0x0e}, 159 {OV13858_REG_PLL2_CTRL_E, 0x05}, 160 {OV13858_REG_PLL2_CTRL_F, 0x01}, 161 {OV13858_REG_PLL2_CTRL_12, 0x01}, 162 {OV13858_REG_MIPI_SC_CTRL0, 0x72}, 163 {OV13858_REG_MIPI_SC_CTRL1, 0x01}, 164 }; 165 166 static const struct ov13858_reg mode_4224x3136_regs[] = { 167 {0x3013, 0x32}, 168 {0x301b, 0xf0}, 169 {0x301f, 0xd0}, 170 {0x3106, 0x15}, 171 {0x3107, 0x23}, 172 {0x350a, 0x00}, 173 {0x350e, 0x00}, 174 {0x3510, 0x00}, 175 {0x3511, 0x02}, 176 {0x3512, 0x00}, 177 {0x3600, 0x2b}, 178 {0x3601, 0x52}, 179 {0x3602, 0x60}, 180 {0x3612, 0x05}, 181 {0x3613, 0xa4}, 182 {0x3620, 0x80}, 183 {0x3621, 0x10}, 184 {0x3622, 0x30}, 185 {0x3624, 0x1c}, 186 {0x3640, 0x10}, 187 {0x3641, 0x70}, 188 {0x3660, 0x04}, 189 {0x3661, 0x80}, 190 {0x3662, 0x12}, 191 {0x3664, 0x73}, 192 {0x3665, 0xa7}, 193 {0x366e, 0xff}, 194 {0x366f, 0xf4}, 195 {0x3674, 0x00}, 196 {0x3679, 0x0c}, 197 {0x367f, 0x01}, 198 {0x3680, 0x0c}, 199 {0x3681, 0x50}, 200 {0x3682, 0x50}, 201 {0x3683, 0xa9}, 202 {0x3684, 0xa9}, 203 {0x3709, 0x5f}, 204 {0x3714, 0x24}, 205 {0x371a, 0x3e}, 206 {0x3737, 0x04}, 207 {0x3738, 0xcc}, 208 {0x3739, 0x12}, 209 {0x373d, 0x26}, 210 {0x3764, 0x20}, 211 {0x3765, 0x20}, 212 {0x37a1, 0x36}, 213 {0x37a8, 0x3b}, 214 {0x37ab, 0x31}, 215 {0x37c2, 0x04}, 216 {0x37c3, 0xf1}, 217 {0x37c5, 0x00}, 218 {0x37d8, 0x03}, 219 {0x37d9, 0x0c}, 220 {0x37da, 0xc2}, 221 {0x37dc, 0x02}, 222 {0x37e0, 0x00}, 223 {0x37e1, 0x0a}, 224 {0x37e2, 0x14}, 225 {0x37e3, 0x04}, 226 {0x37e4, 0x2a}, 227 {0x37e5, 0x03}, 228 {0x37e6, 0x04}, 229 {0x3800, 0x00}, 230 {0x3801, 0x00}, 231 {0x3802, 0x00}, 232 {0x3803, 0x08}, 233 {0x3804, 0x10}, 234 {0x3805, 0x9f}, 235 {0x3806, 0x0c}, 236 {0x3807, 0x57}, 237 {0x3808, 0x10}, 238 {0x3809, 0x80}, 239 {0x380a, 0x0c}, 240 {0x380b, 0x40}, 241 {0x380c, 0x04}, 242 {0x380d, 0x62}, 243 {0x380e, 0x0c}, 244 {0x380f, 0x8e}, 245 {0x3811, 0x04}, 246 {0x3813, 0x05}, 247 {0x3814, 0x01}, 248 {0x3815, 0x01}, 249 {0x3816, 0x01}, 250 {0x3817, 0x01}, 251 {0x3820, 0xa8}, 252 {0x3821, 0x00}, 253 {0x3822, 0xc2}, 254 {0x3823, 0x18}, 255 {0x3826, 0x11}, 256 {0x3827, 0x1c}, 257 {0x3829, 0x03}, 258 {0x3832, 0x00}, 259 {0x3c80, 0x00}, 260 {0x3c87, 0x01}, 261 {0x3c8c, 0x19}, 262 {0x3c8d, 0x1c}, 263 {0x3c90, 0x00}, 264 {0x3c91, 0x00}, 265 {0x3c92, 0x00}, 266 {0x3c93, 0x00}, 267 {0x3c94, 0x40}, 268 {0x3c95, 0x54}, 269 {0x3c96, 0x34}, 270 {0x3c97, 0x04}, 271 {0x3c98, 0x00}, 272 {0x3d8c, 0x73}, 273 {0x3d8d, 0xc0}, 274 {0x3f00, 0x0b}, 275 {0x3f03, 0x00}, 276 {0x4001, 0xe0}, 277 {0x4008, 0x00}, 278 {0x4009, 0x0f}, 279 {0x4011, 0xf0}, 280 {0x4017, 0x08}, 281 {0x4050, 0x04}, 282 {0x4051, 0x0b}, 283 {0x4052, 0x00}, 284 {0x4053, 0x80}, 285 {0x4054, 0x00}, 286 {0x4055, 0x80}, 287 {0x4056, 0x00}, 288 {0x4057, 0x80}, 289 {0x4058, 0x00}, 290 {0x4059, 0x80}, 291 {0x405e, 0x20}, 292 {0x4500, 0x07}, 293 {0x4503, 0x00}, 294 {0x450a, 0x04}, 295 {0x4809, 0x04}, 296 {0x480c, 0x12}, 297 {0x481f, 0x30}, 298 {0x4833, 0x10}, 299 {0x4837, 0x0e}, 300 {0x4902, 0x01}, 301 {0x4d00, 0x03}, 302 {0x4d01, 0xc9}, 303 {0x4d02, 0xbc}, 304 {0x4d03, 0xd7}, 305 {0x4d04, 0xf0}, 306 {0x4d05, 0xa2}, 307 {0x5000, 0xfd}, 308 {0x5001, 0x01}, 309 {0x5040, 0x39}, 310 {0x5041, 0x10}, 311 {0x5042, 0x10}, 312 {0x5043, 0x84}, 313 {0x5044, 0x62}, 314 {0x5180, 0x00}, 315 {0x5181, 0x10}, 316 {0x5182, 0x02}, 317 {0x5183, 0x0f}, 318 {0x5200, 0x1b}, 319 {0x520b, 0x07}, 320 {0x520c, 0x0f}, 321 {0x5300, 0x04}, 322 {0x5301, 0x0c}, 323 {0x5302, 0x0c}, 324 {0x5303, 0x0f}, 325 {0x5304, 0x00}, 326 {0x5305, 0x70}, 327 {0x5306, 0x00}, 328 {0x5307, 0x80}, 329 {0x5308, 0x00}, 330 {0x5309, 0xa5}, 331 {0x530a, 0x00}, 332 {0x530b, 0xd3}, 333 {0x530c, 0x00}, 334 {0x530d, 0xf0}, 335 {0x530e, 0x01}, 336 {0x530f, 0x10}, 337 {0x5310, 0x01}, 338 {0x5311, 0x20}, 339 {0x5312, 0x01}, 340 {0x5313, 0x20}, 341 {0x5314, 0x01}, 342 {0x5315, 0x20}, 343 {0x5316, 0x08}, 344 {0x5317, 0x08}, 345 {0x5318, 0x10}, 346 {0x5319, 0x88}, 347 {0x531a, 0x88}, 348 {0x531b, 0xa9}, 349 {0x531c, 0xaa}, 350 {0x531d, 0x0a}, 351 {0x5405, 0x02}, 352 {0x5406, 0x67}, 353 {0x5407, 0x01}, 354 {0x5408, 0x4a}, 355 }; 356 357 static const struct ov13858_reg mode_2112x1568_regs[] = { 358 {0x3013, 0x32}, 359 {0x301b, 0xf0}, 360 {0x301f, 0xd0}, 361 {0x3106, 0x15}, 362 {0x3107, 0x23}, 363 {0x350a, 0x00}, 364 {0x350e, 0x00}, 365 {0x3510, 0x00}, 366 {0x3511, 0x02}, 367 {0x3512, 0x00}, 368 {0x3600, 0x2b}, 369 {0x3601, 0x52}, 370 {0x3602, 0x60}, 371 {0x3612, 0x05}, 372 {0x3613, 0xa4}, 373 {0x3620, 0x80}, 374 {0x3621, 0x10}, 375 {0x3622, 0x30}, 376 {0x3624, 0x1c}, 377 {0x3640, 0x10}, 378 {0x3641, 0x70}, 379 {0x3660, 0x04}, 380 {0x3661, 0x80}, 381 {0x3662, 0x10}, 382 {0x3664, 0x73}, 383 {0x3665, 0xa7}, 384 {0x366e, 0xff}, 385 {0x366f, 0xf4}, 386 {0x3674, 0x00}, 387 {0x3679, 0x0c}, 388 {0x367f, 0x01}, 389 {0x3680, 0x0c}, 390 {0x3681, 0x50}, 391 {0x3682, 0x50}, 392 {0x3683, 0xa9}, 393 {0x3684, 0xa9}, 394 {0x3709, 0x5f}, 395 {0x3714, 0x28}, 396 {0x371a, 0x3e}, 397 {0x3737, 0x08}, 398 {0x3738, 0xcc}, 399 {0x3739, 0x20}, 400 {0x373d, 0x26}, 401 {0x3764, 0x20}, 402 {0x3765, 0x20}, 403 {0x37a1, 0x36}, 404 {0x37a8, 0x3b}, 405 {0x37ab, 0x31}, 406 {0x37c2, 0x14}, 407 {0x37c3, 0xf1}, 408 {0x37c5, 0x00}, 409 {0x37d8, 0x03}, 410 {0x37d9, 0x0c}, 411 {0x37da, 0xc2}, 412 {0x37dc, 0x02}, 413 {0x37e0, 0x00}, 414 {0x37e1, 0x0a}, 415 {0x37e2, 0x14}, 416 {0x37e3, 0x08}, 417 {0x37e4, 0x38}, 418 {0x37e5, 0x03}, 419 {0x37e6, 0x08}, 420 {0x3800, 0x00}, 421 {0x3801, 0x00}, 422 {0x3802, 0x00}, 423 {0x3803, 0x00}, 424 {0x3804, 0x10}, 425 {0x3805, 0x9f}, 426 {0x3806, 0x0c}, 427 {0x3807, 0x5f}, 428 {0x3808, 0x08}, 429 {0x3809, 0x40}, 430 {0x380a, 0x06}, 431 {0x380b, 0x20}, 432 {0x380c, 0x04}, 433 {0x380d, 0x62}, 434 {0x380e, 0x0c}, 435 {0x380f, 0x8e}, 436 {0x3811, 0x04}, 437 {0x3813, 0x05}, 438 {0x3814, 0x03}, 439 {0x3815, 0x01}, 440 {0x3816, 0x03}, 441 {0x3817, 0x01}, 442 {0x3820, 0xab}, 443 {0x3821, 0x00}, 444 {0x3822, 0xc2}, 445 {0x3823, 0x18}, 446 {0x3826, 0x04}, 447 {0x3827, 0x90}, 448 {0x3829, 0x07}, 449 {0x3832, 0x00}, 450 {0x3c80, 0x00}, 451 {0x3c87, 0x01}, 452 {0x3c8c, 0x19}, 453 {0x3c8d, 0x1c}, 454 {0x3c90, 0x00}, 455 {0x3c91, 0x00}, 456 {0x3c92, 0x00}, 457 {0x3c93, 0x00}, 458 {0x3c94, 0x40}, 459 {0x3c95, 0x54}, 460 {0x3c96, 0x34}, 461 {0x3c97, 0x04}, 462 {0x3c98, 0x00}, 463 {0x3d8c, 0x73}, 464 {0x3d8d, 0xc0}, 465 {0x3f00, 0x0b}, 466 {0x3f03, 0x00}, 467 {0x4001, 0xe0}, 468 {0x4008, 0x00}, 469 {0x4009, 0x0d}, 470 {0x4011, 0xf0}, 471 {0x4017, 0x08}, 472 {0x4050, 0x04}, 473 {0x4051, 0x0b}, 474 {0x4052, 0x00}, 475 {0x4053, 0x80}, 476 {0x4054, 0x00}, 477 {0x4055, 0x80}, 478 {0x4056, 0x00}, 479 {0x4057, 0x80}, 480 {0x4058, 0x00}, 481 {0x4059, 0x80}, 482 {0x405e, 0x20}, 483 {0x4500, 0x07}, 484 {0x4503, 0x00}, 485 {0x450a, 0x04}, 486 {0x4809, 0x04}, 487 {0x480c, 0x12}, 488 {0x481f, 0x30}, 489 {0x4833, 0x10}, 490 {0x4837, 0x1c}, 491 {0x4902, 0x01}, 492 {0x4d00, 0x03}, 493 {0x4d01, 0xc9}, 494 {0x4d02, 0xbc}, 495 {0x4d03, 0xd7}, 496 {0x4d04, 0xf0}, 497 {0x4d05, 0xa2}, 498 {0x5000, 0xfd}, 499 {0x5001, 0x01}, 500 {0x5040, 0x39}, 501 {0x5041, 0x10}, 502 {0x5042, 0x10}, 503 {0x5043, 0x84}, 504 {0x5044, 0x62}, 505 {0x5180, 0x00}, 506 {0x5181, 0x10}, 507 {0x5182, 0x02}, 508 {0x5183, 0x0f}, 509 {0x5200, 0x1b}, 510 {0x520b, 0x07}, 511 {0x520c, 0x0f}, 512 {0x5300, 0x04}, 513 {0x5301, 0x0c}, 514 {0x5302, 0x0c}, 515 {0x5303, 0x0f}, 516 {0x5304, 0x00}, 517 {0x5305, 0x70}, 518 {0x5306, 0x00}, 519 {0x5307, 0x80}, 520 {0x5308, 0x00}, 521 {0x5309, 0xa5}, 522 {0x530a, 0x00}, 523 {0x530b, 0xd3}, 524 {0x530c, 0x00}, 525 {0x530d, 0xf0}, 526 {0x530e, 0x01}, 527 {0x530f, 0x10}, 528 {0x5310, 0x01}, 529 {0x5311, 0x20}, 530 {0x5312, 0x01}, 531 {0x5313, 0x20}, 532 {0x5314, 0x01}, 533 {0x5315, 0x20}, 534 {0x5316, 0x08}, 535 {0x5317, 0x08}, 536 {0x5318, 0x10}, 537 {0x5319, 0x88}, 538 {0x531a, 0x88}, 539 {0x531b, 0xa9}, 540 {0x531c, 0xaa}, 541 {0x531d, 0x0a}, 542 {0x5405, 0x02}, 543 {0x5406, 0x67}, 544 {0x5407, 0x01}, 545 {0x5408, 0x4a}, 546 }; 547 548 static const struct ov13858_reg mode_2112x1188_regs[] = { 549 {0x3013, 0x32}, 550 {0x301b, 0xf0}, 551 {0x301f, 0xd0}, 552 {0x3106, 0x15}, 553 {0x3107, 0x23}, 554 {0x350a, 0x00}, 555 {0x350e, 0x00}, 556 {0x3510, 0x00}, 557 {0x3511, 0x02}, 558 {0x3512, 0x00}, 559 {0x3600, 0x2b}, 560 {0x3601, 0x52}, 561 {0x3602, 0x60}, 562 {0x3612, 0x05}, 563 {0x3613, 0xa4}, 564 {0x3620, 0x80}, 565 {0x3621, 0x10}, 566 {0x3622, 0x30}, 567 {0x3624, 0x1c}, 568 {0x3640, 0x10}, 569 {0x3641, 0x70}, 570 {0x3660, 0x04}, 571 {0x3661, 0x80}, 572 {0x3662, 0x10}, 573 {0x3664, 0x73}, 574 {0x3665, 0xa7}, 575 {0x366e, 0xff}, 576 {0x366f, 0xf4}, 577 {0x3674, 0x00}, 578 {0x3679, 0x0c}, 579 {0x367f, 0x01}, 580 {0x3680, 0x0c}, 581 {0x3681, 0x50}, 582 {0x3682, 0x50}, 583 {0x3683, 0xa9}, 584 {0x3684, 0xa9}, 585 {0x3709, 0x5f}, 586 {0x3714, 0x28}, 587 {0x371a, 0x3e}, 588 {0x3737, 0x08}, 589 {0x3738, 0xcc}, 590 {0x3739, 0x20}, 591 {0x373d, 0x26}, 592 {0x3764, 0x20}, 593 {0x3765, 0x20}, 594 {0x37a1, 0x36}, 595 {0x37a8, 0x3b}, 596 {0x37ab, 0x31}, 597 {0x37c2, 0x14}, 598 {0x37c3, 0xf1}, 599 {0x37c5, 0x00}, 600 {0x37d8, 0x03}, 601 {0x37d9, 0x0c}, 602 {0x37da, 0xc2}, 603 {0x37dc, 0x02}, 604 {0x37e0, 0x00}, 605 {0x37e1, 0x0a}, 606 {0x37e2, 0x14}, 607 {0x37e3, 0x08}, 608 {0x37e4, 0x38}, 609 {0x37e5, 0x03}, 610 {0x37e6, 0x08}, 611 {0x3800, 0x00}, 612 {0x3801, 0x00}, 613 {0x3802, 0x01}, 614 {0x3803, 0x84}, 615 {0x3804, 0x10}, 616 {0x3805, 0x9f}, 617 {0x3806, 0x0a}, 618 {0x3807, 0xd3}, 619 {0x3808, 0x08}, 620 {0x3809, 0x40}, 621 {0x380a, 0x04}, 622 {0x380b, 0xa4}, 623 {0x380c, 0x04}, 624 {0x380d, 0x62}, 625 {0x380e, 0x0c}, 626 {0x380f, 0x8e}, 627 {0x3811, 0x08}, 628 {0x3813, 0x03}, 629 {0x3814, 0x03}, 630 {0x3815, 0x01}, 631 {0x3816, 0x03}, 632 {0x3817, 0x01}, 633 {0x3820, 0xab}, 634 {0x3821, 0x00}, 635 {0x3822, 0xc2}, 636 {0x3823, 0x18}, 637 {0x3826, 0x04}, 638 {0x3827, 0x90}, 639 {0x3829, 0x07}, 640 {0x3832, 0x00}, 641 {0x3c80, 0x00}, 642 {0x3c87, 0x01}, 643 {0x3c8c, 0x19}, 644 {0x3c8d, 0x1c}, 645 {0x3c90, 0x00}, 646 {0x3c91, 0x00}, 647 {0x3c92, 0x00}, 648 {0x3c93, 0x00}, 649 {0x3c94, 0x40}, 650 {0x3c95, 0x54}, 651 {0x3c96, 0x34}, 652 {0x3c97, 0x04}, 653 {0x3c98, 0x00}, 654 {0x3d8c, 0x73}, 655 {0x3d8d, 0xc0}, 656 {0x3f00, 0x0b}, 657 {0x3f03, 0x00}, 658 {0x4001, 0xe0}, 659 {0x4008, 0x00}, 660 {0x4009, 0x0d}, 661 {0x4011, 0xf0}, 662 {0x4017, 0x08}, 663 {0x4050, 0x04}, 664 {0x4051, 0x0b}, 665 {0x4052, 0x00}, 666 {0x4053, 0x80}, 667 {0x4054, 0x00}, 668 {0x4055, 0x80}, 669 {0x4056, 0x00}, 670 {0x4057, 0x80}, 671 {0x4058, 0x00}, 672 {0x4059, 0x80}, 673 {0x405e, 0x20}, 674 {0x4500, 0x07}, 675 {0x4503, 0x00}, 676 {0x450a, 0x04}, 677 {0x4809, 0x04}, 678 {0x480c, 0x12}, 679 {0x481f, 0x30}, 680 {0x4833, 0x10}, 681 {0x4837, 0x1c}, 682 {0x4902, 0x01}, 683 {0x4d00, 0x03}, 684 {0x4d01, 0xc9}, 685 {0x4d02, 0xbc}, 686 {0x4d03, 0xd7}, 687 {0x4d04, 0xf0}, 688 {0x4d05, 0xa2}, 689 {0x5000, 0xfd}, 690 {0x5001, 0x01}, 691 {0x5040, 0x39}, 692 {0x5041, 0x10}, 693 {0x5042, 0x10}, 694 {0x5043, 0x84}, 695 {0x5044, 0x62}, 696 {0x5180, 0x00}, 697 {0x5181, 0x10}, 698 {0x5182, 0x02}, 699 {0x5183, 0x0f}, 700 {0x5200, 0x1b}, 701 {0x520b, 0x07}, 702 {0x520c, 0x0f}, 703 {0x5300, 0x04}, 704 {0x5301, 0x0c}, 705 {0x5302, 0x0c}, 706 {0x5303, 0x0f}, 707 {0x5304, 0x00}, 708 {0x5305, 0x70}, 709 {0x5306, 0x00}, 710 {0x5307, 0x80}, 711 {0x5308, 0x00}, 712 {0x5309, 0xa5}, 713 {0x530a, 0x00}, 714 {0x530b, 0xd3}, 715 {0x530c, 0x00}, 716 {0x530d, 0xf0}, 717 {0x530e, 0x01}, 718 {0x530f, 0x10}, 719 {0x5310, 0x01}, 720 {0x5311, 0x20}, 721 {0x5312, 0x01}, 722 {0x5313, 0x20}, 723 {0x5314, 0x01}, 724 {0x5315, 0x20}, 725 {0x5316, 0x08}, 726 {0x5317, 0x08}, 727 {0x5318, 0x10}, 728 {0x5319, 0x88}, 729 {0x531a, 0x88}, 730 {0x531b, 0xa9}, 731 {0x531c, 0xaa}, 732 {0x531d, 0x0a}, 733 {0x5405, 0x02}, 734 {0x5406, 0x67}, 735 {0x5407, 0x01}, 736 {0x5408, 0x4a}, 737 }; 738 739 static const struct ov13858_reg mode_1056x784_regs[] = { 740 {0x3013, 0x32}, 741 {0x301b, 0xf0}, 742 {0x301f, 0xd0}, 743 {0x3106, 0x15}, 744 {0x3107, 0x23}, 745 {0x350a, 0x00}, 746 {0x350e, 0x00}, 747 {0x3510, 0x00}, 748 {0x3511, 0x02}, 749 {0x3512, 0x00}, 750 {0x3600, 0x2b}, 751 {0x3601, 0x52}, 752 {0x3602, 0x60}, 753 {0x3612, 0x05}, 754 {0x3613, 0xa4}, 755 {0x3620, 0x80}, 756 {0x3621, 0x10}, 757 {0x3622, 0x30}, 758 {0x3624, 0x1c}, 759 {0x3640, 0x10}, 760 {0x3641, 0x70}, 761 {0x3660, 0x04}, 762 {0x3661, 0x80}, 763 {0x3662, 0x08}, 764 {0x3664, 0x73}, 765 {0x3665, 0xa7}, 766 {0x366e, 0xff}, 767 {0x366f, 0xf4}, 768 {0x3674, 0x00}, 769 {0x3679, 0x0c}, 770 {0x367f, 0x01}, 771 {0x3680, 0x0c}, 772 {0x3681, 0x50}, 773 {0x3682, 0x50}, 774 {0x3683, 0xa9}, 775 {0x3684, 0xa9}, 776 {0x3709, 0x5f}, 777 {0x3714, 0x30}, 778 {0x371a, 0x3e}, 779 {0x3737, 0x08}, 780 {0x3738, 0xcc}, 781 {0x3739, 0x20}, 782 {0x373d, 0x26}, 783 {0x3764, 0x20}, 784 {0x3765, 0x20}, 785 {0x37a1, 0x36}, 786 {0x37a8, 0x3b}, 787 {0x37ab, 0x31}, 788 {0x37c2, 0x2c}, 789 {0x37c3, 0xf1}, 790 {0x37c5, 0x00}, 791 {0x37d8, 0x03}, 792 {0x37d9, 0x06}, 793 {0x37da, 0xc2}, 794 {0x37dc, 0x02}, 795 {0x37e0, 0x00}, 796 {0x37e1, 0x0a}, 797 {0x37e2, 0x14}, 798 {0x37e3, 0x08}, 799 {0x37e4, 0x36}, 800 {0x37e5, 0x03}, 801 {0x37e6, 0x08}, 802 {0x3800, 0x00}, 803 {0x3801, 0x00}, 804 {0x3802, 0x00}, 805 {0x3803, 0x00}, 806 {0x3804, 0x10}, 807 {0x3805, 0x9f}, 808 {0x3806, 0x0c}, 809 {0x3807, 0x5f}, 810 {0x3808, 0x04}, 811 {0x3809, 0x20}, 812 {0x380a, 0x03}, 813 {0x380b, 0x10}, 814 {0x380c, 0x04}, 815 {0x380d, 0x62}, 816 {0x380e, 0x0c}, 817 {0x380f, 0x8e}, 818 {0x3811, 0x04}, 819 {0x3813, 0x05}, 820 {0x3814, 0x07}, 821 {0x3815, 0x01}, 822 {0x3816, 0x07}, 823 {0x3817, 0x01}, 824 {0x3820, 0xac}, 825 {0x3821, 0x00}, 826 {0x3822, 0xc2}, 827 {0x3823, 0x18}, 828 {0x3826, 0x04}, 829 {0x3827, 0x48}, 830 {0x3829, 0x03}, 831 {0x3832, 0x00}, 832 {0x3c80, 0x00}, 833 {0x3c87, 0x01}, 834 {0x3c8c, 0x19}, 835 {0x3c8d, 0x1c}, 836 {0x3c90, 0x00}, 837 {0x3c91, 0x00}, 838 {0x3c92, 0x00}, 839 {0x3c93, 0x00}, 840 {0x3c94, 0x40}, 841 {0x3c95, 0x54}, 842 {0x3c96, 0x34}, 843 {0x3c97, 0x04}, 844 {0x3c98, 0x00}, 845 {0x3d8c, 0x73}, 846 {0x3d8d, 0xc0}, 847 {0x3f00, 0x0b}, 848 {0x3f03, 0x00}, 849 {0x4001, 0xe0}, 850 {0x4008, 0x00}, 851 {0x4009, 0x05}, 852 {0x4011, 0xf0}, 853 {0x4017, 0x08}, 854 {0x4050, 0x02}, 855 {0x4051, 0x05}, 856 {0x4052, 0x00}, 857 {0x4053, 0x80}, 858 {0x4054, 0x00}, 859 {0x4055, 0x80}, 860 {0x4056, 0x00}, 861 {0x4057, 0x80}, 862 {0x4058, 0x00}, 863 {0x4059, 0x80}, 864 {0x405e, 0x20}, 865 {0x4500, 0x07}, 866 {0x4503, 0x00}, 867 {0x450a, 0x04}, 868 {0x4809, 0x04}, 869 {0x480c, 0x12}, 870 {0x481f, 0x30}, 871 {0x4833, 0x10}, 872 {0x4837, 0x1e}, 873 {0x4902, 0x02}, 874 {0x4d00, 0x03}, 875 {0x4d01, 0xc9}, 876 {0x4d02, 0xbc}, 877 {0x4d03, 0xd7}, 878 {0x4d04, 0xf0}, 879 {0x4d05, 0xa2}, 880 {0x5000, 0xfd}, 881 {0x5001, 0x01}, 882 {0x5040, 0x39}, 883 {0x5041, 0x10}, 884 {0x5042, 0x10}, 885 {0x5043, 0x84}, 886 {0x5044, 0x62}, 887 {0x5180, 0x00}, 888 {0x5181, 0x10}, 889 {0x5182, 0x02}, 890 {0x5183, 0x0f}, 891 {0x5200, 0x1b}, 892 {0x520b, 0x07}, 893 {0x520c, 0x0f}, 894 {0x5300, 0x04}, 895 {0x5301, 0x0c}, 896 {0x5302, 0x0c}, 897 {0x5303, 0x0f}, 898 {0x5304, 0x00}, 899 {0x5305, 0x70}, 900 {0x5306, 0x00}, 901 {0x5307, 0x80}, 902 {0x5308, 0x00}, 903 {0x5309, 0xa5}, 904 {0x530a, 0x00}, 905 {0x530b, 0xd3}, 906 {0x530c, 0x00}, 907 {0x530d, 0xf0}, 908 {0x530e, 0x01}, 909 {0x530f, 0x10}, 910 {0x5310, 0x01}, 911 {0x5311, 0x20}, 912 {0x5312, 0x01}, 913 {0x5313, 0x20}, 914 {0x5314, 0x01}, 915 {0x5315, 0x20}, 916 {0x5316, 0x08}, 917 {0x5317, 0x08}, 918 {0x5318, 0x10}, 919 {0x5319, 0x88}, 920 {0x531a, 0x88}, 921 {0x531b, 0xa9}, 922 {0x531c, 0xaa}, 923 {0x531d, 0x0a}, 924 {0x5405, 0x02}, 925 {0x5406, 0x67}, 926 {0x5407, 0x01}, 927 {0x5408, 0x4a}, 928 }; 929 930 static const char * const ov13858_test_pattern_menu[] = { 931 "Disabled", 932 "Vertical Color Bar Type 1", 933 "Vertical Color Bar Type 2", 934 "Vertical Color Bar Type 3", 935 "Vertical Color Bar Type 4" 936 }; 937 938 /* Configurations for supported link frequencies */ 939 #define OV13858_NUM_OF_LINK_FREQS 2 940 #define OV13858_LINK_FREQ_540MHZ 540000000ULL 941 #define OV13858_LINK_FREQ_270MHZ 270000000ULL 942 #define OV13858_LINK_FREQ_INDEX_0 0 943 #define OV13858_LINK_FREQ_INDEX_1 1 944 945 /* 946 * pixel_rate = link_freq * data-rate * nr_of_lanes / bits_per_sample 947 * data rate => double data rate; number of lanes => 4; bits per pixel => 10 948 */ 949 static u64 link_freq_to_pixel_rate(u64 f) 950 { 951 f *= 2 * 4; 952 do_div(f, 10); 953 954 return f; 955 } 956 957 /* Menu items for LINK_FREQ V4L2 control */ 958 static const s64 link_freq_menu_items[OV13858_NUM_OF_LINK_FREQS] = { 959 OV13858_LINK_FREQ_540MHZ, 960 OV13858_LINK_FREQ_270MHZ 961 }; 962 963 /* Link frequency configs */ 964 static const struct ov13858_link_freq_config 965 link_freq_configs[OV13858_NUM_OF_LINK_FREQS] = { 966 { 967 .pixels_per_line = OV13858_PPL_540MHZ, 968 .reg_list = { 969 .num_of_regs = ARRAY_SIZE(mipi_data_rate_1080mbps), 970 .regs = mipi_data_rate_1080mbps, 971 } 972 }, 973 { 974 .pixels_per_line = OV13858_PPL_270MHZ, 975 .reg_list = { 976 .num_of_regs = ARRAY_SIZE(mipi_data_rate_540mbps), 977 .regs = mipi_data_rate_540mbps, 978 } 979 } 980 }; 981 982 /* Mode configs */ 983 static const struct ov13858_mode supported_modes[] = { 984 { 985 .width = 4224, 986 .height = 3136, 987 .vts_def = OV13858_VTS_30FPS, 988 .vts_min = OV13858_VTS_30FPS, 989 .reg_list = { 990 .num_of_regs = ARRAY_SIZE(mode_4224x3136_regs), 991 .regs = mode_4224x3136_regs, 992 }, 993 .link_freq_index = OV13858_LINK_FREQ_INDEX_0, 994 }, 995 { 996 .width = 2112, 997 .height = 1568, 998 .vts_def = OV13858_VTS_30FPS, 999 .vts_min = 1608, 1000 .reg_list = { 1001 .num_of_regs = ARRAY_SIZE(mode_2112x1568_regs), 1002 .regs = mode_2112x1568_regs, 1003 }, 1004 .link_freq_index = OV13858_LINK_FREQ_INDEX_1, 1005 }, 1006 { 1007 .width = 2112, 1008 .height = 1188, 1009 .vts_def = OV13858_VTS_30FPS, 1010 .vts_min = 1608, 1011 .reg_list = { 1012 .num_of_regs = ARRAY_SIZE(mode_2112x1188_regs), 1013 .regs = mode_2112x1188_regs, 1014 }, 1015 .link_freq_index = OV13858_LINK_FREQ_INDEX_1, 1016 }, 1017 { 1018 .width = 1056, 1019 .height = 784, 1020 .vts_def = OV13858_VTS_30FPS, 1021 .vts_min = 804, 1022 .reg_list = { 1023 .num_of_regs = ARRAY_SIZE(mode_1056x784_regs), 1024 .regs = mode_1056x784_regs, 1025 }, 1026 .link_freq_index = OV13858_LINK_FREQ_INDEX_1, 1027 } 1028 }; 1029 1030 struct ov13858 { 1031 struct v4l2_subdev sd; 1032 struct media_pad pad; 1033 1034 struct v4l2_ctrl_handler ctrl_handler; 1035 /* V4L2 Controls */ 1036 struct v4l2_ctrl *link_freq; 1037 struct v4l2_ctrl *pixel_rate; 1038 struct v4l2_ctrl *vblank; 1039 struct v4l2_ctrl *hblank; 1040 struct v4l2_ctrl *exposure; 1041 1042 /* Current mode */ 1043 const struct ov13858_mode *cur_mode; 1044 1045 /* Mutex for serialized access */ 1046 struct mutex mutex; 1047 }; 1048 1049 #define to_ov13858(_sd) container_of(_sd, struct ov13858, sd) 1050 1051 /* Read registers up to 4 at a time */ 1052 static int ov13858_read_reg(struct ov13858 *ov13858, u16 reg, u32 len, 1053 u32 *val) 1054 { 1055 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd); 1056 struct i2c_msg msgs[2]; 1057 u8 *data_be_p; 1058 int ret; 1059 __be32 data_be = 0; 1060 __be16 reg_addr_be = cpu_to_be16(reg); 1061 1062 if (len > 4) 1063 return -EINVAL; 1064 1065 data_be_p = (u8 *)&data_be; 1066 /* Write register address */ 1067 msgs[0].addr = client->addr; 1068 msgs[0].flags = 0; 1069 msgs[0].len = 2; 1070 msgs[0].buf = (u8 *)®_addr_be; 1071 1072 /* Read data from register */ 1073 msgs[1].addr = client->addr; 1074 msgs[1].flags = I2C_M_RD; 1075 msgs[1].len = len; 1076 msgs[1].buf = &data_be_p[4 - len]; 1077 1078 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); 1079 if (ret != ARRAY_SIZE(msgs)) 1080 return -EIO; 1081 1082 *val = be32_to_cpu(data_be); 1083 1084 return 0; 1085 } 1086 1087 /* Write registers up to 4 at a time */ 1088 static int ov13858_write_reg(struct ov13858 *ov13858, u16 reg, u32 len, 1089 u32 __val) 1090 { 1091 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd); 1092 int buf_i, val_i; 1093 u8 buf[6], *val_p; 1094 __be32 val; 1095 1096 if (len > 4) 1097 return -EINVAL; 1098 1099 buf[0] = reg >> 8; 1100 buf[1] = reg & 0xff; 1101 1102 val = cpu_to_be32(__val); 1103 val_p = (u8 *)&val; 1104 buf_i = 2; 1105 val_i = 4 - len; 1106 1107 while (val_i < 4) 1108 buf[buf_i++] = val_p[val_i++]; 1109 1110 if (i2c_master_send(client, buf, len + 2) != len + 2) 1111 return -EIO; 1112 1113 return 0; 1114 } 1115 1116 /* Write a list of registers */ 1117 static int ov13858_write_regs(struct ov13858 *ov13858, 1118 const struct ov13858_reg *regs, u32 len) 1119 { 1120 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd); 1121 int ret; 1122 u32 i; 1123 1124 for (i = 0; i < len; i++) { 1125 ret = ov13858_write_reg(ov13858, regs[i].address, 1, 1126 regs[i].val); 1127 if (ret) { 1128 dev_err_ratelimited( 1129 &client->dev, 1130 "Failed to write reg 0x%4.4x. error = %d\n", 1131 regs[i].address, ret); 1132 1133 return ret; 1134 } 1135 } 1136 1137 return 0; 1138 } 1139 1140 static int ov13858_write_reg_list(struct ov13858 *ov13858, 1141 const struct ov13858_reg_list *r_list) 1142 { 1143 return ov13858_write_regs(ov13858, r_list->regs, r_list->num_of_regs); 1144 } 1145 1146 /* Open sub-device */ 1147 static int ov13858_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) 1148 { 1149 struct ov13858 *ov13858 = to_ov13858(sd); 1150 struct v4l2_mbus_framefmt *try_fmt = v4l2_subdev_get_try_format(sd, 1151 fh->state, 1152 0); 1153 1154 mutex_lock(&ov13858->mutex); 1155 1156 /* Initialize try_fmt */ 1157 try_fmt->width = ov13858->cur_mode->width; 1158 try_fmt->height = ov13858->cur_mode->height; 1159 try_fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10; 1160 try_fmt->field = V4L2_FIELD_NONE; 1161 1162 /* No crop or compose */ 1163 mutex_unlock(&ov13858->mutex); 1164 1165 return 0; 1166 } 1167 1168 static int ov13858_update_digital_gain(struct ov13858 *ov13858, u32 d_gain) 1169 { 1170 int ret; 1171 1172 ret = ov13858_write_reg(ov13858, OV13858_REG_B_MWB_GAIN, 1173 OV13858_REG_VALUE_16BIT, d_gain); 1174 if (ret) 1175 return ret; 1176 1177 ret = ov13858_write_reg(ov13858, OV13858_REG_G_MWB_GAIN, 1178 OV13858_REG_VALUE_16BIT, d_gain); 1179 if (ret) 1180 return ret; 1181 1182 ret = ov13858_write_reg(ov13858, OV13858_REG_R_MWB_GAIN, 1183 OV13858_REG_VALUE_16BIT, d_gain); 1184 1185 return ret; 1186 } 1187 1188 static int ov13858_enable_test_pattern(struct ov13858 *ov13858, u32 pattern) 1189 { 1190 int ret; 1191 u32 val; 1192 1193 ret = ov13858_read_reg(ov13858, OV13858_REG_TEST_PATTERN, 1194 OV13858_REG_VALUE_08BIT, &val); 1195 if (ret) 1196 return ret; 1197 1198 if (pattern) { 1199 val &= OV13858_TEST_PATTERN_MASK; 1200 val |= (pattern - 1) | OV13858_TEST_PATTERN_ENABLE; 1201 } else { 1202 val &= ~OV13858_TEST_PATTERN_ENABLE; 1203 } 1204 1205 return ov13858_write_reg(ov13858, OV13858_REG_TEST_PATTERN, 1206 OV13858_REG_VALUE_08BIT, val); 1207 } 1208 1209 static int ov13858_set_ctrl(struct v4l2_ctrl *ctrl) 1210 { 1211 struct ov13858 *ov13858 = container_of(ctrl->handler, 1212 struct ov13858, ctrl_handler); 1213 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd); 1214 s64 max; 1215 int ret; 1216 1217 /* Propagate change of current control to all related controls */ 1218 switch (ctrl->id) { 1219 case V4L2_CID_VBLANK: 1220 /* Update max exposure while meeting expected vblanking */ 1221 max = ov13858->cur_mode->height + ctrl->val - 8; 1222 __v4l2_ctrl_modify_range(ov13858->exposure, 1223 ov13858->exposure->minimum, 1224 max, ov13858->exposure->step, max); 1225 break; 1226 } 1227 1228 /* 1229 * Applying V4L2 control value only happens 1230 * when power is up for streaming 1231 */ 1232 if (!pm_runtime_get_if_in_use(&client->dev)) 1233 return 0; 1234 1235 ret = 0; 1236 switch (ctrl->id) { 1237 case V4L2_CID_ANALOGUE_GAIN: 1238 ret = ov13858_write_reg(ov13858, OV13858_REG_ANALOG_GAIN, 1239 OV13858_REG_VALUE_16BIT, ctrl->val); 1240 break; 1241 case V4L2_CID_DIGITAL_GAIN: 1242 ret = ov13858_update_digital_gain(ov13858, ctrl->val); 1243 break; 1244 case V4L2_CID_EXPOSURE: 1245 ret = ov13858_write_reg(ov13858, OV13858_REG_EXPOSURE, 1246 OV13858_REG_VALUE_24BIT, 1247 ctrl->val << 4); 1248 break; 1249 case V4L2_CID_VBLANK: 1250 /* Update VTS that meets expected vertical blanking */ 1251 ret = ov13858_write_reg(ov13858, OV13858_REG_VTS, 1252 OV13858_REG_VALUE_16BIT, 1253 ov13858->cur_mode->height 1254 + ctrl->val); 1255 break; 1256 case V4L2_CID_TEST_PATTERN: 1257 ret = ov13858_enable_test_pattern(ov13858, ctrl->val); 1258 break; 1259 default: 1260 dev_info(&client->dev, 1261 "ctrl(id:0x%x,val:0x%x) is not handled\n", 1262 ctrl->id, ctrl->val); 1263 break; 1264 } 1265 1266 pm_runtime_put(&client->dev); 1267 1268 return ret; 1269 } 1270 1271 static const struct v4l2_ctrl_ops ov13858_ctrl_ops = { 1272 .s_ctrl = ov13858_set_ctrl, 1273 }; 1274 1275 static int ov13858_enum_mbus_code(struct v4l2_subdev *sd, 1276 struct v4l2_subdev_state *sd_state, 1277 struct v4l2_subdev_mbus_code_enum *code) 1278 { 1279 /* Only one bayer order(GRBG) is supported */ 1280 if (code->index > 0) 1281 return -EINVAL; 1282 1283 code->code = MEDIA_BUS_FMT_SGRBG10_1X10; 1284 1285 return 0; 1286 } 1287 1288 static int ov13858_enum_frame_size(struct v4l2_subdev *sd, 1289 struct v4l2_subdev_state *sd_state, 1290 struct v4l2_subdev_frame_size_enum *fse) 1291 { 1292 if (fse->index >= ARRAY_SIZE(supported_modes)) 1293 return -EINVAL; 1294 1295 if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10) 1296 return -EINVAL; 1297 1298 fse->min_width = supported_modes[fse->index].width; 1299 fse->max_width = fse->min_width; 1300 fse->min_height = supported_modes[fse->index].height; 1301 fse->max_height = fse->min_height; 1302 1303 return 0; 1304 } 1305 1306 static void ov13858_update_pad_format(const struct ov13858_mode *mode, 1307 struct v4l2_subdev_format *fmt) 1308 { 1309 fmt->format.width = mode->width; 1310 fmt->format.height = mode->height; 1311 fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10; 1312 fmt->format.field = V4L2_FIELD_NONE; 1313 } 1314 1315 static int ov13858_do_get_pad_format(struct ov13858 *ov13858, 1316 struct v4l2_subdev_state *sd_state, 1317 struct v4l2_subdev_format *fmt) 1318 { 1319 struct v4l2_mbus_framefmt *framefmt; 1320 struct v4l2_subdev *sd = &ov13858->sd; 1321 1322 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { 1323 framefmt = v4l2_subdev_get_try_format(sd, sd_state, fmt->pad); 1324 fmt->format = *framefmt; 1325 } else { 1326 ov13858_update_pad_format(ov13858->cur_mode, fmt); 1327 } 1328 1329 return 0; 1330 } 1331 1332 static int ov13858_get_pad_format(struct v4l2_subdev *sd, 1333 struct v4l2_subdev_state *sd_state, 1334 struct v4l2_subdev_format *fmt) 1335 { 1336 struct ov13858 *ov13858 = to_ov13858(sd); 1337 int ret; 1338 1339 mutex_lock(&ov13858->mutex); 1340 ret = ov13858_do_get_pad_format(ov13858, sd_state, fmt); 1341 mutex_unlock(&ov13858->mutex); 1342 1343 return ret; 1344 } 1345 1346 static int 1347 ov13858_set_pad_format(struct v4l2_subdev *sd, 1348 struct v4l2_subdev_state *sd_state, 1349 struct v4l2_subdev_format *fmt) 1350 { 1351 struct ov13858 *ov13858 = to_ov13858(sd); 1352 const struct ov13858_mode *mode; 1353 struct v4l2_mbus_framefmt *framefmt; 1354 s32 vblank_def; 1355 s32 vblank_min; 1356 s64 h_blank; 1357 s64 pixel_rate; 1358 s64 link_freq; 1359 1360 mutex_lock(&ov13858->mutex); 1361 1362 /* Only one raw bayer(GRBG) order is supported */ 1363 if (fmt->format.code != MEDIA_BUS_FMT_SGRBG10_1X10) 1364 fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10; 1365 1366 mode = v4l2_find_nearest_size(supported_modes, 1367 ARRAY_SIZE(supported_modes), 1368 width, height, 1369 fmt->format.width, fmt->format.height); 1370 ov13858_update_pad_format(mode, fmt); 1371 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { 1372 framefmt = v4l2_subdev_get_try_format(sd, sd_state, fmt->pad); 1373 *framefmt = fmt->format; 1374 } else { 1375 ov13858->cur_mode = mode; 1376 __v4l2_ctrl_s_ctrl(ov13858->link_freq, mode->link_freq_index); 1377 link_freq = link_freq_menu_items[mode->link_freq_index]; 1378 pixel_rate = link_freq_to_pixel_rate(link_freq); 1379 __v4l2_ctrl_s_ctrl_int64(ov13858->pixel_rate, pixel_rate); 1380 1381 /* Update limits and set FPS to default */ 1382 vblank_def = ov13858->cur_mode->vts_def - 1383 ov13858->cur_mode->height; 1384 vblank_min = ov13858->cur_mode->vts_min - 1385 ov13858->cur_mode->height; 1386 __v4l2_ctrl_modify_range( 1387 ov13858->vblank, vblank_min, 1388 OV13858_VTS_MAX - ov13858->cur_mode->height, 1, 1389 vblank_def); 1390 __v4l2_ctrl_s_ctrl(ov13858->vblank, vblank_def); 1391 h_blank = 1392 link_freq_configs[mode->link_freq_index].pixels_per_line 1393 - ov13858->cur_mode->width; 1394 __v4l2_ctrl_modify_range(ov13858->hblank, h_blank, 1395 h_blank, 1, h_blank); 1396 } 1397 1398 mutex_unlock(&ov13858->mutex); 1399 1400 return 0; 1401 } 1402 1403 static int ov13858_get_skip_frames(struct v4l2_subdev *sd, u32 *frames) 1404 { 1405 *frames = OV13858_NUM_OF_SKIP_FRAMES; 1406 1407 return 0; 1408 } 1409 1410 /* Start streaming */ 1411 static int ov13858_start_streaming(struct ov13858 *ov13858) 1412 { 1413 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd); 1414 const struct ov13858_reg_list *reg_list; 1415 int ret, link_freq_index; 1416 1417 /* Get out of from software reset */ 1418 ret = ov13858_write_reg(ov13858, OV13858_REG_SOFTWARE_RST, 1419 OV13858_REG_VALUE_08BIT, OV13858_SOFTWARE_RST); 1420 if (ret) { 1421 dev_err(&client->dev, "%s failed to set powerup registers\n", 1422 __func__); 1423 return ret; 1424 } 1425 1426 /* Setup PLL */ 1427 link_freq_index = ov13858->cur_mode->link_freq_index; 1428 reg_list = &link_freq_configs[link_freq_index].reg_list; 1429 ret = ov13858_write_reg_list(ov13858, reg_list); 1430 if (ret) { 1431 dev_err(&client->dev, "%s failed to set plls\n", __func__); 1432 return ret; 1433 } 1434 1435 /* Apply default values of current mode */ 1436 reg_list = &ov13858->cur_mode->reg_list; 1437 ret = ov13858_write_reg_list(ov13858, reg_list); 1438 if (ret) { 1439 dev_err(&client->dev, "%s failed to set mode\n", __func__); 1440 return ret; 1441 } 1442 1443 /* Apply customized values from user */ 1444 ret = __v4l2_ctrl_handler_setup(ov13858->sd.ctrl_handler); 1445 if (ret) 1446 return ret; 1447 1448 return ov13858_write_reg(ov13858, OV13858_REG_MODE_SELECT, 1449 OV13858_REG_VALUE_08BIT, 1450 OV13858_MODE_STREAMING); 1451 } 1452 1453 /* Stop streaming */ 1454 static int ov13858_stop_streaming(struct ov13858 *ov13858) 1455 { 1456 return ov13858_write_reg(ov13858, OV13858_REG_MODE_SELECT, 1457 OV13858_REG_VALUE_08BIT, OV13858_MODE_STANDBY); 1458 } 1459 1460 static int ov13858_set_stream(struct v4l2_subdev *sd, int enable) 1461 { 1462 struct ov13858 *ov13858 = to_ov13858(sd); 1463 struct i2c_client *client = v4l2_get_subdevdata(sd); 1464 int ret = 0; 1465 1466 mutex_lock(&ov13858->mutex); 1467 1468 if (enable) { 1469 ret = pm_runtime_resume_and_get(&client->dev); 1470 if (ret < 0) 1471 goto err_unlock; 1472 1473 /* 1474 * Apply default & customized values 1475 * and then start streaming. 1476 */ 1477 ret = ov13858_start_streaming(ov13858); 1478 if (ret) 1479 goto err_rpm_put; 1480 } else { 1481 ov13858_stop_streaming(ov13858); 1482 pm_runtime_put(&client->dev); 1483 } 1484 1485 mutex_unlock(&ov13858->mutex); 1486 1487 return ret; 1488 1489 err_rpm_put: 1490 pm_runtime_put(&client->dev); 1491 err_unlock: 1492 mutex_unlock(&ov13858->mutex); 1493 1494 return ret; 1495 } 1496 1497 /* Verify chip ID */ 1498 static int ov13858_identify_module(struct ov13858 *ov13858) 1499 { 1500 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd); 1501 int ret; 1502 u32 val; 1503 1504 ret = ov13858_read_reg(ov13858, OV13858_REG_CHIP_ID, 1505 OV13858_REG_VALUE_24BIT, &val); 1506 if (ret) 1507 return ret; 1508 1509 if (val != OV13858_CHIP_ID) { 1510 dev_err(&client->dev, "chip id mismatch: %x!=%x\n", 1511 OV13858_CHIP_ID, val); 1512 return -EIO; 1513 } 1514 1515 return 0; 1516 } 1517 1518 static const struct v4l2_subdev_core_ops ov13858_core_ops = { 1519 .log_status = v4l2_ctrl_subdev_log_status, 1520 .subscribe_event = v4l2_ctrl_subdev_subscribe_event, 1521 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 1522 }; 1523 1524 static const struct v4l2_subdev_video_ops ov13858_video_ops = { 1525 .s_stream = ov13858_set_stream, 1526 }; 1527 1528 static const struct v4l2_subdev_pad_ops ov13858_pad_ops = { 1529 .enum_mbus_code = ov13858_enum_mbus_code, 1530 .get_fmt = ov13858_get_pad_format, 1531 .set_fmt = ov13858_set_pad_format, 1532 .enum_frame_size = ov13858_enum_frame_size, 1533 }; 1534 1535 static const struct v4l2_subdev_sensor_ops ov13858_sensor_ops = { 1536 .g_skip_frames = ov13858_get_skip_frames, 1537 }; 1538 1539 static const struct v4l2_subdev_ops ov13858_subdev_ops = { 1540 .core = &ov13858_core_ops, 1541 .video = &ov13858_video_ops, 1542 .pad = &ov13858_pad_ops, 1543 .sensor = &ov13858_sensor_ops, 1544 }; 1545 1546 static const struct media_entity_operations ov13858_subdev_entity_ops = { 1547 .link_validate = v4l2_subdev_link_validate, 1548 }; 1549 1550 static const struct v4l2_subdev_internal_ops ov13858_internal_ops = { 1551 .open = ov13858_open, 1552 }; 1553 1554 /* Initialize control handlers */ 1555 static int ov13858_init_controls(struct ov13858 *ov13858) 1556 { 1557 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd); 1558 struct v4l2_fwnode_device_properties props; 1559 struct v4l2_ctrl_handler *ctrl_hdlr; 1560 s64 exposure_max; 1561 s64 vblank_def; 1562 s64 vblank_min; 1563 s64 hblank; 1564 s64 pixel_rate_min; 1565 s64 pixel_rate_max; 1566 const struct ov13858_mode *mode; 1567 int ret; 1568 1569 ctrl_hdlr = &ov13858->ctrl_handler; 1570 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 10); 1571 if (ret) 1572 return ret; 1573 1574 mutex_init(&ov13858->mutex); 1575 ctrl_hdlr->lock = &ov13858->mutex; 1576 ov13858->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, 1577 &ov13858_ctrl_ops, 1578 V4L2_CID_LINK_FREQ, 1579 OV13858_NUM_OF_LINK_FREQS - 1, 1580 0, 1581 link_freq_menu_items); 1582 if (ov13858->link_freq) 1583 ov13858->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; 1584 1585 pixel_rate_max = link_freq_to_pixel_rate(link_freq_menu_items[0]); 1586 pixel_rate_min = link_freq_to_pixel_rate(link_freq_menu_items[1]); 1587 /* By default, PIXEL_RATE is read only */ 1588 ov13858->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov13858_ctrl_ops, 1589 V4L2_CID_PIXEL_RATE, 1590 pixel_rate_min, pixel_rate_max, 1591 1, pixel_rate_max); 1592 1593 mode = ov13858->cur_mode; 1594 vblank_def = mode->vts_def - mode->height; 1595 vblank_min = mode->vts_min - mode->height; 1596 ov13858->vblank = v4l2_ctrl_new_std( 1597 ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_VBLANK, 1598 vblank_min, OV13858_VTS_MAX - mode->height, 1, 1599 vblank_def); 1600 1601 hblank = link_freq_configs[mode->link_freq_index].pixels_per_line - 1602 mode->width; 1603 ov13858->hblank = v4l2_ctrl_new_std( 1604 ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_HBLANK, 1605 hblank, hblank, 1, hblank); 1606 if (ov13858->hblank) 1607 ov13858->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; 1608 1609 exposure_max = mode->vts_def - 8; 1610 ov13858->exposure = v4l2_ctrl_new_std( 1611 ctrl_hdlr, &ov13858_ctrl_ops, 1612 V4L2_CID_EXPOSURE, OV13858_EXPOSURE_MIN, 1613 exposure_max, OV13858_EXPOSURE_STEP, 1614 OV13858_EXPOSURE_DEFAULT); 1615 1616 v4l2_ctrl_new_std(ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, 1617 OV13858_ANA_GAIN_MIN, OV13858_ANA_GAIN_MAX, 1618 OV13858_ANA_GAIN_STEP, OV13858_ANA_GAIN_DEFAULT); 1619 1620 /* Digital gain */ 1621 v4l2_ctrl_new_std(ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_DIGITAL_GAIN, 1622 OV13858_DGTL_GAIN_MIN, OV13858_DGTL_GAIN_MAX, 1623 OV13858_DGTL_GAIN_STEP, OV13858_DGTL_GAIN_DEFAULT); 1624 1625 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov13858_ctrl_ops, 1626 V4L2_CID_TEST_PATTERN, 1627 ARRAY_SIZE(ov13858_test_pattern_menu) - 1, 1628 0, 0, ov13858_test_pattern_menu); 1629 if (ctrl_hdlr->error) { 1630 ret = ctrl_hdlr->error; 1631 dev_err(&client->dev, "%s control init failed (%d)\n", 1632 __func__, ret); 1633 goto error; 1634 } 1635 1636 ret = v4l2_fwnode_device_parse(&client->dev, &props); 1637 if (ret) 1638 goto error; 1639 1640 ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &ov13858_ctrl_ops, 1641 &props); 1642 if (ret) 1643 goto error; 1644 1645 ov13858->sd.ctrl_handler = ctrl_hdlr; 1646 1647 return 0; 1648 1649 error: 1650 v4l2_ctrl_handler_free(ctrl_hdlr); 1651 mutex_destroy(&ov13858->mutex); 1652 1653 return ret; 1654 } 1655 1656 static void ov13858_free_controls(struct ov13858 *ov13858) 1657 { 1658 v4l2_ctrl_handler_free(ov13858->sd.ctrl_handler); 1659 mutex_destroy(&ov13858->mutex); 1660 } 1661 1662 static int ov13858_probe(struct i2c_client *client) 1663 { 1664 struct ov13858 *ov13858; 1665 int ret; 1666 u32 val = 0; 1667 1668 device_property_read_u32(&client->dev, "clock-frequency", &val); 1669 if (val != 19200000) 1670 return -EINVAL; 1671 1672 ov13858 = devm_kzalloc(&client->dev, sizeof(*ov13858), GFP_KERNEL); 1673 if (!ov13858) 1674 return -ENOMEM; 1675 1676 /* Initialize subdev */ 1677 v4l2_i2c_subdev_init(&ov13858->sd, client, &ov13858_subdev_ops); 1678 1679 /* Check module identity */ 1680 ret = ov13858_identify_module(ov13858); 1681 if (ret) { 1682 dev_err(&client->dev, "failed to find sensor: %d\n", ret); 1683 return ret; 1684 } 1685 1686 /* Set default mode to max resolution */ 1687 ov13858->cur_mode = &supported_modes[0]; 1688 1689 ret = ov13858_init_controls(ov13858); 1690 if (ret) 1691 return ret; 1692 1693 /* Initialize subdev */ 1694 ov13858->sd.internal_ops = &ov13858_internal_ops; 1695 ov13858->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | 1696 V4L2_SUBDEV_FL_HAS_EVENTS; 1697 ov13858->sd.entity.ops = &ov13858_subdev_entity_ops; 1698 ov13858->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1699 1700 /* Initialize source pad */ 1701 ov13858->pad.flags = MEDIA_PAD_FL_SOURCE; 1702 ret = media_entity_pads_init(&ov13858->sd.entity, 1, &ov13858->pad); 1703 if (ret) { 1704 dev_err(&client->dev, "%s failed:%d\n", __func__, ret); 1705 goto error_handler_free; 1706 } 1707 1708 ret = v4l2_async_register_subdev_sensor(&ov13858->sd); 1709 if (ret < 0) 1710 goto error_media_entity; 1711 1712 /* 1713 * Device is already turned on by i2c-core with ACPI domain PM. 1714 * Enable runtime PM and turn off the device. 1715 */ 1716 pm_runtime_set_active(&client->dev); 1717 pm_runtime_enable(&client->dev); 1718 pm_runtime_idle(&client->dev); 1719 1720 return 0; 1721 1722 error_media_entity: 1723 media_entity_cleanup(&ov13858->sd.entity); 1724 1725 error_handler_free: 1726 ov13858_free_controls(ov13858); 1727 dev_err(&client->dev, "%s failed:%d\n", __func__, ret); 1728 1729 return ret; 1730 } 1731 1732 static void ov13858_remove(struct i2c_client *client) 1733 { 1734 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1735 struct ov13858 *ov13858 = to_ov13858(sd); 1736 1737 v4l2_async_unregister_subdev(sd); 1738 media_entity_cleanup(&sd->entity); 1739 ov13858_free_controls(ov13858); 1740 1741 pm_runtime_disable(&client->dev); 1742 } 1743 1744 static const struct i2c_device_id ov13858_id_table[] = { 1745 {"ov13858", 0}, 1746 {}, 1747 }; 1748 1749 MODULE_DEVICE_TABLE(i2c, ov13858_id_table); 1750 1751 #ifdef CONFIG_ACPI 1752 static const struct acpi_device_id ov13858_acpi_ids[] = { 1753 {"OVTID858"}, 1754 { /* sentinel */ } 1755 }; 1756 1757 MODULE_DEVICE_TABLE(acpi, ov13858_acpi_ids); 1758 #endif 1759 1760 static struct i2c_driver ov13858_i2c_driver = { 1761 .driver = { 1762 .name = "ov13858", 1763 .acpi_match_table = ACPI_PTR(ov13858_acpi_ids), 1764 }, 1765 .probe = ov13858_probe, 1766 .remove = ov13858_remove, 1767 .id_table = ov13858_id_table, 1768 }; 1769 1770 module_i2c_driver(ov13858_i2c_driver); 1771 1772 MODULE_AUTHOR("Kan, Chris <chris.kan@intel.com>"); 1773 MODULE_AUTHOR("Rapolu, Chiranjeevi"); 1774 MODULE_AUTHOR("Yang, Hyungwoo"); 1775 MODULE_DESCRIPTION("Omnivision ov13858 sensor driver"); 1776 MODULE_LICENSE("GPL v2"); 1777